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ELF > n @ ( @ 8 @ * ) @ @ @ P P P * * 0 0 0 i$ i$ ( ( ( Pd Pd hǍ hǍ hǍ ? h @) @) @) p p p D D hǍ hǍ hǍ Std p p p Ptd { { { , , Qtd Rtd hǍ hǍ hǍ x x /lib64/ld-linux-x86-64.so.2 GNU GNU ݓl *N| GNU ` J` ` d i bk em( +uov' 8 logUa+_y҅y H ; : ` r > I t < L , F j r W B S 4 / B E I b Q 4 l _ * ; K \ _ / [ g U b h ! < / K 9 Q - " Q v < v - 4 + E W v 5 4 L 6 z 4 = w l E # r q @ H R b 4 [ & L \ o j ' j & ' l , F # a Y ] H u , * L : H P 2 P M u g > x } o N : p % C t t 1 a & v ? K s # g g T N ' W \ . 3 $ R Z 6 $ u 3 T v L F p - ` & B s 0 | u c { 3 [ b U j @ # g C . / a { } 5 , l ) b L 2 3 m v P ! > k " P h K ; l O $ @ 8 m < D k o A ( \ $ F f { a u < r ^ b R P x T m ` | " + $ e j " 8 \ M v _ITM_deregisterTMCloneTable __gmon_start__ _ITM_registerTMCloneTable round log10 sqrt log2 inflateEnd inflateInit2_ inflate gzopen64 gzgets gzclose ZSTD_isError elf_version elf64_newphdr elf_rawdata elf64_getehdr gelf_getshdr gelf_update_phdr elf_getshdrnum gelf_fsize elf_nextscn elf_getphdrnum elf_getident gelf_newphdr gelf_getehdr elf_getdata gelf_getclass elf_ndxscn elf_getshdrstrndx elf_errmsg gelf_getverdaux gelf_getrela elf_begin gelf_getrel gelf_getnote gelf_getsym gelf_getphdr elf_memory gelf_getverdef elf64_newehdr gelf_update_ehdr elf_strptr elf_update elf_getscn elf_kind elf64_getshdr elf_newscn gelf_newehdr gelf_xlatetom elf_newdata elf_end gelf_getversym ZSTD_decompressStream dwfl_module_relocation_info dwarf_diename dwarf_lineprologueend dwarf_entrypc dwarf_getcfi dwarf_child dwarf_lineaddr dwarf_getelf dwarf_linesrc dwfl_module_build_id dwfl_end dwarf_bitsize dwarf_formstring dwarf_linebeginstatement dwarf_cfi_end dwarf_addrdie dwfl_begin dwarf_decl_line dwarf_highpc dwarf_formref_die dwarf_getfuncs dwfl_offline_section_address dwarf_tag dwarf_filesrc dwfl_module_addrsym dwarf_cu_die dwarf_getlocation_addr dwarf_cfi_addrframe dwarf_attr_integrate dwarf_formudata dwarf_getsrclines dwarf_lineendsequence dwarf_attr dwfl_build_id_find_elf dwarf_onesrcline dwarf_haspc dwarf_getlocation dwarf_offdie dwfl_module_relocations dwarf_bitoffset dwarf_lineno dwarf_formsdata dwfl_report_offline dwarf_siblingof dwfl_report_begin dwfl_module_getelf dwfl_module_getdwarf dwarf_bytesize dwarf_diecu dwarf_getcfi_elf dwarf_ranges dwarf_aggregate_size dwarf_frame_cfa dwfl_report_end dwarf_dieoffset dwarf_getscopes_die dwarf_getlocations dwarf_nextcu dwarf_getpubnames dwarf_getsrcfiles dwfl_standard_find_debuginfo _Ux86_64_step _Ux86_64_set_caching_policy _Ux86_64_flush_cache _Ux86_64_create_addr_space _Ux86_64_destroy_addr_space _Ux86_64_dwarf_search_unwind_table _Ux86_64_is_signal_frame _Ux86_64_init_remote _Ux86_64_get_reg backtrace lzma_stream_decoder lzma_code lzma_end EVP_DigestInit_ex EVP_MD_CTX_new EVP_md5 EVP_DigestFinal_ex EVP_DigestUpdate EVP_MD_CTX_free SLsmg_fill_region SLkp_init SLsmg_vprintf SLkp_getkey SLtt_Screen_Rows SLang_TT_Read_FD SLsmg_write_char SLang_reset_tty SLsmg_set_color SLsmg_gotorc SLsmg_write_string SLtt_set_color SLtty_set_suspend_state SLsmg_draw_vline SLutf8_enable SLtt_Screen_Cols SLang_getkey SLtt_set_cursor_visibility SLkp_define_keysym SLtt_get_terminfo SLtt_get_screen_size SLsmg_reinit_smg SLsmg_draw_box SLsmg_write_nstring SLang_init_tty SLsmg_refresh SLsmg_draw_hline SLang_ungetkey SLsmg_write_wrapped_string SLsmg_set_char_set SLsmg_reset_smg SLsmg_init_smg Py_DecodeLocale PyMem_RawFree _Py_BuildValue_SizeT PyBytes_FromStringAndSize PyLong_FromUnsignedLongLong PyCapsule_New PyArg_UnpackTuple PyModule_Create2 PyImport_AddModule _Py_Dealloc PyObject_SetAttrString PyLong_FromLong PyErr_Print PyImport_AppendInittab PyBool_FromLong PyErr_Occurred _Py_FatalErrorFunc PyByteArray_FromStringAndSize PyObject_IsTrue PyTuple_SetItem PyLong_AsLong PyRun_SimpleFileExFlags PyErr_Clear PyCapsule_GetPointer PyDict_New PyObject_CallObject PyLong_FromUnsignedLong PyTuple_New _PyTuple_Resize _Py_NoneStruct PyList_New PyObject_GetAttrString Py_Finalize PyUnicode_FromStringAndSize PyList_Append PyUnicode_AsUTF8 PyModule_GetDict PyCallable_Check PySys_SetArgv PyDict_SetItemString Py_Initialize PyDict_GetItemString PyUnicode_FromString __cxa_demangle ZSTD_createDStream ZSTD_flushStream ZSTD_compressStream ZSTD_freeCStream ZSTD_initCStream ZSTD_getErrorName ZSTD_freeDStream ZSTD_initDStream ZSTD_createCStream cap_free cap_get_flag cap_get_proc numa_nodes_ptr numa_allocate_cpumask numa_bitmask_free numa_num_possible_cpus numa_allocate_nodemask numa_bitmask_isbitset mbind numa_bitmask_clearall numa_node_to_cpus numa_bitmask_setbit numa_max_node numa_num_configured_cpus numa_node_of_cpu set_mempolicy tep_set_file_bigendian tep_get_header_page_size tep_get_events_count tep_alloc tep_print_fields pr_stat tep_find_field tep_find_event tep_set_flag tep_set_loglevel tep_get_page_size tep_set_function_resolver tep_get_long_size tep_print_field tep_find_any_field tep_print_event trace_seq_init tep_read_number_field tep_get_first_event tep_parse_format tep_parse_event trace_seq_do_fprintf trace_seq_destroy tep_find_common_field tep_event_fields tep_load_plugins tep_set_long_size tep_register_print_string tep_unload_plugins tep_set_page_size tep_parse_header_page tep_read_number tep_set_local_bigendian tep_register_comm tep_free tep_list_events fgetc fgets pthread_exit strcpy sync nanosleep regfree setvbuf getpagesize fchmod writev snprintf reallocarray pthread_attr_setstacksize stdin epoll_ctl strcasestr setsockopt __isoc23_strtoull prctl pthread_rwlock_destroy sem_destroy fopen64 ctime perror ungetc sem_init strncpy pthread_sigmask __realpath_chk aio_suspend64 symlink dirfd __strcpy_chk asprintf setsid clock_gettime qsort_r __ctype_toupper_loc openat64 __stack_chk_fail __printf_chk fread chdir lseek64 setbuf pthread_once pread64 timerfd_create __assert_fail execlp sigaddset readdir64 regcomp unshare sigfillset pthread_rwlock_rdlock pthread_self setns dlclose sigaction __longjmp_chk strdup fcntl fnmatch sched_setaffinity aio_return64 __sched_cpualloc get_current_dir_name closedir realpath getpwnam_r __getdelim strspn pthread_mutexattr_destroy pthread_barrier_wait socketpair strrchr statfs64 putchar unlink munmap ferror strpbrk fflush mkstemp64 memmove mmap64 strtod strtof gettimeofday memmem clearerr strtok poll fopen strndup __isoc23_sscanf system socket __openat64_2 creat64 localtime_r fork mkdtemp __xpg_strerror_r dirname strlen pthread_cond_init getppid aio_write64 pthread_join getrusage __ctype_b_loc pthread_condattr_setpshared rmdir __vasprintf_chk __sched_cpufree usleep wait4 epoll_wait unsetenv __memcpy_chk strstr gmtime mount faccessat inotify_add_watch __sigsetjmp send pthread_mutex_destroy pthread_mutex_trylock timerfd_settime __strncpy_chk mkdir pthread_attr_init __vfprintf_chk feof getrlimit64 pthread_mutexattr_init __isoc23_strtol __vsnprintf_chk ptrace pthread_cond_signal pthread_create dup2 getpid inotify_init1 signalfd nftw64 pthread_getspecific readlink stdout execve pthread_mutex_lock realloc pthread_cond_broadcast getline isatty __isoc23_strtoll lockf64 execvp clock_getres pthread_attr_destroy __sprintf_chk strcat flockfile name_to_handle_at strftime strcasecmp __fprintf_chk open_memstream lstat64 __xpg_basename atoi strcspn malloc pclose __libc_start_main recvmsg funlockfile pthread_key_create bsearch pread execl pthread_rwlock_unlock pthread_rwlock_wrlock sigprocmask remove stderr fdopen pthread_kill listen __memset_chk memchr pthread_cond_destroy memfd_create alphasort64 epoll_create getpgid strncasecmp __read_chk srandom __strcat_chk fopencookie backtrace_symbols_fd mlockall fcntl64 dlsym pthread_barrier_init sem_wait backtrace_symbols fdopendir raise inet_ntop pthread_rwlock_init getsid __ctype_tolower_loc fstat64 getsockname scandirat64 eventfd dlopen warn srand __isoc99_fscanf __cxa_finalize putenv setlocale epoll_create1 strchr popen __open64_2 ftell strerror setrlimit64 sigqueue mkfifo getenv pthread_mutex_init calloc accept memcmp fclose gettid ftruncate64 __asprintf_chk memset pthread_setspecific pthread_mutexattr_setpshared sem_post __isoc23_strtoul pthread_barrier_destroy regerror ioctl pthread_attr_setdetachstate fputc rename vfprintf __isoc23_vfscanf psignal waitpid tcgetattr fputs sched_setscheduler connect __isoc99_sscanf pwrite64 pthread_mutex_unlock strlcpy __snprintf_chk toupper sigemptyset regexec access getpwuid_r tcsetattr scandir64 aio_error64 memcpy fileno getcwd fwrite select strcmp qsort pthread_condattr_destroy uname fseek __sysconf strsep __errno_location madvise __isoc23_vsscanf syscall abort fmemopen sched_getaffinity mmap pthread_attr_setaffinity_np pthread_cond_wait pause pipe sched_getcpu pthread_condattr_init strtok_r strncmp geteuid __strncat_chk warnx errx memrchr rewinddir alarm __cxa_atexit libm.so.6 libz.so.1 libelf.so.1 libdw.so.1 libunwind-x86_64.so.8 libunwind.so.8 liblzma.so.5 libcrypto.so.3 libslang.so.2 libpython3.12.so.1.0 libstdc++.so.6 libzstd.so.1 libcap.so.2 libnuma.so.1 libtraceevent.so.1 libc.so.6 ZLIB_1.2.3.3 GLIBC_2.29 GLIBC_2.2.5 CXXABI_1.3 XZ_5.0 OPENSSL_3.0.0 SLANG2 libnuma_1.1 libnuma_1.3 libnuma_1.2 ELFUTILS_1.6 ELFUTILS_1.3 ELFUTILS_1.5 ELFUTILS_1.0 ELFUTILS_0.126 ELFUTILS_0.161 ELFUTILS_0.160 ELFUTILS_0.138 ELFUTILS_0.130 ELFUTILS_0.142 ELFUTILS_0.127 ELFUTILS_0.157 ELFUTILS_0.143 ELFUTILS_0.122 GLIBC_2.22 GLIBC_2.33 GLIBC_2.3.3 GLIBC_2.26 GLIBC_2.27 GLIBC_2.9 GLIBC_2.8 GLIBC_2.30 GLIBC_2.17 GLIBC_2.11 GLIBC_2.4 GLIBC_2.6 GLIBC_2.32 GLIBC_2.3.4 GLIBC_2.28 GLIBC_2.3 GLIBC_2.15 GLIBC_2.14 GLIBC_2.38 GLIBC_2.3.2 GLIBC_2.34 GLIBC_2.7 ! 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L z A4 L y A7 L z A= L z AF L fz AD L Ry A@ vL @y AI dL Oz AW RL y AX @L +z Ae .L x Af ff. @ UHSHH dH%( HE1uq{tH H5 C8 @ C8 u] 1HUdH+%( H]L Ix A 5{ H x H x _J L hx A 5F H w Hw 1 (J L %x A L x A L w A L x A L x A L \w A L蔰 @ UHAWAVE1AULmATL%W SM|$<HXdH%( HE1A HH LP~ A L1L LHw AuDLd~ Ht I M9uHEdH+%( HXD[A\A]A^A_]f D LM5 LEH 1H LL L} HJt DE5ij 1L Hw DEH DEAEEYAX UHAWAVAUATSH H $ H H0H8dH%( HE1 H I ILL;w 1LhLHHL HܶH3 x.LxuA tހx.uA.u A tf D H MLAWLx 1 LV AXZEtH5 LH(HHgH@ HH 萷H L LH(Ƅ? 蔱L<L0LI*L8HI(I>HtXI? tRHEdH+%( uYHeD[A\A]A^A_]f HE1 H( 賩H8H8褩=ff. fUHAUATSHHHdH%( HEHGHt Є ;> IH LmLz H3E11A LL*t u>LSL{ L^q HEdH+%( HH[A\A]]f D H LMA 5 HD 1E H3LE| H}HtH5t H q 5V Ht 1?E \58 11Hot E < D UI Lwt HSHHHP dH%( HE1V HDž !HjHHH@HUdH+%( uH]Vf D UHAUATHuH}SH(dH%( HE1tGLeLmLL,LbLZHEdH+%( uH([A\A]]f D ̪ff. UHSHdH%( HEGu#9wun1HUdH+%( H] H& HHtuH趍 uċ5 L (s A H q Hq gC 2 D L q A 5Q H p Hp 1 3C ]L r A D UHAWAVAUATSHHDgdH%( HE1 ¸ A9b 裿 { HE1L%+ L-r L H C8S @ C: C8 H HH p L;L L u{AG8 @ AG: AG8 I HLs Ap $ w u+1HUdH+%( * H[A\A]A^A_] A蟽 A9}I f苽 s @ { x랐L o A 5 H n Hn 1 A ef D L n A L n A 뱐L ~p A 롐L p A 두L n A 끐L up A nf D L np A 5y H n H n ]@ X L Cp A f D L n A f D L n A f D L n A f D L o A f D L o A f D L m A f D L }o A vf D L vo A f D L ko A FL %m A 4 ff. @ UHATSHH DgdH%( HE1 ¸ u3A9u8{ufH{un1HUdH+%( ulH[A\] L l A 5 H Gl HUl 1 > L l A L =l A G UHAWAVAUATSHHDgdH%( HE1耺 D@A9 H L;L9x E1E1L5:n f AG { A AG8 @ AG: / AG8 I L9 A Ap M D I( I AG8 @) AG:. 8 AG8 < M M9> I Lȳ9 A = A$ A9 : Ep EJ MM?L91 @ HUdH+%( B H[A\A]A^A_]f D I AG8 @ AG: I AG8 _ LL t I A + Ap 7L k A3 H> LAG8v @ AG: AG8 M; Ap L Ck AB 5> H h Hh 1 ; ~f D @ AG: N AG8Щ O LL t'I V I A + uIAp L j A C A9 L j A! L j A L h A L h A L g A L g A L h A L i A L i A L g A yL i A gL |i A UL i A CL i A 1L #g A* L 6g A+ L 7g A, L :g A- L g A; L h A. L f A< L f A= L h A/ L }h A> }L f A0 kL mh A? YL f A@ GL mh AA 5L 4f A #L Vh A L h A2 L Rh A L g A L f A L f A L e A L g A L e A L e A oL g A ]L _g A KL e A 9L ;g A 'L <g A L Hg A$ ff. UHSHdH%( HE1 H HH9uXHz( ufHz uoHH9t?ztL Rd Aj 5¡ H Jd HXd 1 6 HUdH+%( ugH] L e Al 뭐L e An 띋5_ L d Af H c Hc 66 L Gf Ag ^ff. f UHHdH%( HE1 HH9u2~ f D @ @8 H H9tQP8tL c AO 5 H !c H/c 1 {5 HEdH+%( ɸÐHEdH+%( u{ L 2c AP f L /c AQ f D L (c AR k5 L b AL H b Hb 4 [衛 UHSHH dH%( HE1uKB { H{( u\H{ HUdH+%( H]f D 5^ L b AY H a Ha 54 L b A\ 5 H a Ha 1 4 L a A[ L b A^ L c AZ 蝚ff. f UH= HHdH%( HE1 HHUdH+%( uMff. f UH=c HHdH%( HE1蹥 HHUdH+%( uff. f UH=B HHdH%( HE1i Ht$HHEdH+%( u%H5 E{ D HEdH+%( u1舙 UHATSHL'dH%( HE1 A|$ I|$} HLr H5b H3 {I<$ Hut7 H5b H HUdH+%( H[A\] @ L _ A 5ᜄ H i_ Hw_ 1 1 @ L j_ A Ƌ5 L b_ A H "_ H0_ ~1 L ^ A L ,_ A xL ^ A fL a A TL a A B UHSHH dH%( HE1 {uaH H5ia H躧 H;uqԣ H5Pa H蕧 HUdH+%( H] @ L ^ Ac 5 H ^ H^ 1 c0 @ L ] Ah Ƌ5G L ^ Aa H ] H] 0 L ` Ad L s` Ai xƖf D UHAWAVAUATSHWdH%( HE11 1I HH E1A { { E11f [ HHt'G;CuEufA ED4 HHuE HL HHuE 1HUdH+%( H[A\A]A^A_] L _ A 5 H y\ H\ 1 . L ~\ A L U_ A L z_ A L _ A 띋5 L I\ Az H \ H\ e. .ff. UHHdH%( HEHH9u.} D @ @8 H H9tQP8uL [ A^ 5阄 1H o[ H}[ - HEdH+%( u^ɸ D HEdH+%( uC L [ A_ f L [ A` 놐L [ Aa s)f UHSHwdH%( HE1j H1=f D @ B8 9tdHB8tL Z A @ 5Ɨ H NZ H\Z 1 , HUdH+%( P H]f. HH x C8 @ C8 1f D L Z A Vf D L Z A >f D L Z A &f D L Z A f D L Z A L }Y A L Z A L Y A L Y A L `Y A L ;Y A L X A x ff. UHAWAVAUATSH H $ H H $ H E1dH%( HE1Dž L輖 IH HDž I HDž x H Lx IH HHSH1٭H H*AYAZ H2IH f D L(H HXf. HDž H) XHuHLLLLh SL 2_AX= H59 LIH HHH ޡHm H? H轖HH 舌LHDž œ5C 1L Hw )) LH LHL IH$HEdH+%( V He[A\A]A^A_] @ LLHDž )HMLS LY 1L ګHSLL HY^ I>Kq - H膕HSIٺ L8Y A6 LhHLHXZ5䒄 1L Hv ' D؉s 5 11Hu ' PI5 1LHu m' 5^ L1HHv >' DDDDf D 5 H1Hu & LtDž5㑄 Hٿ 1HNu & H5 1HW & DžVf D UH5W HSHHH?dH%( HE1R t HEdH+%( uTHH]rf5. L ZW A H S HS & HEdH+%( u H]趌f D UH5t HHH?dH%( HE1趜 t1HUdH+%( u4Ë5 L V A H S H&S t% 8 UH5V HHH?dH%( HE16 t1HUdH+%( u4Ë5 L IV A H R HR $ 踋 UH5EV HHH?dH%( HE1趛 t1HUdH+%( u4Ë5 L U A H R H&R t$ 8 UH5U HHH?dH%( HE16 t1HUdH+%( u4Ë5 L IU A H Q HQ # 踊 UH5 HHH?dH%( HE1趚 t1HUdH+%( u4Ë5 L T A H Q H&Q t# 8 UHAWAVAUATSH(H}dH%( HE1ś H HE1L- } D H H' x.L`uA|$ t݀x.uA|$.uA|$ t LL譙tH5WT L蚙tH5QT L臙tL蠚 HEH HfIH f. LXHt]x.LpuA~ tx.uA~.u A~ tf D LL tLH5 LAHuL>H}h HݐH @ HHED9xu]HEdH+%( H}H([A\A]A^A_]t5 L ES A? H O H+O y! A뙋5o 1L 6S AX H N HN D! HEdH+%( uUH([A\A]A^A_]L R A0 5 H N HN 1 vL R AB 談ff. U1HR Lp HAUL-p ATLeSH(5 dH%( HE1 Lma 1LLpK u4LLa HEdH+%( u6H([A\A]]f D 56 ALHo 1 UHAWAVL5Q AUE1ATL% 4 S1HdH%( HE1 I t]M$5 L 1 LAADžtM$5 1HEo { AEEI uHEdH+%( uHD[A\A]A^A_] UHAWAVL5Q AUE1ATL%O6 S1HdH%( HE1 IJt]M$5 L 1 LqADžtM$5ĉ 1Hun AEEIJuHEdH+%( uHD[A\A]A^A_]AUHHdH%( HEGu$Gum1HUdH+%( f D 詑 HHtxH57T 5h uċ5 L M A H K HK 1 @ L K A 5ш H YK HgK 1 ^L 1M A e D UHAVAUATSHHDgdH%( HE1B ¸ A9 H A ¸ D9 HE1L% L H C8t @ C: C8 H; p L3L AF8 @ AF: AF8% = HL I A + 2 Ap ; Θ u*1HUdH+%( S H[A\A]A^] A A9}I f. ۗ A @ ˗ [f D 軗 ^뇐L GI A| 5^ H H HH 1 @ Nf D L I A} L I A~ 뱐L J A 롐L J A 두L I A 끐L J A nf D L J A Vf D L J A >f D L oH A &f D L jH A f D L gH A f D L I A f D L I A f D L 0H A f D 5 L I A H G HG L J A ^f D L I A FL eG An 4L I Ap "Mff. f UHAUATISH_dH%( HE1% ¸ 6 9 L I $I9 E1 u {j Hz7 C8 @ C: C8 H; p HI9 CrH{ C8 @( C:. 8 C8 = H H9? D 9 D p I[L E A 5 H VE HdE 1 HUdH+%( H[A\A]] D C8 @ C: 1 C8 LH tH + u;p L G A 4 @ ; D f1>L 0G A L D A L D A L aF A L cF A L D A L cF A L ^F A L D A wL D A eL D A SL "D A AL E A /L E A L C A L E A L E A L E A L dC A L }C A L XC A L nC A L PE A {L D A iL IC A WL D A EL (E A 3{ff. UHAVAUATSHHDgdH%( HE1袑 ¸ A9 腑 A H+ D9 a HE1L% H9 C8 @ C: C8% = H H H9 9 p L3L L AF8 @ AF:) 9 AF8% = = HL" B I A + ] Ap f u%1HUdH+%( ~ H[A\A]A^] A7 A9}I ~f. ! @ A, :댐L @ AZ 5} H &@ H4@ 1 Sf D L Z@ A[ L _@ A\ 뱐L A A^ 롐L B A_ 두L @@ A` 끐L A Aa nf D L A Ab Vf D L !B Ac >f D L B Ad &f D L A Ae f D L ? Am f D L z? An f D L w? Ao f D L A Aq f D L A Ar f D L @? As ~f D 5| L @ At H > H> h L 'A Au .f D L @ Av L u> AL L @ AN ]wff. f UHAVAUATSHHDgdH%( HE12 ¸ A9 H A ¸ D9 HE1L%u H C8t @ C: C8 H H H9 9 p L3L L]e AF8 @ AF:+ ; AF8 E HL J I A + e Ap n 衋 蔋 1ۄ M&L/ AD$8g q @ AD$: w AD$8 V I$ I$ I9 A$ A9$ [ A$p M4$Hs L AF8x @z AF: AF8 { LLV I A + L 6 ? 1ۄt 蔉 9~hM6LuaAF8 w @ AF: AF8 p M; - ω u1f D HUdH+%( H[A\A]A^]A A9I f D ۈ P ˈ i @ 軈 E1k L ?: A 5Vw H 9 H9 1 8 Nf 9tf L 9 A 멐L 9 A 뙐L ; A 뉐L ; A vf D L 9 A ^f D L ; A Ff D L ~; A .f D L ; A f D L ; A f D L C; A f D L 9 A f D L 9 A f D L 9 A f D L : A f D L : A nf D L 8 A Vf D L : A 5u H !8 H*8 } @ L : A f D L K: A L 8 A L G: A L 7 A L 7 A L 8 A L 9 A L 9 A pL 7 A ^L 9 A LL 9 A :L x9 A (L U9 A L a9 A L 37 A L I7 A L "7 A L 67 A L 8 A L 8 A L 8 A CL %9 A toL 8 A ]L 6 A KL z6 A 9L 6 A 'L A8 A L 8 A L Z6 A f UHAVAUATSHHDgdH%( HE1 ¸ A9 H Aʄ ¸ D9v 譄 HE1L%9 H@ C8l @ C: C8 H H H9 9 L3L L+u{AF8 @ AF: AF8 HL I A + ' 肃 u&1HUdH+%( ? H[A\A]A^] @ A诂 A9}I f蛂 Q @ 苂 kf D { n듐L 4 A 5 q H 3 H3 1 Zf D L 3 A L 3 A 뱐L ~5 A 롐L 5 A 두L 3 A 끐L u5 A nf D L n5 A Vf D L 5 A >f D L 5 A &f D L 3 A f D L 3 A f D L 3 A f D L 4 A f D L 4 A f D L 2 A f D 5o L 4 A H )2 H72 L 4 A NL -2 A <L o4 A *k D UHAVAUATSHHDgdH%( HE1 ¸ A9 H Aʀ ¸ D9v 譀 HE1L%5 H@ C8l @ C: C8 H H H9 9 L3L L+u{AF8 @ AF: AF8 HL I A + ' u&1HUdH+%( ? H[A\A]A^] @ A~ A9}I f~ Q @ ~ kf D {~ n듐L 0 A 5 m H / H/ 1 Zf D L / A L / A 뱐L ~1 A 롐L 1 A! 두L / A" 끐L u1 A# nf D L n1 A$ Vf D L 1 A% >f D L 1 A& &f D L / A. f D L / A/ f D L / A0 f D L 0 A1 f D L 0 A2 f D L . A3 f D 5k L 0 A4 H ). H7. L 0 A5 NL -. A <L o0 A *g D UHAVAUATSHHDgdH%( HE1| ¸ A9 H A| ¸ D9v | HE1L%1 H@ C8l @ C: C8 H H H9 9 L3L L+u{AF8 @ AF: AF8 HL I A + ' { u&1HUdH+%( ? H[A\A]A^] @ Az A9}I fz Q @ z kf D {z n듐L , AL 5 i H + H+ 1 Zf D L + AM L + AN 뱐L ~- AO 롐L - AP 두L + AQ 끐L u- AR nf D L n- AS Vf D L - AT >f D L - AU &f D L + A] f D L + A^ f D L + A_ f D L , A` f D L , Aa f D L * Ab f D 5g L , Ac H )* H7* L , Ad NL -* A> <L o, A@ *c D UHAVAUATSHHDgdH%( HE1x ¸ A9 H Ax ¸ D9v x HE1L%- H@ C8l @ C: C8 H H H9 9 L3L L+u{AF8 @ AF: AF8 HL I A + ' w u&1HUdH+%( ? H[A\A]A^] @ Av A9}I fv Q @ v kf D {v n듐L ( A{ 5 e H ' H' 1 Zf D L ' A| L ' A} 뱐L ~) A~ 롐L ) A 두L ' A 끐L u) A nf D L n) A Vf D L ) A >f D L ) A &f D L ' A f D L ' A f D L ' A f D L ( A f D L ( A f D L & A f D 5c L ( A H )& H7& L ( A NL -& Am <L o( Ao *_ D UHAWAVAUATSHHDgdH%( HE1t ¸ A9 t L3E1H ) L%' L_ AF8 @ AF: % AF8 ' I ) LL. . Ap W M>Hھ LT AG8G W @g AG:r AG8 LL Ap M?L Lײu{AG8 @ AG: AG8 I LL* Ap .s u*1HUdH+%( H[A\A]A^A_]f D AWr A9}M73f. ;r @ +r ~fL # A 5` H V# Hd# 1 ^f D L # A L # A 뱐L .% A 롐L 2% A 두L p# A 끐L %% A nf D L % A 5)` H " H" X L $ A f D L " A f D L " A f D L " A f D L N$ A f D L J$ A f D L " A f D L >$ A f D L 3$ A ^f D L ! A Ff D L ! A .f D L ! A f D L # A f D L # A f D L ! A f D L m# A f D L f# A Cf D L [# A L ! A tZff. @ UHAVAUATSHHDgdH%( HE1o ¸ A9 o HE1L%$ L-" HQ H HH` n u C8# HL H聮u6C8 HL H`uC8 o u)1HUdH+%( H[A\A]A^] AGn A9}H1f. +n @ n 또L ! A# 5\ H I HR d L ~! A$ f L d A/ 뮐L T A7 L E A' 5R\ H H 1 4 L A Wff. UHAVAUATSHHDgdH%( HE1m ¸ A9 m HE1L%" L- H1 H HH@ l u C8# HL Hau6C8 HL H@uC8 l u)1HUdH+%( H[A\A]A^] A'l A9}H1f. l @ k 또L AY 5Z H ) H2 d L ^ AZ f L Q Ae 뮐L A Am L 2 A] 52Z H H 1 L AM Uff. UHHdH%( HEHP8 @ @8 u,u]xufHxun1HUdH+%( fL A 5nY H H 1 P L A L A L A L A L A L A |T UHAUATSHWdH%( HE1 1I胬 HH L- #f D { HLS HHtS{t` HH Ls7 uL A 5@X H H $ Of1HUdH+%( udH[A\A]] @ L A 5W H y H 1 L T A L | A ivSf D UHHHdH%( HE1B8 tu@ B8 ~ tHEdH+%( `L 1 AD 51W 1H H HEdH+%( uCɸL AA L A@ L AC L AB Rff. UHHHdH%( HE1B8 J: @ B8 u HEdH+%( Vf D L @ A 5!V 1H H HEdH+%( ugɸL A L A L A L A L A |L A jXQ UHHHdH%( HE1B8 J: @ B8 u HEdH+%( &f D L A 5T 1H w H HEdH+%( ugɸL A L \ A L a A L z A L X A |L n A j(P UHAUATISH_dH%( HE1f ¸ 9` e I $E1C8usf @ C8 e u*HEdH+%( HL[A\A]] D Ad A9}HC8tL V A 5pS 1H H R HEdH+%( H[A\A]]Ðkd f D [d Lf D L A f L A lf D L A Tf D L A <L m A *gN UHHdH%( HEHH9ue D usH H9tSP:uL A 5CR 1H H % HEdH+%( u5ɸ HEdH+%( u L A Mff. UHHdH%( HEHH9ue D tsH H9tSP:tL @ A 5Q 1H H e HEdH+%( u5ɸ HEdH+%( uS L A Lff. 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D AU1 ATUSH^ 1ljnIHa I9S E1A L1艙IAXHcI HH, L(DD`A EIQML9 ID J9rqHtl8PKudHHL I9uVfx p fx f;p HAD@ r&D9r!AMtK sHH[]A\A] D HHx I9uHLLHH踈f D +HHcH[]A\A]f D H"HH[]A\A] @ HšLLHuU SHwH?]H[4 @ AWAVAUATUSH(Dg_ HT$Eq HDo.r{A9t$rrL7LtjHE1蟎t$H;PKuPDC 1LA@E9r:u6C tHC s ADE9 ǃ.r A9rLHuH([]A\A]A^A_ @ H9uLHDD$ HT$HT$DD$ uS*r sA9rHLt9PKuA uQArA9ry rA9yyAE1AAE9`EWIH\$fnfnfbf LfDCHKIfC Ls#f D f. @ H6H?!AWAVLw`AULoHATUSHHHo8dH%( HD$1H;o r H;k H{LAH1HtCL; u͋SHHs(H;~IHtH;sN*HHtL躉HtH{Hk8L{@ǃ ƃ Ht3HT$D膡H]D$f HC@ @ HT$dH+%( u H[]A\A]A^A_f 1 AWAVEAUIATA̹ USHH H$H$ dH%( H$ 1HHH E1Hl$P LH%IHt}HL袈HtD9d$TuHt$LHt$脈Ha D$81LIE(虠IEHL H@1I] E Ht$HIE A tT1$ H$1 H5>\ 9H$ dH+%( & H []A\A]A^A_ E1 D LHEIHtHLHt݁|$TouL1E1֟IEfLHIHMHL~Htف|$Tou1L蕟IEHtoHt$LOHt]D$8IE01'H$H5[ 1H1:薙H$H5[[ 1H1H$H5[ 11肆f ATI UHSH dH%( H$ 1N L1gÅxA1Ҿ 蓡HtvHE ]1H$ dH+%( HĐ []A\˛H満 ۉHLH5 1H12LH5Z 1`듿~LH5Z 1H1_|brf HtSHH?+{[Rfff. @ AWAVAUATUHSH Ht$(H|$0dH%( H$ 1H\` H$8 H$@ HHD$8WH[ @ HD$P HIH\ II)x@ IH$8 fDl$FHD$ H$ HD$Lt$HD$ HT$(A Ht$0H|$ D$@Hc H AH|$&IH I>LHH|$WuH|$B'uH|$ t|$@ HuAF IN0I~IV8H~<HHH)H9zAt [ <cHAH)U D H H HD$ HL$8HD$ H9Dl$FH HL$(H11H5Y ~H$ dH+%( HĘ H[]A\A]A^A_ H$ AN`HT$`HLt$HIAH\$L蚉Ht5D$dA9 D$pt H$ LkHuf D H\$Vf D IHL$(IH H5X 1}% @ HxIILD$(H1H5 X 1H_}t$lAHT$XH$ Lt$HH\$D{HH$ T$XH$ ёHHHt$ۑ~fAHBW HL$(HL[W H5W HLD11|DH_RHT$(H5U 1H1|P AUATIUHSH(dH%( HD$1HHcHu&L,$LHLLHϛ|$~HD$dH+%( uH(H[]A\A]Ӏ AWAAVAUATIUHSH8 t$XHt$`HL$HDD$4dH%( H$( 1H[ H$ D$0t0H$( dH+%( D$0H8 []A\A]A^A_ Mc L0 LHD$ IHHD$`HD$8Mn He H1E~fHL B HHHJI9uH LHH$( Lt$H$ HD$PHD$pHD$Hl$(Ld$@HD$(DD$4HT$@Ht$8H|$D$\ D H|$>HtyH Ld$E1Lp8L(LpL+p0L$L4$IL D I9s-I, LHHHM$I4$xatoL}I9rH|$LHu @ HD$(HD$(H9D$P(T$X9T$0 H{D$0|f. Hp IcD$ HT$ LLHLMtlH $I9}tr|$LD$@L11H5T yD$0H~zH|$ tzH|$8ژ|$h| @ D$0H$HD$E|$u{HD$HHT$ HH zD$\D$0 tD$\D$0v}HyD$0df AWIAVAUATUSHH( H|$Ht$PHL$0dH%( H$ 1HX HD$@ HD$H H$ Aą HD$PL|$8Hl$`L$ HD$H$ HD$(HD$@HD$AHT$A HHt$D$$ D$$ E1L|$H HIHtZI<$Hd`tIH|$ LLT HT$@ID$8HID$I+D$0JD.IHuMufIL9t$(CAH|$@rxH|$ؖ|$XyH$ dH+%( u=H( D[]A\A]A^A_ËD$$ AHD$@L|$8Dd$$IHD$0L({f. Hg 1^ HH HH r~@8|5H H LLNLVL^Hv LLOLWL_H sԃ DHHH H LFLNLVL^HvLGLOLWL_Hs҃ H)H)׃r$LLNLTL\LLOLTL\ÐrLLLLLLf. rDDDDff. rtLFL DGD ÐI@HLÐI@HHAAupHHt9f HHHGHGHGHG HG(HG0HG8H@u у8tf D HHut ʈHuLHvHI M)LL)r HH zD.QTv_Q(knN $tI = cmd_config @@@ Hh V #%P%#$&%%%! 5+,+**(trigger_on trigger_hit setup and enables call-graph (stack chain/backtrace): record_mode: call graph recording mode (fp|dwarf|lbr) record_size: if record_mode is 'dwarf', max size of stack recording (<bytes>) default: 8192 (bytes) Default: fp cmd_report Display call graph (stack chain/backtrace): print_type: call graph printing style (graph|flat|fractal|folded|none) threshold: minimum call graph inclusion threshold (<percent>) print_limit: maximum number of call graph entry (<number>) order: call graph order (caller|callee) sort_key: call graph sort key (function|address) branch: include last branch info to call graph (branch) value: call graph value (percent|period|count) Default: graph,0.5,caller,function,percent ąԅ__\0p00Pt\L<,̔ P@h0 `` J = 0 b U # 0 setup and enables call-graph (stack chain/backtrace): record_mode: call graph recording mode (fp|dwarf|lbr) record_size: if record_mode is 'dwarf', max size of stack recording (<bytes>) default: 8192 (bytes) print_type: call graph printing style (graph|flat|fractal|folded|none) threshold: minimum call graph inclusion threshold (<percent>) print_limit: maximum number of call graph entry (<number>) order: call graph order (caller|callee) sort_key: call graph sort key (function|address) branch: include last branch info to call graph (branch) value: call graph value (percent|period|count) Default: fp,graph,0.5,caller,function 666(7P7p776@6i %cmd_script per_vcpu_record ENTER Toggle callchains (if present) n Toggle Node details info s Toggle full length of symbol and source line columns q Return back to cacheline list d Display cacheline details ENTER Toggle callchains (if present) q Quit Display call graph (stack chain/backtrace): print_type: call graph printing style (graph|flat|fractal|folded|none) threshold: minimum call graph inclusion threshold (<percent>) print_limit: maximum number of call graph entry (<number>) order: call graph order (caller|callee) sort_key: call graph sort key (function|address) branch: include last branch info to call graph (branch) value: call graph value (percent|period|count) Default: graph,0.5,caller,function,percent insert_caller_stat insert_alloc_stat ^_?_?(alloc|get_free|get_zeroed)_pages? page_sort_dimension__add setup_page_sorting slab_sort_dimension__add setup_slab_sorting No %s allocation events found. Have you run 'perf kmem record --%s'? rate, runtime avg, max, count runtime, max, count RSDTtZXxKWP add_sched_out_event thread_atoms_insert avg, max, switch, runtime /-g/-/g/1E1/1001AAAAA|ApAdAXALA@A4A(A AAA@@@@@@@@@@@t@h@\@P@D@8@,@ @@@????A???????x?l?`?T?H?<?0?$??A ? ?>>>>>>>>>>|>p>d>X>L>@>4>(> >>>===========t=h=\=P=D=8=,= ===<<<<<<<<<<<x<l<`<T<H<<<0<$<<< < <;;;;;;;;?F F FEEEEEEEEEE|EpEdEXELE@E4E(E EEEDDDDDDDDDDDtDhD\DPDDD8D,D DDDCCCCCCCCCCCxClC`CTCHC<C0C$CC C? CBBB?????BB?BBBBB|BpBdBXBLB@B4B(B BBBAAAAAAA?AAAAtAhA\APADA8A,A AAA@@@@@@@@@@@{@r@i@`@W@N@E@<@3@*@!@LDJtJhJ\JPJDJ8J,J JJJIIIIIIIIIIIxIlI`ITIHI<I0I$II I IHHHHHHHHHH|HpHdHLDLDLDXHLH@H4H(H HHLDLDHGGGGGGGGGGGtGLDhG\GLDLDPGDG8G,G GGGFFFFFFFFFFFxFlF`FTFHFLDLDLDLDLDLDLDLDLDLDLDLDLDLDLDLDLDLDLDLD<F0F$FF F FEEEEEEEEEELD|EpEdEXELE@E4E(E EEEDDDDLDLDLDLDLDLDDDDDDDDDDzDqDXHtNhN\NPNDN8N,N NNNMMMMMMMMMMMxMlM`MTMHM<M0M$MM M MLLLLLLLLLL|LpLdLXLLLXHXH@L4L(L LLLXHKKKKKXHXHKXHKKKKKtKhKXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXH\KPKDK8K,K KKKJJJJJJJJJJJxJlJ`JTJHJ<J0J$JJXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXH J JIIIIIIIIII|IpIdIXILI@I4I(I IIIHXHHHXHHHXHHHHXHHXHHHHH}HPPPPPPPPPtPhP\PPPDP8P,P PPPOOOOOOOOOOOxOlO`OTOHO<O0O$OO O OPNNNNNNNNNN|NpNdNXNLN@N4N(N NNNMMMMMMMMMMMtMhM\MPMDM8M,M MMMLLLLLLLLLLLxLlL`LTLHL<L0L$LL L LKKKKKKKKKK|KpKdKXKLK@K7K.K%K KK KKJJJJJ`UTUHU<U0U$UU U UTTTTTTTTTT|TpTdTXTLT@T4T(T TTTSSSSS`USSSSSStShS\SPSDS8S,S SSSRRRRRRRRRRRxRlR`RTRHR<R0R$RR R RQQQQQQQQQQ|QpQdQXQLQ@Q4Q(Q QQQPPPPPPPPPPPtPhP\PPPDP8P,P PPPOOOOOOOOOOOO{OrOiO`OWONOEO"O(XXXYYYYY(X(X(X Zs\s,srrrlr<r rqq|qLq qppp\p,pooolo<o onn|nLn nmm|vvvw<w\w|wwwwxduDvHB`BAAAAAAAxBAA">%~/ event-hyphen event-two-hyph test__syscall_openat_tp_fields pjjpjjkpjpjpjpjjk print_hists_out print_hists_in QQRQQ write_mmap write_comm leafloop sqrtloop brstack datasym p symbol__disassemble evsel__get_arch __symbol__inc_addr_samples $..--$-..\/D/t/<.,/t0\0D0,0t/01|11d1012222124l4Y4434 add_config_item add_section collect_config (((((AAAAAABBBBBB PP `xXX evlist__prepare_workload bbbaac utXt8ttsssqq(sqr t T t T 4 <0$ Xxh. 0$ H<X||<||||||||||||||||||||||l||\||<|| ||||\|||||T,d$\<4D3d34432L2L23T42L2L2L2L2L2L2L24 3L242t4lp\p\oLo<o,o o onnnnnnnn|nlnoooooo|olo p poo<p,pLp<n<n<n<n<n<n<n<n<n<n<n<n<n\npp0q@qPq`qpqqqp qq qppp@rHrXr@rhr@r8sxrrrrrrrrrss(s rsstttttttpt`tPt@t0t tt t`uPu@u0u uu utuuupuuuux xwwwwwwwwpw`wPw@w0w ww wvvvvvvvvxxpv`vPv(vxxx0| || |{{{{{{{{p{`{P{@{0{ {{ {zzzzzzyyypy`yPy@y0y yy yxxxxx zz zyyyyy`zPz@z0zzpzzD| |4}$}}}||||||||t|d|T|}}}}t}d}T}D}}}}}~~$~~|~tdTD4$~~~~~$dTD4t|l\L<, ܂̂|l\L<, ||ll\\LL<<,, ́́܁܁ d$$$$$$$t$$$$$$$D$$$$$$$$$$$$$d$$$$$$$t$$$$$$$D See 'perf help COMMAND' for more information on a specific command. perf [--version] [--help] [OPTIONS] COMMAND [ARGS] P P00kgvVjlBDfuxbdGMKm o fefePePeffPePePePePe[e[e[e[efePepd cpd cm_m_ddm_m_m_m_m_`_`_`_`_pd c symbol__new symbols__fixup_end perf_event__process_tracing_data do_write_feat write_tracing_data write_build_id write_auxtrace build_mem_topology 6.8.12 get_tls_callchain_cursor 4T,l 8vwwx8x8v8vx8v8v8yxyxv`v`vvvv(w`ww maps__set_modules_path_dir machine__process_text_poke pstack__pop pstack__push pstack__remove 0xP0 H0D D$dT4 dD prefetch_event 9(99x889 ttk٠JТ>uҝCw Sթ iG>MMM-x˰9V ݮmMSæ3kۧ/dG@V x۫hBkXk H $ & . $ . . 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C R a 9 p ~ cond_broadcast cond_signal cond_wait cond_destroy __cond_init mutex_trylock mutex_unlock mutex_lock mutex_destroy __mutex_init populate_sdt_note dso__load_sym_internal symsrc__init filename__read_debuglink sysfs__read_build_id elf_read_build_id read_build_id dso__synthesize_plt_symbols D܅x] ܅08ЭP T8pT`````set_table_handlers python_process_general_event python_process_brstacksym python_process_brstack get_sample_value_as_tuple set_sample_read_in_dict get_perf_sample_dict python_process_callchain define_field define_value python_process_tracepoint process_stat stat__interval python_process_stat_interval handler_call_die tuple_new ......#/>//.5/,/$9877777877777777777l8777777L8L8L87L877L8L879777777L877d9777L8L9 jit_add_pid perf_env__add_bpf_info perf_event__synthesize_one_bpf_prog perf_event__synthesize_bpf_events get_bpf_prog_info_linear intel_pt_track_switches intel_pt_find_snapshot intel_bts_find_snapshot Q / F / F - M m 1 Q q ! A a = ] } C C @ @ ! " Y s s s s ? @ # È 2 b " " "4 4 " V V c c c c 3 3 ! ! S " S? " ? bp_2 bp_1 v pP 0 * F! y( ! F! " F! F!# T# " &% \%A% ! % % ~% & &% "$!F!$"$$+ n & 7 n ! n n ! |! 8 N# #i# 3# # # A$2$# !# n "J")")### #####` ###)############# ################### )############ # #### ###` #s!####!!################# X!##!#!#f"W"!#* =! !o N 0ЕЕ0ЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕЕ Е 2ǙDDCDDDDDDDDDDDDDDDDDDDDDDDDDDDPPPPPsPPPȠPPPPPPPPPPPPPХPPPPPPPPPPPPPPPPPPP:hhhhhhhhhhPPPPPPPPPPPPPPPP PPP;PPPPPPPPPPPPPPPPͧPmPQP&PȠPPPPPPPP q Quit h/?/F1 Show this window UP/DOWN/PGUP PGDN/SPACE Navigate q/ESC/CTRL+C Exit browser or go back to previous screen For multiple event sessions: TAB/UNTAB Switch events For symbolic views (--sort has sym): ENTER Zoom into DSO/Threads & Annotate current symbol ESC Zoom out + Expand/Collapse one callchain level a Annotate current symbol C Collapse all callchains d Zoom into current DSO e Expand/Collapse main entry callchains E Expand all callchains F Toggle percentage of filtered entries H Display column headers k Zoom into the kernel map L Change percent limit m Display context menu S Zoom into current Processor Socket P Print histograms to perf.hist.N t Zoom into current Thread V Verbose (DSO names in callchains, etc) z Toggle zeroing of samples f Enable/Disable events / Filter symbol by name h/?/F1 Show this window UP/DOWN/PGUP PGDN/SPACE Navigate q/ESC/CTRL+C Exit browser or go back to previous screen For multiple event sessions: TAB/UNTAB Switch events For symbolic views (--sort has sym): ENTER Zoom into DSO/Threads & Annotate current symbol ESC Zoom out + Expand/Collapse one callchain level a Annotate current symbol C Collapse all callchains d Zoom into current DSO e Expand/Collapse main entry callchains E Expand all callchains F Toggle percentage of filtered entries H Display column headers k Zoom into the kernel map L Change percent limit m Display context menu S Zoom into current Processor Socket i Show header information P Print histograms to perf.hist.N r Run available scripts s Switch to another data file in PWD t Zoom into current Thread V Verbose (DSO names in callchains, etc) / Filter symbol by name 0-9 Sort by event n in group h/?/F1 Show this window UP/DOWN/PGUP PGDN/SPACE LEFT/RIGHT Navigate q/ESC/CTRL+C Exit browser Usage: %14s: %s # Running %s/%s benchmark... # Running '%s/%s' benchmark: --help Unknown collection: '%s' default|simple repeat sched Scheduler and IPC benchmarks System call benchmarks Memory access benchmarks futex Futex stressing benchmarks epoll Epoll stressing benchmarks internals Perf-internals benchmarks Breakpoint benchmarks uprobe uprobe benchmarks All benchmarks trace_printk enable Run all breakpoint benchmarks kallsyms-parse Benchmark kallsyms parsing inject-build-id Benchmark build-id injection evlist-open-close pmu-scan Run all futex benchmarks wake-parallel lock-pi memcpy find_bit basic getpgid Benchmark for fork(2) calls execve Benchmark for execve(2) calls Run all syscall benchmarks messaging seccomp-notify Run all scheduler benchmarks Benchmark for NUMA workloads Run all NUMA benchmarks %10d %10d %10d %*s%s %s %*s} Annotate data type stats: no_sym %10d : %s no_insn no_insn_ops no_mem_ops no_reg no_dbginfo no_cuinfo no_var no_typeinfo invalid_size bad_offset Instruction Annotate %s stats Bad Good %-10s: %5s %5s %-10s: %5d %5d struct union event[%d] = %s %*s %10s %10s %s hist_entry__gtk_annotate GTK browser not found! dso,type input input file name dsos dso[,dso...] symbol to annotate don't complain, do it quiet dump-raw-trace dump raw trace in ASCII tui Use the TUI interface stdio Use the stdio interface stdio2 ignore-vmlinux vmlinux pathname print-line full-paths skip-missing list of cpus to profile symfs asm-raw disassembler-style disassembler style prefix-strip Enable symbol demangling demangle-kernel show-total-period show-nr-samples stdio-color always percent-type local-period percent data-type type-stat insn-stat The %s data has no samples! perf_gtk__show_annotations perf annotate [<options>] HOME %s/.perfconfig system Error: takes no arguments %s.%s=%s %s: strdup failed invalid config variable: %s Failed to add '%s=%s' %s = %s show current config variables use system config file use user config file %%%d.2f%%%% %s/%d diff.order diff.compute delta delta-abs wdiff Invalid compute method: %s ± %s%5.1f%% %s %6.2f%% %+4.2F%% %14.6F %.0F / %.0F (%lu * %ld) - (%lu * %ld) [%s -> %s] %4ld [%7lx -> %7lx] %4ld %%%d.6f %%14ld %%%+d.2f%%%% perf.data.host perf.data.guest Order option out of limit. Failed to open %s srcline,symbol,dso Memory allocation failed Invalid time string Failed to process %s %s# Event '%s' # # Data files: (Baseline) # [%d] %s %s perf.data.old baseline-only Show period values. formula Show formula. cycles-hist kallsyms pathname comms comm[,comm...] symbol[,symbol...] only consider these symbols sort key[,key2...] field-separator Specify compute sorting. relative|absolute pid[,pid...] tid[,tid...] stream Baseline Period Base period Delta Ratio Weighted diff Formula Delta Abs stddev/Hist Input file name Show the sample frequency Show all event attr details Show event group information trace-fields Show tracepoint fields perf evlist [<options>] nosleep-time noirqs irq-info cannot get tracing file: %s failed to allocate cpu mask tracing_cpumask ftrace. ftrace.tracer function_graph Filter parse error at %td. Source: "%s" %*c available_filter_functions cannot open tracing file: %s tracing_on nop current_tracer set_ftrace_pid max_graph_depth tracing_thresh set_ftrace_filter set_ftrace_notrace set_graph_function set_graph_notrace function-fork options/%s func_stack_trace funcgraph-irqs funcgraph-proc funcgraph-abstime latency-format invalid graph depth: %d failed to set graph depth buffer_size_kb failed to set tracing thresh failed to set ftrace pid s ftrace only works for %s! failed to reset ftrace trace_pipe failed to open trace_pipe can't enable tracing workload failed: %s No data found GRAPH DURATION # %14s | %10s | %-*s | %s tracer is used func Trace on existing process id Be more verbose all-cpus List of cpus to monitor [FILTER] notrace-funcs Do not trace given functions func-opts nograph-funcs graph-opts Trace children processes use-nsec Use nano-second histogram help.format web unrecognized help format '%s' man.viewer man. .path woman konqueror .cmd emacsclient kfmclient failed to exec '%s': %s Failed to start emacsclient. (woman "%s") -e DISPLAY man:%s(1) newTab -c /bin/sh '%s': unknown man viewer. %-*s print all available commands show man page show manual in web browser show info page buildid-list bench timechart kmem inject Usage: %s perf commands usage: %s %s perf-%s PERF_MAN_VIEWER MANPATH share/man %s:%s Unable to setup man path share/info INFOPATH perfman share/doc/perf-doc %s/perf.html %s/%s.html help.browser web--browse %s %16lx %16lx with-hits Show only DSOs with hits Show current kernel build id kernel-maps be more verbose perf buildid-list [<options>] buildid-cache.debuginfod [kernel.kcore] %s/%s/modules same kcore found in %s %s/%s/%s/%s file list file(s) to add kcore file to add file(s) to remove purge purge-all purge all cached files list all cached files file(s) to update debuginfod urls target-ns -l is exclusive. Failed to get buildids: -%d %s already in the cache Couldn't add %s: %s %s wasn't in the cache Couldn't remove %s: %s Ok Purging %s: %s Purged all: %s Couldn't update %s: %s Couldn't add %s Updating %s %s: %s Removing %s (%s): %s Removing %s %s: %s Adding %s %s: %s Couldn't read /proc/kallsyms %s: not found [ %*s %s%.*s %s. Unit: %s %s Unit: %s %s: %s OR %s default_core Metric Groups: Metrics: %s: [%s] \n %s{ "MetricGroup": "%S" %s "MetricName": "%S" %s "MetricExpr": "%S" %s "MetricThreshold": "%S" %s "ScaleUnit": "%S" %s "BriefDescription": "%S" %s "PublicDescription": "%S" "Unit": "%S" %s "Topic": "%S" %s "EventName": "%S" %s "EventAlias": "%S" %s "EventType": "%S" %s "Deprecated": "%S" %s "Encoding": "%S" raw-dump Dump raw events long-desc output file name deprecated Print deprecated events. cputype PMU name Enable debugging output hwcache metricgroup metricgroups *%s* threads_spec: %s Invalid synth option: %s record.build-id no-cache record.call-graph call-graph.record-mode record.aio record.debuginfod Couldn't synthesize cpu map. callchain: type %s callchain: disabled Failed to allocate CPUs mask Failed to init cpu mask Failed to allocate full mask Empty maps mask: %s Empty affinity mask: %s Intersecting maps mask: %s thread_masks[%d]: nr_threads: %d [ perf record: Dump %s.%s ] .<timestamp> %s/proc/kcore Couldn't run the workload! failed to mmap with %d (%s) %s/proc ERROR: Failed to copy kcore Failed to start threads: %s threads[%d]: sent %s Events disabled Events enabled perf record has started Failed to switch to new file written=%lu read LOST count failed (%lu samples) cycles:P cycles:Pu No such process no BUILD_BPF_SKEL=1 off-cpu switch-output Failed to allocate NUMA spec threads_spec[%d]: %s maps mask: %s affinity mask: %s nr_cblocks: %d mmap flush: %d comp level: %d DWARF LBR event filter exclude-perf realtime no-buffering list of cpus to monitor event period to sample no-inherit tail-synthesize use overwrite mode no-bpf-event do not record bpf events strict-freq freq or 'max' profile at this frequency mmap-pages pages[,pages] mmap-flush number enables call-graph recording record_mode[,record_size] per thread counts Record the sample addresses code-page-size Record the sample cpu sample-identifier Record the sample identifier Record the sample timestamps Record the sample period no-samples don't sample no-buildid-cache no-buildid copy /proc/kcore user to profile branch-any branch any sample any taken branches branch-filter branch filter mask branch stack filter modes per-thread use per-thread mmaps intr-regs any register user-regs running-time aux-sample sample AUX area namespaces Record namespaces events all-cgroups Record cgroup events Record context switch events kernel-callchains collect kernel callchains user-callchains collect user callchains buildid-mmap Record build-id in map events timestamp-filename timestamp-boundary switch-output-event switch output event switch-max-files dry-run Parse options then exit node|cpu compression-level max-size num-thread-synthesize no|all|task|mmap|cgroup Enable off-cpu analysis switch_output_trigger auxtrace_snapshot_trigger undefined package UNDEFINED report.group report.percent-limit report.children report.queue-size report.sort_order report.skip-empty time quantum cannot be 0 %8d %8d %8d |%*s disable-order total-cycles show-on-off-events switch-off switch-on time-quantum time (ms|us|ns|s) socket-filter stitch-lbr show-ref-call-graph full-source-path branch-history branch-stack group-sort-idx show-info hide-unresolved column-widths width[,width...] symbol-filter regex inverted max-stack exclude-other parent showcpuutilization show-cpu-utilization header-only pretty perf report [<options>] normal sort by key(s): Display event stats Display recorded tasks Show data header. Show only data header. key[,keys...] alias for inverted call graph ignore-callees Disable symbol demangling mem access profile Show entries in a hierarchy Show inline function Show times in nanosecs Disable raw trace ordering ipc ipc_lbr ipc_null failed to set cpu bitmap arm_spe failed to process sample # %8s %8s %8s %s failed to process hist entry Merging related events... Sorting events for output... share/doc/perf-tip evlist__gtk_browse_hists # Samples: %lu%c of event%s '%s' (time slices: %s) call-graph=no , show reference callgraph # Total weight : %lu # Sort order : %s # Event count (approx.): %lu # Processor Socket: %d # # (%s) # failed to read counter %s failed to process counter %s cannot build %s map failed to write stat event %s: %d: %lu %lu %lu stats double allocation cannot allocate aggr counts Perf session creation failed per-socket per-die per-cache cache level per-core per-node no-aggr disable CPU count aggregation log-fd failed to create output file # started on %s Failed opening logfd interval-clear duration_time failed to setup -r option for-each-cgroup Missing transaction metrics devices/cpu/freeze_on_smi Failed to set freeze_on_smi. Missing smi metrics stalled-cycles-frontend stalled-cycles-backend Default failed to parse CPUs map %s: %s interval-count timeout must be >= 10ms. failed to prepare workload reopening weak %s Workload failed: %s perf stat report [<options>] perf stat record [<options>] none unset detailed hybrid-merge json-output print counts in JSON format expand events for each cgroup append append to the output file pre post interval-print aggregate counts per thread metric-only metric-no-group metric-no-merge metric-no-threshold topdown measure top-down statistics td-level smi-cost measure SMI cost metric/metric group list percore-show-thread hybrid cpu type iostat %s: failed to process events [unknown] modules Can't parse sample, err = %d top.call-graph top.children Couldn't annotate %s: %s perf-top-UI yes [H[2J %-*.*s [31m Showing %s for %s Events Pcnt (>=%d%%) Mapped keys: [S] stop annotation. [qQ] quit. Enter display delay Enter display entries (lines) Available events: Enter details event counter %d %s exiting. Enter details symbol Sorry, %s is not active. hide_user_symbols sym-annotate symbol name count-filter dump-symtab number of mmap data pages hide_kernel_symbols hide kernel symbols zero history across updates display this many functions hide user symbols perf top [<options>] Failed to mmap with %d (%s) xed -F insn: -A -64 | less xed -F insn: -A -64 description: args: ENA record -R DATA_SRC WEIGHT IREGS UREGS PHYS_ADDR DATA_PAGE_SIZE CODE_PAGE_SIZE WEIGHT_STRUCT cannot resolve %lx-%lx BPF output: %17s %04x: %02x Invalid field requested. crewp cewp |%-8d %.*s +insn,-event,-period +disasm,-event,-period Only accept raw|disasm i0nse %+d ABORT INTX MISPRED PRED %016lx %-30s ilen: %d #%s%s%s%s %d cycles [%d] %.2f IPC /%c/%c/%c/%d/%s/%s :-1 VM:%5d VCPU:%03d %8.8s %16s %7d/%-7d %7d %3d [%03d] disabled %F %H:%M:%S %s.%09lu %s.%06lu %5lu.%09llu: %12s: metric: ABI:%lu %5s:0x%lx %s.%s.dump %s/scripts %s/%s/bin -report %-36s %s %s/scripts/%s/%s invalid language specifier invalid script extension %-42s [%s] %d: %lx-%lx patching up to %lx-%lx %016lx %s ilen: %d ... not reaching sample ... ilen: %d insn: vmexit jcc iret sysret hw int tx abrt tr strt tr end vmentry (%s%s%s) %-15s%6s tr strt %-7s%6s tr end %-7s%6s via unknown %10lu %*s: %-21s ) %*s%s %*s%16lx IPC: %u.%02u (%lu/%lu) IP: %u payload: %#lx %s hints: %#x extensions: %#x IP: %u cbr: %2u freq: %4u MHz (%3u%%) psb offs: %#lx SMI RSM SIPI VMEXIT VMEXIT_INTR UINTR UIRET PFA VMXQ VMXR cfe: %s IP: %d vector: %u cfe: %u IP: %d vector: %u %s: %#lx EVD_%u: %#lx IFLAG: %d->%d %s branch %16lx %s %16lu %16u BPF string: %17s "%s" top. %s/bin/%s-record dump-unsorted-raw-trace list available scripts list-dlfilters list available dlfilters gen-script dlfilter filter .so file name dlarg filter argument debug-mode hide-call-graph addr-range insn-trace raw|disasm call-trace Decode calls from itrace call-ret-trace graph-function stop-bt reltime deltatime show-kernel-path show-task-events show-mmap-events Show the mmap events show-switch-events show-namespace-events show-cgroup-events show-lost-events show-round-events show-bpf-events show-text-poke-events per-event-dump max-blocks guestmount guestvmlinux file saving guest os vmlinux guestkallsyms guestmodules guest-code perf script [<options>] failed to create pipe failed to fork -a -q -o x86_64 i386 failed to open file failed to stat file perf-script Misordered timestamps: %lu perf script stopped dsoff iregs uregs brstack brstacksym data_src bpf-output callindent brstackinsn brstackoff phys_addr misc tod code_page_size brstackinsnlen machine_pid vcpu Failed to allocate kvm info %s.%06ld 00:00:00.000000 Analyze events for all VMs, pid(s) %s, all VCPUs: VCPU %d: Samples %10s Samples% Time% Min Time %11s Max Time Avg time %10llu %8.2f%% %9.2fus %9.2fus ( +-%7.2f%% ) Lost events: %lu %s: Not enough memory %.2F%% Invalid field key: '%s' UNKNOWN Output file name Collect guest os data Collect host os data perf.data.kvm # Available commands: record: record kvm events sort-key report event -m 1024 vcpu id to report use the stdio interface Invalid vcpu:%d. ev_name max_t min_t mean_t Unsupported sort key: %s kvm record Failed to look up CPU type CPU %s is not supported. Sorting... ? - help live display timerfd_create failed timerfd_settime failed: %d Failed to parse sample Failed to enqueue sample: %d Failed to read timer fd: %d Missed timer beats: %lu percent_sample Sample% percent_time Mean Time (ns) Min Time (ns) Max Time (ns) Event name [vdso] CPU %u/KVM Invalid VCPU %u //anon /dev/zero /anon_hugepage [stack /SYSV [heap] no build_id found for %s Bad id_hdr_size %u Bad event size %u No evsel for id %lu Bad id sample size %d Bad new event size %u Failed to find guest id %lu Failed to add guest attr. known-build-ids sched-stat jit vm-time-correlation guest-data perf inject [<options>] sched:sched_switch sched:sched_process_exit sched:sched_stat_ Guest data has no sample IDs Failed to flush guest events Failed to copy guest kcore %d%s%d%s0x%lx%s0x%lx%s %lu%s0x%lx%s%s:%s %5lu%s0x%06lx%s%s:%s ??? 0x%016lx%s dump-raw-samples dump raw samples in ASCII ldlat collect only user level data -W --phys-data --data-page-size --all-user --all-kernel -C calling: record # PID, TID, IP, ADDR, PHYS ADDR, DATA PAGE SIZE, LOCAL WEIGHT, DSRC, SYMBOL --mem-mode -n ,phys_daddr ,data_page_size store You must specify --to-json. Unknown command: %s to-json Convert to JSON format Convert all events perf data convert [<options>] perf version %s dwarf %22s: [ %-3s [32m HAVE_DWARF_SUPPORT # %s dwarf_getlocations syscall_table HAVE_SYSCALL_TABLE_SUPPORT libbfd HAVE_LIBBFD_SUPPORT HAVE_DEBUGINFOD_SUPPORT HAVE_LIBELF_SUPPORT libnuma HAVE_LIBNUMA_SUPPORT numa_num_possible_cpus libperl HAVE_LIBPERL_SUPPORT libpython HAVE_LIBPYTHON_SUPPORT libslang HAVE_SLANG_SUPPORT libcrypto HAVE_LIBCRYPTO_SUPPORT libunwind HAVE_LIBUNWIND_SUPPORT libdw-dwarf-unwind zlib HAVE_ZLIB_SUPPORT lzma HAVE_LZMA_SUPPORT get_cpuid HAVE_AUXTRACE_SUPPORT HAVE_LIBBPF_SUPPORT HAVE_AIO_SUPPORT zstd HAVE_ZSTD_SUPPORT libpfm4 HAVE_LIBPFM libtraceevent HAVE_LIBTRACEEVENT bpf_skeletons HAVE_BPF_SKEL perf version [<options>] build-options display the build options setup mem-loads latency --sample-cpu calling: Cacheline 0x%lx Invalid --fields key: `%s' Unknown --fields key: `%s' WARNING: failed to find node WARNING: no sample cpu value %21s %2d{%2d %5.1f%% n/a %5.1f%%} %6s} %2d{ %*u %6.0f builtin-c2c.c assertion failed at %s:%d cl_srcline, dso, symbol, mean_rmt_peer,mean_lcl_peer, iaddr, mean_rmt,mean_lcl, tid, cl_num_empty, tot_hitm rmt_hitm,lcl_hitm lcl_hitm,rmt_hitm tot_peer Data address Double-Cacheline Double-CL the input file to process node-info full-symbols no-source show-all Show all captured HITM lines. Switch HITM output type tot,lcl,rmt,peer coalesce coalesce fields double-cl Error creating perf session arm64 tot offset,%s unrecognized sort token: %s %s%s%s%s%s%s%s%s%s%s%s%s mean_load,tot_recs,cpucnt, coalesce sort fields: %s coalesce resort fields: %s coalesce output fields: %s dcacheline Failed to initialize hists node/cpu topology bug Failed setup nodes failed to setup UI Events %-36s: %s failed to setup sort entries Node{cpu list} Node{cpus %peers %stores} Node{cpus %hitms %stores} Node Num cl_num_empty cl_num Index cl_idx cpucnt lcl peer mean_lcl_peer ---------- cycles ---------- rmt peer mean_rmt_peer mean_load lcl hitm mean_lcl rmt hitm mean_rmt Shared Tid Pid Rmt dram_rmt --- Load Dram ---- Lcl dram_lcl percent_stores_na L1 Miss percent_stores_l1miss ------- Store Refs ------ L1 Hit percent_stores_l1hit percent_lcl_peer -- Peer Snoop -- percent_rmt_peer LclHitm percent_lcl_hitm ----- HITM ----- RmtHitm percent_rmt_hitm percent_costly_snoop Tot Peer Total Loads tot_loads records tot_recs - RMT Load Hit -- RmtHit ld_rmthit - LLC Load Hit -- LclHit ld_lclhit ld_l2hit ld_l1hit ----- Core Load Hit ----- ld_fbhit cl_stores_na cl_stores_l1miss cl_stores_l1hit L1Miss --------- Stores -------- L1Hit Stores tot_stores cl_lcl_peer ----- Peer ----- cl_rmt_peer cl_lcl_hitm cl_rmt_hitm Remote Local ------- Load Peer ------- ------- Load Hitm ------- Code address offset_node --- Data address - Off PA cnt dcacheline_count dcacheline_node --- Cacheline ---- cl_srcline perf c2c report perf c2c {record|report} Local HITMs Remote HITMs Total HITMs Peer Snoop daemon.base failed: control ack timeout ack failed: read ack %d %s/lock failed: write failed: ftruncate failed: realpath failed: socket %s/control failed: connect failed to read signal fd failed: poll failed: base not defined failed: fdopen session- config file path base directory field separator foreground stay on console failed: config not found reconfig: started failed: chdir failed: open failed: fcntl FD_CLOEXEC daemon started (pid %d) socket: %s failed: bind failed: listen failed: inotify_init config file: %s, dir: %s failed: inotify_add_watch %s/session-%s failed: asprintf failed: mkdir failed: open /dev/null failed: open session output failed: create control fifo failed: create ack fifo failed: accept failed: read daemon %d%c%s%c%s%c%s/%s %c%lu [%d:daemon] base: %s output: %s/%s lock: %s/lock up: %lu minutes %d%c%s%c%s %c%s/%s%c%s/%s [%d:%s] perf record %s base: %s control: %s/%s ack: %s/%s perf daemon is exciting %-4s %s %-4s %s (not found) failed to wait for sessions daemon exited Ping to specific session failed: unknown command '%s' perf daemon [<options>] %s: memdup failed Unknown slab --sort key: '%s' Unknown page --sort key: '%s' Invalid regex: %s %s cannot load kernel map alloc func: %s call_site bytes_req bytes_alloc %s: malloc failed kmem.default slab ... thread: %s:%d gfp_flags migratetype pfn gfp_flags= unknown callsite: %lx skipping alloc function: %s Callsite Alloc Ptr %-34s | %s+%lx Live PFN Page caller show per-callsite statistics show n lines raw-ip show raw ip instead of symbol Analyze slab allocator Analyze page allocator Show live page stat kmem:kmalloc kmem:kfree kmem:kmem_cache_alloc kmem:kmem_cache_free kmem:kmalloc_node kmem:kmem_cache_alloc_node kmem:mm_page_alloc kmem:mm_page_free -g frag,hit,bytes bytes,hit page,order,migtype,gfp callsite,order,migtype,gfp kmem record SUMMARY (SLAB allocator) ======================== Total bytes requested: %'lu Total bytes allocated: %'lu Total bytes freed: %'lu Internal fragmentation: %f%% # GFP flags # --------- # %08x: %*s: %s %.105s SUMMARY (page allocator) Total allocation requests Total free requests Total alloc+freed requests Total alloc-only requests Total free-only requests Total allocation failures Movable Reclaimable Unmovable Order CMA/Isolated Reserved %5d %'12d %12c UNMOVABL CMA/ISLT GFP_TRANSHUGE THP GFP_TRANSHUGE_LIGHT THL GFP_HIGHUSER_MOVABLE HUM GFP_HIGHUSER HU GFP_USER GFP_KERNEL_ACCOUNT KAC GFP_KERNEL GFP_NOFS NF GFP_ATOMIC GFP_NOIO NI GFP_NOWAIT NW GFP_DMA __GFP_HIGHMEM HM GFP_DMA32 D32 __GFP_HIGH __GFP_IO __GFP_FS __GFP_NOWARN NWR __GFP_RETRY_MAYFAIL __GFP_NOFAIL __GFP_NORETRY NR __GFP_COMP __GFP_ZERO __GFP_NOMEMALLOC NMA __GFP_MEMALLOC __GFP_HARDWALL HW __GFP_THISNODE __GFP_RECLAIMABLE __GFP_MOVABLE __GFP_ACCOUNT __GFP_WRITE __GFP_RECLAIM __GFP_DIRECT_RECLAIM __GFP_KSWAPD_RECLAIM KR (s)%s:%lu Capture signal %d common_pid prev_pid prev_comm next_pid next_comm irq, softirq, workqueue Unknown --event key: `%s' Config event list: Invalid report type %d Invalid cpu bitmap Invalid time span Runtime end Runtime start Delaytime Kwork name Cpu (TYPE)NAME:NUM Unknown --sort key: `%s' Sort order: %s (w)%s (w)0x%lx vec Failed to copy symbol name Kwork Name Sorting %s ... Total Runtime Avg delay Count Max runtime start Max runtime %-*s | %-*s | %-*s | Max runtime end Max delay start Max delay Max delay end %.*s %0*d | %*.*f ms | %*lu | %*.*f ms | %*s s | %*s s | %lu %s%s INFO: use %lld atom pages Failed to zalloc kwork work %*s [%0*d] %-*s %*.*f __softirqentry_text_start __do_softirq SPID event name to profile kwork with-summary Show summary with statistics perf kwork report [<options>] perf kwork top [<options>] timehist record comm: sched, irq, softirq Total : %*.*f ms, %d cpus %%Cpu%-*d[%.*s%.*s %*.*f%%] %*s %s%*s%s %*s %*s %-*s RUNTIME %CPU %*lu %*.*f ms %s%s%s avg irq:softirq_raise irq:softirq_entry irq:softirq_exit irq:irq_handler_entry irq:irq_handler_exit rwlock:R rwlock:W rwsem:R rwsem:W rwlock-rt:R rwlock-rt:W pcpu-sem:R pcpu-sem:W mutex-spin semaphore spinlock rwlock rt-mutex rwlock-rt percpu-rwsem Unknown lock flags: %s Failed to create cgroup: %s Memory allocation failure invalid max stack depth: %s invalid max stack depth: %ld Cannot open %s Unknown output field: %s %*llu === output for debug === bad: %d, total: %d bad rate: %.2f %% %10s: %d h %*.2f %s %*llu %s memory allocation failed invalid BPF map length: %s lock record Unknown compare key: %s Thread ID %10s: comm %10d: %s %#llx: %s Unknown type of information %20s lock_addr Invalid aggregation mode: %d lockdep_addr powerpc Unknown ignore unknown symbol: %s memory allocation failure %s+%#lx lock:contention_end lock:contention_begin dump thread list in perf.data combine-locks show per-thread lock stats wait_total use-bpf map-nr-entries Max number of BPF map entries stack-skip lock-addr show lock stats by address type-filter Filter specific type of locks lock-filter ADDRS/NAMES callstack-filter lock-owner lock-cgroup show lock stats by cgroup cgroup-filter CGROUPS Filter specific cgroups perf lock info [<options>] contention perf lock report [<options>] --synth lock:lock_acquire lock:lock_acquired lock:lock_contended lock:lock_release --call-graph fp,8 # output: %s%s %s%s %s stacktrace %s%s %s%s %s %10s %s %16s %s %d%s %s %llx%s %s%s %s %s %#lx %s %10s %s %10d %s %016llx %s (%s) %#lx %s # debug: total=%d%s bad=%d %s bad_%s=%d histogram of failure reasons total wait wait_max max wait wait_min min wait avg_wait avg wait (due to lost events?) kernel/pid_max fork event ... parent: %s/%d ... child: %s/%d %15s lost %llu events on cpu %d sched:sched_stat_runtime sched:sched_wakeup sched:sched_waking sched:sched_wakeup_new sched:sched_migrate_task Error creating perf session %s[%d/%d] <- Non memory at %s %*s %5d %9lu %*lu.%03lu %5.2f %5lu No memory at %s sched_wakeup event %p ... pid %d woke up %s/%d <unknown> prev_state sched_switch event %p hm, delta: %lu < 0 ? %15s [%04d] %9s %9s %9s awakened: %s orig_cpu dest_cpu migrated: %s cpu %d => %d [34m [41m swapper %2s %12s secs %s => %s:%d (CPU %d) __schedule preempt_schedule %5c next: %s[%d] in-event: Internal tree error RSDTtZXxKWP CPU to profile on compact map output in compact mode color-pids highlight given pids in map color-cpus highlight given CPUs in map display given CPUs in map wakeups Show wakeup events next Show next task Show migration events cpu-visual Add CPU visual idle-hist Show idle events only perf sched replay [<options>] perf sched map [<options>] replay sched:sched_process_fork sched:sched_stat_wait sched:sched_stat_sleep sched:sched_stat_iowait %s:(%d) %s:%d the run test took %lu nsecs nr_run_events: %ld nr_sleep_events: %ld nr_wakeup_events: %ld target-less wakeups: %ld multi-target wakeups: %ld run atoms optimized: %ld #%-3ld: %0.3f, ravg: %0.2f, cpu: %0.2f / %0.2f (%ld sleep corrections) %15s %6s sch delay wait time %-*s %9s %9s %9s run time %15s %-6s [tid/pid] %5s %.15s %.6s %.*s %.*s %.9s %.9s %.9s %.5s Idle-time summary %*s parent sched-out Wait-time summary %*s parent sched-in Runtime summary %*s (count) %.117s <no still running tasks> Idle stats: CPU %2d idle for msec (%6.2f%%) (x %d) Idle stats by callchain: CPU %2d: msec Callchains Idle time (msec) %16s %8s %s %.16s %.8s %.50s %8d %lu%cs open_memstream error ..... %016lx %s ..... %016lx Invalid pidcomm! problem building topology common_flags disk output.svg power-only output power data only tasks-only output processes data only page width highlight duration or task name proc-num min. number of tasks to print io-skip-eagain skip EAGAIN errors io-min-time io-merge-dist io-only record only IO data record callchain syscalls:sys_enter_read syscalls:sys_enter_pread64 syscalls:sys_enter_readv syscalls:sys_enter_preadv syscalls:sys_enter_write syscalls:sys_enter_pwrite64 syscalls:sys_enter_writev syscalls:sys_enter_pwritev syscalls:sys_enter_sync syscalls:sys_enter_fsync syscalls:sys_enter_msync syscalls:sys_exit_read syscalls:sys_exit_pread64 syscalls:sys_exit_readv syscalls:sys_exit_preadv syscalls:sys_exit_write syscalls:sys_exit_pwrite64 syscalls:sys_exit_writev syscalls:sys_exit_pwritev syscalls:sys_exit_sync syscalls:sys_exit_fsync syscalls:sys_exit_msync syscalls:sys_enter_recvfrom syscalls:sys_enter_recvmmsg syscalls:sys_enter_recvmsg syscalls:sys_enter_sendto syscalls:sys_enter_sendmsg syscalls:sys_enter_sendmmsg syscalls:sys_exit_recvfrom syscalls:sys_exit_recvmmsg syscalls:sys_exit_recvmsg syscalls:sys_exit_sendto syscalls:sys_exit_sendmsg syscalls:sys_exit_sendmmsg syscalls:sys_enter_epoll_wait syscalls:sys_enter_poll syscalls:sys_enter_ppoll syscalls:sys_enter_pselect6 syscalls:sys_enter_select syscalls:sys_exit_epoll_pwait syscalls:sys_exit_epoll_wait syscalls:sys_exit_poll syscalls:sys_exit_ppoll syscalls:sys_exit_pselect6 syscalls:sys_exit_select --filter power:cpu_frequency power:cpu_idle power:power_start power:power_end power:power_frequency timechart record process3 %s:%i (%3.1f %sbytes) %s:%i (%2.2fs) %s:%i (%3.1fms) [%i] EPERM ENOENT ESRCH EINTR ENXIO E2BIG ENOEXEC EBADF ECHILD EAGAIN ENOMEM EACCES EFAULT ENOTBLK EBUSY EEXIST EXDEV ENODEV ENOTDIR EISDIR EINVAL ENFILE EMFILE ENOTTY ETXTBSY EFBIG ENOSPC ESPIPE EROFS EMLINK EPIPE EDOM ERANGE EDEADLK ENAMETOOLONG ENOLCK ENOSYS ENOTEMPTY ELOOP ENOMSG EIDRM ECHRNG EL2NSYNC EL3HLT EL3RST ELNRNG EUNATCH ENOCSI EL2HLT EBADE EBADR EXFULL ENOANO EBADRQC EBADSLT EBFONT ENOSTR ENODATA ETIME ENOSR ENONET ENOPKG EREMOTE ENOLINK EADV ESRMNT ECOMM EPROTO EMULTIHOP EDOTDOT EBADMSG EOVERFLOW ENOTUNIQ EBADFD EREMCHG ELIBACC ELIBBAD ELIBSCN ELIBMAX ELIBEXEC EILSEQ ERESTART ESTRPIPE EUSERS ENOTSOCK EDESTADDRREQ EMSGSIZE EPROTOTYPE ENOPROTOOPT EPROTONOSUPPORT ESOCKTNOSUPPORT EOPNOTSUPP EPFNOSUPPORT EAFNOSUPPORT EADDRINUSE EADDRNOTAVAIL ENETDOWN ENETUNREACH ENETRESET ECONNABORTED ECONNRESET ENOBUFS EISCONN ENOTCONN ESHUTDOWN ETOOMANYREFS ETIMEDOUT ECONNREFUSED EHOSTDOWN EHOSTUNREACH EALREADY EINPROGRESS ESTALE EUCLEAN ENOTNAM ENAVAIL EISNAM EREMOTEIO EDQUOT ENOMEDIUM EMEDIUMTYPE ECANCELED ENOKEY EKEYEXPIRED EKEYREVOKED EKEYREJECTED EOWNERDEAD ENOTRECOVERABLE ERFKILL EHWPOISON (unknown) EDEADLOCK EINIT EREMDEV ECANCELLED EPROCLIM ERREMOTE UNTRACED CONTINUED %s%#x NOHANG SOCK_ STREAM DGRAM RDM SEQPACKET DCCP |%s NONBLOCK |%#x SECCOMP_FILTER_FLAG_ TSYNC SECCOMP_SET_MODE_ STRICT SCHED_ NORMAL ISO IDLE DEADLINE RESET_ON_FORK |%s%s MSG_ PEEK DONTROUTE CTRUNC PROBE DONTWAIT EOR WAITALL FIN SYN CONFIRM ERRQUEUE NOSIGNAL MORE WAITFORONE ZEROCOPY SPLICE_PAGES FASTOPEN CMSG_CLOEXEC OOB PERF_ FD_OUTPUT PID_CGROUP FD_NO_GROUP %s%s: %s MADV_%s HUP QUIT TRAP ABRT BUS FPE USR1 SEGV USR2 TERM CHLD CONT TSTP TTIN TTOU URG XCPU XFSZ VTALRM PROF WINCH PWR STKFLT GRND_ RANDOM FUTEX_ WAKE CMP_REQUEUE CMP_REQUEUE_PI WAKE_OP UNLOCK_PI TRYLOCK_PI WAIT_BITSET WAKE_BITSET WAIT_REQUEUE_PI PRIVATE_FLAG CLOCK_REALTIME "%.*s" EFD_ SEMAPHORE _OK F%s "%-.*s" IALLUGO IRWXUGO IRUGO IWUGO IXUGO IFMT IFSOCK IFLNK IFREG IFBLK IFDIR IFCHR IFIFO ISUID ISGID ISVTX IRWXU IRUSR IWUSR IXUSR IRWXG IRGRP IWGRP IXGRP IRWXO IROTH IWOTH IXOTH maj trace.add_events Not enough memory for %s trace.show_timestamp trace.show_duration trace.show_arg_names trace.show_zeros trace.show_prefix trace.no_inherit trace.args_alignment trace.tracepoint_beautifiers libbeauty __syscall_nr %s@ %s+0x%lx const char * pid_t umode_t share/perf-core/strace/groups Skipping unknown syscalls: sys_enter_%s exit_group %sNONE FUTEX_BITSET_ MATCH_ANY %#xd LOST %lu events! Summary of events: %s (%d), %lu events, , %lu majfaults , %lu minfaults , %.3f msec %-15s %8lu %6lu %9.3f %9.3f %9.3f %9.3f %9.2f%% %s: %d %10.3f ? %6.3f ms [33m %.14s/ arg%d: /proc/%d/fd/%d /proc/%d/task/%d/fd/%d /* %s??? */ raw_syscalls %22s %10.3f %s %d/%d [%d] ... [ continued ]: %s() )%*s= -1 %s (%s) 0 (Timeout) vruntime AT_FD CWD %sfault [ ] => (%c%c) ( ): sys_enter_ %*s= ? alpha mips parisc sparc x86 RDONLY RDWR APPEND CREAT DIRECT DIRECTORY LARGEFILE TMPFILE NOATIME NOCTTY DSYNC WRONLY expr tool_stats show tool stats Analyze events in file filter-pids CSV list of pids float errno-summary all|maj|min Trace pagefaults Trace syscalls libtraceevent_print kernel-syscall-graph max-events min-stack sort-events print-sample Not enough memory to run! raw_syscalls:sys_exit syscalls:sys_exit_ raw_syscalls:sys_enter major-faults minor-faults %s.old probe:vfs_getname sys_(enter|exit) probe:vfs_getname* sshd gnome-terminal errno=%d,%s %.*s%s%s out of memory! =<>! New filter for %s: %s SEQUENTIAL WILLNEED DONTNEED DONTFORK DOFORK UNMERGEABLE NOHUGEPAGE DONTDUMP DODUMP WIPEONFORK KEEPONFORK COLD PAGEOUT POPULATE_READ POPULATE_WRITE DONTNEED_LOCKED COLLAPSE SOFT_OFFLINE vector arch_prctl brk clock_gettime clock_nanosleep clone child_stack parent_tidptr child_tidptr tls epoll_ctl eventfd2 fchmodat fchownat fcntl flock fsconfig fsmount fspick newfstat newfstatat futimesat getitimer getpid getppid getrandom getrlimit gettid ioctl kcmp pid1 pid2 idx1 idx2 keyctl lseek newlstat mkdirat mknodat move_mount mq_unlink mremap name_to_handle_at open_by_handle_at pipe2 pkey_alloc pkey_free pkey_mprotect pread prlimit64 pwrite readlinkat renameat renameat2 rt_sigaction rt_sigprocmask rt_sigqueueinfo rt_tgsigqueueinfo sched_setscheduler seccomp sendfile sendfile64 set_tid_address setitimer setrlimit socketpair newstat statx swapoff swapon symlinkat sync_file_range tgkill tkill umount2 umount newuname unlinkat utimensat wait4 waitid MREMAP_ MAYMOVE FIXED DONTUNMAP SHARED PRIVATE ANONYMOUS 32BIT GROWSDOWN DENYWRITE EXECUTABLE NORESERVE POPULATE HUGETLB FIXED_NOREPLACE PROT_ GROWSUP CLOCK_ MONOTONIC PROCESS_CPUTIME_ID THREAD_CPUTIME_ID MONOTONIC_RAW REALTIME_COARSE MONOTONIC_COARSE BOOTTIME REALTIME_ALARM BOOTTIME_ALARM SGI_CYCLE TAI SIG_ UNBLOCK SETMASK RLIMIT_ FSIZE RSS NPROC NOFILE MEMLOCK SIGPENDING MSGQUEUE NICE RTPRIO RTTIME SETLEASE GETLEASE NOTIFY CANCELLK DUPFD_CLOEXEC SETPIPE_SZ GETPIPE_SZ ADD_SEALS GET_SEALS GET_RW_HINT SET_RW_HINT GET_FILE_RW_HINT SET_FILE_RW_HINT DUPFD GETFD SETFD GETFL SETFL GETLK SETLK SETLKW SETOWN GETOWN SETSIG GETSIG GETLK64 SETLK64 SETLKW64 SETOWN_EX GETOWN_EX GETOWNER_UIDS SEEK_ CUR HOLE KEYCTL_ GET_KEYRING_ID JOIN_SESSION_KEYRING REVOKE CHOWN SETPERM DESCRIBE UNLINK SEARCH INSTANTIATE NEGATE SET_REQKEY_KEYRING SET_TIMEOUT ASSUME_AUTHORITY GET_SECURITY SESSION_TO_PARENT REJECT INSTANTIATE_IOV INVALIDATE GET_PERSISTENT ITIMER_ REAL VIRTUAL EPOLL_CTL_ DEL MOD FSCONFIG_ SET_FLAG SET_STRING SET_BINARY SET_PATH SET_PATH_EMPTY SET_FD CMD_CREATE CMD_RECONFIGURE CMD_CREATE_EXCL FSMOUNT_ BPF_ MAP_CREATE MAP_LOOKUP_ELEM MAP_UPDATE_ELEM MAP_DELETE_ELEM MAP_GET_NEXT_KEY PROG_LOAD OBJ_PIN OBJ_GET PROG_ATTACH PROG_DETACH PROG_TEST_RUN PROG_GET_NEXT_ID MAP_GET_NEXT_ID PROG_GET_FD_BY_ID MAP_GET_FD_BY_ID OBJ_GET_INFO_BY_FD PROG_QUERY RAW_TRACEPOINT_OPEN BTF_LOAD BTF_GET_FD_BY_ID TASK_FD_QUERY MAP_LOOKUP_AND_DELETE_ELEM MAP_FREEZE BTF_GET_NEXT_ID MAP_LOOKUP_BATCH MAP_LOOKUP_AND_DELETE_BATCH MAP_UPDATE_BATCH MAP_DELETE_BATCH LINK_CREATE LINK_UPDATE LINK_GET_FD_BY_ID LINK_GET_NEXT_ID ENABLE_STATS ITER_CREATE LINK_DETACH PROG_BIND_MAP CLONE_ FILES PIDFD PTRACE VFORK NEWNS SYSVSEM SETTLS PARENT_SETTID CHILD_CLEARTID DETACHED CHILD_SETTID NEWCGROUP NEWUTS NEWIPC NEWUSER NEWPID NEWNET CLEAR_SIGHAND INTO_CGROUP RDLCK WRLCK UNLCK NB RW MOUNT_ATTR_ RELATIME NOSUID STRICTATIME NODIRATIME IDMAP NOSYMFOLLOW SYMLINK_NOFOLLOW NO_AUTOMOUNT FSPICK_ VHOST_%s (%#x, %#x, %#x) KVM_%s DRM_%s SNDRV_CTL_%s SNDRV_PCM_%s PERF_%s _IOC_ USBDEVFS_%s (%c, %#x, %#x) , %#x, %#x, %#x) REFRESH PERIOD SET_OUTPUT SET_FILTER SET_BPF PAUSE_OUTPUT QUERY_BPF MODIFY_ATTRIBUTES TTSTAMP USER_PVERSION HW_REFINE HW_PARAMS HW_FREE SW_PARAMS HWSYNC SYNC_PTR STATUS_EXT CHANNEL_INFO PREPARE DRAIN REWIND XRUN FORWARD WRITEI_FRAMES READI_FRAMES WRITEN_FRAMES READN_FRAMES TCGETS TCSETS TCSETSW TCSETSF TCGETA TCSETA TCSETAW TCSETAF TCSBRK TCXONC TCFLSH TIOCEXCL TIOCNXCL TIOCSCTTY TIOCGPGRP TIOCSPGRP TIOCOUTQ TIOCSTI TIOCGWINSZ TIOCSWINSZ TIOCMGET TIOCMBIS TIOCMBIC TIOCMSET TIOCGSOFTCAR TIOCSSOFTCAR FIONREAD TIOCLINUX TIOCCONS TIOCGSERIAL TIOCSSERIAL TIOCPKT FIONBIO TIOCNOTTY TIOCSETD TIOCGETD TCSBRKP TIOCSBRK TIOCCBRK TIOCGSID TCGETS2 TCSETS2 TCSETSW2 TCSETSF2 TIOCGRS48 TIOCSRS485 TIOCGPTN TIOCSPTLCK TIOCGDEV TCSETX TCSETXF TCSETXW TIOCSIG TIOCVHANGUP TIOCGPKT TIOCGPTLCK TIOCGEXCL TIOCGPTPEER TIOCGISO7816 TIOCSISO7816 FIONCLEX FIOCLEX FIOASYNC TIOCSERCONFIG TIOCSERGWILD TIOCSERSWILD TIOCGLCKTRMIOS TIOCSLCKTRMIOS TIOCSERGSTRUCT TIOCSERGETLSR TIOCSERGETMULTI TIOCSERSETMULTI TIOCMIWAIT TIOCGICOUNT CARD_INFO ELEM_LIST ELEM_INFO ELEM_READ ELEM_WRITE ELEM_LOCK ELEM_UNLOCK SUBSCRIBE_EVENTS ELEM_ADD ELEM_REPLACE ELEM_REMOVE TLV_READ TLV_WRITE TLV_COMMAND HWDEP_NEXT_DEVICE HWDEP_INFO PCM_NEXT_DEVICE PCM_INFO PCM_PREFER_SUBDEVICE RAWMIDI_NEXT_DEVICE RAWMIDI_INFO RAWMIDI_PREFER_SUBDEVICE UMP_NEXT_DEVICE UMP_ENDPOINT_INFO UMP_BLOCK_INFO POWER POWER_STATE GET_UNIQUE GET_MAGIC IRQ_BUSID GET_MAP GET_CLIENT GET_STATS SET_VERSION MODESET_CTL GEM_CLOSE GEM_FLINK GEM_OPEN GET_CAP SET_CLIENT_CAP SET_UNIQUE AUTH_MAGIC ADD_MAP ADD_BUFS MARK_BUFS INFO_BUFS MAP_BUFS FREE_BUFS RM_MAP SET_SAREA_CTX GET_SAREA_CTX SET_MASTER DROP_MASTER ADD_CTX RM_CTX MOD_CTX GET_CTX SWITCH_CTX NEW_CTX RES_CTX ADD_DRAW RM_DRAW PRIME_HANDLE_TO_FD PRIME_FD_TO_HANDLE AGP_ACQUIRE AGP_RELEASE AGP_ENABLE AGP_INFO AGP_ALLOC AGP_FREE AGP_BIND AGP_UNBIND SG_ALLOC SG_FREE WAIT_VBLANK CRTC_GET_SEQUENCE CRTC_QUEUE_SEQUENCE UPDATE_DRAW I915_INIT I915_FLUSH I915_FLIP I915_BATCHBUFFER I915_IRQ_EMIT I915_IRQ_WAIT I915_GETPARAM I915_SETPARAM I915_ALLOC I915_FREE I915_INIT_HEAP I915_CMDBUFFER I915_DESTROY_HEAP I915_SET_VBLANK_PIPE I915_GET_VBLANK_PIPE I915_VBLANK_SWAP I915_HWS_ADDR I915_GEM_INIT I915_GEM_EXECBUFFER I915_GEM_PIN I915_GEM_UNPIN I915_GEM_BUSY I915_GEM_THROTTLE I915_GEM_ENTERVT I915_GEM_LEAVEVT I915_GEM_CREATE I915_GEM_PREAD I915_GEM_PWRITE I915_GEM_MMAP I915_GEM_SET_DOMAIN I915_GEM_SW_FINISH I915_GEM_SET_TILING I915_GEM_GET_TILING I915_GEM_GET_APERTURE I915_GEM_MMAP_GTT I915_GET_PIPE_FROM_CRTC_ID I915_GEM_MADVISE I915_OVERLAY_PUT_IMAGE I915_OVERLAY_ATTRS I915_GEM_EXECBUFFER2 I915_GET_SPRITE_COLORKEY I915_SET_SPRITE_COLORKEY I915_GEM_WAIT I915_GEM_CONTEXT_CREATE I915_GEM_CONTEXT_DESTROY I915_GEM_SET_CACHING I915_GEM_GET_CACHING I915_REG_READ I915_GET_RESET_STATS I915_GEM_USERPTR I915_GEM_CONTEXT_GETPARAM I915_GEM_CONTEXT_SETPARAM I915_PERF_OPEN I915_PERF_ADD_CONFIG I915_PERF_REMOVE_CONFIG I915_QUERY I915_GEM_VM_CREATE I915_GEM_VM_DESTROY I915_GEM_CREATE_EXT MODE_GETRESOURCES MODE_GETCRTC MODE_SETCRTC MODE_CURSOR MODE_GETGAMMA MODE_SETGAMMA MODE_GETENCODER MODE_GETCONNECTOR MODE_ATTACHMODE MODE_DETACHMODE MODE_GETPROPERTY MODE_SETPROPERTY MODE_GETPROPBLOB MODE_GETFB MODE_ADDFB MODE_RMFB MODE_PAGE_FLIP MODE_DIRTYFB MODE_CREATE_DUMB MODE_MAP_DUMB MODE_DESTROY_DUMB MODE_GETPLANERESOURCES MODE_GETPLANE MODE_SETPLANE MODE_ADDFB2 MODE_OBJ_GETPROPERTIES MODE_OBJ_SETPROPERTY MODE_CURSOR2 MODE_ATOMIC MODE_CREATEPROPBLOB MODE_DESTROYPROPBLOB SYNCOBJ_CREATE SYNCOBJ_DESTROY SYNCOBJ_HANDLE_TO_FD SYNCOBJ_FD_TO_HANDLE SYNCOBJ_WAIT SYNCOBJ_RESET SYNCOBJ_SIGNAL MODE_CREATE_LEASE MODE_LIST_LESSEES MODE_GET_LEASE MODE_REVOKE_LEASE SYNCOBJ_TIMELINE_WAIT SYNCOBJ_QUERY SYNCOBJ_TRANSFER SYNCOBJ_TIMELINE_SIGNAL MODE_GETFB2 SYNCOBJ_EVENTFD MODE_CLOSEFB GET_API_VERSION CREATE_VM GET_MSR_INDEX_LIST CHECK_EXTENSION GET_VCPU_MMAP_SIZE GET_SUPPORTED_CPUID GET_EMULATED_CPUID GET_MSR_FEATURE_INDEX_LIST CREATE_VCPU GET_DIRTY_LOG SET_NR_MMU_PAGES GET_NR_MMU_PAGES SET_USER_MEMORY_REGION SET_TSS_ADDR SET_IDENTITY_MAP_ADDR SET_USER_MEMORY_REGION2 CREATE_IRQCHIP IRQ_LINE GET_IRQCHIP SET_IRQCHIP CREATE_PIT GET_PIT SET_PIT IRQ_LINE_STATUS SET_GSI_ROUTING REINJECT_CONTROL IRQFD CREATE_PIT2 SET_BOOT_CPU_ID IOEVENTFD XEN_HVM_CONFIG SET_CLOCK GET_CLOCK GET_REGS SET_REGS GET_SREGS SET_SREGS TRANSLATE GET_MSRS SET_MSRS SET_CPUID SET_SIGNAL_MASK GET_FPU SET_FPU GET_LAPIC SET_LAPIC SET_CPUID2 GET_CPUID2 TPR_ACCESS_REPORTING SET_VAPIC_ADDR GET_MP_STATE SET_MP_STATE SET_GUEST_DEBUG X86_SETUP_MCE X86_GET_MCE_CAP_SUPPORTED X86_SET_MCE GET_VCPU_EVENTS SET_VCPU_EVENTS ENABLE_CAP SIGNAL_MSI GET_XCRS SET_XCRS CREATE_SPAPR_TCE ALLOCATE_RMA DIRTY_TLB GET_ONE_REG SET_ONE_REG KVMCLOCK_CTRL GET_REG_LIST SET_PMU_EVENT_FILTER MEMORY_ENCRYPT_OP MEMORY_ENCRYPT_REG_REGION MEMORY_ENCRYPT_UNREG_REGION HYPERV_EVENTFD GET_NESTED_STATE SET_NESTED_STATE CLEAR_DIRTY_LOG GET_SUPPORTED_HV_CPUID X86_SET_MSR_FILTER RESET_DIRTY_RINGS XEN_HVM_GET_ATTR XEN_HVM_SET_ATTR XEN_VCPU_GET_ATTR XEN_VCPU_SET_ATTR GET_SREGS2 SET_SREGS2 GET_STATS_FD XEN_HVM_EVTCHN_SEND SET_MEMORY_ATTRIBUTES CREATE_GUEST_MEMFD CREATE_DEVICE SET_DEVICE_ATTR GET_DEVICE_ATTR HAS_DEVICE_ATTR SET_FEATURES RESET_OWNER SET_MEM_TABLE SET_LOG_BASE SET_LOG_FD FREE_WORKER SET_VRING_NUM SET_VRING_ADDR SET_VRING_BASE SET_VRING_ENDIAN GET_VRING_ENDIAN ATTACH_VRING_WORKER SET_VRING_KICK SET_VRING_CALL SET_VRING_ERR SET_VRING_BUSYLOOP_TIMEOUT GET_VRING_BUSYLOOP_TIMEOUT SET_BACKEND_FEATURES NET_SET_BACKEND SCSI_SET_ENDPOINT SCSI_CLEAR_ENDPOINT SCSI_GET_ABI_VERSION SCSI_SET_EVENTS_MISSED SCSI_GET_EVENTS_MISSED VSOCK_SET_GUEST_CID VSOCK_SET_RUNNING VDPA_SET_STATUS VDPA_SET_CONFIG VDPA_SET_VRING_ENABLE VDPA_SET_CONFIG_CALL VDPA_SET_GROUP_ASID VDPA_SUSPEND VDPA_RESUME GET_FEATURES NEW_WORKER GET_VRING_BASE GET_VRING_WORKER GET_BACKEND_FEATURES VDPA_GET_DEVICE_ID VDPA_GET_STATUS VDPA_GET_CONFIG VDPA_GET_VRING_NUM VDPA_GET_IOVA_RANGE VDPA_GET_CONFIG_SIZE VDPA_GET_AS_NUM VDPA_GET_VRING_GROUP VDPA_GET_VRING_DESC_GROUP VDPA_GET_VQS_COUNT VDPA_GET_GROUP_NUM BULK RESETEP SETINTERFACE SETCONFIGURATION GETDRIVER SUBMITURB DISCARDURB REAPURB REAPURBNDELAY DISCSIGNAL CLAIMINTERFACE RELEASEINTERFACE CONNECTINFO IOCTL HUB_PORTINFO CLEAR_HALT DISCONNECT CLAIM_PORT RELEASE_PORT GET_CAPABILITIES DISCONNECT_CLAIM ALLOC_STREAMS FREE_STREAMS DROP_PRIVILEGES GET_SPEED CONNINFO_EX FORBID_SUSPEND ALLOW_SUSPEND WAIT_FOR_RESUME KCMP_ EPOLL_TFD SYNCHRONOUS REMOUNT MANDLOCK DIRSYNC REC SILENT POSIXACL UNBINDABLE SLAVE KERNMOUNT LAZYTIME SUBMOUNT NOREMOTELOCK NOSEC BORN ACTIVE NOUSER MS_ F_SYMLINKS F_AUTOMOUNTS F_EMPTY_PATH T_SYMLINKS T_AUTOMOUNTS T_EMPTY_PATH SET_GROUP BENEATH MOVE_MOUNT_ 0x%# DISABLE_ACCESS DISABLE_WRITE PKEY_ ARCH_ GET_UNTAG_MASK ENABLE_TAGGED_ADDR GET_MAX_TAG_BITS FORCE_TAGGED_SVA MAP_VDSO_X32 MAP_VDSO_32 MAP_VDSO_64 SET_GS SET_FS GET_FS GET_GS GET_CPUID GET_XCOMP_SUPP GET_XCOMP_PERM REQ_XCOMP_PERM GET_XCOMP_GUEST_PERM REQ_XCOMP_GUEST_PERM PR_SET_MM_ PR_ START_CODE END_CODE START_DATA END_DATA START_STACK START_BRK ARG_START ARG_END ENV_START ENV_END AUXV EXE_FILE SET_PDEATHSIG GET_PDEATHSIG GET_DUMPABLE SET_DUMPABLE GET_UNALIGN SET_UNALIGN GET_KEEPCAPS SET_KEEPCAPS GET_FPEMU SET_FPEMU GET_FPEXC SET_FPEXC GET_TIMING SET_TIMING SET_NAME GET_NAME GET_ENDIAN SET_ENDIAN GET_SECCOMP SET_SECCOMP CAPBSET_READ CAPBSET_DROP GET_TSC SET_TSC GET_SECUREBITS SET_SECUREBITS SET_TIMERSLACK GET_TIMERSLACK TASK_PERF_EVENTS_DISABLE TASK_PERF_EVENTS_ENABLE MCE_KILL MCE_KILL_GET SET_MM SET_CHILD_SUBREAPER GET_CHILD_SUBREAPER SET_NO_NEW_PRIVS GET_NO_NEW_PRIVS GET_TID_ADDRESS SET_THP_DISABLE GET_THP_DISABLE MPX_ENABLE_MANAGEMENT MPX_DISABLE_MANAGEMENT SET_FP_MODE GET_FP_MODE CAP_AMBIENT SVE_SET_VL SVE_GET_VL GET_SPECULATION_CTRL SET_SPECULATION_CTRL PAC_RESET_KEYS SET_TAGGED_ADDR_CTRL GET_TAGGED_ADDR_CTRL SET_IO_FLUSHER GET_IO_FLUSHER SET_SYSCALL_USER_DISPATCH PAC_SET_ENABLED_KEYS PAC_GET_ENABLED_KEYS SCHED_CORE SME_SET_VL SME_GET_VL SET_MDWE GET_MDWE SET_MEMORY_MERGE GET_MEMORY_MERGE RISCV_V_SET_CONTROL RISCV_V_GET_CONTROL EXCHANGE WHITEOUT RENAME_ , path: %s , port: %d, addr: %s , flowinfo: %lu , scope_id: %lu { .family: %s UNSPEC LOCAL INET AX25 IPX APPLETALK NETROM BRIDGE ATMPVC INET6 ROSE DECnet NETBEUI NETLINK ASH ECONET ATMSVC RDS SNA IRDA PPPOX WANPIPE LLC IB MPLS CAN TIPC BLUETOOTH IUCV RXRPC ISDN PHONET IEEE802154 CAIF ALG NFC VSOCK KCM QIPCRTR SMC XDP MCTP SOL_ %sSOCKET IPPROTO_ UDP IPV6 ICMPV6 SCTP UDPLITE ATALK DECNET ATM AAL PPPOL2TP PNPIPE MPTCP ICMP IGMP IPIP EGP PUP IDP RSVP GRE AH MTP BEETPH ENCAP PIM ETHERNET AT_STATX_ AT_ SYNC_AS_STAT REMOVEDIR SYMLINK_FOLLOW STATX_FORCE_SYNC STATX_DONT_SYNC MTIME CTIME INO BLOCKS BTIME MNT_ID DIOALIGN MNT_ID_UNIQUE SYNC_FILE_RANGE_ WRITE_AND_WAIT WAIT_BEFORE WAIT_AFTER _VECTOR IA32_SYSCALL LOCAL_TIMER HYPERV_STIMER0 HYPERV_REENLIGHTENMENT MANAGED_IRQ_SHUTDOWN POSTED_INTR_NESTED POSTED_INTR_WAKEUP POSTED_INTR HYPERVISOR_CALLBACK DEFERRED_ERROR IRQ_WORK X86_PLATFORM_IPI REBOOT THRESHOLD_APIC THERMAL_APIC CALL_FUNCTION_SINGLE CALL_FUNCTION RESCHEDULE ERROR_APIC SPURIOUS_APIC MSR_ K7_EVNTSEL0 K7_EVNTSEL1 K7_EVNTSEL2 K7_EVNTSEL3 K7_PERFCTR0 K7_PERFCTR1 K7_PERFCTR2 K7_PERFCTR3 AMD64_SYSCFG K7_HWCR K8_TOP_MEM1 K7_CLK_CTL K8_TOP_MEM2 AMD64_NB_CFG AMD64_PATCH_LOADER K7_FID_VID_CTL K7_FID_VID_STATUS AMD64_MC0_MASK K8_INT_PENDING_MSG FAM10H_MMIO_CONF_BASE AMD_PERF_CTL AMD_PERF_STATUS AMD_PSTATE_DEF_BASE F15H_CU_PWR_ACCUMULATOR F15H_CU_MAX_PWR_ACCUMULATOR K8_TSEG_ADDR K8_TSEG_MASK VM_CR VM_IGNNE VM_HSAVE_PA AMD64_SVM_AVIC_DOORBELL AMD64_VM_PAGE_FLUSH AMD64_VIRT_SPEC_CTRL AMD64_SEV_ES_GHCB AMD64_SEV AMD64_OSVW_ID_LENGTH AMD64_OSVW_STATUS F15H_PERF_CTL F15H_PERF_CTR F16H_L2I_PERF_CTL F16H_L2I_PERF_CTR F15H_NB_PERF_CTL F15H_NB_PERF_CTR F15H_PTSC AMD_RAPL_POWER_UNIT AMD_CORE_ENERGY_STATUS AMD_PKG_ENERGY_STATUS AMD_CPPC_CAP1 AMD_CPPC_ENABLE AMD_CPPC_CAP2 AMD_CPPC_REQ AMD_CPPC_STATUS AMD_PPIN_CTL AMD_PPIN AMD_SAMP_BR_FROM F19H_UMC_PERF_CTL F19H_UMC_PERF_CTR EFER LSTAR CSTAR SYSCALL_MASK K6_UWCCR K6_EPMR K6_PSOR K6_PFIR F17H_IRPERF FS_BASE KERNEL_GS_BASE TSC_AUX AMD64_TSC_RATIO AMD64_LBR_SELECT AMD_DBG_EXTN_CFG IA32_MBA_BW_BASE IA32_SMBA_BW_BASE AMD64_PERF_CNTR_GLOBAL_STATUS AMD64_PERF_CNTR_GLOBAL_CTL IA32_EVT_CFG_BASE IA32_P5_MC_ADDR IA32_P5_MC_TYPE IA32_TSC IA32_PLATFORM_ID IA32_APICBASE KNC_PERFCTR0 KNC_PERFCTR1 KNC_EVNTSEL0 KNC_EVNTSEL1 IA32_EBL_CR_POWERON EBC_FREQUENCY_ID TEST_CTRL SMI_COUNT IA32_FEAT_CTL IA32_TSC_ADJUST LBR_CORE_FROM IA32_SPEC_CTRL IA32_PRED_CMD LBR_CORE_TO IA32_UCODE_WRITE IA32_MKTME_KEYID_PARTITIONING AMD64_PATCH_LEVEL IA32_SGXLEPUBKEYHASH0 IA32_SGXLEPUBKEYHASH1 IA32_SGXLEPUBKEYHASH2 IA32_SGXLEPUBKEYHASH3 IA32_SMM_MONITOR_CTL IA32_SMBASE IA32_PERFCTR0 IA32_PERFCTR1 FSB_FREQ PLATFORM_INFO IA32_CORE_CAPS PKG_CST_CONFIG_CONTROL IA32_MPERF IA32_APERF MTRRcap IDT_FCR1 IDT_FCR2 IDT_FCR3 IA32_ARCH_CAPABILITIES IA32_FLUSH_CMD TSX_FORCE_ABORT IDT_MCR0 IDT_MCR1 IDT_MCR2 IDT_MCR3 IDT_MCR4 IDT_MCR5 IDT_MCR6 IDT_MCR7 IA32_BBL_CR_CTL IA32_BBL_CR_CTL3 IDT_MCR_CTRL IA32_TSX_CTRL IA32_MCU_OPT_CTRL MISC_FEATURES_ENABLES IA32_SYSENTER_CS IA32_SYSENTER_ESP IA32_SYSENTER_EIP IA32_MCG_CAP IA32_MCG_STATUS IA32_MCG_CTL ERROR_CONTROL IA32_MCG_EAX IA32_MCG_EBX IA32_MCG_ECX IA32_MCG_EDX IA32_MCG_ESI IA32_MCG_EDI IA32_MCG_EBP IA32_MCG_ESP IA32_MCG_EFLAGS IA32_MCG_EIP IA32_MCG_RESERVED IA32_PERF_STATUS IA32_PERF_CTL IA32_THERM_CONTROL IA32_THERM_INTERRUPT IA32_THERM_STATUS THERM2_CTL IA32_MISC_ENABLE IA32_TEMPERATURE_TARGET MISC_FEATURE_CONTROL OFFCORE_RSP_0 OFFCORE_RSP_1 MISC_PWR_MGMT TURBO_RATIO_LIMIT1 TURBO_RATIO_LIMIT2 IA32_ENERGY_PERF_BIAS IA32_PACKAGE_THERM_STATUS IA32_PACKAGE_THERM_INTERRUPT IA32_XFD IA32_XFD_ERR LBR_TOS IA32_DEBUGCTLMSR IA32_LASTBRANCHFROMIP IA32_LASTBRANCHTOIP IA32_LASTINTFROMIP IA32_LASTINTTOIP IA32_POWER_CTL MTRRfix64K_00000 MTRRfix16K_80000 MTRRfix16K_A0000 MTRRfix4K_C0000 MTRRfix4K_C8000 MTRRfix4K_D0000 MTRRfix4K_D8000 MTRRfix4K_E0000 MTRRfix4K_E8000 MTRRfix4K_F0000 MTRRfix4K_F8000 IA32_CR_PAT IA32_MC0_CTL2 INTEGRITY_CAPS MTRRdefType CORE_PERF_FIXED_CTR0 CORE_PERF_FIXED_CTR1 CORE_PERF_FIXED_CTR2 CORE_PERF_FIXED_CTR3 PERF_METRICS IA32_PERF_CAPABILITIES CORE_PERF_FIXED_CTR_CTRL CORE_PERF_GLOBAL_STATUS CORE_PERF_GLOBAL_CTRL CORE_PERF_GLOBAL_OVF_CTRL IA32_PEBS_ENABLE PEBS_DATA_CFG PEBS_LD_LAT_THRESHOLD PEBS_FRONTEND PKG_C3_RESIDENCY PKG_C6_RESIDENCY PKG_C7_RESIDENCY CORE_C3_RESIDENCY CORE_C7_RESIDENCY KNL_CORE_C6_RESIDENCY IA32_MC0_CTL IA32_MC0_STATUS IA32_MC0_ADDR IA32_MC0_MISC IA32_VMX_BASIC IA32_VMX_PINBASED_CTLS IA32_VMX_PROCBASED_CTLS IA32_VMX_EXIT_CTLS IA32_VMX_ENTRY_CTLS IA32_VMX_MISC IA32_VMX_CR0_FIXED0 IA32_VMX_CR0_FIXED1 IA32_VMX_CR4_FIXED0 IA32_VMX_CR4_FIXED1 IA32_VMX_VMCS_ENUM IA32_VMX_PROCBASED_CTLS2 IA32_VMX_EPT_VPID_CAP IA32_VMX_TRUE_PINBASED_CTLS IA32_VMX_TRUE_PROCBASED_CTLS IA32_VMX_TRUE_EXIT_CTLS IA32_VMX_TRUE_ENTRY_CTLS IA32_VMX_VMFUNC IA32_VMX_PROCBASED_CTLS3 IA32_PMC0 IA32_MCG_EXT_CTL IA32_RTIT_OUTPUT_BASE IA32_RTIT_OUTPUT_MASK IA32_RTIT_CTL IA32_RTIT_STATUS IA32_RTIT_CR3_MATCH IA32_RTIT_ADDR0_A IA32_RTIT_ADDR0_B IA32_RTIT_ADDR1_A IA32_RTIT_ADDR1_B IA32_RTIT_ADDR2_A IA32_RTIT_ADDR2_B IA32_RTIT_ADDR3_A IA32_RTIT_ADDR3_B IA32_DS_AREA VR_CURRENT_CONFIG PKGC3_IRTL PKGC6_IRTL PKGC7_IRTL PKG_C2_RESIDENCY PKG_POWER_LIMIT PKG_PERF_STATUS PKG_POWER_INFO DRAM_POWER_LIMIT DRAM_ENERGY_STATUS DRAM_PERF_STATUS DRAM_POWER_INFO PKG_C8_RESIDENCY PKG_C9_RESIDENCY PKG_C10_RESIDENCY PKGC8_IRTL PKGC9_IRTL PKGC10_IRTL PP0_POWER_LIMIT PP0_ENERGY_STATUS PP0_POLICY PP0_PERF_STATUS PP1_POWER_LIMIT PP1_ENERGY_STATUS PP1_POLICY CONFIG_TDP_NOMINAL CONFIG_TDP_LEVEL_1 CONFIG_TDP_LEVEL_2 CONFIG_TDP_CONTROL TURBO_ACTIVATION_RATIO PLATFORM_ENERGY_STATUS PPERF SECONDARY_TURBO_RATIO_LIMIT PKG_WEIGHTED_CORE_C0_RES PKG_ANY_CORE_C0_RES PKG_ANY_GFXE_C0_RES PKG_BOTH_CORE_GFXE_C0_RES CORE_C1_RES MODULE_C6_RES_MS CC6_DEMOTION_POLICY_CONFIG MC6_DEMOTION_POLICY_CONFIG LBR_NHM_FROM CORE_PERF_LIMIT_REASONS IA32_U_CET IA32_S_CET IA32_PL0_SSP IA32_PL1_SSP IA32_PL2_SSP IA32_PL3_SSP IA32_INT_SSP_TAB GFX_PERF_LIMIT_REASONS RING_PERF_LIMIT_REASONS LBR_NHM_TO PM_ENABLE HWP_CAPABILITIES HWP_REQUEST_PKG HWP_INTERRUPT HWP_REQUEST HWP_STATUS IA32_BNDCFGS IA32_PASID IA32_XSS LBR_INFO_0 IA32_BNDCFGS_RSVD Add filter: %s probe-definition(%d): %s %d arguments [GROUP:]EVENT list up probe events del delete a probe event. definition Show source code lines. externs path to kernel source no-inlines dry run max-probes !_* & !*@plt [!]FILTER executable|path modname|path Manipulate probe cache bootconfig '-' is not supported. Error: Command Parse Error. Reason: %s (Code: %d) lda !__k???tab_* & !__crc_* Error: Failed to show vars. Delete filter: '%s' Failed to get buildids: %d Removed event: %s "%s" does not hit any event. Added new event%s CLIENT: ready write SERVER: read pipe() socketpair() SENDER: write main:malloc() fork() pthread_attr_init: pthread_attr_setstacksize pthread_create failed Reading for readyfds Writing to start them # %d groups == %d %s run Total time %14s: %lu.%03lu [sec] %lu.%03lu Unknown format:%d Specify number of groups nr_loops cgroup.threads cgroup.procs Cannot enter to cgroup: %s perf_event Hint: try to run as root %14s: %lu.%03lu [sec] %14lf usecs/op %14d ops/sec Specify number of loops threaded SEND,RECV unexpected syscall: %d waitpid(%d) failed unexpected exit code: %d # Executed %lu system calls sync-mode getppid() # Executed %'d %s calls %'14d ops/sec getpgid() fork failed waitpid failed /bin/true execve /bin/true failed execve() perf bench syscall <options> # function '%s' (%s) # Copying %s bytes ... %14lf cycles/byte %14lf bytes/sec %14lfd KB/sec %14lf MB/sec %14lf GB/sec %lf Invalid size:%s Unknown function: %s Available functions: %s ... %s x86-64-unrolled x86-64-stosq x86-64-movsq 1MB shared private mlockall pthread_attr_setaffinity_np pthread_create pthread_join calloc Specify amount of threads Specify runtime (in seconds) silent nwakes Must be perfectly divisible nwakers futex_wait futex_wait_requeue_pi PI cpu_map__new nrequeue broadcast Requeue all threads at once Use multiple futexes epoll_create lineal single (EPOLLONESHOT semantics) (nonblocking) CPU affinity Using %s queue model Nesting level(s): %d eventfd main thread: toggling done nfds noaffinity Disables CPU affinity randomize Verbose mode multiq nonblocking nested oneshot Use EPOLLONESHOT semantics edge epoll_ct data Session creation failed. Thread map creation failed. Run single threaded benchmark Run multi-threaded benchmark min-threads max-threads single-iterations multi-iterations outer-iterations inner-iterations Adding DSO: %s Iteration #%d -b --buildid-all Build-id injection failed [%d] injecting: %s Child %d exited with %d Memory allocation failed /usr/lib/ Collected %d DSOs nr-mmaps strbuf_init: %s strbuf_add: %s strbuf_addch: %s Number of cpus: %d Number of threads: %d Number of iterations: %d Started iteration %d evlist__mmap: %s Iteration %d took: %luus nr-events dummy %14lf usecs/op/cpu Unknown format: %d ioctl(PERF_EVENT_IOC_DISABLE) ioctl(PERF_EVENT_IOC_ENABLE) passive Specify amount of breakpoints Specify amount of parallelism Cannot find PMU %s core usleep(1000) usec %14s: %'lu %ss %s%'ld to baseline %s%'ld to previous %'.3f %ss/op %'.3f %ss/op to baseline %'.3f %ss/op to previous perf bench uprobe <options> got NODE list: {%s} got CPU list: {%s} thread %d/%d # %5.1f%% [%.1f mins] %2d/%-2d [%2d/%-2d] l:%3d-%-3d (%3d) [%4.1f%%] {%d-%d} (%6.1fs converged) (%6.1fs de-converged) main, g->p.nr_tasks: %d # binding tasks to CPUs: # token: {%s}, end: {%s} CPUs: %d_%d-%d#%dx%d %2d/%d # binding tasks to NODEs: NODEs: %d-%d #%d ,%2d ### # # process %2d: PID %d process %d NUMA-convergence-latency %-30s %15.3f, %-15s %s secs latency to NUMA-converge %14.3f %s runtime-max/thread runtime-min/thread runtime-avg/thread secs average thread-runtime spread-runtime/thread %, data/thread GB, GB data processed, per thread data-total GB data processed, total runtime/byte/thread nsecs, nsecs/byte/thread runtime thread-speed GB/sec, GB/sec/thread speed total-speed GB/sec total speed process%d:thread%d GB/sec thread-system-time system CPU time/thread thread-user-time user CPU time/thread RAM-bw-local, -p -t -P -M -s -zZq --thp --no-data_rand_walk RAM-bw-local-NOTHP, RAM-bw-remote, RAM-bw-local-2x, 0,2 RAM-bw-remote-2x, 1x2 RAM-bw-cross, 0,8 1,0 1x3-convergence, -zZ0qcm 1x4-convergence, 1x6-convergence, 1020 2x3-convergence, 3x3-convergence, 4x4-convergence, 4x4-convergence-NOTHP, 4x6-convergence, 4x8-convergence, 8x4-convergence, 8x4-convergence-NOTHP, 3x1-convergence, 4x1-convergence, 8x1-convergence, 16x1-convergence, 32x1-convergence, 2x1-bw-process, -zZ0q 3x1-bw-process, 4x1-bw-process, 8x1-bw-process, 512 8x1-bw-process-NOTHP, 16x1-bw-process, 1x4-bw-thread, -T 1x8-bw-thread, 1x16-bw-thread, 1x32-bw-thread, 2x3-bw-process, 4x4-bw-process, 4x6-bw-process, 4x8-bw-process, 4x8-bw-process-NOTHP, 3x3-bw-process, 5x5-bw-process, 2x16-bw-process, 1x32-bw-process, 2048 numa02-bw, numa02-bw-NOTHP, numa01-bw-thread, 192 numa01-bw-thread-NOTHP, perf bench numa <options> nr_proc number of processes nr_threads number of threads per process mb_global global memory (MBs) mb_proc process memory (MBs) mb_proc_locked mb_thread thread memory (MBs) nr_secs usleep data_reads data_writes data_backwards data_zero_memset init_zero bzero the initial allocations init_random init_cpu0 perturb_secs show_details Show details Run all tests in the suite show_convergence measure_convergence measure convergence latency serialize-startup serialize thread startup cpu[,cpu2,...cpuN] memnodes node[,node2,...nodeN] annotate.objdump -v --- start --- failed to fork test: %s test child forked, pid %d test child finished with %d test child interrupted ---- end ---- %s: %s subtest %d: Ok Skip (%s) Skip FAILED! tests to skip dont-fork Do not fork for testcase workload to run for testing dso to test %3d: %s %3d:%1d: %s No workload found: %s %3d: %-*s: Skip (user override) %3d.%1d: %-*s: .sh Too many script files ./tools/perf/tests ./tests %s/shell %s/tests/shell wrong type tests/parse-events.c FAILED %s:%d %s wrong config wrong number of entries wrong exclude_user wrong exclude_kernel wrong exclude_hv wrong precise_ip wrong period wrong callgraph wrong time wrong config1 wrong config2 wrong config3 wrong bp_type wrong bp_len wrong sample_type wrong sample_period wrong type term wrong type val wrong val r0xead wrong pinned wrong exclusive check_parse_fake %s failed %s/bus/event_source/devices/ ... SKIP Failed allocation can't access trace events %s/event=1/,%s/event=1/ unexpected PMU type PMU missing event wrong exclude guest wrong exclude host wrong group name wrong leader wrong sample_read branch-misses wrong number of groups group1 wrong core.nr_members wrong group_idx intel_pt krava wrong name cpu/config=2/u breakpoint1 breakpoint2 event not parsed as raw type PMU type expected once No PMU found for type Raw PMU not matched can't open pmu event dir: %s %s:u,%s/event=%s/u cachepmu wrong name setting wrong complex name parsing intel_pt//u numpmu rawpmu Can't open events dir header_event header_page Can't get sys path Can't open sys dir wrong events count running test %d '%s' cache-misses wrong exclude idle mem:0:u mem:0:x:k mem:0:r:hp mem:0:w:up l1d mem:0:rw:kp Test event parsing permissions pmu_events pmu_events2 alias no aliases in sysfs pmu_events_alias2 Parsing of aliased events terms2 software/r1a/ software/r0x1a/ cpu/L1-dcache-load-miss/ cpu/L1-dcache-load-miss/kp cpu/instructions/ cpu/instructions/h cpu/instructions/G cpu/instructions/H cpu/instructions/uDp cpu/instructions/I cpu/instructions/kIG cpu/cycles/u cpu/cycles/k cpu/instructions/uep cpu/cycles,name=name/ cpu/cycles,name=l1d/ syscalls:sys_enter_openat syscalls:* r1a 1:1 cycles/period=100000,config2/ L1-dcache-load-miss mem:0 mem:0:x mem:0:r mem:0:w syscalls:sys_enter_openat:k syscalls:*:u r1a:kp 1:1:hp instructions:h faults:u L1-dcache-load-miss:kp instructions:G instructions:H mem:0:rw {instructions:k,cycles:upp} {cycles:u,instructions:kp}:p *:* {cycles,cache-misses:G}:H {cycles,cache-misses:H}:G {cycles:G,cache-misses:H}:u {cycles:G,cache-misses:H}:uG instructions:uDp mem:0/1 mem:0/2:w mem:0/4:rw:u instructions:I instructions:kIG task-clock:P,cycles instructions/name=insn/ r1234/name=rawpmu/ 4:0x6530160/name=numpmu/ cycles//u cycles:k instructions:uep cycles/name=name/ cycles/name=l1d/ mem:0/name=breakpoint/ mem:0:x/name=breakpoint/ mem:0:r/name=breakpoint/ mem:0:w/name=breakpoint/ mem:0/name=breakpoint/u mem:0:x/name=breakpoint/k mem:0:r/name=breakpoint/hp mem:0:w/name=breakpoint/up mem:0:rw/name=breakpoint/ mem:0:rw/name=breakpoint/kp mem:0/1/name=breakpoint/ mem:0/2:w/name=breakpoint/ mem:0/4:rw/name=breakpoint/u %s/self/fd fd path: %s failed to open fd directory tests/dso-data.c mkstemp failed No test file Failed to access to dso Wrong size Wrong data ENOMEM file limit %ld, new %d failed to set file limit failed to alloc dsos array failed to get dso file failed to get dso failed to create dsos failed to get fd failed to read dso dsos[0] is not open failed to close dsos[0] nr start %ld, nr stop %ld failed leaking files failed to open extra fd failed to close dso_0 failed to close dso_1 DSO data tests dso_data dso_data_cache dso_data_reopen %s/event-%d-%llu-%d [event-%d-%llu-%d] group_fd=%d cpu=%d pid=%d flags=%lu size=%u config=%llu sample_period=%llu read_format=%llu disabled=%d inherit=%d pinned=%d exclusive=%d exclude_user=%d exclude_kernel=%d exclude_hv=%d exclude_idle=%d mmap=%d comm=%d freq=%d inherit_stat=%d enable_on_exec=%d task=%d watermark=%d precise_ip=%d mmap_data=%d sample_id_all=%d exclude_host=%d exclude_guest=%d exclude_callchain_kernel=%d exclude_callchain_user=%d mmap2=%d comm_exec=%d context_switch=%d write_backward=%d namespaces=%d use_clockid=%d wakeup_events=%u bp_type=%u config1=%llu config2=%llu branch_sample_type=%llu sample_regs_user=%llu sample_stack_user=%u Skip test on hybrid systems ./perf %s/tests /usr/bin %s/perf PERF_TEST_ATTR test attr FAILED Setup struct perf_event_attr : WARN: *%lx-%lx %lx kallsyms_offsets _from_arm .long_branch. machine__load_kallsyms failed __kernel_syscall_via_break __kernel_syscall_via_epc __kernel_sigtramp __gp WARN: Maps only in kallsyms: WARN: Maps only in vmlinux: .plt_branch. _from_thumb _veneer __crc_ __efistub_ __kvm_nvhe_$ __kvm_nvhe_.L __AArch64ADRPThunk_ __ARMV5PILongThunk_ __ARMV7PILongThunk_ __ThumbV7PILongThunk_ __LA25Thunk_ __microLA25Thunk_ kallsyms_relative_base kallsyms_num_syms kallsyms_names kallsyms_markers kallsyms_token_table kallsyms_token_index _SDA_BASE_ _SDA2_BASE_ vmlinux_matches_kallsyms thread_map__new /etc/passwd evsel__read_on_cpu Detect openat syscall event openat_syscall_event perf_cpu_map__new Ignoring CPU %d %s: evlist__new %s: evsel__newtp %s: evlist__create_maps perf_evlist__open: %s %s: no events! syscall_openat_tp_fields failed to create threads tests/mmap-basic.c failed to create evsel failed to open evsel: %s failed to mmap evsel: %s loop = %u, count = %llu getsid evsel__new(%s) unexpected %s event mmap interface tests basic_mmap mmap_user_read_instr mmap_user_read_cycles sched_getaffinity sched_setaffinity: %s Couldn't parse sample %lu %d %s with unexpected pid/tid %s with different pid/tid! %s with unexpected comm! coreutils libc No PERF_RECORD_EXIT event! PERF_RECORD Failed to alloc evlist Roundtrip evsel->name %s: "%s" field not found! evsel__newtp failed with %ld prev_prio next_prio target_cpu perf_evsel__tp_sched_test fdarray__new() failed! before after before growing array after 3rd add after 4th add fdarray__add fdarray__filter perf-pmu-test rm -f %s/* rmdir %s Parse perf pmu format krava01 krava02 krava03 krava11 krava12 krava13 krava21 krava22 krava23 config:0-1,62-63 config:10-17 config:5 config1:0,2,4,6,8,20-28 config1:63 config1:45-47 config2:8,18,48,58 config2:28-29,38 Found metric '%s' Didn't find parsed metric %s Result %f Broken metric %s pmu_events__test_soc_sys testcpu testarch parsing '%s': '%s' expr__ctx_new failed expr__find_ids failed check_parse_fake failed expr__parse failed for %s tma_clears_resteers tma_mispredicts_resteers skipping testing core PMU %s bp_l1_btb_correct testing event table %s: pass PMU events pmu_event_table PMU event table sanity PMU event map aliases some metrics failed parsing_fake parsing_threshold hisi_sccl1_ddrc2 uncore_cbox_0 hisi_sccl3_l3c7 uncore_imc_free_running_0 uncore_imc_0 uncore_sys_ddr_pmu0 v8 uncore_sys_ccn_pmu4 0x01 uncore_sys_cmn_pmu0 43401 43602 43c03 43a01 sys_cmn_pmu.hnf_cache_miss (434|436|43c|43a).* eventid=0x1,type=0x5 uncore uncore_sys_cmn_pmu sys_ccn_pmu.read_cycles config=0x2c ccn read-cycles event uncore_sys_ccn_pmu sys_ddr_pmu.write_cycles event=0x2b ddr write-cycles event uncore_sys_ddr_pmu uncore_imc.cache_hits event=0x34 Total cache hits uncore_imc event=0x12 Total cache misses uncore_imc_free_running uncore_hisi_l3c.rd_hit_cpipe event=0x7 Total read hits hisi_sccl,l3c event-two-hyph event=0xc0,umask=0x00 UNC_CBO_TWO_HYPH uncore_cbox event=0xc0,umask=0 event-hyphen event=0xe0,umask=0x00 UNC_CBO_HYPHEN event=0xe0,umask=0 event=0x22,umask=0x81 uncore_hisi_ddrc.flux_wcmd event=0x2 DDRC write commands hisi_sccl,ddrc l3_cache_rd event=0x40 L3 cache access, read eist_trans dispatch_blocked.any segment_reg_loads.any bp_l2_btb_correct event=0x8b L2 BTB Correction event=0x8a L1 BTB Correction ----- %s -------- bash [kernel] page_fault sys_perf_event_open realloc main xmalloc xfree run_command cmd_record Can't find the matched entry cpu-clock task-clock Match and link multiple hists hists_link No memory tests/hists_filter.c Normal histogram Invalid nr samples Invalid nr hist entries Invalid total period Unmatched nr samples Unmatched nr hist entries Unmatched total period Histogram for thread filter Histogram for dso filter Histogram for symbol filter Histogram for socket filters Histogram for all filters Filter hist entries hists_filter tests/hists_output.c cpu,pid,comm,dso,sym dso,pid [fields = %s, sort = %s] Invalid hist entry overhead,cpu dso,sym,comm,overhead,dso Sort output of hist entries hists_output tests/hists_cumulate.c callchains expected Invalid hist entry #%zd Cumulate child hist entries hists_cumulate 2> /dev/null '/usr/bin/python3' python usage test: "%s" 'import perf' in python python_use failed opening event %llx failed to read: %d bp_signal count %lld, overflow %d Breakpoint overflow sampling bp_signal_overflow wp %d created failed to create wp tests/bp_account.c failed to modify wp wp 0 modified to bp failed to create max wp wp max created Breakpoint accounting bp_accounting failed opening event %x WO watchpoint tests/wp.c RW watchpoint Modify watchpoint missing kernel support wp_ro Read Only Watchpoint missing hardware support wp_wo Write Only Watchpoint wp_rw Read / Write Watchpoint wp_modify Modify Watchpoint evlist__new_dummy Couldn't open the evlist: %s received %d EXIT records task_exit evsel__new Error during parse sample sw_clock_freq mmap failed tid = %d, map = %p failed to notify tests/mmap-thread-lookup.c failed to destroy threads failed to synthesize maps looking for map %p failed, couldn't find map map %p, addr %lx failed with sythesizing all Lookup mmap thread mmap_thread_lookup tests/thread-maps-share.c wrong refcnt FAILED %s:%d %s (%d != %d) maps don't match failed to find other leader Share thread maps thread_maps_share thread_map__new failed! perf_cpu_map__new failed! evlist__new failed! cpu-clock:u cycles:u Failed to parse event %s No sched_switch Failed to create event %s cycles event already at front dummy:u Tracking event not tracking Not supported evlist__mmap failed! spin_sleep failed! Test COMM 1 PR_SET_NAME failed! Test COMM 2 Test COMM 3 Test COMM 4 evlist__parse_sample failed event with no time Missing sched_switch events cycles event Duplicate comm event comm event: %s nr: %d Unexpected comm event %u events recorded Missing comm events Missing cycles events Track with sched_switch switch_tracking threads failed! cpus failed! evlist failed! keep_tracking qsort failed map__load failed perf_cpu_map__new failed evlist__new failed Parsing event '%s' parse_events failed evlist__mmap failed pipe failed thread__find_map failed File is: %s On file address is: %#lx dso__data_read_offset failed kcore map tested already - skipping decompression failed Objdump command is: %s 2>/dev/null popen failed getline failed Reducing len to %zu objdump failed for kcore read_via_objdump failed buf1 (dso): 0x%02x buf2 (objdump): no vmlinux no kcore no access no kernel obj Object code reading code_reading Samples differ at 'id' Samples differ at 'ip' Samples differ at 'pid' Samples differ at 'tid' Samples differ at 'time' Samples differ at 'addr' Samples differ at 'cpu' Samples differ at 'period' Samples differ at 'raw_size' Samples differ at 'raw_data' Samples differ at 'weight' Samples differ at 'data_src' Samples differ at 'cgroup' perf_event__synthesize_sample evsel__parse_sample read_format %#lx parse_no_sample_id_all kmod_path__parse tests/kmod-path.c wrong kmod wrong comp [x_x] /xxxx/xxxx/x-x.ko is_kernel_module false [x] /xxxx/xxxx/x.ko.gz /xxxx/xxxx/x.gz [test_module] [test.module] [vdso32] [vdsox32] [vsyscall] [kernel.kallsyms] failed to set process name tests/thread-map.c failed to alloc map wrong nr wrong pid wrong comm failed to synthesize map %d,%d failed to allocate map string failed to allocate thread_map failed to remove thread thread_map count != 1 thread_map count != 0 failed to not remove thread Remove thread map thread_map_remove Synthesize thread map thread_map_synthesize Thread map can't get templ file tests/topology.c templ file: %s can't get session can't get evlist failed to write header failed to get system cpumap s390 aarch64 CPU %d, core %d, socket %d Cpu map - Node ID is set Cpu map - Thread IDX is set Core map - Node ID is set Core map - Thread IDX is set Die map - Node ID is set Die map - Core is set Die map - CPU is set Die map - Thread IDX is set Socket map - Node ID is set Socket map - Die ID is set Socket map - Core is set Socket map - CPU is set Node map - Socket is set Node map - Die ID is set Node map - Core is set Node map - CPU is set Node map - Thread IDX is set ppc64le Session topology session_topology unexpected %s tests/mem.c N/AL4 hit N/ARemote L4 hit N/APMEM miss N/ARemote PMEM miss FwdRemote RAM miss Test data source output 1-2 tests/cpumap.c not equal 4,2,1 4,5,7 failed to merge map: bad nr 1-2,4-5,7 0,2-20 1,256 1-256 wrong cpu wrong any_cpu wrong start_cpu wrong end_cpu wrong long_size 6-8 6-9 1-8 6-8,15 6-9,15 1-8,12-20 failed to convert map 1,5 2-5 1,3-6,8-10,24,35-37 1-10,12-20,22-30,32-40 CPU map cpu_map_synthesize Synthesize cpu map cpu_map_print Print cpu map cpu_map_merge Merge cpu map cpu_map_intersect Intersect cpu map cpu_map_equal Equal cpu map tests/stat.c wrong thread wrong id wrong run wrong ena wrong aggr_mode wrong scale wrong interval Synthesize stat round synthesize_stat_round Synthesize stat synthesize_stat Synthesize stat config synthesize_stat_config tests/event_update.c failed to get evlist failed to allocate ids KRAVA 1,2,3 wrong cpus wrong unit Synthesize attr update event_update OK failed to create event list SKIP : not enough rights failed to attach tests/event-times.c %s: ena %lu, run %lu failed to detach Event times event_times ids__new tests/expr.c foo ids__insert bar baz Intel ids_union expr__ctx_new FOO 1+1 parse test failed unexpected value FOO+BAR (BAR/2)%2 1 - -4 (FOO-1)*2 + (BAR/2)%2 - -4 1-1 | 1 1-1 & 1 min(1,2) + 1 max(1,2) + 1 1+1 if 3*4 else 0 1.1 + 2.1 .1 + 2. d_ratio(1, 2) d_ratio(2.5, 0) 1.1 < 2.2 2.2 > 1.1 1.1 < 1.1 2.2 > 2.2 2.2 < 1.1 1.1 > 2.2 1.1e10 < 1.1e100 1.1e2 > 1.1e-2 FOO/0 division by zero BAR/ missing operand FOO + BAR + BAZ + BOZO find ids BAZ EVENT1,param=3@ EVENT2,param=3@ dash\-event1 - dash\-event2 dash-event1 dash-event2 EVENT1 if #smt_on else EVENT2 EVENT1 0 & EVENT1 > 0 EVENT1 > 0 & 0 1 & EVENT1 > 0 EVENT1 > 0 & 1 1 | EVENT1 > 0 EVENT1 > 0 | 1 0 | EVENT1 > 0 EVENT1 > 0 | 0 #num_cpus #num_cpus >= #num_cpus_online #num_cpus >= #num_cores #num_cores >= #num_dies #num_dies >= #num_packages #system_tsc_freq #system_tsc_freq > 0 #system_tsc_freq == 0 source_count(EVENT1) source count strcmp_cpuid_str(0x0) \- \, \= strcmp_cpuid_str(%s) has_event(cycles) Simple expression parser p:%d Unexpected record of type %d Read backward ring buffer backward_ring_buffer Probe SDT events sdt_event failed: test %u is_printable_array bitmap: %s tests/bitmap.c Print bitmap bitmap_print Setting failed: %d (%p) perf hooks perf_hooks 1B 10K 20M 30G 0B n %lu, str '%s', buf '%s' unit_number__scnprintf unit_number__scnprint failed: alloc bitmap tests/mem2node.c failed: mem2node__init failed: mem2node__node mem2node 5-7,9 Expected %d maps, got %d Expected: Got: bpf_prog_1 bpf_prog_2 bpf_prog_3 kcore1 kcore3 failed to create maps tests/maps.c failed to create map failed to insert map kcore2 failed to merge map merge check failed maps__merge_in parse_nsec_time("%s") failed to keep 0 failed to skip %lu failed to keep %lu 0.000000001 1.000000001 123456.123456 18446744073.709551615 perf_time__parse_str("%s") Error %d Failed. Expected %lu to %lu 1234567.123456789, 0,1234567.123456789 10%/1 10%/1,10%/2 10%/1,10%/3,10%/10 time utils time_utils Writing jit code to: %s Test jit_write_elf short write Failed to open '%s' Failed to allocate memory tests/api-io.c %s:%d: %d != %d %s:%d: %lld != %lld 12345678abcdef90 a b c d 1 2 3 12345678ABCDEF90;a;b 0x1x2x x1x 12345678;1;2 Test api io api_io Ljava/lang/Object;<init>()V void java.lang.Object<init>() FAILED: %s: %s != %s Demangle Java demangle_java (null) camlStdlib__array__map_154 Stdlib.array.map_154 Stdlib.bytes.++_2205 Demangle OCaml demangle_ocaml Test libpfm4 support pfm_events not compiled in pfm_group test groups of --pfm-events inst_retired.any cpu_clk_unhalted.thread failed to compute metric tests/parse-metric.c idq_uops_not_delivered.core cpu_clk_unhalted.ref_xclk Frontend_Bound_SMT IPC failed l2_rqsts.demand_data_rd_hit l2_rqsts.pf_hit l2_rqsts.rfo_hit l2_rqsts.all_demand_data_rd l2_rqsts.pf_miss l2_rqsts.rfo_miss DCache_L2_Hits frontend failed DCache_L2_Misses DCache_L2 failed failed to find recursion l1d.replacement L1D_Cache_Fill_BW recursion fail failed l1d-loads-misses l1i-loads-misses cache_miss_cycles Memory bandwidth cache_miss_cycles failed group IPC failed, wrong ratio test metric group Parse and process metrics parse_metric PE file support pe_file_parsing evlist is empty tests/expand-cgroup.c event count doesn't match event name doesn't match: cgroup name doesn't match: failed to expand event group libpfm was not enabled failed to parse '%s' metric Event expansion for cgroups expand_cgroup_events evlist__open() failed Convert perf time to TSC tsc_is_supported TSC support perf_time_to_tsc Perf time to TSC >/dev/null 2>&1 Command: %s Failed with return value %d dlfilter-test-api-v%d.so dlfilter to test v%d C API /tmp/dlfilter-test-%u-prog.c /tmp/dlfilter-test-%u-prog %s/dlfilters/%s dlfilters not found Checking for gcc gcc --version gcc not found dlfilters path: %s Failed to write test C file cat %s ; echo gcc -g -o %s %s objdump -x -dS %s Failed to write sample %s script -i %s -D dlfilter C API FAILED sigaction(): %s FAILED pthread_create(): %s misfired signal? tests/sigtrap.c enable failed pthread_join() failed disable failed unexpected sigtraps unexpected si_addr Sigtrap sigtrap Pass Fail amd_l3 amd_df hv_24x7 Event groups event_groups machine__new_host() failed! Testing %s Failed to create map! dso__load() failed! DSO has no symbols! Overlapping symbols: Zero-length symbol: Symbols 123 empty string tests/util.c no match 124 replace 1 abcabc efbcefbc replace 2 longlong longlongbclonglongbc replace long util got: %s 0x%lx, expecting %s failed to get unwind sample unwind failed Could not get machine Failed to create kernel maps Could not init machine Could not get thread test__arch_unwind_sample test_dwarf_unwind__thread test_dwarf_unwind__compare bsearch test_dwarf_unwind__krava_3 test_dwarf_unwind__krava_2 test_dwarf_unwind__krava_1 test__dwarf_unwind Test dwarf unwind noploop thloop cat PERF_PAGER pager. tui. gtk. perf-help PERF_EXEC_PATH libexec/perf-core /usr PERF_CONFIG -vv --exec-path --html-path --paginate --no-pager --debugfs-dir --buildid-dir --debugfs-dir= --list-cmds --list-opts --%s --debug --debug-file Unknown option: %s FATAL: unable to run '%s' archive c2c ftrace %-*s %s %-*s %s,%s %-*s %.*s%lx (%r %s: unsupported arch %s ^blr?$ ↓ ↑ ← → sub dec Sorted summary for file %s Nothing higher than %1.1f%% %7.2f %-*s *%lx [35m %7lu %11lu %*lx: # +%.2f%% -%.2f%% (p:%.2f%%) // %s %*s: %*s: %-*d %s %s: addr=%#lx bez bnez bnezad bhsz bhz blsz blz jmpi bsr rts jsri jsr brinc bper bnl bnl+ bnl- bnla bnla+ bnla- bras brasl basr lrl lgrl llgfrl strl stgrl %*[^,],%u,%u,%u AuthenticAMD annotate. annotate.offset_level annotate.hide_src_code annotate.jump_arrows annotate.show_linenr annotate.show_nr_jumps annotate.show_nr_samples annotate.show_total_period annotate.use_offset annotate.disassembler_style annotate.addr2line annotate.demangle annotate.demangle_kernel (%rip) Percent %6.2f %6lu %11lu %*.2f %lu(%lu/%lu) Cycle(min/max) %-*s %lx: %*lx: --prefix-strip= --prefix -S --no-show-raw-insn -l -M to be implemented Executing: %s Failure starting to run %s Error running %s No output from %s nop nopl nopw jirl bltu bgeu bgezal bltzal bgtzal blezal beqzal bnezal bgtzl bltzl bgezl blezl jialc beql bnel jal jr jmpl retl mov account_cycles failed %d ^/[^:]+:([0-9]+) Invalid BPF file: %s. util/annotate.h %-*.*s---- h->nr_samples %*s: %lu %*lx: %lu %s.annotation %s() %s Event: %s %.*s %s Couldn't annotate %s: %s %s, [percent: %s] %s() %s local hits global hits local period global period csky bwlq riscv64 loongarch adc andps btr cmovbe cmove cmovae cmpxch cmpxchg divsd divss imul ja jae jb jbe jc jcxz je jecxz jg jge jl jle jna jnae jnb jnbe jnc jne jng jnge jnl jnle jno jnp jns jnz jo jp jpe jpo jrcxz js jz lea movapd movaps movdqu movss movsb movsw movsl movupd movups movzb movzw movzl mulss paddq pcmpeqb por rcl sbb sete tzcnt ucomiss vaddsd vandpd vmovdqa vmovq vmovsd vmulsd vorpd vsubsd vucomisd xadd xbegin xor xorpd xorps [%s -> %s] [%7lx -> %7lx] %.1fM %.1fK %1d Sampled Cycles% Sampled Cycles Avg Cycles% Avg Cycles [Program Block Range] (%d:%d):(%d:%d) %s/sys/kernel/notes %s/%s/%s/kallsyms %s/.build-id/%.2s/%s vdso %s/.build-id/ Error in lsdir(%s): %d /usr/lib/debug/.build-id/ %.2s/%s.debug Can't read link: %s Found %d SDTs in %s util/build-id.c /etc/perfconfig PERF_CONFIG_NOGLOBAL core. core.proc-map-timeout core.addr2line-timeout hist. ui.show-headers call-graph. buildid. buildid.dir Invalid buildid directory! stat. stat.big-num stat.no-csv-summary stat.bpf-counter-events PERF_CONFIG_NOSYSTEM %s.%s Missing value for '%s' PERF_BUILDID_DIR %s.XXXXXXx no branch trace begin / %s %s / trace end unconditional jump software interrupt return from interrupt return from system call asynchronous branch hardware interrupt transaction abort trace begin vm entry vm exit duplicated bpf prog info %u duplicated btf %u mips64 parisc64 s390x sparc64 pmu mappings not available %u:%s sun4u sa110 Old New %s bytes: INVALID exec %s: %s:%d/%d %u/%s: %lu/%#lx%s cgroup: %llu %s nr: pid: %u tid: %u hw_id: %#llx OUT preempt IN OUT prev %s %s pid/tid: %5d/%-5d type %u, flags %u, id %u %llx old len %u new len %u lost %llu <not found> [hypervisor] ...... dso: %s TOTAL LOST UNTHROTTLE SAMPLE MMAP2 ITRACE_START LOST_SAMPLES SWITCH_CPU_WIDE NAMESPACES KSYMBOL BPF_EVENT TEXT_POKE AUX_OUTPUT_HW_ID EVENT_TYPE TRACING_DATA BUILD_ID FINISHED_ROUND ID_INDEX AUXTRACE_INFO AUXTRACE AUXTRACE_ERROR THREAD_MAP CPU_MAP STAT_CONFIG STAT_ROUND EVENT_UPDATE TIME_CONV FEATURE COMPRESSED FINISHED_INIT kernel/perf_event_mlock_kb mmap size %zuB %s && common_pid != %d failed to create 'ready' pipe failed to create 'go' pipe perf-exec unable to read pipe unable to write to pipe Hint: Shouldn't get there Weak group for %s/%d failed fifo: \0 Message from ctl_fd: "%s%s" disable is snapshot failed: wrong command Event %s %s -F ctlfd: unsupported %d , %u - %u %n timerfd_create failed: %s timerfd_settime failed: %s %s... mem-loads-aux %-32s %s %s/%s/comm oprofiled ppp user_time system_time ftrace:function unknown-hardware %s-%s-%s unknown-ext-hardware-cache-op invalid-cache unknown-software raw 0x%lx unknown tracepoint mem:0x%lx: unknown attr type: %d anon group %s { , %s offcpu-time (%s) && (%s) %.60s perf_event_attr: switching off bpf_event switching off ksymbol switching off write_backward switching off clockid switching off use_clockid switching off cloexec flag switching off mmap2 switching off sample_id_all switching off group read Opening: %s broken group leader for %s user stack dump failure %s%su fs/selinux/enforce wrong clockid (%d). Reference prefetch prefetches speculative-read speculative-load L1-dcache l1-d L1-data L1-icache l1-i l1i L1-instruction dTLB d-tlb Data-TLB iTLB i-tlb Instruction-TLB bpu btb bpc page-faults context-switches cpu-migrations alignment-faults emulation-faults cache-references bus-cycles ref-cycles sample_freq %s{ %s=%lu (not a tracepoint) (no trace field) trace_fields: %s <- %c%16lx (inlined) PERF_TYPE_HARDWARE PERF_TYPE_BREAKPOINT PERF_TYPE_RAW PERF_TYPE_HW_CACHE PERF_TYPE_TRACEPOINT PERF_TYPE_SOFTWARE PERF_COUNT_HW_INSTRUCTIONS PERF_COUNT_HW_CPU_CYCLES PERF_COUNT_HW_REF_CPU_CYCLES PERF_COUNT_HW_BUS_CYCLES PERF_COUNT_HW_BRANCH_MISSES PERF_COUNT_HW_CACHE_MISSES PERF_COUNT_SW_CPU_CLOCK PERF_COUNT_SW_CGROUP_SWITCHES PERF_COUNT_SW_BPF_OUTPUT PERF_COUNT_SW_DUMMY PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_CPU_MIGRATIONS PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_TASK_CLOCK PERF_COUNT_HW_CACHE_L1D PERF_COUNT_HW_CACHE_L1I PERF_COUNT_HW_CACHE_LL PERF_COUNT_HW_CACHE_DTLB PERF_COUNT_HW_CACHE_ITLB PERF_COUNT_HW_CACHE_BPU PERF_COUNT_HW_CACHE_NODE PERF_COUNT_HW_CACHE_OP_READ PERF_COUNT_HW_CACHE_OP_WRITE %lu (%s) %#lx (%s) %#lx (%s | %s | %s) CALLCHAIN STREAM_ID BRANCH_STACK REGS_USER STACK_USER IDENTIFIER REGS_INTR TOTAL_TIME_ENABLED TOTAL_TIME_RUNNING read_format exclude_idle inherit_stat enable_on_exec mmap_data exclude_host exclude_guest exclude_callchain_kernel exclude_callchain_user mmap2 comm_exec use_clockid context_switch write_backward ksymbol bpf_event aux_output text_poke build_id inherit_thread remove_on_exec { bp_addr, config1 } { bp_len, config2 } HV ANY_CALL ANY_RETURN IND_CALL ABORT_TX IN_TX NO_TX CALL_STACK IND_JUMP NO_FLAGS NO_CYCLES TYPE_SAVE HW_INDEX PRIV_SAVE COUNTERS branch_sample_type sample_regs_user sample_stack_user sample_regs_intr aux_watermark sample_max_stack aux_sample_size sig_data %p: %s mask[%zd]: %s event syntax error: %s'%s' %*s\___ %s %s failed to add tracepoint <no help> *? expected numeric value expected string value hardware-cache No PMU found for '%s' Initial error: nr_addr_filters unknown term %s=%#lx valid terms: %s,%s valid terms: %s invalid branch sample type expected 0 or 1 Invalid term_type %s// Attempt to add: %s %s -> %s/%s/ fake_pmu <sysfs term> branch_type stack-size no-overwrite driver-config percore aux-output aux-sample-size metric-id legacy-cache cgroup-switches cpu-cycles branch-instructions idle-cycles-frontend idle-cycles-backend Tracepoint event %s:%s@%s %s@%s(%.12s) SDT event %s/%s/ Hardware cache event tool Tool event OR Hardware event Software event rNNN Raw hardware event descriptor mem:<addr>[/len][:access] Hardware breakpoint riscv regs0 regs1 regs2 regs3 regs4 regs5 regs6 regs7 regs8 regs9 %r1 %r2 %r3 %r4 %r5 %r6 %r7 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 $1 $2 $3 $4 $5 $6 $7 $8 $9 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $20 $21 $22 $23 $24 $25 $28 $29 $30 $31 nip orig_r3 ccr softe sier mmcra mmcr0 mmcr1 mmcr2 mmcr3 sier2 sier3 pmc1 pmc2 pmc3 pmc4 pmc5 pmc6 sdar siar t0 s10 s11 t3 t5 R8 R9 R10 R11 R12 R13 R14 R15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 /bad-path/ devices/system/cpu/smt/active || != && %s %s %d file:// %lu%s ], (target_pid: %s (target_tid: %s (uid: %s (all , CPU%s: %s) , %d CPU%s) Usage: %s /usr/lib/debug .debug%s dso open failed: %s failed to get fd limit dso cache fstat failed: %s [guest.kernel.kallsyms [%.*s] NOT dso: %s ( %sloaded, /tmp/perf-%d.map Invalid ELF file Can not read build id Mismatching build id Decompression failure %.0s%s %s/.debug/%s /usr/lib/debug%s/%s [JIT] tid %d Duplicated dso name: %s %-40s %s acpi_idle_do_entry arch_cpu_idle cpu_startup_entry idle_cpu intel_idle intel_idle_ibrs default_idle native_safe_halt enter_idle exit_idle mwait_idle mwait_idle_with_hints poll_idle ppc64_runlatch_off pseries_dedicated_idle_sleep psw_idle psw_idle_exit /boot/vmlinux __entry_SYSCALL_64_trampoline [guest.kernel].%d [kernel].%d _stext Using %s for kernel data %s: %s %#lx-%#lx compat_SyS %s sym:%s end:%#lx @@ Using %s for symbols (deleted) problems parsing %s list Invalid file: %s /boot/vmlinux-%s /lib/modules/%s/build/vmlinux %lx-%lx %c %s [%#lx] [m never auto dumb color.ui TopdownL No_group found event %s ,metric-id= /metric-id= ,-=@ }:W Parsing metric events '%s' Matched metric-id %s to %s metric expr %s for %s __threshold__ %s/level %s/coherency_line_size %s/number_of_sets %s/ways_of_associativity %s/type %s/size %s/shared_cpu_list # hostname : %s # os release : %s # arch : %s # cpudesc : %s # nrcpus online : %u # nrcpus avail : %u # perf version : %s # clockid frequency: %lu MHz # hybrid cpu system: # %s cpu list : %s , %s = %s # total memory : %llu kB # cpuid : %s # contains stat data # CPU cache info: L%d %-15s %8s [%s] Zstd # sibling sockets : %s # sibling dies : %s # sibling threads : %s # btf info of id %u # %3lu [%s]: %s # time of first sample : %s # time of last sample : %s # group: %s{%s # pmu mappings: %s%s = %u # node%u cpu list : # cmdline : %s\' broken or missing trace data # %s pmu capabilities: # reference time disabled %F %T %s.%06d # clockid: %s (%u) legacy perf.data format %s/devices/system/node/ node%u memory%u ibs_op /proc/meminfo MemTotal: %*s %lu util/header.c branch_counter_nr branch_counter_width group desc not available {anon_group} invalid group desc # event : name = %s, , id = { failed to write perf header failed to write feature %s /proc/cpuinfo model name /sys/devices/system/cpu/cpu%d # captured on : %s # header version : %u # data offset : %lu # data size : %lu # feat offset : %lu # missing features: magic/endian check failed endian/magic failed incompatible file format ... id: %llu ... scale: %f ... unit: %s ... name: %s ... failed to get cpus ... unknown type %s: reading input file HOSTNAME OSRELEASE NRCPUS CPUDESC TOTAL_MEM CMDLINE EVENT_DESC CPU_TOPOLOGY NUMA_TOPOLOGY PMU_MAPPINGS GROUP_DESC SAMPLE_TIME MEM_TOPOLOGY CLOCKID DIR_FORMAT BPF_PROG_INFO BPF_BTF CPU_PMU_CAPS CLOCK_DATA HYBRID_TOPOLOGY flat fractal folded Chain comparison error callee dump-size print-type Invalid callchain mode: %s Invalid callchain order: %s print-limit %s: not enough memory %s %s%s (calltrace) %s%s:%.1f%% %s%s:%ld avg_cycles # %*s %*s %*s %*s %*s Raw %*d %*d %*s %*lx %*lu # %*s %*s %*d %*d %04x: debug_file not set [%s.%06lu] [%13lu.%06lu] Obtained %zd stack frames. ordered-events stderr data-convert perf-event-open Thread init failed thread %d _edata _etext %s: cannot open %s dir build %s/proc/modules %s/proc/version Linux version %s/lib/modules/%s [guest.kernel.kallsyms.%d] [guest.kernel.kallsyms] [guest/%d] Can't access file %s : id:%llu: lost:%llu : id:%lu: lost samples :%llu bpf_trampoline_ bpf_dispatcher_ [0] %s [%d] %s Threads: %u [kernel.vmlinux] _entry_trampoline __entry_trampoline_start [guest.kernel] %s/%s/proc/kallsyms __sched_text_start __sched_text_end __lock_text_start __lock_text_end _text /data/app-lib/ /system/lib/ APP_ABI APK_PATH %s/libs/%s/%s NDK_ROOT APP_PLATFORM bpf_prog_ %s with build id %s not found Failed to open %s , continuing without symbols %lx-%lx %lx %s Map missing from maps overlapping maps: Map: %s: %p not on the pstack! %s: top=%d, overflow! %s: underflow! : unhandled! Couldn't decompress data decomp (B): %zd to %zd failed to mmap file %#lx@%s [%#x]: event: %d -1 -1 %#lx [%#x]: PERF_RECORD_%s .... %-5s 0x%016lx ... LBR call chain: nr:%lu ..... %2d: %016lx ... FP chain: nr:%lu ... branch stack %s: nr:%lu ... branch callstack ..... %2lu: %016lx ... weight: %lu ,0x%x . data_src: 0x%lx .. phys_addr: 0x%lx .. data page size: %s .. code page size: %s ... transaction: %lx ... sample_read: ...... time enabled %016lx ...... time running %016lx .... group nr %lu ..... id %016lx, value %016lx , lost %lu : %d %d %s %llu ... time enabled : %llu ... time running : %llu ... id : %llu ... lost : %llu non matching sample_type non matching sample_id_all non matching read_format Cannot read kernel map failed to read event header bad event header size failed to read event data Sorting events... Processing events... Aggregated stats:%s Invalid cpu_list # ======== # ======== # Too big: nr %zu max_nr %zu Too big2: nr %zu max_nr %zu nr: %zu ... id: %llu idx: %llu cpu: %lld tid: %lld machine_pid: %lld vcpu: %llu 32-bit 64-bit event= event=%x NNPA_ALL CRYPTO_ALL cpum_cf L2Miss 1 L2Miss 0 uOps OpBrnMisp 1 OpBrnMisp 0 OpBrnTaken 1 OpBrnTaken 0 OpReturn 1 OpReturn 0 CacheHitSt 1=O-State CacheHitSt 0=M-state L1TlbPgSz 4KB L1TlbPgSz 1GB L1TlbPgSz 2MB IcMiss 0 IcMiss 1 L1TlbPgSz RESERVED L1TlbPgSz 16KB IbsFetchLinAd: %016llx IbsFetchPhysAd: %016llx L3MissOnly %d IbsOpRip: %016llx L2Miss %d OpDcMissOpenMemReqs %2d OpMemWidth %2d bytes IbsDCLinAd: %016llx IbsDCPhysAd: %016llx IbsBrTarget: %016llx %u:%9s ibs_fetch zen4_ibs_extensions %*[^,],%u,%u problem parsing cpuid DataSrc 1=(reserved) DataSrc 2=Local node cache DataSrc 3=DRAM DataSrc 4=Remote node cache DataSrc 5=(reserved) DataSrc 6=(reserved) DataSrc 7=Other DataSrc 4=(reserved) DataSrc 6=Long-latency DIMM DataSrc 8=Extension Memory DataSrc 9=(reserved) DataSrc 10=(reserved) DataSrc 11=(reserved) munmap rt_sigreturn sched_yield mincore shmget shmat shmctl dup dup2 pause alarm shutdown vfork semget semop semctl shmdt msgget msgsnd msgrcv msgctl fdatasync getdents getcwd fchdir rename rmdir creat symlink readlink fchmod fchown lchown gettimeofday getrusage sysinfo ptrace getuid syslog getgid setuid setgid geteuid getegid setpgid getpgrp setsid setreuid setregid getgroups setgroups setresuid getresuid setresgid getresgid setfsuid setfsgid capget capset rt_sigpending rt_sigtimedwait rt_sigsuspend sigaltstack utime mknod uselib personality ustat fstatfs getpriority setpriority sched_setparam sched_getparam sched_getscheduler sched_get_priority_max sched_get_priority_min sched_rr_get_interval mlock munlock munlockall vhangup modify_ldt pivot_root adjtimex chroot acct settimeofday reboot sethostname setdomainname iopl ioperm create_module delete_module get_kernel_syms query_module quotactl nfsservctl getpmsg putpmsg afs_syscall tuxcall security readahead lsetxattr fsetxattr lgetxattr fgetxattr llistxattr flistxattr lremovexattr fremovexattr sched_setaffinity set_thread_area io_setup io_destroy io_getevents io_submit io_cancel get_thread_area lookup_dcookie epoll_ctl_old epoll_wait_old remap_file_pages getdents64 restart_syscall semtimedop fadvise64 timer_create timer_settime timer_gettime timer_getoverrun timer_delete clock_settime clock_getres utimes vserver mbind set_mempolicy get_mempolicy mq_open mq_timedsend mq_timedreceive mq_notify mq_getsetattr kexec_load add_key request_key ioprio_set ioprio_get inotify_rm_watch migrate_pages faccessat unshare set_robust_list get_robust_list tee vmsplice move_pages signalfd timerfd_create fallocate timerfd_settime timerfd_gettime accept4 signalfd4 epoll_create1 dup3 inotify_init1 fanotify_init fanotify_mark clock_adjtime syncfs setns getcpu process_vm_readv process_vm_writev finit_module sched_setattr sched_getattr memfd_create kexec_file_load execveat userfaultfd membarrier mlock2 copy_file_range preadv2 pwritev2 io_pgetevents rseq pidfd_send_signal io_uring_setup io_uring_enter io_uring_register open_tree fsopen pidfd_open clone3 close_range openat2 pidfd_getfd faccessat2 process_madvise epoll_pwait2 mount_setattr quotactl_fd landlock_create_ruleset landlock_add_rule landlock_restrict_self memfd_secret process_mrelease futex_waitv set_mempolicy_home_node cachestat fchmodat2 map_shadow_stack futex_wake futex_requeue statmount listmount lsm_get_self_attr lsm_set_self_attr lsm_list_modules queue_event nr_events %u empty queue max_timestamp last_flush out of order event FINAL HALF TOP TIME Tgid: NStgid: /proc/%d/ns/mnt /proc/%d/status nsinfo refcnt unbalanced util/namespaces.c /proc/self/status uts %d/task/%d/comm Thread %d %s /proc/%s %d thread%s: %s/%d/comm input in flex scanner failed bad buffer in yy_scan_bytes() Bad modifier uncore_ Bad event or PMU Bad event name parser error %s/events/%s.snapshot %s/events/%s.per-pkg %s/events/%s.unit %s/events/%s.scale long_desc topic no value assigned for term Invalid sysfs entry %s=%s value too big for format events/%s Cannot parse alias %s: %d %s/events Cannot set up %s PERF_CPUID Using CPUID %s Failure to duplicate terms %.*s/%s ,%s=%s %G%s kprobe caps caps/max_precise Unexpected event %s/%s/ cpu_ Kernel PMU event Cannot open %s for output ]]> </style> </defs> <g> </g> %.1f us %.1f ms <desc>Blocked on: %s</desc> blocked sample_hi waiting WAITING <desc>Waiting on: %s</desc> CPU %i c%i %9lli %6lli Mhz %6.2f Ghz <desc>%s</desc> Disk Network Sync Poll Running Deeper Idle Deepest Idle process2 Sleeping Waiting for cpu Blocked on IO </svg> topology: no memory Can't read '%s' writing file size failed can't read directory '%s' can't write count %s/%s/format Can't make temp file 0.6 can't read '%s' can't write header_page can't write header_event can't get tracing/events printk_formats saved_cmdlines Python Perl common_lock_depth common_preempt_count %d %16s HI_SOFTIRQ NET_TX_SOFTIRQ NET_RX_SOFTIRQ BLOCK_SOFTIRQ IRQ_POLL_SOFTIRQ TASKLET_SOFTIRQ SCHED_SOFTIRQ HRTIMER_SOFTIRQ RCU_SOFTIRQ HRTIMER_NORESTART HRTIMER_RESTART repiping input file no data repiping input file string no trace data in the file trace_event__init failed did not read header page did not read header event error reading ftrace file. error parsing ftrace file. error parsing event file. error reading saved cmdlines %7d:%-*.*s [other] %*.*d %lu/0x%lx %-*llu %-*u [%c] %-#*llx %-5.2f [%5.1f%%] %-5s %2s %*.*s SVE [e] %s [p] %s [.] %s %-*hd :%lx [%c] %-#.*llx [%c] %s+0x%llx %-#*llx %c %s %+d (%s) local_p_stage_cyc local_ins_lat unsupported field option %s trace_fields Cannot find event: %s %s is not a tracepoint event # %s: %s sym_from sym_to dso_from dso_to addr_from addr_to Invalid --sort key: `+' overhead overhead_children {}, Invalid --sort key: `%s' Invalid --fields key: `+' overhead_sys overhead_us overhead_guest_sys overhead_guest_us symbol_daddr dso_daddr symbol_iaddr symbol_from symbol_to mispredict in_tx srcline_from srcline_to srcfile local_weight symbol_size dso_size cgroup_id local_retire_lat simd typeoff Data Type Offset Data Type DSO size Symbol size Transaction Branch in transaction Transaction abort Code Page Size Data Page Size Data Physical Address Blocked Data Cacheline Memory access TLB access Locked Data Object Code Symbol Data Symbol Local Pipeline Stage Cycle Local INSTR Latency Local Weight Branch Mispredicted Basic Block Cycles Target Address Source Address Target Symbol Source Symbol Target Shared Object Source Shared Object Trace output Socket Cgroup cgroup id (dev/inode) Parent symbol Source File IPC [IPC Coverage] To Source:Line From Source:Line Symbol Offset Simd Pid:Command comm,dso,symbol %s stats: %16s events: %10d , UID: %s , Thread: %s(%d) , Thread: %s , DSO: %s , Processor Socket: %d %d Hz, relative Invalid percentage: %s hist.percentage kcore_dir__[1-9]* kernel/perf_event_max_stack kernel/nmi_watchdog data.* kernel/perf_event_paranoid /proc/version_signature %d.%d.%d tips.txt Tip: %s /proc/self/exe DEBUGINFOD_URLS DEBUGINFOD_URLS=%s /proc/%d/root %s/devices/system/cpu/present physical_package_id die_id core_id cpu_map not initialized %s: calloc failed %s/devices/system/node cpu%u %s%d-%d cpumask list: %s Error creating CPU topology %s/devices/system/node/online %*s %*d %31s %lu MemFree: no access to cgroup %s {}[]()|*+?^$ no cgroup matched: %s PID/TID switch overriding CPU PID/TID switch overriding UID UID switch overriding CPU UID switch overriding SYSTEM BPF switch overriding CPU BPF switch overriding PID/TID BPF switch overriding UID BPF switch overriding THREAD Invalid User: %s /proc/self/maps cannot open maps %p-%p r-xp %*x %*x:%*x %*u %n perf-read-vdso32 perf-read-vdsox32 %s: %lu %lu %lu Invalid CPU %d for event %s. INTERVAL ... time %llu, type %s ... aggr_mode %d ... scale %d ... interval %u CPUs utilized %8.3f Invalid tool event 'max' Unknown tool event '%s' of all branches %7.2f%% insn per cycle %7.2f stalled cycles per insn of all dTLB cache accesses frontend cycles idle of all LL-cache accesses of all L1-dcache accesses of all L1-icache accesses of all iTLB cache accesses of all cache refs backend cycles idle %s %s_%d %s %s %8.1f %8.2f %c/sec "metric-value" : "%f", "metric-unit" : "%s" "variance" : %.2f, %s%.2f%% ( +-%6.2f%% ) of all time, "core" : "S%d-D%d-C%d" "cpu" : "%d", "thread" : "%s-%d", S%d-D%d-C%d%s%d%s S%d-D%d-L%d-ID%d%s%d%s S%d-D%d%s%d%s S%d%s%d%s N%d%s%d%s S%d-D%d-C%d%s CPU%d%s %s-%d%s S%d-D%d-C%d S%d-D%d-L%d-ID%d S%d-D%d S%d N%d S%d-D%d-C%d CPU%-*d %*s-%-*d %-*s %*d { %s%lu%s%.2f (%.2f%%) # %s"%s" : "%s" "cgroup" : "%s", "metricgroup" : "%s"} <not counted> <not supported> %.2f%s %.0f%s %'*.2f %'*.0f %*.0f "counter-value" : "%f", "counter-value" : "%s", "unit" : "%s", "event" : "%s", %s [%s] "interval" : %lu.%09lu, %lu.%09lu%s %6lu.%09lu #%*s %-*s cpus #%*s %-*s #%*s %*s-%-*s #%*s %*s %*s events 'BPF program(s) %s 'system wide 'CPU(s) %s process id '%s thread id '%s (%d runs) "metric-value" : "none" %17.9f seconds time elapsed %17.9f seconds user %17.9f seconds sys %17.*f %*s# Final result: %17.*f (%+.*f) comm-pid cpu, socket,cpus, die,cpus, cache,cpus, core,cpus, comm-pid, node, instructions:u %s:%u ??:0 .debug_line -f %c%s %016lx , /tmp/perf- %s[%lx] cannot open source file %s cannot mmap source file %s /proc/%u/ns/%s /proc/%d/task/%d/status couldn't open %s Name: PPid: VmPeak: Threads: process synth event failed failed to open directory: %s %s/proc/%d/task/%d/maps %s/proc/%d/task Synthesizing id index Couldn't synthesize attrs. Couldn't synthesize config. Error writing feature Unknown file found failed to open %s: %s (try 'perf record' first) failed to open %s : %s util/data.c %s/data.%d %s/data Failed to rename %s to %s Failed to lseek to %zu: %s %s/kcore_dir %s/kcore_dir/kallsyms %s/kcore_dir__%d/kallsyms ... Time Shift %llu ... Time Muliplier %llu ... Time Zero %llu ... Time Cycles %llu ... Time Mask %#llx ... Cap Time Zero %d ... Cap Time Short %d Error flushing thread stack! __x86_indirect_thunk_ ▁ ▂ ▃ ▄ ▅ ▆ ▇ █ hot chain %d: cycles: %ld, hits: %.2f%% %35s %35s %35s %35s hot chain pair %d: --------------------------- [ Matched hot streams ] %s 0x%lx/0x%lx%s%s %s 0x%lx%s%s #%d 0x%lx %c %s which is near %s Symbol '%s' not found. Kernel symbol lookup: Uninitialized auxtrace_mmap failed to mmap AUX area AUX area mmap length %zu No AUX area event to sample type: %u itrace.debug-log-buffer-size unknown AUX %s error type %u time %lu.%09llu time 0 machine_pid %d vcpu %d %u %s errors instruction trace tracestop , Address filter: %s TNT %s no ip %s 0x%llx %s CTC 0x%x FC 0x%x MODE.Exec %s IF:%d %lld MODE.TSX %s TXAbort:%u InTX:%u %s 0x%llx (NR=%d) PTWRITE %s 0x%llx IP:0 %s 0x%llx IP:1 %s IP:0 %s IP:1 PWRE PWRX BBP %s SZ %s-byte Type 0x%llx BIP %s ID 0x%02x Value 0x%llx EVD %s Type 0x%02x Payload 0x%llx %s 0x%llx (%d) Bad Packet! PAD TIP.PGD MTC TIP CYC PSB CBR TraceSTOP OVF EXSTOP <bad> %s %s%d Call Jcc Jmp Loop IRet Int Syscall Sysret VMentry Erets Eretu .log Dumping debug log buffer End of debug log buffer dump %08lx: Bad instruction! Getting more data No more data Reference timestamp 0x%lx ERROR: Bad packet Scanning for PSB Setting timestamp %s to 0x%lx %s at 0x%lx ERROR: Never-ending loop ERROR: Internal error Wraparound timestamp Suppressing bad timestamp Timestamp out of range ERROR: Unexpected packet ERROR: Buffer overflow ERROR: Missing TIP after FUP Omitting PGE ip 0x%lx Setting IP Emulated ptwrite detected Skipping zero TIP.PGE Skipping zero FUP ERROR: Missing FUP after BEP ERROR: Missing FUP after CFE ERROR: Too many EVD packets timestamp: mtc_shift %u timestamp: tsc_ctc_mult %u timestamp: tsc_slip %#x Unknown error! Scanning for full IP ERROR: PSB without PSBEND Surprising PGE change in OVF! ERROR: TSC without TMA %s: last_mtc_ctc %#lx %s: last_ctc %#x %s: ctc_delta %#lx %s: delta %#lx %s: ctc %#x %s: new_ctc_delta %#lx %s: last_ctc_timestamp %#lx %s: fc %#x %s: expected_tsc %#lx ERROR: Missing VMCS VMCS: %#lx TSC Offset %#lx ERROR: Unknown VMCS Internal error Bad packet No more data Failed to get instruction Overflow packet Lost trace data Broken emulated ptwrite GenuineIntel,6,92, intel-pt.mispred-all intel-pt.max-loops intel-pt.cache-divisor %08x: Bad packet! ERROR: no guest machine ERROR: no guest thread ERROR: no thread perf,ptwrite switch: cpu %d tid %d perf_trace_sched_switch __perf_event_task_sched_out __switch_to switch_ip: %lx ptss_ip: %lx TSC %lx est. TSC %lx queue %u getting timestamp queue %u has no timestamp queue %u timestamp 0x%lx Bad AUX output hardware ID transactions cbr psb mwait pwre exstop pwrx evt iflag Max non-turbo ratio %lu Filter string len. %lu %s: bad filter string length Filter string %-20s%s Cap Event Trace %d TSC frequency %lu Maximum non-turbo ratio %u %s: %u range(s) PMU Type %ld Time Shift %lu Time Muliplier %lu Time Zero %lu Cap Time Zero %ld TSC bit %#lx NoRETComp bit %#lx Have sched_switch %ld Snapshot mode %ld Per-cpu maps %ld MTC bit %#lx MTC freq bits %#lx TSC:CTC numerator %lu TSC:CTC denominator %lu CYC bit %#lx %lx -> %lx %s Bad record! PMU Type %ld Time Shift %lu Time Muliplier %lu Time Zero %lu Cap Time Zero %ld Snapshot mode %ld l1d-miss l1d-access llc-miss llc-access tlb-miss tlb-access branch-miss remote-access COND-SELECT INSN-OTHER EXCEPTION-GEN RETIRED L1D-ACCESS L1D-REFILL TLB-ACCESS TLB-REFILL NOT-TAKEN LLC-ACCESS LLC-REFILL REMOTE-ACCESS ALIGNMENT SVE-PARTIAL-PRED SVE-EMPTY-PRED SVE-OTHER EVLEN %d FP AT EXCL AR SIMD-FP GP-REG UNSPEC-REG NV-SYSREG MTE-TAG MEMCPY MEMSET SG COND IND %s %lld %s 0x%llx el%d ns=%d VA 0x%llx PA 0x%llx ns=%d ch=%d pat=%x CONTEXT %s 0x%lx el%d %s %d TOT ISSUE XLAT TGT PBT OP-TYPE DATA-SOURCE Get packet error! Prefix Header DW0 Header DW1 Header DW2 Header DW3 Format Length T8 T9 auxtrace.dumpdir %s/aux.ctr.%02x %s/aux.smp.%02x %*[^,],%u , version supported <= %x Magic number %llx CPU %lld NR_TRC_PARAMS %llx TRCCONFIGR %llx TRCTRACEIDR %llx TRCIDR0 %llx TRCIDR1 %llx TRCIDR2 %llx TRCIDR8 %llx TRCAUTHSTATUS %llx TS_SOURCE %lld ETMCR %llx ETMTRACEIDR %llx ETMCCER %llx ETMIDR %llx Header version %llx Snapshot %llx any_call any_ret ind_call abort_tx no_tx cond ind_jmp no_flags no_cycles save_type hw_index priv -I --user-regs= available registers: Unknown option name '%s' LINES COLUMNS help.autocorrect this Did you mean %s? one of these ./%s dlopen failed for: '%s' filter_event filter_event_early perf_dlfilter_fns filter_description %39s%s List of available dlfilters: %s/dlfilters %s/devices/%s : available %-*s%-*s%s Fwd Yes N/A Data Addr |OP STORE PFETCH |LVL |SNP |TLB |LCK |BLK None HitM core, same node node, same socket socket, same board Uncached CXL I/O Any cache LFB/MAB PMEM HIT MISS Local RAM Remote RAM (1 hop) Remote RAM (2 hops) Remote Cache (1 hop) Remote Cache (2 hops) Walker Fault ldlat-loads cpu/mem-loads,ldlat=%u/P cpu/events/mem-loads ldlat-stores cpu/mem-stores/P cpu/events/mem-stores start time %lu, end time %lu start time %d: %lu, end time %d: %lu %lu.%06lu %lu.%09lu %Y%m%d%H%M%S %s%02u Error creating IDs for '%s' division by zero syntax error memory exhausted %s/firmware/acpi/tables/NFIT adding ref metric %s: %s %s not found lookup(%s): val %f processing metric: %s ENTRY parsing metric: %s %s failed to count #smt_on #core_wide #slots #has_pmem Unrecognized literal '%s' literal: %s = %f FAULT_ALGN FAULT_DATA FAULT_INST ARCH_1 ARCH_2 ARCH_3 ARCH_4 ARCH_5 UNCOND SYSRET COND_CALL COND_RET ERET SERROR # # Branch Statistics: COND_FWD %8s: %5.1f%% COND_BWD CROSS_4K CROSS_2M SPEC_WRONG_PATH NON_SPEC_CORRECT_PATH monotonic (not found) monotonic_raw boottime tai mono real %s error: '%s' [%d] = %d, [%d] = ERROR, .text %s: cannot get elf header. .note.gnu.build-id .notes .note .plt.got .rela.dyn %s@plt offset_%#lx@plt .plt.sec .rela.plt .rel.plt %s: cannot read %s ELF file. .gnu_debuglink .symtab .dynsym .opd adtx %s/kcore .note.stapsdt gelf_xlatetom : %s %s : cannot get elf header. .stapsdt.base .probes Failed to get cache from %s %s/probes Failed to open cache(%d): %s Opening %s write=%d README uprobe_events CONFIG_UPROBE_EVENTS=y kprobe_events CONFIG_KPROBE_EVENTS=y {k,u}probe_events strlist__add failed (%d) Writing event: %s Failed to write event: %s -:%s Failed to delete event: %s Cache open error: %d Cache read error: %d Failed to add probe caches Added probe cache: %d Failed to get sdt note: %d sdt_%s %s:%s=%s p:%s/%s %s:0x%llx (0x%llx) [sp, Allocation error arg%d=%s%s Cache committed: %d Writing cache: %s%s Removed cached event: %s list cache with filter: %s %s (%s): *type: * x8/16/32/64,* *place (kretprobe): * *ref_ctr_offset* *u]<offset>* *Create/append/* *\imm-value,* :s64 :s32 :s16 :s8 :u8 :u16 :u32 :u64 %return .gnu.linkonce.this_module Failed to find module %s. Rebuild with -g, %s is out of .text, skip it. %7d File read error: %s Debuginfo analysis failed. <%s@%s:%d> <%s:%d> Failed to open %s: %s +u %s%ld( %+ld( %s= %s%+ld __return .@ snprintf() failed: %d %s/kprobes/blacklist 0x%lx-0x%lx Blacklist: 0x%lx-0x%lx, %s Failed to init symbol map. Use vmlinux: %s machine__new_host() failed. Failed to init vmlinux path. Searching variables at %s Available variables at %s @<%s+%lu> (No matched variables) start line end line Line range is %d to %d Failed to split arguments. sdt_ ;=@+% %%%s ;: ;:+@% util/probe-event.c %s_L%d parsing arg: %s into name:%s user_access type:%s -.[ %s(%d), %s(%d) $params $vars Parsing probe_events: %s Group:%s Event:%s probe:%c -> %s:%s= %c:%s/%s 0x0 %s:0x%lx (0x%lx) %s%s0x%lx %s%s%s+%lu %-20s (on in %s with %s_%s Failed to make a group name. abs_%lx Found %d probe_trace_events. Probe point '%s' not found. Trying to use symbols. *?[ [$+-]* Failed to get a map for %s Failed to load symbols in %s \%ld DW_OP %x is not supported. converting %s in %s Var real type: %s (%x) Array real type: %s (%x) Probe point found: %s+%lu Expanding %s into: ustring b%d@%d/%zd %s type is %s. Out of memory error unsigned char %c%d Ignoring tail call from %s fname: %s, lineno:%d New line range: %d to %d [INV] [VAL] [EXT] Add new var: %s Error in strbuf Reversed line: %s:%d Matched function: %s [%lx] %s has no entry PC. Skipped .eh_frame \%lx found inline addr: 0x%jx Get %zd lines from this CU enum (function_type) void* (unknown_type) @<%s+[%lu-%lu ,%lu-%lu ]> ,) %r0 $0 $26 $27 %29 $hi $lo %g0 %g1 %g2 %g3 %g4 %g5 %g6 %g7 %o0 %o1 %o2 %o3 %o4 %o5 %sp %o7 %l0 %l1 %l2 %l3 %l4 %l5 %l6 %l7 %i0 %i1 %i2 %i3 %i4 %i5 %fp %i7 %f0 %f1 %f2 %f3 %f4 %f5 %f6 %f7 %f8 %f9 %f10 %f11 %f12 %f13 %f14 %f15 %f16 %f17 %f18 %f19 %f20 %f21 %f22 %f23 %f24 %f25 %f26 %f27 %f28 %f29 %f30 %f31 %f32 %f33 %f34 %f35 %f36 %f37 %f38 %f39 %f40 %f41 %f42 %f43 %f44 %f45 %f46 %f47 %f48 %f49 %f50 %f51 %f52 %f53 %f54 %f55 %f56 %f57 %f58 %f59 %f60 %f61 %f62 %f63 %c0 %c1 %c2 %c3 %c4 %c5 %c6 %c7 %c8 %c9 %c10 %c11 %c12 %c13 %c14 %c15 %a0 %a1 %a2 %a3 %a4 %a5 %a6 %a7 %a8 %a9 %a10 %a11 %a12 %a13 %a14 %a15 %pswm %pswa %gpr0 %gpr1 %gpr2 %gpr3 %gpr4 %gpr5 %gpr6 %gpr7 %gpr8 %gpr9 %gpr10 %gpr11 %gpr12 %gpr13 %gpr14 %gpr15 %gpr16 %gpr17 %gpr18 %gpr19 %gpr20 %gpr21 %gpr22 %gpr23 %gpr24 %gpr25 %gpr26 %gpr27 %gpr28 %gpr29 %gpr30 %gpr31 %msr %xer %link %ctr %dsisr %dar %x0 %x1 %x2 %x3 %x4 %x5 %x6 %x7 %x8 %x9 %x10 %x11 %x12 %x13 %x14 %x15 %x16 %x17 %x18 %x19 %x20 %x21 %x22 %x23 %x24 %x25 %x26 %x27 %x28 %x29 %lr %ip %pc %ax %dx %cx %bx %si %di %bp $stack Open Debuginfo file: %s cannot get the debug info variable has no type no pointer or no type type size is unknown (unknown type) unwind: resume unsupported '' WARNING: ui->thread is NULL unwind: Only supports local. unwind: Unspecified error. unwind: access_reg w %d unwind: can't read reg %d unwind: reg %d, val %lx unwind: no map for %lx .eh_frame_hdr \" \\ \b \f \r \t \u%04x "0x%lx" Sample resolution failed! Error opening output file! Error creating perf session! Symbol init error! "linux-perf-json-version": 1 "headers": { header-version %FT%TZ captured-on data-offset data-size feat-offset os-release cpu-desc nrcpus-online nrcpus-avail clock-time real-time perf-version cmdline "samples": [ %s.py import os import sys from Core import * def trace_begin(): print("in trace_begin") def trace_end(): print("in trace_end") def %s__%s( event_name, context, common_cpu, common_secs, common_nsecs, common_pid, common_comm, common_callchain, perf_sample_dict print(" " \ " %%u " %% \ ( flag_str(" %s__%s", "%s", %s) symbol_str(" )) if 'sym' in node: else: print() generated Python script: %s couldn't create Python tuple stat__%s can't find python handler %s error resizing Python tuple couldn't create Python list %s+0x%x trace_end unthrottle define_symbolic_field define_flag_field define_flag_value define_symbolic_value auxtrace_error binding sym_off sym_srcline Can't open python script "%s" __main__ perf_trace_context perf_script_context trace_begin failed to initialize export perf_db_export_mode perf_db_export_calls perf_db_export_callchains evsel_table machine_table comm_table comm_thread_table dso_table symbol_table branch_type_table sample_table call_path_table call_return_table context_switch_table synth_data bcrosyiABExghDt time_enabled time_running values datasrc datasrc_decode raw_buf mispred from_dsoname to_dsoname cpumode addr_correlates_sym addr_dso_map_end addr_dso_map_start addr_dso_bid addr_dso addr_symoff addr_symbol flags_disp insn_cnt cyc_cnt %s__%s trace_unhandled couldn't create Python dict common_cpu common_s common_ns common_comm common_callchain func_code __code__ co_argcount 1.3 Compressed file is corrupt Unknown error, possibly a bug rb lzma: read error: %s lzma: write error: %s lzma: failed %s [] void byte double boolean $SP$ $BP$ $RF$ $LT$ $GT$ $LP$ $RP$ $u20$ $u27$ $u5b$ $u5d$ $u7e$ jit marker trying : %s /jit- jit marker found: %s [anon: /memfd: %s/jitted-%d-%lu.so write ELF image %s cannot create jit ELF %s: %s injected: %s (%d) ELF initialization failed elf_begin failed cannot get ehdr cannot create section cannot get new data cannot get section header cannot allocate strsym failed to create EVP_MD_CTX elf_update 4 failed elf_update debug failed Overwrite existing hook: %s record_end record_start [bpf] bpf_trampoline_%lu bpf_dispatcher_%s -- kernel too old? # bpf_prog_info %u: can't get prog info: %s %s: mismatch in rec size CROSS_COMPILE riscv32 mips-unknown-linux-gnu- mipsel-linux-android- mips-linux-gnu- mips64-linux-gnu- mips64el-linux-gnuabi64- mips64-linux-gnuabi64- mipsel-linux-gnu- x86_64-pc-linux-gnu- x86_64-unknown-linux-gnu- i686-pc-linux-gnu- i586-pc-linux-gnu- i486-pc-linux-gnu- i386-pc-linux-gnu- i686-linux-android- i686-android-linux- x86_64-linux-gnu- i586-linux-gnu- sparc-unknown-linux-gnu- sparc64-unknown-linux-gnu- sparc64-linux-gnu- sh-unknown-linux-gnu- sh-linux-gnu- s390-ibm-linux- s390x-linux-gnu- riscv64-unknown-linux-gnu- riscv64-linux-android- riscv64-linux-gnu- riscv32-unknown-linux-gnu- riscv32-linux-android- riscv32-linux-gnu- powerpc-unknown-linux-gnu- powerpc-linux-gnu- powerpc64-unknown-linux-gnu- powerpc64-linux-gnu- powerpc64le-linux-gnu- aarch64-linux-android- aarch64-linux-gnu- arm-eabi- arm-linux-androideabi- arm-unknown-linux- arm-unknown-linux-gnu- arm-unknown-linux-gnueabi- arm-linux-gnu- arm-linux-gnueabihf- arm-none-eabi- arc-linux- arc-snps-linux-uclibc- arc-snps-linux-gnu- %s,%u,%u,%u$ %s-%u-%X-%X$ @ @ %lfGHz intel_bts %#llx:%s POUT %#lx:%s kvm:kvm_msr kvm:kvm_pio kvm:kvm_mmio gpa VMX Hygon SVM ioport kvm:kvm_entry kvm:kvm_exit MSR Access IO Port Access MMIO Access exit_reason vcpu_id VM-EXIT read_cr0 read_cr2 read_cr3 read_cr4 read_cr8 write_cr0 write_cr2 write_cr3 write_cr4 write_cr8 read_dr0 read_dr1 read_dr2 read_dr3 read_dr4 read_dr5 read_dr6 read_dr7 write_dr0 write_dr1 write_dr2 write_dr3 write_dr4 write_dr5 write_dr6 write_dr7 DE excp DB excp BP excp OF excp BR excp UD excp NM excp DF excp TS excp NP excp SS excp GP excp PF excp MF excp AC excp MC excp XF excp nmi vintr cr0_sel_write read_idtr read_gdtr read_ldtr read_rt write_idtr write_gdtr write_ldtr write_rt rdtsc rdpmc pushf popf rsm swint hlt invlpg invlpga task_switch ferr_freeze vmrun hypercall vmload vmsave stgi clgi skinit rdtscp icebp wbinvd xsetbv write_efer_trap write_cr0_trap write_cr4_trap write_cr8_trap invpcid npf avic_incomplete_ipi avic_unaccelerated_access vmgexit vmgexit_mmio_read vmgexit_mmio_write vmgexit_nmi_complete vmgexit_ap_hlt_loop vmgexit_ap_jump_table vmgexit_page_state_change vmgexit_guest_request vmgexit_ext_guest_request vmgexit_ap_creation vmgexit_hypervisor_feature invalid_guest_state EXCEPTION_NMI EXTERNAL_INTERRUPT TRIPLE_FAULT INIT_SIGNAL SIPI_SIGNAL INTERRUPT_WINDOW NMI_WINDOW TASK_SWITCH INVLPG RDPMC RDTSC VMCALL VMCLEAR VMLAUNCH VMPTRLD VMPTRST VMREAD VMRESUME VMWRITE VMOFF VMON CR_ACCESS DR_ACCESS IO_INSTRUCTION MSR_READ MSR_WRITE INVALID_STATE MSR_LOAD_FAIL MWAIT_INSTRUCTION MONITOR_TRAP_FLAG MONITOR_INSTRUCTION PAUSE_INSTRUCTION MCE_DURING_VMENTRY TPR_BELOW_THRESHOLD APIC_ACCESS EOI_INDUCED GDTR_IDTR LDTR_TR EPT_VIOLATION EPT_MISCONFIG INVEPT RDTSCP PREEMPTION_TIMER INVVPID WBINVD XSETBV APIC_WRITE RDRAND INVPCID ENCLS RDSEED PML_FULL XSAVES XRSTORS UMWAIT TPAUSE BUS_LOCK %eax Regex compilation error. +0 %.*s%.*s%.*s%.*s%.*s %rax %al %ah %ebx %rbx %bl %bh %ecx %rcx %cl %ch %edx %rdx %dl %dh %esi %rsi %sil %edi %rdi %dil %ebp %rbp %bpl %rsp %esp %spl %r8b %r8w %r8d %r9b %r9w %r9d %r10b %r10w %r10d %r11b %r11w %r11d %r12b %r12w %r12d %r13b %r13w %r13d %r14b %r14w %r14d %r15b %r15w %r15d Local Retire Latency uops_retired.slots cpu_core mem-ldst ibs_op// %s/mem-loads,ldlat=%u/P %s/events/mem-loads %s/mem-stores/P %s/events/mem-stores %s/devices/uncore_iio_%d devices/uncore_iio_%d/die%d %04x:%02hhx Mode iostat is not supported Failed to realloc memory %08x:%02hhx S%d-uncore_iio_%d<%04x:%02x> %6lu.%09lu%s%04x:%02x%s port, port %8.0f Inbound Read(MB) Inbound Write(MB) Outbound Read(MB) Outbound Write(MB) unwind: invalid reg id %d GenuineIntel, -%u caps/topa_multiple_entries psb_period %s psb_period %zu not %s: failed, error %d caps/mtc caps/mtc_periods ,mtc,mtc_period=%d caps/psb_cyc caps/psb_periods ,psb_period=%d format/pt format/branch ,pt,branch %s default config: %s noretcomp mtc_period max_nonturbo_ratio caps/event_trace cyc_thresh caps/cycle_thresholds Intel PT snapshot size: %zu JITDUMP_USE_ARCH_TIMESTAMP Intel BTS: TSC not available Intel BTS snapshot size: %zu failed to get stack map x86 hybrid x86 hybrid event parsing not hybrid AMD IBS via core pmu amd_ibs_via_core_pmu x86 Sample parsing x86_sample_parsing x86 bp modify bp_modify Intel PT intel_pt_pkt_decoder Intel PT packet decoder intel_pt_hybrid_compat Samples differ at 'ins_lat' arch/x86/tests/hybrid.c wrong hybrid type missing pmu unexpected pmu cpu_core/cycles/ {cpu-clock,cpu_core/cycles/} {cpu_core/cycles/,cpu-clock} cpu_core/r1a/ cpu_core/LLC-loads/ intel_pt_pkt_desc failed! eax = 0x%08x ebx = 0x%08x ecx = 0x%08x edx = 0x%08x Decoding failed! Decoding: Packet context changed! Decoded ok: CPU %d not found CPU %d OK failed to PTRACE_TRACEME tracee exited prematurely 1 failed to set dr7: %s failed to PTRACE_CONT: %s tracee exited prematurely 2 rip %lx, bp_1 %p failed to PTRACE_DETACH: %s modify test 1 failed arch/x86/tests/bp-modify.c failed to set breakpoint: %s modify test 2 failed Fail Pass libperf-gtk.so Error: Warning: %*.2f%% Self Overhead guest sys guest usr Children | Not enough memory! %s Bad callchain mode / # %s%-.*s %*sno entry >= %.2f%% %.10s end %16s events: %10d (%4.1f%%) colors. Press any key... Warning! medium green selected black yellow blue magenta white %s %s [Percent: %s] String not found! Press ESC to exit No source file location. Source file location: %s ENTER: OK, ESC: Cancel String: Search Invalid jump offset: %lx ui/browsers/annotate.c %*s%c %s lost: %lu/%lu drop: %lu/%lu [z] -c %s -S %s --time %s,%s # Samples: %lu of event '%s' %lu%c%s%s : %ld%c%schunks LOST! PWD <...> no entry >= %.2f%% Run scripts for all samples%s the Kernel %.*lx Annotate %s ui/browsers/hists.c out of into Collapse Expand Collecting samples... perf.hist.%d Couldn't write to %s: %s %s written! Verbosity level set to %d Symbol to show Percent Limit Invalid percent: %.2f Do you really want to exit? Zoom %s %s(%d) thread Zoom %s %s thread Browse map details Zoom %s Processor Socket %d with assembler with source Exit Available samples %*lx %*lx %c restart with -v to use Search by name/addr %s not found! scripts. Running %s Cannot run %s [c[H[J --inline -i perf script -s Show individual samples %s script %s -F +metric %s %s -F +insn --xed -F +srcline,+srccode perf script command %s script %s %s%s %s %s%s 2>&1 | less Press 'q' to exit Header information samples.context --tid --cpu %s: CPU %d tid %d --show-lost-events TUI initialization failed. ^(kB) Fatal Error -------- backtrace -------- Error: Warning: Help Enter: Yes, ESC: No %s [%s/%s] (sI) (sIs#) common_pc perf_sample_insn perf_set_itrace_options Set --itrace options. perf_sample_srcline perf_sample_srccode GenuineIntel-6-BE GenuineIntel-6-(3D|47) GenuineIntel-6-56 GenuineIntel-6-4F GenuineIntel-6-9[6C] GenuineIntel-6-CF GenuineIntel-6-5[CF] GenuineIntel-6-7A GenuineIntel-6-B6 GenuineIntel-6-A[DE] GenuineIntel-6-(3C|45|46) GenuineIntel-6-3F GenuineIntel-6-7[DE] GenuineIntel-6-6[AC] GenuineIntel-6-3A GenuineIntel-6-3E GenuineIntel-6-2D GenuineIntel-6-(57|85) GenuineIntel-6-BD GenuineIntel-6-A[AC] GenuineIntel-6-1[AEF] GenuineIntel-6-2E GenuineIntel-6-A7 GenuineIntel-6-2A GenuineIntel-6-8F GenuineIntel-6-AF GenuineIntel-6-55-[01234] GenuineIntel-6-86 GenuineIntel-6-8[CD] GenuineIntel-6-2C GenuineIntel-6-25 GenuineIntel-6-2F AuthenticAMD-23-[[:xdigit:]]+ AuthenticAMD-25-[[:xdigit:]]+ Fatal: Too long path: %.*s PREFIX %s%s/%s /usr/local/bin:/usr/bin:/bin Out of memory, realloc failed %s%s/ available %s in '%s' FRSX LESS /usr/bin/less /usr/bin/pager -%c --%s [=<n>] [<n>] <n> [=<%s>] [<%s>] <%s> [=...] [...] ... %*s%s %*s(not built-in because %s) Error: %s or: %s requires a value Error: switch `%c' %s Error: option `no-%s' %s Error: option `%s' %s is being ignored because %s is not available because %s takes no value isn't available is not usable cannot be used with %s Warning: switch `%c' %s Warning: option `no-%s' %s Warning: option `%s' %s expects a numerical value vasprintf failed no- %s%s %s [<options>] { help-all %sunknown option `%s' %sunknown switch `%c' exec %s: cd to %s failed (%s) Error: waitpid failed (%s) BUG: signal out of range: %d struct enum fwd typedef func_proto datasec decl_tag type_tag enum64 GPL libbpf_%u_%s_0x%zx_%d det_arg_ctx libbpf_mmap libbpf_nametest kretprobes kprobes uretprobes uprobes /sys/kernel/debug/tracing -:%s/%s /proc/%d/fdinfo/%d map_type: %u key_size: %u value_size: %u max_entries: %u map_flags: %i config:%d x64 __%s_sys_bpf %c:%s/%s %s+0x%zx libbpf_det_bind libbpf_global libbpf-placeholder-fd /boot/config-%s /proc/config.gz %zu bytes %.1f KiB %.1f MiB .so. LD_LIBRARY_PATH /usr/lib64:/usr/lib /lib/x86_64-linux-gnu /usr/bin:/usr/sbin /sys/kernel/tracing %s/events/%s/%s/id libbpf: map %td is "%s" <?> bpf_trace_opts v1.4 libbpf_tristate map-in-map inner prog-array value max_entries map_flags numa_node key_size value_size %s.inner pinning map_extra invalid func unknown#200100 %d: (%*d) call unknown#%d invalid func unknown#2002 btf_trace_ bpf_lsm_ bpf_iter_ %llx %c %499s%*[^ ] gen_loader_opts libbpf_prog_handler_opts .rodata /sys/fs/bpf static libbpf: map #%d: empty name. .kconfig libbpf: invalid map pointer libbpf: pinned map '%s' (mem buf) <? bpf_object_open_opts .debug_ .rel .BTF .BTF.ext license libbpf: license of %s is %s .data. .rodata. .rel.struct_ops .rel.struct_ops.link .rel.maps .bss .bss. .ksyms dummy_ksym libbpf: internal error at %d %lx-%zx bpf_perf_event_opts kretprobe bpf_kprobe_opts kretprobe/ %m[a-zA-Z0-9_.]+%li bpf_ksyscall_opts __%s_sys_%s __se_sys_%s ksyscall kretsyscall kretsyscall/ bpf_kprobe_multi_opts %llx %499s%*[^ ] kprobe.multi kretprobe.multi kretprobe.multi/ %m[a-zA-Z0-9_.*?] bpf_uprobe_multi_opts %m[^/]/%m[^:]:%m[^ ] uretprobe.multi uretprobe bpf_uprobe_opts !/ libbpf_%u_%s_0x%zx %c:%s/%s %s:0x%zx +%li%n uretprobe.s usdt usdt/%m[^:]:%m[^:]:%m[^:] bpf_tracepoint_opts netns xdp bpf_tcx_opts tcx bpf_netkit_opts netkit freplace bpf_iter_attach_opts bpf_netfilter_opts libbpf: Empty CPU range %d%n-%d%n <anon> LINUX_KERNEL_VERSION LINUX_HAS_BPF_COOKIE LINUX_HAS_SYSCALL_WRAPPER LINUX_ bpf_struct_ops_ exception_callback: arg:ctx pt_regs enum64_placeholder BTF is optional, ignoring. perf_buffer_opts perf_buffer_raw_opts raw_tracepoint raw_tp.w raw_tracepoint.w sk_reuseport/migrate sk_reuseport kprobe+ uprobe+ uprobe.s+ kretprobe+ uretprobe+ uretprobe.s+ kprobe.multi+ kretprobe.multi+ uprobe.multi+ uretprobe.multi+ uprobe.multi.s+ uretprobe.multi.s+ ksyscall+ kretsyscall+ usdt+ usdt.s+ tc/ingress tc/egress tcx/ingress tcx/egress classifier netkit/primary netkit/peer raw_tracepoint+ raw_tp+ raw_tracepoint.w+ raw_tp.w+ tp_btf+ fentry+ fmod_ret+ fexit+ fentry.s+ fmod_ret.s+ fexit.s+ freplace+ lsm+ lsm.s+ lsm_cgroup+ iter+ iter.s+ xdp.frags/devmap xdp/devmap xdp.frags/cpumap xdp/cpumap xdp.frags lwt_in lwt_out lwt_xmit lwt_seg6local sockops sk_skb/stream_parser sk_skb/stream_verdict sk_skb sk_msg lirc_mode2 flow_dissector cgroup_skb/ingress cgroup_skb/egress cgroup/skb cgroup/sock_create cgroup/sock_release cgroup/sock cgroup/post_bind4 cgroup/post_bind6 cgroup/bind4 cgroup/bind6 cgroup/connect4 cgroup/connect6 cgroup/connect_unix cgroup/sendmsg4 cgroup/sendmsg6 cgroup/sendmsg_unix cgroup/recvmsg4 cgroup/recvmsg6 cgroup/recvmsg_unix cgroup/getpeername4 cgroup/getpeername6 cgroup/getpeername_unix cgroup/getsockname4 cgroup/getsockname6 cgroup/getsockname_unix cgroup/sysctl cgroup/getsockopt cgroup/setsockopt cgroup/dev struct_ops+ struct_ops.s+ netfilter bpf_cgroup_dev_ctx __sk_buff bpf_sock bpf_sock_addr bpf_sockopt bpf_sysctl bpf_user_pt_regs_t bpf_nf_ctx bpf_perf_event_data bpf_raw_tracepoint_args bpf_sk_lookup sk_msg_md sk_reuseport_md bpf_sock_ops xdp_md BPF program name global variables minimal BTF BTF functions BTF data section and variable BTF global function ARRAY map mmap() BPF_PROG_BIND_MAP support module BTF support BTF_KIND_FLOAT support BPF perf link support BTF_KIND_DECL_TAG support BTF_KIND_TYPE_TAG support memcg-based memory accounting BPF cookie support BTF_KIND_ENUM64 support Kernel using syscall wrapper BPF multi-uprobe link support unspec socket_filter sched_cls sched_act cgroup_skb cgroup_sock cgroup_device cgroup_sock_addr cgroup_sysctl raw_tracepoint_writable cgroup_sockopt lsm prog_array perf_event_array percpu_array cgroup_array lru_hash lru_percpu_hash lpm_trie array_of_maps hash_of_maps sockmap xskmap sockhash reuseport_sockarray percpu_cgroup_storage devmap_hash inode_storage task_storage bloom_filter user_ringbuf cgrp_storage cgroup_inet_ingress cgroup_inet_egress cgroup_inet_sock_create cgroup_sock_ops sk_skb_stream_parser sk_skb_stream_verdict sk_msg_verdict cgroup_inet4_bind cgroup_inet6_bind cgroup_inet4_connect cgroup_inet6_connect cgroup_inet4_post_bind cgroup_inet6_post_bind cgroup_udp4_sendmsg cgroup_udp6_sendmsg cgroup_udp4_recvmsg cgroup_udp6_recvmsg cgroup_getsockopt cgroup_setsockopt trace_raw_tp trace_fentry trace_fexit modify_return lsm_mac trace_iter cgroup_inet4_getpeername cgroup_inet6_getpeername cgroup_inet4_getsockname cgroup_inet6_getsockname xdp_devmap cgroup_inet_sock_release xdp_cpumap sk_skb_verdict sk_reuseport_select trace_kprobe_multi lsm_cgroup tcx_ingress tcx_egress trace_uprobe_multi cgroup_unix_connect cgroup_unix_sendmsg cgroup_unix_recvmsg cgroup_unix_getpeername cgroup_unix_getsockname netkit_primary netkit_peer bpf_map_batch_opts bpf_map_create_opts bpf_prog_load_opts bpf_obj_pin_opts bpf_obj_get_opts bpf_prog_attach_opts bpf_prog_detach_opts bpf_link_update_opts bpf_prog_query_opts bpf_test_run_opts bpf_get_fd_by_id_opts bpf_link_create_opts bpf_btf_load_opts bpf_prog_bind_opts libbpf: BTF header not found type name field name enum name param name rbe libbpf: BTF.ext has no data func_info line_info core_relo /sys/kernel/btf/vmlinux /boot/vmlinux-%1$s /sys/kernel/btf/%s btf_dedup_opts unsigned long int unsigned int long long unsigned int long int unsigned int unsigned long int long unsigned Unknown libbpf error %d Something wrong in libelf BPF object format invalid Endian mismatch Internal error in libbpf Relocation failed Program too big Incorrect kernel version Wrong pid in netlink message Invalid netlink sequence ERROR: strerror_r(%d)=%d bpf_tc_hook bpf_tc_opts bpf_xdp_attach_opts bpf_xdp_query_opts %s:[%u] Debian Debian %u.%u.%u %*s %*s %u.%u.%u invalid func unknown func volatile const restrict %s%s: %d; %s___%zu enum%s%s %s%s = %d, %s%s = %u, %s%s___%zd = %d, %s%s___%zd = %u, %s%s = %lldLL, %s%s = %lluULL, %s%s___%zd = %lldLL, %s%s___%zd = %lluULL, %s} __attribute__((mode(byte))) __attribute__((mode(word))) %u%s%s %lldLL %lluULL%s%s enum %s union %s struct %s volatile const restrict void) %s%s%s { __attribute__((packed)) __gnuc_va_list typedef __builtin_va_list typedef %s %s; static extern .%s = <unsupported kind:%u> 0x%llx%s%s 0x%llx%016llx%s%s %lld%s%s %llu%s%s %d%s%s '%c'%s%s %Lf%s%s %lf%s%s %f%s%s %p%s%s 0x%x%s%s [%s ]%s%s }%s%s %s = SEC("%s") %s%s btf_dump_opts btf_dump_emit_type_decl_opts btf_dump_type_data_opts __Poly8_t __Poly16_t unsigned short __Poly64_t unsigned long long __Poly128_t unsigned __int128 user_ring_buffer_opts key type inner map value type bpf_linker_opts .strtab bpf_linker_file_opts .extern libbpf: BTF dedup failed: %d r=%d close(%%d) = %%d find_by_name_kind(%s,%d) libbpf: gen: finish %d btf_load size %d ld64 prog_load %s insn_cnt %d kallsyms_lookup_name(%s,%d) func (%s:count=%d): btf_fd map_freeze byte_off byte_sz field_exists lshift_u64 rshift_u64 local_type_id target_type_id type_exists type_matches type_size enumval_exists enumval_value ::%s = %d ::%s = %u ::%s = %lld ::%s = %llu <%s> [%u] %s %s @ offset %u.%u) @ offset %u) success non-matching /proc/%d/root%s /proc/%d/maps %zx-%zx %s %zx %*s %*d%[^ ] __bpf_usdt_specs __bpf_usdt_ip_to_spec_id lib %d @ %ld ( %%%15[^)] ) %n %d @ ( %%%15[^)] ) %n %d @ %%%15s %n %d @ $%ld %n eip perf bench [<common options>] <collection> <benchmark> [<options>] # List of all available benchmark collections: Unknown format descriptor: '%s' Invalid repeat option: Must specify a positive value # List of available benchmarks for collection '%s': Unknown benchmark: '%s' for collection '%s' Specify the output formatting style Specify number of times to repeat the run NUMA scheduling and MM benchmarks Baseline libc usleep(1000) call Attach empty BPF prog to uprobe on usleep, system wide Attach trace_printk BPF prog to uprobe on usleep syswide Benchmark thread start/finish with breakpoints Benchmark breakpoint enable/disable Benchmark perf event synthesis Benchmark evlist open and close Benchmark sysfs PMU info scanning Benchmark epoll concurrent epoll_waits Benchmark epoll concurrent epoll_ctls Benchmark for futex hash table Benchmark for futex wake calls Benchmark for parallel futex wake calls Benchmark for futex requeue calls Benchmark for futex lock_pi calls Benchmark for memcpy() functions Benchmark for memset() functions Benchmark for find_bit() functions Run all memory access benchmarks Benchmark for basic getppid(2) calls Benchmark for getpgid(2) calls Benchmark for scheduling and IPC Benchmark for pipe() between two processes Benchmark for seccomp user notify problem processing %d event, skipping it. problem incrementing symbol count, skipping event total %d, ok %d (%.1f%%), bad %d (%.1f%%) ----------------------------------------------------------- total %d, ok %d (%.1f%%), bad %d (%.1f%%) Annotate type: '%s' in %s (%d samples): ============================================================================ only consider symbols in these dsos be more verbose (show symbol address, etc) do now show any warnings or messages don't load vmlinux even if found load module symbols - WARNING: use only with -k and LIVE kernel print matching source lines (may be slow) Don't shorten the displayed pathnames Skip symbols that cannot be annotated Show event group information together Look for files with symbols relative to this directory Interleave source code with assembly code (default) Display raw encoding of assembly instructions (default) Specify disassembler style (e.g. -M intel for intel syntax) Add prefix to source file path names in programs (with --prefix-strip) Strip first N entries of source file path name in programs (with --prefix) objdump binary to use for disassembly and annotations addr2line binary to use for line numbers Enable kernel symbol demangling Show a column with the sum of periods Show a column with the number of samples 'always' (default), 'never' or 'auto' only applicable to --stdio mode Set percent type local/global-period/hits Don't show entries under that percent Instruction Tracing options i[period]: synthesize instructions events y[period]: synthesize cycles events (same period as i) b: synthesize branches events (branch misses for Arm SPE) c: synthesize branches events (calls only) r: synthesize branches events (returns only) x: synthesize transactions events w: synthesize ptwrite events p: synthesize power events o: synthesize other events recorded due to the use of aux-output (refer to perf record) I: synthesize interrupt or similar (asynchronous) events (e.g. Intel PT Event Trace) e[flags]: synthesize error events each flag must be preceded by + or - error flags are: o (overflow) l (data lost) d[flags]: create a debug log each flag must be preceded by + or - log flags are: a (all perf events) o (output to stdout) f: synthesize first level cache events m: synthesize last level cache events t: synthesize TLB events a: synthesize remote access events g[len]: synthesize a call chain (use with i or x) G[len]: synthesize a call chain on existing event records l[len]: synthesize last branch entries (use with i or x) L[len]: synthesize last branch entries on existing event records sNUMBER: skip initial number of events q: quicker (less detailed) decoding A: approximate IPC Z: prefer to ignore timestamps (so-called "timeless" decoding) T: use the timestamp trace as kernel time PERIOD[ns|us|ms|i|t]: specify period to sample stream concatenate multiple options. Default is iybxwpe or cewp Show data type annotate for the memory accesses Show stats for the data type annotation Show instruction stats for the data type annotation Error: only one config file at a time The config variable does not contain a section name: %s The config variable does not contain a variable name: %s The config variable does not contain a value: %s # this file is auto-generated. Failed to set the configs on %s perf config [<file-option>] [options] [section.name[=value] ...] problem incrementing symbol period, skipping event problem adding hist entry, skipping event compute wdiff w1(%ld) w2(%ld) Failed: wrong weight data, use 'wdiff:w1,w2' Failed: extra option specified '%s' Failed: '%s' is not computation method (use 'delta','ratio' or 'wdiff') (%lu * 100 / %lu) - (%lu * 100 / %lu) Do not show any warnings or messages Show only items with match in baseline delta,delta-abs,ratio,wdiff:w1,w2 (default delta-abs),cycles Entries differential computation selection Show cycles histogram and standard deviation - WARNING: use only with -c cycles. only consider symbols in these comms sort by key(s): pid, comm, dso, symbol, parent, cpu, srcline, ... Please refer the man page for the complete list. separator for columns, no spaces will be added between columns '.' is reserved. How to display percentage of filtered entries Time span (time percent or absolute timestamp) only consider symbols in these pids only consider symbols in these tids Enable hot streams comparison. perf diff [<options>] [old_file] [new_file] [Program Block Range] Cycles Diff --group option is not compatible with other options # Tip: use 'perf evlist --trace-fields' to show fields for tracepoint events buffer size too small, must larger than 1KB. cannot open tracing file: %s: %s write '%s' to tracing/%s failed: %s Please select "function_graph" (default) or "function" failed to set tracing cpumask failed to set tracing option func_stack_trace failed to set tracing option irq-info failed to set tracing filters failed to set tracing per-cpu buffer size failed to set tracing option function-fork failed to set tracing option sleep-time failed to set tracing option funcgraph-irqs failed to set tracing option funcgraph-proc/funcgraph-abstime users with the CAP_PERFMON or CAP_SYS_ADMIN capability failed to set current_tracer to function_graph %4d - %-4d %s | %10d | %.*s%*s | %4d - %-4s %s | %10d | %.*s%*s | failed to set current_tracer to %s Trace on existing thread id (exclusive to --pid) System-wide collection from all CPUs Tracer to use: function_graph(default) or function Show available functions to filter Trace given functions using function tracer Function tracer options, available options: call-graph,irq-info Trace given functions using function_graph tracer Set nograph filter on given functions Graph tracer options, available options: nosleep-time,noirqs,verbose,thresh=<n>,depth=<n> Size of per cpu buffer, needs to use a B, K, M or G suffix. Number of milliseconds to wait before starting tracing after program start Show latency of given function perf ftrace [<options>] [<command>] perf ftrace [<options>] -- [<command>] [<options>] perf ftrace {trace|latency} [<options>] [<command>] perf ftrace {trace|latency} [<options>] -- [<command>] [<options>] Should provide a function to measure Config with no key for man viewer: %s '%s': path for unsupported man viewer. Please consider using 'man.<tool>.%s' instead. '%s': unsupported man viewer sub key. Failed to read emacsclient version Failed to parse emacsclient version. emacsclient version '%d' too old (< 22). The most commonly used perf commands are: perf help [--all] [--man|--web|--info] [command] no man viewer handled the request '%s': not a documentation directory. Show build id of current kernel + modules Decompression initialization failed. Reported data may be incomplete. Problems with %s file, consider removing it from the cache kcore added to build-id cache directory %s file(s) to remove (remove old caches too) to find missing build ids in the cache Enable debuginfod data retrieval from DEBUGINFOD_URLS or specified urls target pid for namespace context perf buildid-cache [<options>] Couldn't read a build-id in %s Couldn't remove some caches. Error: %s. be more verbose (show counter open errors, etc) perf kallsyms [<options>] symbol_name %s: %s %s %#lx-%#lx (%#lx-%#lx) List of pre-defined events (to be used in -e or -M): Unexpected format character '%c' JSON encode events and metrics Print extra event descriptions. --no-desc to not print. Print longer event descriptions. Print information on the perf event names and expressions used internally by events. Limit PMU or metric printing to the given PMU (e.g. cpu, core or atom). Limit PMU or metric printing to the specified PMU. perf list [<options>] [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] ERROR: cputype is not supported! Critical: Not enough memory! Trying to continue... failed to write perf data, error: %m failed to queue perf data, error: %m failed to signal wakeup fd, error: %m Couldn't record kernel reference relocation symbol Symbol resolution may be skewed if relocation was used (e.g. kexec). Check /proc/kallsyms permission or run as root. Couldn't record kernel module information. Symbol resolution may be skewed if relocation was used (e.g. kexec). Check /proc/modules permission or run as root. Couldn't synthesize thread map. Couldn't synthesize bpf events. Couldn't synthesize cgroup events. Recording AUX area tracing snapshot failed to sync perf data, error: %m Couldn't record guest kernel [%d]'s reference relocation symbol. callchain: stack dump size %d trigger '%s' state transist error: %d in %s() [ perf record: perf size limit reached (%lu KB), stopping session ] threads[%d]: running on cpu%d: threads[%d]: failed to notify on start: %s threads[%d]: started on cpu%d threads[%d]: failed to notify on termination: %s Failed to allocate thread mask Failed to initialize maps thread mask Failed to initialize affinity thread mask Intersecting affinity mask: %s Failed to reallocate thread masks Failed to get current timestamp Perf session creation failed. Parallel trace streaming is not available in pipe mode. Parallel trace streaming is not available in AUX area tracing mode. Compression initialization failed. Failed to create wakeup eventfd, error: %m Failed to add wakeup eventfd to poll list ERROR: kcore is not readable. gettimeofday failed, cannot set reference time. clock_gettime failed, cannot set reference time. WARNING: --timestamp-filename option is not available in pipe mode. perf record opening and mmapping events WARNING: Kernel address maps (/proc/{kallsyms,modules}) are restricted, check /proc/sys/kernel/kptr_restrict and /proc/sys/kernel/perf_event_paranoid. Samples in kernel functions may not be resolved if a suitable vmlinux file is not found in the buildid cache or in the vmlinux path. Samples in kernel modules won't be resolved at all. If some relocation was applied (e.g. kexec) symbols may be misresolved even with a suitable vmlinux or kallsyms file. failed to set filter "%s" on event %s with %d (%s) Permission error mapping pages. Consider increasing /proc/sys/kernel/perf_event_mlock_kb, or try again with a smaller value of -m/--mmap_pages. (current value: %u,%u) Failed to allocate thread data thread_data[%p]: nr_mmaps=%d, maps=%p, ow_maps=%p thread_data[%p]: cpu%d: maps[%d] -> mmap[%d] thread_data[%p]: cpu%d: ow_maps[%d] -> ow_mmap[%d] Failed to initialize thread[%d] maps thread_data[%p]: pollfd[%d] <- event_fd=%d thread_data[%p]: msg=[%d,%d], ack=[%d,%d] Failed to open thread[%d] communication pipes Failed to add descriptor to thread[%d] pollfd thread_data[%p]: pollfd[%d] <- ctl_fd=%d Failed to duplicate descriptor in main thread pollfd thread_data[%p]: pollfd[%d] <- non_perf_event fd=%d Failed to map thread and evlist pollfd indexes Failed to create data directory: %s perf record done opening and mmapping events WARNING: No sample_id_all support, falling back to unordered processing Couldn't generate buildids. Use --no-buildid to profile anyway. Couldn't create side band evlist. . Couldn't ask for PERF_RECORD_BPF_EVENT side band events. . Couldn't start the BPF side band thread: BPF programs starting from now on won't be annotatable Could not set realtime priority. Failed to block signals on threads start: %s threads[%d]: failed to receive termination notification from %d threads[%d]: failed to receive start notification from %d Failed to unblock signals on threads start: %s AUX area tracing snapshot failed [ perf record: dump data: Woken up %ld times ] Thread and evlist pollfd index mismatch Failed to collect '%s' for the '%s' workload: %s [ perf record: Woken up %ld times to write data ] threads[%d]: samples=%lld, wakes=%ld, transferred=%lu, compressed=%lu Unmatched FD vs. sample ID: skip reading LOST count [ perf record: Captured and wrote %.3f MB %s%s%s , compressed (original %.3f MB, ratio is %.3f) Failed to initialize thread[%d] pollfd cgroup monitoring only available in system-wide mode Failed: no support to record build id in mmap events, update your kernel. Enabling build id in mmap2 events. Kernel has no cgroup sampling support. --affinity option is mutually exclusive to parallel streaming mode. Asynchronous streaming mode (--aio) is mutually exclusive to parallel streaming mode. Compression enabled, disabling build id collection at the end of the session. kernel does not support recording context switch events WARNING: --switch-output-event option is not available in parallel streaming mode. WARNING: --switch-output option is not available in parallel streaming mode. switch-output with SIGUSR2 signal switch-output with %s size threshold switch-output with %s time threshold (%lu seconds) WARNING: switch-output data size lower than wakeup kernel buffer size (%s) expect bigger perf.data sizes WARNING: --timestamp-filename option is not available in parallel streaming mode. AUX area tracing options are not available in parallel streaming mode. Couldn't create thread/CPU maps: %s record__config_text_poke failed, error %d record__config_off_cpu failed, error %d record__config_tracking_events failed, error %d Failed to allocate thread masks Failed to allocate thread masks[%d] --per-thread option is mutually exclusive to parallel streaming mode. Failed to allocate CPU topology Failed to allocate NUMA topology Failed to reallocate maps spec Failed to allocate maps spec[%d] Invalid thread maps or affinity specs Failed to reallocate affinity spec Failed to allocate affinity spec[%d] Failed to initialize parallel data streaming masks event selector. use 'perf list' to list available events don't record events from perf itself record events on existing process id record events on existing thread id collect data with this RT SCHED_FIFO priority collect data without buffering collect raw sample records from all opened counters system-wide collection from all CPUs child tasks do not inherit counters synthesize non-sample events at the end of output Fail if the specified frequency can't be used number of mmap data pages and AUX area tracing mmap pages Minimal number of bytes that is extracted from mmap data pages (default: 1) don't print any warnings or messages Record the sample physical addresses Record the sampled data address data page size Record the sampled code address (ip) page size do not update the buildid cache do not collect buildids in perf.data monitor event in cgroup name only ms to wait before starting measurement after program start (-1: start with events disabled), or ranges of time to enable events e.g. '-D 10-20,30-40' sample by weight (on special events only) sample transaction flags (special events only) sample selected machine registers on interrupt, use '-I?' to list register names sample selected machine registers on interrupt, use '--user-regs=?' to list register names Record running/enabled time of read (:S) events clockid to use for events, see clock_gettime() AUX area tracing Snapshot Mode per thread proc mmap processing timeout in ms Configure all used events to run in kernel space. Configure all used events to run in user space. Record build-id of all DSOs regardless of hits append timestamp to output filename Record timestamp boundary (time of first/last samples) signal or size[BKMG] or time[smhd] Switch output when receiving SIGUSR2 (signal) or cross a size or time threshold switch output event selector. use 'perf list' to list available events Limit number of switch output generated files Use <n> control blocks in asynchronous trace writing mode (default: 1, max: 4) Set affinity mask of trace reading thread to NUMA node cpu mask or cpu of processed mmap buffer Compress records using specified level (default: 1 - fastest compression, 22 - greatest compression) Limit the maximum size of the output file number of threads to run for event synthesis fd:ctl-fd[,ack-fd] or fifo:ctl-fifo[,ack-fifo] Listen on ctl-fd descriptor for command to control measurement ('enable': enable events, 'disable': disable events, 'snapshot': AUX area tracing snapshot). Optionally send control command completion ('ack\n') to ack-fd descriptor. Alternatively, ctl-fifo / ack-fifo will be opened and used as ctl-fd / ack-fd. Fine-tune event synthesis: default=all write collected trace data into several data files using parallel threads perf record [<options>] [<command>] perf record [<options>] -- <command> [<options>] Invalid --ignore-callees regex: %s %s Not enough memory for report.sort_order %s variable unknown, ignoring... Cannot parse time quantum `%s' failed: wrong feature ID: %llu %*s %lx-%lx %c%c%c%c %08lx %lu %s As no suitable kallsyms nor vmlinux was found, kernel samples can't be resolved. If some relocation was applied (e.g. kexec) symbols may be misresolved. Stop considering events after the occurrence of this event Consider events after the occurrence of this event Set time quantum for time sort key (default 100ms) Time span of interest (start,stop) how to display percentage of filtered entries use branch records for per branch histogram filling don't try to adjust column width, use these fixed values only show symbols that (partially) match with this filter ignore callees of these functions in call graphs print_type,threshold[,print_limit],order,sort_key[,branch],value regex filter to identify parent, see: '--sort parent' pretty printing style key: normal raw output field(s): overhead period sample Display recorded tasks memory maps Show per-thread event counters Show sample percentage for different cpu modes Only display entries with parent-match Accumulate callchains of children and show total overhead as well. Enabled by default, use --no-children to disable. Set the maximum stack depth when parsing the callchain, anything beyond the specified depth will be ignored. Default: kernel.perf_event_max_stack or 127 Only display entries resolved to a symbol Display extended information about perf.data file Sort the output by the event at the index n in group. If n is invalid, sort by the first event. WARNING: should be used on grouped events. add last branch records to call history Number of samples to save per histogram entry for individual browsing Show full source file name path for source lines Show callgraph from reference event Enable LBR callgraph stitching approach only show processor socket that match with this filter Show raw trace event output (do not use print fmt or plugins) Show the on/off switch events, used with --switch-on and --switch-off Sort all blocks by 'Sampled Cycles%' Do not display empty (or dummy) events in the output branch and mem mode incompatible Error: --hierarchy and --fields options cannot be used together Error: --tasks and --mmaps can't be used together with --stats # To display the perf.data header info, please use --header/--header-only options. # %s: failed to set libtraceevent function resolver Selected --sort parent, but no callchain data. Did you call 'perf record' without -g? Selected -g or --branch-history. But no callchain or branch data. Did you call 'perf record' without -g or -b? Can't register callchain params. Selected -b but no branch data. Did you call perf record without -b? Selected --mem-mode but no mem data. Did you call perf record without -d? Can't find LBR callchain. Switch off --stitch-lbr. Please apply --call-graph lbr when recording. Error: failed to process tasks Kernel address maps (/proc/{kallsyms,modules}) were restricted. Check /proc/sys/kernel/kptr_restrict before running 'perf record'. %s Samples in kernel modules can't be resolved as well. Failed to setup hierarchy output formats /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/perf/Documentation Cannot load tips.txt file, please install perf! # # Total Lost Samples: %lu # Cache level must be of form L[1-%d], or l[1-%d] perf only supports max cache level of %d. Consider increasing MAX_CACHE_LVL Must define cputype before events/metrics --cputype %s is not supported! %s event is not supported by the kernel. skipping event %s that kernel failed to open . Extra cpu map event, ignoring. --cgroup and --for-each-cgroup cannot be used together warning: processing task data, aggregation mode not set failed to write stat round event Extra thread map event, ignoring. perf stat [<options>] [<command>] Cannot use -r option with perf stat record. aggregate counts per processor socket aggregate counts per processor die aggregate count at this cache level (Default: LLC) aggregate counts per physical processor core aggregate counts per numa node cannot use both --output and --log-fd --metric-only is not supported with --per-thread --metric-only is not supported with -r --table is only supported with -r argument to --log-fd must be a > 0 --interval-clear does not work with output -B option not supported with -x Run count must be a positive number The --per-thread option is only available when monitoring via -p -t -a options or only --per-thread. both cgroup and no-aggregation modes only available in system-wide mode freeze_on_smi is not supported. Topdown requested but the topdown metric groups aren't present. (See perf list the metric groups have names like TopdownL1) Invalid top-down metrics level. The max level is %u. Topdown accuracy may decrease when measuring long periods. Please print the result regularly, e.g. -I1000 Problems finding threads of monitor WARNING: grouped events cpus do not match. Events with CPUs not matching the leader will be removed from the group. interval-count option should be used together with interval-print. timeout < 100ms. The overhead percentage could be high in some cases. Please proceed with caution. timeout option is not supported with interval-print. [ perf stat: executing run #%d ... ] Couldn't synthesize the kernel mmap record, harmless, older tools may produce warnings about this file . cpu_aggr_map refcnt unbalanced hardware transaction statistics stat events on existing process id stat events on existing thread id Use --no-scale to disable counter scaling for multiplexing repeat command and print average + stddev (max: 100, forever: 0) display details about each run (only with -r option) null run - dont start any counters detailed run - start a lot of events call sync() before starting a run print large numbers with thousands' separators list of cpus to monitor in system-wide disable aggregation across CPUs or PMUs disable aggregation the same as -A or -no-aggr Merge identical named hybrid events print counts with custom separator log output to fd, instead of stderr command to run prior to the measured command command to run after to the measured command print counts at regular interval in ms (overhead is possible for values <= 100ms) print counts for fixed number of times clear screen in between new interval stop workload and print counts after a timeout period in ms (>= 10ms) ms to wait before starting measurement after program start (-1: start with events disabled) Only print computed metrics. No raw values don't group metric events, impacts multiplexing don't try to share events between metrics in a group disable adding events for the metric threshold calculation Set the metrics level for the top-down statistics (0: max level) monitor specified metrics or metric groups (separated by ,) Use with 'percore' event qualifier to show the event counts of one hardware thread by sum up total hardware threads of same physical core print summary for interval mode don't print 'summary' for CSV summary output don't print any output, messages or warnings (useful with record) Only enable events on applying cpu with this type for hybrid platform (e.g. core or atom) Listen on ctl-fd descriptor for command to control measurement ('enable': enable events, 'disable': disable events). Optionally send control command completion ('ack\n') to ack-fd descriptor. Alternatively, ctl-fifo / ack-fifo will be opened and used as ctl-fd / ack-fd. measure I/O performance metrics provided by arch/platform Out of bounds address found: Addr: %lx DSO: %s %c Map: %lx-%lx Symbol: %lx-%lx %c %s Arch: %s Kernel: %s Tools: %s Not all samples will be on the annotation output. Please report to linux-kernel@vger.kernel.org Not enough memory for annotating '%s' symbol! Can't find guest [%d]'s kernel information %u unprocessable samples recorded. Kernel address maps (/proc/{kallsyms,modules}) are restricted. Check /proc/sys/kernel/kptr_restrict and /proc/sys/kernel/perf_event_paranoid. Kernel%s samples will not be resolved. The %s file can't be used: %s %s A vmlinux file was not found. %s Problem incrementing symbol period, skipping event Too slow to read ring buffer (change period (-c/-F) or limit CPUs (-C) Can't annotate %s: No vmlinux file was found in the path For a higher level overview, try: perf top --sort comm,dso WARNING: LOST %d chunks, Check IO/CPU overload %d lines not displayed, maybe increase display entries [e] [d] display refresh delay. (%d) [e] display entries (lines). (%d) [E] active event counter. (%s) [f] profile display filter (count). (%d) [F] annotate display filter (percent). (%d%%) [s] annotate symbol. (%s) [K] hide kernel symbols. (%s) [U] hide user symbols. (%s) [z] toggle sample zeroing. (%d) Enter selection, or unmapped key to continue: Sorry, no such event, using %s. Enter display event count filter Enter details display event filter (percent) record_mode[,record_size],print_type,threshold[,print_limit],order,sort_key[,branch] output field(s): overhead, period, sample plus all of sort keys profile events on existing thread id profile events on existing process id number of seconds to delay between refreshes dump the symbol table used for profiling only display functions with more events than this enables call-graph recording and display Accumulate callchains of children and show total overhead as well Set the maximum stack depth when parsing the callchain. Default: kernel.perf_event_max_stack or 127 Use a backward ring buffer, default: no number of thread to run event synthesize Couldn't read the cpuid for this machine: %s Error: --stitch-lbr must be used with --call-graph lbr --cgroup and --all-cgroups cannot be used together Couldn't synthesize BPF events: Pre-existing BPF programs won't have symbols resolved. Could not read the CPU topology map: %s perf top only support consistent per-event overwrite setting for all events fall back to non-overwrite mode Could not create process thread. Could not create display thread. Samples for '%s' event do not have %s attribute set. Cannot print '%s' field. Samples for '%s' event do not have %s attribute set. Skipping '%s' field. %3s %8s %15s %15s %15s %15s %s %3d %8d %15lu %15lu %15lu %15lu %s Display of symbols requested but neither sample IP nor sample address available. Hence, no addresses to convert to symbols. Display of offsets requested but symbol is notselected. Display of DSO requested but no address to convert. Display of source line number requested but sample IP is not selected. Hence, no address to lookup the source line number. Display of branch stack assembler requested, but non all-branch filter set Hint: run 'perf record -b ...' Hint: run 'perf record --all-cgroups ...' block %lx-%lx transfers between kernel and user brstack does not reach to final jump (%lx-%lx) block %lx-%lx (%lu) too long to dump cannot fetch code for block at %lx-%lx Invalid event type in field string. Overriding previous field request for %s events. Cannot set fields to 'none' for all event types. Overriding previous field request for all events. '%s' not valid for %s events. Ignoring. '%s' not valid for %s events. No fields requested for %s type. Events will not be displayed. Cannot mix +-field with overridden fields -ip,-addr,-event,-period,+callindent,+flags -ip,-addr,-event,-period,+callindent open(%s) failed. Check "PERF_EXEC_PATH" env to set scripts dir. List of available trace scripts: Scripting language extensions (used in perf script -s [spec:]script.[spec]): mismatch of LBR data and executable Samples misordered, previous: %lu this: %lu hw: %u cstate: %u sub-cstate: %u deepest cstate: %u last cstate: %u wake reason: %#x dump unsorted raw trace in ASCII show latency attributes (irqs/preemption disabled, etc) script file name (lang:script name, script name, or *) generate perf-script.xx script in specified language do various checks like samples ordering and lost events When printing symbols do not display call chain comma separated output fields prepend with 'type:'. +field to add and -field to remove.Valid types: hw,sw,trace,raw,synth. Fields: comm,tid,pid,time,cpu,event,trace,ip,sym,dso,dsoff,addr,symoff,srcline,period,iregs,uregs,brstack,brstacksym,flags,data_src,weight,bpf-output,brstackinsn,brstackinsnlen,brstackoff,callindent,insn,insnlen,synth,phys_addr,metric,misc,srccode,ipc,tod,data_page_size,code_page_size,ins_lat,machine_pid,vcpu,cgroup,retire_lat only consider symbols in these DSOs Use with -S to list traced records within address range Decode instructions from itrace Run xed disassembler on output Decode calls and returns from itrace Only print symbols and callees with --call-trace/--call-ret-trace Stop display of callgraph at these symbols only display events for these comms Show time stamps relative to start Show time stamps relative to previous event display extended information from perf.data file Show the path of [kernel.kallsyms] Show the fork/comm/exit events Show context switch events (if recorded) Show namespace events (if recorded) Show cgroup events (if recorded) Show lost events (if recorded) Show round events (if recorded) Show bpf related events (if recorded) Show text poke related events (if recorded) Dump trace output to files named by the monitored events Maximum number of code blocks to dump with brstackinsn Use 9 decimal places when displaying time guest mount directory under which every guest os instance has a subdir file saving guest os /proc/kallsyms file saving guest os /proc/modules Guest code can be found in hypervisor process perf script [<options>] record <script> [<record-options>] <command> perf script [<options>] report <script> [script-args] perf script [<options>] <script> [<record-options>] <command> perf script [<options>] <top-script> [script-args] Please specify a valid report script(see 'perf script -l' for listing) reltime and deltatime - the two don't get along well. Please limit to --reltime or --deltatime. Couldn't find script `%s' See perf script -l for available scripts. `%s' script requires options. See perf script -l for available scripts and options. custom fields not supported for generated scripts zero-sized file, nothing to do! perf script started with script %s %s events do not exist. Remove corresponding -F option to proceed. Can't provide 'tod' time, missing clock data. Please record with -k/--clockid option. Couldn't create the per event dump files [ perf script: Wrote %.3f MB %s (%lu samples) ] KVM event statistics (%lu entries) Failed to allocate hist entry Fail to find format for sorting %s. Fail to find format for output field %s. dazed and confused on what is monitored, Total Samples:%lu, Total events handled time:%.2fus. Fail to resolve address location, skip sample. End time before begin time; skipping event. %lu VM %d, vcpu %d: %s event took %luusec unknown kvm exit code:%lld on %s Failed to allocate memory for filename Usage: perf kvm stat <command> report: report statistical data of kvm events live: live reporting of statistical data of kvm events Otherwise, it is the alias of 'perf stat': key for sorting: sample(sort by samples number) time (sort by avg time) event for reporting: vmexit, mmio (x86 only), ioport (x86 only) perf kvm stat record [<options>] Unable to setup the kvm tracepoints analyze events only for given process id(s) perf kvm stat report [<options>] Error parsing process id string Initializing perf session failed Failed to look up CPU type: %s ev_name,sample,percent_sample,time,percent_time,max_t,min_t,mean_t time in seconds between display updates show events other than HLT (x86 only) or Wait state (s390 only) that take longer than duration usecs perf kvm stat live [<options>] Error parsing %s tracepoint: subsystem delimiter not found Failed to add %s tracepoint to the list Couldn't create the events: %s Failed to mmap the events: %s Failed to get current flags for fd %d Failed to set non-block option on fd %d Error reading timer fd - invalid size returned cannot find or create a task %d/%d. --guest-data option requires guest perf.data file name, guest machine PID, and optionally guest timestamp offset, and guest timestamp scale factor, separated by commas. Found VCPU: tid %u comm %s vcpu %u Fatal error: Two threads found with the same VCPU Not enough memory to process sched switch event! Can't synthesize build_id event for %s Unexpected type fetching guest event Parse failed fetching guest event Guest event with unknown id %llu Guest event with unknown VCPU %u No VCPU threads found for pid %u Failed to synthesize id_index Failed to add guest build IDs Switch event does not have CPU Inject build-ids into the output stream Inject build-ids of all DSOs into the output stream buildid path [,buildid path...] build-ids to use for given paths Merge sched-stat and sched-switch for getting events where and how long tasks slept merge jitdump files into perf.data file be more verbose (show build ids, etc) strip non-synthesized events (use with --itrace) correlate time between VM guests and the host inject events from a guest perf.data file --strip option requires --itrace option Input file name required for in-place updating Output file name must not be specified for in-place updating The input file would be updated in place, the --force option is required. Decompression initialization failed. Couldn't write a new pipe header. Couldn't parse known build ids. Samples for %s event do not have %s attribute set. Guest session decompression initialization failed. Failed to process %s, error %d cp -r -n %s/kcore_dir* %s >/dev/null 2>&1 cp -r -n %s/kcore_dir %s/kcore_dir__%u >/dev/null 2>&1 unknown sampling op %s, check man page %5d%s%5d%s0x%016lx%s0x016%lx%s memory operations(load,store) Default load,store Record/Report sample physical addresses Record/Report sample data address page size event selector. use 'perf mem record -e list' to list available events collect only kernel level data failed: memory events not supported perf mem record [<options>] [<command>] perf mem record [<options>] -- <command> [<options>] You cannot specify both --to-ctf and --to-json. converts data file between formats HAVE_DWARF_GETLOCATIONS_SUPPORT event selector. Use 'perf c2c record -e list' to list available events Shared Data Cache Line Table (%lu entries, sorted on %s) percent_rmt_peer,percent_lcl_peer, percent_rmt_hitm,percent_lcl_hitm, cl_idx,dcacheline,dcacheline_node,dcacheline_count,percent_costly_snoop,tot_hitm,lcl_hitm,rmt_hitm,tot_recs,tot_loads,tot_stores,stores_l1hit,stores_l1miss,stores_na,ld_fbhit,ld_l1hit,ld_l2hit,ld_lclhit,lcl_hitm,ld_rmthit,rmt_hitm,dram_lcl,dram_rmt cl_idx,dcacheline,dcacheline_node,dcacheline_count,percent_costly_snoop,tot_peer,lcl_peer,rmt_peer,tot_recs,tot_loads,tot_stores,stores_l1hit,stores_l1miss,stores_na,ld_fbhit,ld_l1hit,ld_l2hit,ld_lclhit,lcl_hitm,ld_rmthit,rmt_hitm,dram_lcl,dram_rmt cl_num,cl_rmt_hitm,cl_lcl_hitm,cl_stores_l1hit,cl_stores_l1miss,cl_stores_na,dcacheline cl_num,cl_rmt_peer,cl_lcl_peer,cl_stores_l1hit,cl_stores_l1miss,cl_stores_na,dcacheline show extra node info in report (repeat for more info) Display only statistic tables (implies --stdio) Display full length of symbols Do not display Source Line column coalesce fields: pid,tid,iaddr,dso Detect adjacent cacheline false sharing failed: unknown display type: %s percent_stores_l1hit,percent_stores_l1miss,percent_stores_na,offset,offset_node,dcacheline_count, No pipe support at the moment. ================================================= Trace Event Information Total records : %10d Locked Load/Store Operations : %10d Load Operations : %10d Loads - uncacheable : %10d Loads - IO : %10d Loads - Miss : %10d Loads - no mapping : %10d Load Fill Buffer Hit : %10d Load L1D hit : %10d Load L2D hit : %10d Load LLC hit : %10d Load Local HITM : %10d Load Remote HITM : %10d Load Remote HIT : %10d Load Local DRAM : %10d Load Remote DRAM : %10d Load MESI State Exclusive : %10d Load MESI State Shared : %10d Load LLC Misses : %10d Load access blocked by data : %10d Load access blocked by address : %10d Load HIT Local Peer : %10d Load HIT Remote Peer : %10d LLC Misses to Local DRAM : %10.1f%% LLC Misses to Remote DRAM : %10.1f%% LLC Misses to Remote cache (HIT) : %10.1f%% LLC Misses to Remote cache (HITM) : %10.1f%% Store Operations : %10d Store - uncacheable : %10d Store - no mapping : %10d Store L1D Hit : %10d Store L1D Miss : %10d Store No available memory level : %10d No Page Map Rejects : %10d Unable to parse data source : %10d Global Shared Cache Line Event Information Total Shared Cache Lines : %10d Load HITs on shared lines : %10d Fill Buffer Hits on shared lines : %10d L1D hits on shared lines : %10d L2D hits on shared lines : %10d LLC hits on shared lines : %10d Load hits on peer cache or nodes : %10d Locked Access on shared lines : %10d Blocked Access on shared lines : %10d Store HITs on shared lines : %10d Store L1D hits on shared lines : %10d Total Merged records : %10d c2c details Cachelines sort on : %s Cacheline data grouping : %s Shared Data Cache Line Table Shared Cache Line Distribution Pareto ---------------------------------------------------------------------- perf c2c record [<options>] [<command>] perf c2c record [<options>] -- <command> [<options>] failed: write to control pipe: %d (%s) failed: did not received an ack failed: another perf daemon (pid %d) owns %s failed: control path too long '%s' session '%s' exited, status=%d session '%s' killed (signal %d) session '%s' stopped (signal %d) session '%s' Unexpected status (0x%x) failed to wait for session %s failed: permission denied for '%s' base failed: base '%s' does not exists failed: can't access base '%s': %s failed: base '%s' is not directory reconfig: found new session %s reconfig: found current session %s reconfig: session %s is changed failed: can't redefine base, bailing out reconfig: session '%s' killed reconfig: ruining session [%s:%d]: %s %s record --control=fifo:%s,%s %s signal %d sent to session '%s [%d]' Sent signal to specific session perf daemon {start|signal|stop|ping} [<options>] invalid default value ('slab' or 'page' required): %s Total_alloc/Per | Total_req/Per | Hit | Ping-pong | Frag ... | ... | ... | ... | ... | ... %9llu/%-5lu | %9llu/%-5lu | %8lu | %9lu | %6.3f%% missing free at page %lx (order: %d) %16llu | %'16llu | %'9d | %5d | %8s | %-*s | %s %016llx | %'16llu | %'9d | %5d | %8s | %-*s | %s show per-allocation statistics sort by keys: ptr, callsite, bytes, hit, pingpong, frag, page, order, migtype, gfp Initializing perf session tracepoint handlers failed error during process events: %d Net total bytes allocated: %'lu Total bytes wasted on internal fragmentation: %'lu Cross CPU allocations: %'lu/%'lu ... | ... | ... | ... | %-*s | ... %'16llu | %'9d | %5d | %8s | %-*s | %s %-16s | %5s alloc (KB) | Hits | Order | Mig.type | %-*s | Callsite ... | ... | ... | ... | ... | %-*s | ... %-30s: %'16lu [ %'16lu KB ] %5s %12s %12s %12s %12s %12s %.5s %.12s %.12s %.12s %.12s %.12s Failed to set irq tracepoints handlers Failed to set softirq tracepoints handlers Failed to set workqueue tracepoints handlers Failed to set sched tracepoints handlers Samples do not have callchains Failed to set libtraceevent function resolver %-*s %-*s %-*s %-*s %-*s %-*s %.*s %.*s %.*s %.*s %.*s %.*s Failed to process events, error %d Failed to zalloc kwork atom page Total count : %9lu Total runtime (msec) : %9.3f (%.3f%% load average) Total time span (msec) : %9.3f INFO: %.3f%% lost events (%ld out of %ld, in %ld chunks) INFO: %.3f%% skipped events (%lu including Problem processing event, skipping it Failed to get thread for pid %d Failed to resolve callchain, skipping Time span for analysis (start,stop) list of kwork to profile (irq, softirq, workqueue, sched, etc) sort by key(s): runtime, max, count sort by key(s): avg, max, count Display call chains if present Maximum number of functions to display backtrace. sort by key(s): rate, runtime, tid perf kwork latency [<options>] perf kwork timehist [<options>] Failed to validate sym arguments %%Cpu(s): %*.*f%% id, %*.*f%% hi, %*.*f%% si |||||||||||||||||||||||||||||||||||||||||||||||| workqueue:workqueue_activate_work workqueue:workqueue_execute_start workqueue:workqueue_execute_end Failed to read cgroup id for %s histogram of events caused bad sequence Address of instance: name of class map of lock instances (address:name table) key for sorting (acquired / contended / avg_wait / wait_total / wait_max / wait_min) output fields (acquired / contended / avg_wait / wait_total / wait_max / wait_min) combine locks in the same class key for sorting (contended / wait_total / wait_max / wait_min / avg_wait) contended,wait_total,wait_max,avg_wait output fields (contended / wait_total / wait_max / wait_min / avg_wait) use BPF program to collect lock contention stats Set the maximum stack depth when collecting lock contention, Default: 8 Set the number of stack depth to skip when finding a lock caller, Default: 4 Filter specific address/symbol of locks Filter specific function in the callstack show lock owners instead of waiters print result in CSV format with custom separator perf lock contention [<options>] tracepoint %s is not enabled. Are CONFIG_LOCKDEP and CONFIG_LOCK_STAT enabled? tracepoint %s is not enabled. Cannot use thread and addr mode together Lock owners are available only with BPF Cannot use owner and addr mode together Cgroups are available only with BPF Cannot use cgroup and addr mode together Cannot use cgroup and thread mode together Cannot use the separator that is already used lock contention evsel not found INFO: %.3f%% unordered timestamps (%ld out of %ld) INFO: %.3f%% context switch bugs (%ld out of %ld) registered task #%ld, PID %ld (%s) thread does not exist on fork event: child %p, parent %p Failed to process events, error %d time travel: wakeup time for task > previous sched_switch event time travel: last sched out time for task > previous sched_switch event Internal error: can't find thread Failed to malloc memory for runtime data. ... switch from %s/%d to %s/%d [ran %lu nsecs] problem processing %d event. skipping it Failed to get idle thread for cpu %d. Failed to get thread for tid %d. skipping sample. Failed to get thread for pid %d. Failed to resolve callchain. Skipping wakeup-event: Internal tree error migration-event: Internal tree error out-event: Internal tree error sort by key(s): runtime, switch, avg, max latency stats per pid instead of per comm repeat the workload replay N times (-1: infinite) Display call chains if present (default on) Show only syscall summary with statistics Show all syscalls and summary with statistics Show task state when sched-out analyze events only for given thread id(s) perf sched latency [<options>] perf sched timehist [<options>] ------------------------------------------------------------------------------------------------------------------------------------------- Task | Runtime ms | Switches | Avg delay ms | Max delay ms | Max delay start | Max delay end | ------------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------- TOTAL: |%11.3f ms |%9lu | --------------------------------------------------- |%11.3f ms |%9lu | avg:%8.3f ms | max:%8.3f ms | max start: %12s s | max end: %12s s failed to get cpus map from %s failed to get thread map from %s run measurement overhead: %lu nsecs sleep measurement overhead: %lu nsecs the sleep test took %lu nsecs task %6ld (%20s:%10ld), nr_events: %ld ------------------------------------------------------------ Error: sys_perf_event_open() syscall returned with %d (%s) %s Error: -s and -[n|w] are mutually exclusive. Failed to allocate memory for evsel runtime data Samples of sched_switch event do not have callchains. No sched_switch events found. Have you run 'perf sched record'? idle-time min-idle avg-idle max-idle stddev migrations run-time sleep iowait preempt delay run-time min-run avg-run max-run stddev migrations (msec) (msec) (msec) (msec) %s CPU %2d idle entire time window Total number of unique tasks: %lu Total number of context switches: %lu Total run time (msec): Total scheduling time (msec): invalid callchain context: %ld Skip invalid end event: previous event already ended! Skip invalid end event: invalid event type! Skip invalid start event: previous event already started! highlight tasks. Pass duration in ns or process name. process selector. Pass a pid or process name. sort CPUs according to topology all IO faster than min-time will visually appear longer merge events that are merge-dist us apart perf timechart [<options>] {record} perf timechart record [<options>] -P and -T options cannot be used at the same time. syscalls:sys_enter_sync_file_range syscalls:sys_exit_sync_file_range syscalls:sys_enter_epoll_pwait Initializing session tracepoint handlers failed Written %2.1f seconds of trace to %s. trace.show_zeros has to be set when trace.show_arg_names=no Kernel address maps (/proc/{kallsyms,modules}) are restricted. Check /proc/sys/kernel/kptr_restrict and /proc/sys/kernel/perf_event_paranoid. Kernel samples will not be resolved. Not enough memory to parse event qualifier Error: Not enough memory for allocating events qualifier ids Error: Not enough memory for parsing Invalid syscall %d id, skipping (%s, %lu) ... Problems reading syscall %d: %d (%s) Can't parse sample, err = %d, skipping... Unknown tp ID %lu, skipping... %s sample with no payload for tid: %d, cpu %d, raw_size=%d, skipping... Error sorting output by nr_events! syscall calls errors total min avg max stddev (msec) (msec) (msec) (msec) (%%) --------------- -------- ------ -------- --------- --------- --------- ------ WARNING: not enough memory, dropping samples! Not enough memory for errno stats for thread "%s"(%d/%d), results will be incomplete Problem processing %s callchain, skipping... %s: comm=%s,pid=%u,runtime=%lu,vruntime=%lu) raw_syscalls:sys_enter,raw_syscalls:sys_exit syscalls:sys_enter,syscalls:sys_exit perf trace [<options>] [<command>] perf trace [<options>] -- <command> [<options>] perf trace record [<options>] [<command>] perf trace record [<options>] -- <command> [<options>] event/syscall selector. use 'perf list' to list available events show the thread COMM next to its id list of syscalls/events to trace trace events on existing process id trace events on existing thread id pids to filter (by the kernel) show only events with duration > N.M ms show blocking scheduler events Show full timestamp, not time relative to first start Show only syscalls that failed Show errno stats per syscall, use with -s or -S Use libtraceevent to print the tracepoint arguments. Show the kernel callchains on the syscall exit path Set the maximum number of events to print, exit after that is reached. Set the minimum stack depth when parsing the callchain, anything below the specified depth will be ignored. Sort batch of events before processing, use if getting out of order events print the PERF_RECORD_SAMPLE PERF_SAMPLE_ info, for debugging ms to wait before starting measurement after program start Neither raw_syscalls nor syscalls events exist. Error during initialize raw_syscalls:sys_enter event Error during initialize raw_syscalls:sys_exit event Problems parsing the target to trace, check your options! Problems initializing symbol libraries! event qualifier tracepoint filter: %s trying to expand "%s" "%.*s" "%.*s" -> "%s" not found in "%s", can't set filter "%s" "%.*s" not found for "%s" in "%s", can't set filter "%s" No resolver (strtoul) for "%s" in "%s", can't set filter "%s" Failed to set filter "%s" on event %s with %d (%s) Stats: vfs_getname : %lu proc_getname: %lu failed to set syscalls:* tracepoint fields { .tv_sec: %lu, .tv_nsec: %lu } AMD64_PERF_CNTR_GLOBAL_STATUS_CLR Failed to parse %s as a pid: %s Failed to get the absolute path of %s: %m Too many probes (> %d) were specified. Warning: more than one --line options are detected. Only the first one is valid. Error: '--vars' doesn't accept arguments. [EVENT=]FUNC[@SRC][+OFF|%return|:RL|;PT]|SRC:AL|SRC;PT [[NAME=]ARG ...] perf probe [<options>] 'PROBEDEF' ['PROBEDEF' ...] perf probe [<options>] --add 'PROBEDEF' [--add 'PROBEDEF' ...] perf probe [<options>] --del '[GROUP:]EVENT' ... perf probe --list [GROUP:]EVENT ... perf probe [<options>] --line 'LINEDESC' perf probe [<options>] --vars 'PROBEPOINT' perf probe [<options>] --funcs be more verbose (show parsed arguments, etc) be quiet (do not show any warnings or messages) probe point definition, where GROUP: Group name (optional) EVENT: Event name FUNC: Function name OFF: Offset from function entry (in byte) %return: Put the probe at function return SRC: Source code path RL: Relative line number from function entry. AL: Absolute line number in file. PT: Lazy expression of line code. ARG: Probe argument (local variable name or kprobe-tracer argument format.) Show trace event definition of given traceevent for k/uprobe_events. forcibly add events with existing name FUNC[:RLN[+NUM|-RLN2]]|SRC:ALN[+NUM|-ALN2] FUNC[@SRC][+OFF|%return|:RL|;PT]|SRC:AL|SRC;PT Show accessible variables on PROBEDEF Show external variables too (with --vars only) Show variables location range in scope (with --vars only) Don't search inlined functions Set how many probe points can be found for a probe. Show potential probe-able functions. Set a filter (with --vars/funcs only) (default: "!__k???tab_* & !__crc_*" for --vars, "!_* & !*@plt" for --funcs) target executable name or path target module name (for online) or path (for offline) target pid for namespace contexts Output probe definition with bootconfig format Error: -v and -q are exclusive. another command except --add is set. Error: Don't use --list with --exec. Error: Failed to show event list. Error: Failed to show functions. Error: Failed to show lines. Failed to remove entries for %s Error: Failed to delete events. Error: --bootconfig doesn't support uprobes. Error: -x/-m must follow the probe definitions. You can now use it in all perf tools, such as: perf record -e %s:%s -aR sleep 1 Error: Failed to add events. # %d sender and receiver %s per group perf bench sched messaging <options> Use pipe() instead of socketpair() Be multi thread instead of multi process Specify the number of loops to run (default: 100) Failed to open cgroup file in %s Hint: create the cgroup first, like 'mkdir %s/%s' it should have two cgroup names: %s # Executed %d pipe operations between two %s perf bench sched pipe <options> Specify threads/process based task setup Put sender and receivers in given cgroups can't create a notification descriptor can't set the parent death signal can't set SECCOMP_USER_NOTIF_FD_SYNC_WAKE_UP SECCOMP_IOCTL_NOTIF_RECV failed SECCOMP_IOCTL_NOTIF_SEND failed perf bench sched secccomp-notify <options> Enable the synchronous mode for seccomp notifications # Memory allocation failed - maybe size (%s) is too large? No CONFIG_PERF_EVENTS=y kernel support configured? Failed to open cycles counter Default memset() provided by glibc unrolled memset() in arch/x86/lib/memset_64.S movsq-based memset() in arch/x86/lib/memset_64.S perf bench mem memset <options> perf bench mem memcpy <options> Default memcpy() provided by glibc unrolled memcpy() in arch/x86/lib/memcpy_64.S movsq-based memcpy() in arch/x86/lib/memcpy_64.S Specify the size of the memory buffers. Available units: B, KB, MB, GB and TB (case insensitive) Specify the function to run, "all" runs all available functions, "help" lists them Specify the number of loops to run. (default: 1) Use a cycles event instead of gettimeofday() to measure performance Non-expected futex return call Run summary [PID %d]: %d threads, each operating on %d [%s] futexes for %d secs. [thread %2d] futex: %p [ %ld ops/sec ] [thread %2d] futexes: %p ... %p [ %ld ops/sec ] %sAveraged %ld operations/sec (+- %.2f%%), total secs = %d perf bench futex hash <options> Specify amount of futexes per threads Silent mode: do not display data/details Use shared futexes instead of private ones Lock all current and future memory Run summary [PID %d]: blocking on %d threads (at [%s] futex %p), waking up %d at a time. Wokeup %d of %d threads in %.4f ms (+-%.2f%%) [Run %d]: Wokeup %d of %d threads in %.4f ms perf bench futex wake <options> Specify amount of threads to wake at once couldn't wakeup all tasks (%d/%d) Run summary [PID %d]: blocking on %d threads (at [%s] futex %p), %d threads waking up %d at a time. Avg per-thread latency (waking %d/%d threads) in %.4f ms (+-%.2f%%) [Run %d]: Avg per-thread latency (waking %d/%d threads) in %.4f ms (+-%.2f%%) perf bench futex wake-parallel <options> Specify amount of waking threads Run summary [PID %d]: Requeuing %d threads (from [%s] %p to %s%p), %d at a time. Requeued %d of %d threads in %.4f ms (+-%.2f%%) couldn't requeue from %p to %p [Run %d]: Requeued %d of %d threads in %.4f ms [Run %d]: Awoke and Requeued (%d+%d) of %d threads in %.4f ms perf bench futex requeue <options> Specify amount of threads to requeue at once Use PI-aware variants of FUTEX_CMP_REQUEUE thread %d: Could not lock pi-lock for %p (%d) thread %d: Could not unlock pi-lock for %p (%d) Run summary [PID %d]: %d threads doing pi lock/unlock pairing for %d secs. [thread %3d] futex: %p [ %ld ops/sec ] perf bench futex lock-pi <options> starting writer-thread: doing %s writes ... exiting writer-thread (total full-loops: %zd) Setting RLIMIT_NOFILE rlimit from %lu to: %lu Run summary [PID %d]: %d threads monitoring%s on %d file-descriptors for %d secs. starting worker/consumer %sthreads%s [thread %2d] fdmap: %p [ %04ld ops/sec ] [thread %2d] fdmap: %p ... %p [ %04ld ops/sec ] Averaged %ld operations/sec (+- %.2f%%), total secs = %d perf bench epoll wait <options> Specify amount of file descriptors to monitor for each thread Enable random write behaviour (default is lineal) Use multiple epoll instances (one per thread) Nonblocking epoll_wait(2) behaviour Nesting level epoll hierarchy (default is 0, no nesting) Use Edge-triggered interface (default is LT) Run summary [PID %d]: %d threads doing epoll_ctl ops %d file-descriptors for %d secs. [thread %2d] fdmap: %p [ add: %04ld; mod: %04ld; del: %04lds ops ] [thread %2d] fdmap: %p ... %p [ add: %04ld ops; mod: %04ld ops; del: %04ld ops ] Averaged %ld ADD operations (+- %.2f%%) Averaged %ld MOD operations (+- %.2f%%) Averaged %ld DEL operations (+- %.2f%%) perf bench epoll ctl <options> Perform random operations on random fds Average %ssynthesis took: %.3f usec (+- %.3f usec) Average num. events: %.3f (+- %.3f) Average time per event %.3f usec Computing performance of single threaded perf event synthesis by synthesizing events on the perf process itself: Computing performance of multi threaded perf event synthesis by synthesizing events on CPU 0: Number of synthesis threads: %u Average synthesis took: %.3f usec (+- %.3f usec) Average num. events: %.3f (+- %.3f) Average time per event %.3f usec perf bench internals synthesize <options> Minimum number of threads in multithreaded bench Maximum number of threads in multithreaded bench Number of iterations used to compute single-threaded average Number of iterations used to compute multi-threaded average Average kallsyms__parse took: %.3f ms (+- %.3f ms) perf bench internals kallsyms-parse <options> Number of iterations used to compute average %d operations %d bits set of %d bits Average for_each_set_bit took: %.3f usec (+- %.3f usec) Average test_bit loop took: %.3f usec (+- %.3f usec) perf bench mem find_bit <options> Number of outer iterations used Number of inner iterations used Build-id%s injection benchmark Build-id injection setup failed Average build-id%s injection took: %.3f msec (+- %.3f msec) Average time per event: %.3f usec (+- %.3f usec) Average memory usage: %.0f KB (+- %.0f KB) Cannot collect DSOs for injection perf bench internals inject-build-id <options> Number of iterations used to compute average (default: 100) Number of mmap events for each iteration (default: 100) Number of sample events per mmap event (default: 100) be more verbose (show iteration count, DSO name, etc) Not enough memory to create evlist Run 'perf list' for a list of valid events Not enough memory to create thread/cpu maps Number of events: %d (%d fds) Average open-close took: %.3f usec (+- %.3f usec) perf bench internals evlist-open-close <options> number of dummy events to create (default 1). If used with -e, it clones those events n times (1 = no change) Number of iterations used to compute average (default=100) list of cpus where to open events Skipping perf bench breakpoint thread: No hardware support # Created/joined %d threads with %d breakpoints and %d parallelism Skipping perf bench breakpoint enable: No hardware support # Enabled/disabled breakpoint %d time with %d passive and %d active threads perf bench breakpoint enable <options> Specify amount of passive threads Specify amount of active threads perf bench breakpoint thread <options> Computing performance of sysfs PMU event scan for %u times pmu[%d] name=%s, nr_caps=%d, nr_aliases=%d, nr_formats=%d Failed to initialize PMU scan result Unmatched number of event caps in %s: expect %d vs got %d Unmatched number of event aliases in %s: expect %d vs got %d Unmatched number of event formats in %s: expect %d vs got %d Average%s PMU scanning took: %.3f usec (+- %.3f usec) perf bench internals pmu-scan <options> binding to node %d, mask: %016lx => %d WARNING: Could not enable THP - do: 'echo madvise > /sys/kernel/mm/transparent_hugepage/enabled' WARNING: Could not disable THP: run a CONFIG_TRANSPARENT_HUGEPAGE kernel? # thread %2d / %2d global mem: %p, process mem: %p, thread mem: %p (injecting perturbalance, moved to CPU#%d) #%2d / %2d: %14.2lf nsecs/op [val: %016lx] Test not applicable, system has only %d CPUs. Test not applicable, bind_cpu_0 or bind_cpu_1 is offline # NOTE: ignoring bind CPUs starting at CPU#%d # # NOTE: %d tasks bound, %d tasks unbound Test not applicable, system has only %d nodes. # NOTE: ignoring bind NODEs starting at NODE#%d # NOTE: %d tasks mem-bound, %d tasks unbound # %d %s will execute (on %d nodes, %d CPUs): # %5dx %5ldMB global shared mem operations # %5dx %5ldMB process shared mem operations # %5dx %5ldMB thread local mem operations # Startup synchronization: ... # process %2d global mem: %p, process mem: %p threads initialized in %.6f seconds. secs slowest (max) thread-runtime secs fastest (min) thread-runtime % difference between max/avg runtime # Running %s "perf bench numa echo ' #'; echo ' # Running test on: '$(uname -a); echo ' #' perf bench numa mem [<options>] process serialized/locked memory access (MBs), <= process_memory max number of loops to run (default: unlimited) max number of seconds to run (default: 5 secs) usecs to sleep per loop iteration access the data via reads (can be mixed with -W) access the data via writes (can be mixed with -R) access the data backwards as well access the data via glibc bzero only access the data with random (32bit LFSR) walk randomize the contents of the initial allocations do the initial allocations on CPU#0 perturb thread 0/0 every X secs, to test convergence stability MADV_NOHUGEPAGE < 0 < MADV_HUGEPAGE show convergence details, convergence is reached when each process (all its threads) is running on a single NUMA node. quiet mode (do not show any warnings or messages) bind the first N tasks to these specific cpus (the rest is unbound) bind the first N tasks to these specific memory nodes (the rest is unbound) perf test [<options>] [{list <test-name-fragment>|[<test-name-fragments>|<test-numbers>]}] Out of memory while building test list Out of memory while duplicating test script string failed to parse event '%s', err %d, str '%s' %s/bus/event_source/devices/%s/alias %s/bus/event_source/devices/%s/events/ skipping PMU %s events tests: %s pmu event name crossed PATH_MAX(%d) size can't open pmu event file for '%s' pmu event: %s is a null event skipping parameterized PMU event: %s which contains ? Test PMU event failed for '%s' COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks config=10,config1,config2=3,config3=4,umask=1,read,r0xead failed to parse terms '%s', err %d Event test failure: test %d '%s' Parse event definition strings Parsing of all PMU events from sysfs Parsing of given PMU events from sysfs Parsing of aliased events from sysfs Parsing of terms (event modifiers) cpu/config=10,config1=1,config2=3,period=1000/u cpu/config=1,name=krava/u,cpu/config=2/u cpu/config=1,call-graph=fp,time,period=100000/,cpu/config=2,call-graph=no,time=0,period=2000/ cpu/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks',period=0x1,event=0x2/ukp cpu/L1-dcache-misses,name=cachepmu/ cpu/cycles,period=100000,config2/ {cpu/instructions/k,cpu/cycles/upp} {cpu/cycles/u,cpu/instructions/kp}:p {cpu/cycles/,cpu/cache-misses/G}:H {cpu/cycles/,cpu/cache-misses/H}:G {cpu/cycles/G,cpu/cache-misses/H}:u {cpu/cycles/G,cpu/cache-misses/H}:uG {cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:S {cpu/instructions/,cpu/branch-misses/}:Su {cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:D {cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:e r1,syscalls:sys_enter_openat:k,1:1:hp {faults:k,cache-references}:u,cycles:k group1{syscalls:sys_enter_openat:H,cycles:kppp},group2{cycles,1:3}:G,instructions:u {cycles,instructions}:G,{cycles:G,instructions:G},cycles {cycles,cache-misses,branch-misses}:S {instructions,branch-misses}:Su {cycles,cache-misses,branch-misses}:D L1-dcache-misses/name=cachepmu/ cycles/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks'/Duk {cycles,cache-misses,branch-misses}:e mem:0/1/name=breakpoint1/,mem:0/4:rw/name=breakpoint2/ test attr - failed to open event file test attr - failed to write event file '/usr/bin/python3' %s/attr.py -d %s/attr/ -p %s %.*s WARN: Maps in vmlinux with a different name in kallsyms: WARN: %lx-%lx %lx %s in kallsyms as machine__create_kernel_maps failed Couldn't find a vmlinux that matches the kernel running on this machine, skipping test WARN: %#lx: diff end addr for %s v: %#lx k: %#lx WARN: %#lx: diff name v: %s k: %s ERR : %#lx: %s not on kallsyms vmlinux symtab matches kallsyms failed to open counter: %s, tweak /proc/sys/kernel/perf_event_paranoid? evsel__read_on_cpu: expected to intercept %d calls, got %lu sched_setaffinity() failed on CPU %d: %s evsel__read_on_cpu: expected to intercept %d calls on cpu %d, got %lu Detect openat syscall event on all cpus openat_syscall_event_on_all_cpus %s: Expected flags=%#x, got %#x syscalls:sys_enter_openat event fields failed to get mmapped address userspace counter access not %s userspace counter width not set (%d) failed to read value for evsel failed to mmap events: %d (%s) event with id %lu doesn't map to an evsel expected %d %s events, got %d Read samples using the mmap interface User space counter reading of instructions User space counter reading of cycles sched__get_first_possible_cpu: %s %s going backwards in time, prev=%lu, curr=%lu %s with unexpected cpu, expected %d, got %d %s with unexpected pid, expected %d, got %d %s with unexpected tid, expected %d, got %d Unexpected perf_event->header.type %d! Excessive number of PERF_RECORD_COMM events! Missing PERF_RECORD_COMM for %s! PERF_RECORD_MMAP for %s missing! PERF_RECORD_* events & perf_sample fields failed to parse event '%s', err %d Failure to parse cache event '%s' possibly as PMUs don't support it perf_evsel__roundtrip_name_test %s: "%s" signedness(%d) is wrong, should be %d %s: "%s" size (%d) should be %d! Parse sched tracepoints fields fdarray__filter()=%d != %d shouldn't have filtered anything fdarray__filter()=%d != %d, should have filtered all fds filtering all but fda->entries[2]: fdarray__filter()=%d != 1, should have left just one event filtering all but (fda->entries[0], fda->entries[3]): fdarray__filter()=%d != 2, should have left just two events %d: fdarray__add(fda, %d, %d) failed! %d: fdarray__add(fda, %d, %d)=%d != %d %d: fda->entries[%d](%d) != %d! %d: fda->entries[%d].revents(%d) != %d! Add fd to a fdarray, making it autogrow Filter fds with revents mask in a fdarray config2:0-3,10-13,20-23,30-33,40-43,50-53,60-63 Expected broken metric %s skipping testing event table: found %d, but expected %d Missing test event in test architecture testing core PMU %s aliases: failed testing core PMU %s aliases: no events to match testing core PMU %s aliases: pass testing aliases uncore PMU %s: mismatch expected aliases (%d) vs found (%d) testing aliases uncore PMU %s: mismatched matching_pmu, %s vs %s testing aliases uncore PMU %s: could not match alias %s testing aliases uncore PMU %s: mismatch found aliases (%d) vs matched (%d) testing aliases PMU %s: mismatched name, %s vs %s testing aliases PMU %s: mismatched desc, %s vs %s testing aliases PMU %s: mismatched long_desc, %s vs %s testing aliases PMU %s: mismatched topic, %s vs %s testing aliases PMU %s: mismatched str, %s vs %s testing aliases PMU %s: mismatched pmu_name, %s vs %s testing aliases core PMU %s: matched event %s testing event e1 %s: mismatched name string, %s vs %s testing event e1 %s: mismatched compat string, %s vs %s testing event e1 %s: mismatched event, %s vs %s testing event e1 %s: mismatched desc, %s vs %s testing event e1 %s: mismatched topic, %s vs %s testing event e1 %s: mismatched long_desc, %s vs %s testing event e1 %s: mismatched pmu string, %s vs %s testing event e1 %s: mismatched unit, %s vs %s testing event e1 %s: mismatched perpkg, %d vs %d testing event e1 %s: mismatched deprecated, %d vs %d testing sys event table %s: pass testing sys event table: could not find event %s testing event table: could not find event %s Parsing of PMU event table metrics Parsing of PMU event table metrics with fake PMUs Parsing of metric thresholds with fake PMUs (unc_p_power_state_occupancy.cores_c0 / unc_p_clockticks) * 100. imx8_ddr0@read\-cycles@ * 4 * 4 imx8_ddr0@axid\-read\,axi_mask\=0xffff\,axi_id\=0x0000@ * 4 (cstate_pkg@c2\-residency@ / msr@tsc@) * 100 (imx8_ddr0@read\-cycles@ + imx8_ddr0@write\-cycles@) Counts total cache misses in first lookup result (high priority) uncore_imc_free_running.cache_miss unc_cbo_xsnp_response.miss_eviction A cross-core snoop resulted from L3 Eviction which misses in some processor core Attributable Level 3 cache access, read event=0x3a,period=200000,umask=0x0 Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions event=0x3a,period=0x30d40,umask=0 event=0x9,period=200000,umask=0x20 Memory cluster signals to block micro-op dispatch for any reason event=0x9,period=0x30d40,umask=0x20 event=0x6,period=200000,umask=0x80 Number of segment register loads event=0x6,period=0x30d40,umask=0x80 Not enough memory for machine setup %2d: entry: %-8s [%-8s] %20s: period = %lu %2d: entry: %8s:%5d [%-8s] %20s: period = %lu/%lu Invalid count for matched entries: %zd of %zd A entry from the other hists should have pair Invalid count of dummy entries: %zd of %zd Invalid count of total leader entries: %zd of %zd Other hists should not have dummy entries: %zd Not enough memory for adding a hist entry Unmatched nr samples for thread filter Unmatched nr hist entries for thread filter Unmatched total period for thread filter Unmatched nr samples for dso filter Unmatched nr hist entries for dso filter Unmatched total period for dso filter Unmatched nr samples for symbol filter Unmatched nr hist entries for symbol filter Unmatched total period for symbol filter Unmatched nr samples for socket filter Unmatched nr hist entries for socket filter Unmatched total period for socket filter Unmatched nr samples for all filter Unmatched nr hist entries for all filter Unmatched total period for all filter use callchain: %d, cumulate callchain: %d Incorrect number of hist entry Invalid callchain entry #%zd/%zd Incorrect number of callchain entry echo "import sys ; sys.path.insert(0, '%s'); import perf" | %s %s failed setting up signal handler failed setting up signal handler 2 count1 %lld, count2 %lld, count3 %lld, overflow %d, overflows_2 %d failed: RF EFLAG recursion issue detected failed: wrong count for bp1: %lld, expected 1 failed: wrong overflow (%d) hit, expected 3 failed: wrong overflow_2 (%d) hit, expected 3 failed: wrong count for bp2 (%lld), expected 3 failed: wrong count for bp3 (%lld), expected 2 Breakpoint overflow signal handler Wrong number of executions %lld != %d Wrong number of overflows %d != %d way too many debug registers, fix the test watchpoints count %d, breakpoints count %d, has_ioctl %d, share %d ioctl(PERF_EVENT_IOC_MODIFY_ATTRIBUTES) failed Failed after retrying 1000 times Number of exit events of a simple workload /proc/sys/kernel/perf_event_max_sample_rate Couldn't open evlist: %s Hint: check %s, using %lu in this test. failed to mmap event: %d (%s) All (%d) samples have period value of 1! Software clock events period values failed with sythesizing process Failed to parse event dummy:u Failed to move cycles event to front Front event no longer at front Non-tracking event is tracking perf_evlist__disable_event failed! sched_switch: cpu: %d prev_tid %d next_tid %d cycles events even though event was disabled parse_event(evlist, "dummy:u") failed! parse_event(evlist, "cycles:u") failed! Unable to open dummy and cycles event evlist__mmap(evlist, UINT_MAX) failed! prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0) failed! First time, failed to find tracking event. evsel__disable(evsel) failed! Second time, failed to find tracking event. Use a dummy software event to keep tracking machine__create_kernel_maps failed thread_map__new_by_tid failed perf_event__synthesize_thread_map failed machine__findnew_thread failed perf_evlist__open() failed! %s temp-perf-code-reading-test-file-- Reading object code for memory address: %#lx Hypervisor address can not be resolved - skipping Unexpected kernel address - skipping skipping the module address %#lx after text end Too many kcore maps - skipping %s -z -d --start-address=0x%lx --stop-address=0x%lx %s addr going backwards, read beyond section? objdump read too few bytes: %zd Bytes read differ from those read by objdump Bytes read match those read by objdump machine__process_event failed, event type %u Samples differ at 'stream_id' Samples differ at 'read.group.nr' Samples differ at 'read.one.value' Samples differ at 'read.time_enabled' Samples differ at 'read.time_running' Samples differ at 'read.group.values[i]' Samples differ at 'read.one.id' Samples differ at 'read.one.lost' Samples differ at 'callchain->nr' Samples differ at 'callchain->ips[i]' Samples differ at 'branch_stack->nr' Samples differ at 'branch_stack->hw_idx' Samples differ at 'branch_stack->entries[i]' Samples differ at 'user_regs.mask' Samples differ at 'user_regs.abi' Samples differ at 'user_regs' Samples differ at 'user_stack.size' Samples differ at 'user_stack' Samples differ at 'transaction' Samples differ at 'intr_regs.mask' Samples differ at 'intr_regs.abi' Samples differ at 'intr_regs' Samples differ at 'phys_addr' Samples differ at 'data_page_size' Samples differ at 'code_page_size' Samples differ at 'aux_sample.size' Samples differ at 'aux_sample' %s failed for sample_type %#lx, error %d Event size mismatch: actual %zu vs expected %zu parsing failed for sample_type %#lx perf_event__process_attr failed Parse with no sample_id_all bit set %s - alloc name %d, kmod %d, comp %d, name '%s' %s (cpumode: %d) - is_kernel_module: %s Session header CPU map not set Cpu map - CPU ID doesn't match Cpu map - Core ID doesn't match Cpu map - Socket ID doesn't match Cpu map - Die ID doesn't match Core map - Core ID doesn't match Core map - Socket ID doesn't match Core map - Die ID doesn't match Die map - Socket ID doesn't match Die map - Die ID doesn't match Socket map - Socket ID doesn't match Socket map - Thread IDX is set Node map - Node ID doesn't match failed to intersect map: bad nr failed to intersect map: bad result failed to merge map: bad result 1,3,5,7,9,11,13,15,17,19,21-40 failed to synthesize stat_config failed to synthesize attr update unit failed to synthesize attr update scale failed to synthesize attr update name failed to synthesize attr update cpus failed to parse event cpu-clock:u attaching to spawned child, enable on exec attaching to current thread as enabled failed to call thread_map__new attaching to current thread as disabled Failed to open event cpu-clock:u attaching to CPU 0 as enabled failed to call perf_cpu_map__new 100 if 1 else 200 if 1 else 300 100 if 0 else 200 if 1 else 300 100 if 1 else 200 if 0 else 300 100 if 0 else 200 if 0 else 300 EVENT1\,param\=?@ + EVENT2\,param\=?@ EVENT1 if #core_wide else EVENT2 1.0 if EVENT1 > 100.0 else 1.0 syscalls:sys_enter_prctl/overwrite/ Failed to parse tracepoint event, try use root Unexpected counter: sample_count=%d, comm_count=%d Skip SDT event test because SDT support is not compiled SIGSEGV is observed as expected, try to recover. start: %lu end: %lu name: '%s' refcnt: %d start: %lu end: %lu name: '%s' refcnt: 1 Failed. ptime %lu expected %lu perf_time__parse_for_ranges("%s") first_sample_time %lu last_sample_time %lu bad size: range_size %d range_num %d expected num %d bad range %d expected %lu to %lu 1234567.123456789,1234567.123456789 1234567.123456789,1234567.123456790 1234567.123456789,1234567.123456790 7654321.987654321,7654321.987654444 8000000,8000000.000000005 10000000000000000000000000000abcdefgh99i 10000000000000000000000000000000000000000000000000000000000123456789ab99c Ljava/lang/StringLatin1;equals([B[B)Z boolean java.lang.StringLatin1.equals(byte[], byte[]) Ljava/util/zip/ZipUtils;CENSIZ([BI)J long java.util.zip.ZipUtils.CENSIZ(byte[], int) Ljava/util/regex/Pattern$BmpCharProperty;match(Ljava/util/regex/Matcher;ILjava/lang/CharSequence;)Z boolean java.util.regex.Pattern$BmpCharProperty.match(java.util.regex.Matcher, int, java.lang.CharSequence) Ljava/lang/AbstractStringBuilder;appendChars(Ljava/lang/String;II)V void java.lang.AbstractStringBuilder.appendChars(java.lang.String, int, int) camlStdlib__anon_fn$5bstdlib$2eml$3a334$2c0$2d$2d54$5d_1453 Stdlib.anon_fn[stdlib.ml:334,0--54]_1453 camlStdlib__bytes__$2b$2b_2205 test of individual --pfm-events cpu_clk_unhalted.one_thread_active Frontend_Bound_SMT failed, wrong ratio DCache_L2_Hits failed, wrong ratio DCache_L2_Misses failed, wrong ratio L1D_Cache_Fill_BW, wrong ratio cache_miss_cycles failed, wrong ratio group cache_miss_cycles failed, wrong ratio failed to expand events for cgroups evsel[%d]: %s expected: %s event group doesn't match: got %s, expect %s event group member doesn't match: %d vs %d failed to expand default events failed to expand metric events perf_read_tsc_conversion is not supported in current kernel prctl(PR_SET_NAME, (unsigned long)comm1, 0, 0, 0) failed! prctl(PR_SET_NAME, (unsigned long)comm2, 0, 0, 0) failed! evsel = evlist__event2evsel(evlist, event) failed! evsel__parse_sample(evsel, event, &sample) failed! 1st event perf time %lu tsc %lu rdtsc time %lu tsc %lu 2nd event perf time %lu tsc %lu This architecture does not support perf_read_tsc_conversion is not supported -- Testing version %d API -- /tmp/dlfilter-test-%u-perf-data Filter used by the 'dlfilter C API' perf test Failed to get expected filter description int bar(){};int foo(){bar();};int main(){foo();return 0;} Creating new host machine structure Failed to find program symbols Failed to create test perf.data file perf_header__write_pipe() failed perf_event__synthesize_attr() failed perf_event__synthesize_sample() failed %s script -i %s --dlfilter %s/%s --dlarg first --dlarg %d --dlarg %lu --dlarg %lu --dlarg %d --dlarg last perf_event_attr doesn't have sigtrap FAILED sys_perf_event_open(): %s missing signals or incorrectly delivered Using %s for uncore pmu event 0x%x 0x%lx, 0x%x 0x%lx, 0x%x 0x%lx: %s machine__findnew_thread() failed! failed: crossed the max stack value %d failed: got unresolved address 0x%lx got wrong number of stack entries %lu != %d write failure on standard output: %s unknown write failure on standard output close failed on standard output: %s No directory given for --debugfs-dir. No directory given for --buildid-dir. No variable specified for --debug. No path given for --debug-file. Open debug file '%s' failed: %s Failed to run command '%s': %s %s: failed to initialize %s arch priv area ^[ct]?br?\.?(cc|cs|eq|ge|gt|hi|hs|le|lo|ls|lt|mi|ne|pl|vc|vs)?n?z?$ ^blx?(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl|vc|vs)?$ ^bx?(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl|vc|vs)?$ ---------------------------------------------- %*[^,],%u,%[^,],%[^,],%[^,],%s %s(%d): ERANGE! sym->name=%s, start=%#lx, addr=%#lx, end=%#lx %s(%d): ENOMEM! sym->name=%s, start=%#lx, addr=%#lx, end=%#lx, func: %d %#lx %s: period++ [addr: %#lx, %#lx, evidx=%d] => nr_samples: %lu, period: %lu Not enough memory for annotate.disassembler_style Not enough memory for annotate.objdump Not enough memory for annotate.addr2line (Average IPC: %.2f, IPC Coverage: %.1f%%) %s: filename=%s, sym=%s, start=%#lx, end=%#lx annotating [%p] %30s : [%p] %30s %s %s%s --start-address=0x%016lx --stop-address=0x%016lx %s -d %s %s %s %c%s%c %s%s -C "$1" Failure allocating memory for the command to run Failure creating FILE stream for %s Failure allocating memory for tab expansion BB with bad start: addr %lx start %lx sym %lx saddr %lx No vmlinux file%s was found in the path. Note that annotation using /proc/kcore requires CAP_SYS_RAWIO capability. Please use: perf buildid-cache -vu vmlinux or: --vmlinux vmlinux Please link with binutils's libopcode to enable BPF annotation Problems with arch specific instruction name regular expressions. Problems while parsing the CPUID in the arch specific initialization. The %s BPF file has no BTF section, compile with -g or use pahole -J. Internal error: Invalid %d error code %-*.*s| Source code & Disassembly of %s for %s (%lu samples, percent: %s) --prefix-strip requires --prefix build <%s> already linked to %s Failed to update/scan SDT cache for %s bad config value for '%s' in %s, ignoring... bad config value for '%s', ignoring... Not enough memory to process %s/.perfconfig, ignoring it. File %s not owned by current user or root, ignoring it. bad config file line %d in %s Error in the given config file: wrong config key-value pair %s=%s no arch specific strerrno function unknown stat config term %llu %d/%d - nr_namespaces: %u [ %d/%d: [%#llx(%#llx) @ %#llx]: %c %s %d/%d: [%#llx(%#llx) @ %#llx <%s>]: %c%c%c%c %s %d/%d: [%#llx(%#llx) @ %#llx %02x:%02x %llu %llu]: %c%c%c%c %s failed to get threads from event failed to get cpumap from event offset: %#llx size: %#llx flags: %#llx [%s%s%s] addr %llx len %u type %u flags 0x%x name %s rounding mmap pages size to %s (%lu pages) Invalid argument for --mmap_pages/-m Read format differs %#lx vs %#lx FATAL: evlist->threads need to be set at this point (%s:%d). Error: %s. Hint: Check /proc/sys/kernel/perf_event_paranoid setting. For your workloads it needs to be <= 1 Hint: For system wide tracing it needs to be set to -1. Hint: Try: 'sudo sh -c "echo -1 > /proc/sys/kernel/perf_event_paranoid"' Hint: The current value is %d. kernel/perf_event_max_sample_rate Error: %s. Hint: Check /proc/sys/kernel/perf_event_max_sample_rate. Hint: The current value is %d and %lu is being requested. Error: %s. Hint: Check /proc/sys/kernel/perf_event_mlock_kb (%d kB) setting. Hint: Tried using %zd kB. Hint: Try 'sudo sh -c "echo %d > /proc/sys/kernel/perf_event_mlock_kb"', or Hint: Try using a smaller -m/--mmap-pages value. Control descriptor is not initialized Failed to add ctl fd entry: %m failed to write to ctl_ack_fd %d: %m Failed to read from ctlfd %d: %m failed: can't find '%s' event WARNING: A requested CPU in '%s' is not supported by PMU '%s' (CPUs %s) for event '%s' cannot locate proper evsel for the side band event enabling sample_id_all for all side band events LBR callstack option is only available to get user callchain information. Falling back to framepointers. Cannot use LBR callstack with branch stack. Falling back to framepointers. WARNING: The use of --call-graph=dwarf may require all the user registers, specifying a subset with --user-regs may render DWARF unwinding unreliable, so the minimal registers set (IP, SP) is explicitly forced. Cannot use DWARF unwind for function trace event, falling back to framepointers. Disabling user space callchains for function trace event. unknown-ext-hardware-cache-type unknown-ext-hardware-cache-result per-event callgraph setting for %s failed. Apply callgraph global setting for it decreasing precise_ip by one (%d) switching off branch counters support switching off PERF_FORMAT_LOST support switching off weight struct support Kernel has no PERF_SAMPLE_CODE_PAGE_SIZE support, bailing out Kernel has no PERF_SAMPLE_DATA_PAGE_SIZE support, bailing out Kernel has no cgroup sampling support, bailing out switching off branch HW index support Kernel has no attr.aux_output support, bailing out PMU has no exclude_host/guest support, bailing out switching off exclude_guest, exclude_host switching off branch sample type no (cycles/flags) sys_perf_event_open: pid %d cpu %d group_fd %d flags %#lx sys_perf_event_open failed, error %d failed to attach bpf fd %d: %s WARNING: Ignored open failure for pid %d The cycles event is not supported, trying to fall back to %s kernel.perf_event_paranoid=%d, trying to fall back to excluding kernel and hypervisor samples Access to performance monitoring and observability operations is limited. Enforced MAC policy settings (SELinux) can limit access to performance monitoring and observability operations. Inspect system audit records for more perf_event access control information and adjusting the policy. No permission to enable %s event. Consider adjusting /proc/sys/kernel/perf_event_paranoid setting to open access to performance monitoring and observability operations for processes without CAP_PERFMON, CAP_SYS_PTRACE or CAP_SYS_ADMIN Linux capability. More information can be found at 'Perf events and tool security' document: https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html perf_event_paranoid setting is %d: -1: Allow use of (almost) all events by all users Ignore mlock limit after perf_event_mlock_kb without CAP_IPC_LOCK >= 0: Disallow raw and ftrace function tracepoint access >= 1: Disallow CPU event access >= 2: Disallow kernel profiling To make the adjusted perf_event_paranoid setting permanent preserve it in /etc/sysctl.conf (e.g. kernel.perf_event_paranoid = <setting>) The %s event is not supported. Too many events are opened. Probably the maximum number of open file descriptors has been reached. Hint: Try again after reducing the number of events. Hint: Try increasing the limit with 'ulimit -n <limit>' /proc/sys/kernel/perf_event_max_stack Not enough memory to setup event with callchain. Hint: Try tweaking /proc/sys/kernel/perf_event_max_stack Hint: Current value: %d No such device - did you specify an out-of-range profile CPU? %s: PMU Hardware or event type doesn't support branch stack sampling. %s: PMU Hardware doesn't support 'aux_output' feature %s: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat' 'precise' request may not be supported. Try removing 'p' modifier. No hardware sampling interrupt available. The PMU counters are busy/taken by another profiler. We found oprofile daemon running, please stop it and try again. Asking for the code page size isn't supported by this kernel. Asking for the data page size isn't supported by this kernel. Reading from overwrite event is not supported by this kernel. clockid feature not supported. The 'aux_output' feature is not supported, update the kernel. Invalid event (%s) in per-thread mode, enable system wide with '-a'. Cannot collect data source with the load latency event alone. Please add an auxiliary event in front of the load latency event. The sys_perf_event_open() syscall returned with %d (%s) for event (%s). /bin/dmesg | grep -i perf may provide additional information. <not enough memory for the callchain cursor>%s PERF_COUNT_HW_STALLED_CYCLES_BACKEND PERF_COUNT_HW_STALLED_CYCLES_FRONTEND PERF_COUNT_HW_BRANCH_INSTRUCTIONS PERF_COUNT_HW_CACHE_REFERENCES PERF_COUNT_SW_EMULATION_FAULTS PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_CONTEXT_SWITCHES PERF_COUNT_HW_CACHE_OP_PREFETCH PERF_COUNT_HW_CACHE_RESULT_ACCESS PERF_COUNT_HW_CACHE_RESULT_MISS { sample_period, sample_freq } { wakeup_events, wakeup_watermark } ERROR: switch-%s event not found (%s) HINT: use 'perf evlist' to see the available event names failed to mmap perf event ring buffer, error %d failed to alloc mmap affinity mask, error %d failed to init mmap compressor, error %d failed to mmap data buffer, error %d failed to allocate aiocb for data buffer, error %m failed to allocate cblocks for data buffer, error %m failed to allocate data buffer, error %m failed to allocate data buffer area, error %m Failed to allocate node mask for mbind: error %m Failed to bind [%p-%p] AIO buffer to node %lu: error %m invalid or unsupported event: WARNING: failed to provide error string or struct Multiple errors dropping message: %s (%s) WARNING: failed to set leader: empty list WARNING: event parser found nothing WARNING: events were regrouped to match PMUs --filter option should follow a -e tracepoint or HW tracer option not enough memory to hold filter string --exclude-perf option should follow a -e tracepoint option '%s' is not usable in 'perf stat' valid terms: call-graph,stack-size Failed to find PMU for type %d Cannot find PMU `%s'. Missing kernel support? ..after resolving event: %s/%s/ Error: failed to open tracing events directory Failed to allocate new strlist for SDT Failed to allocate new strlist for symbol events %s/t1=v1[,t2=v2,t3 ...]/modifier (see 'man perf-list' on how to encode it) Fail to find IP register for arch %s, returns 0 Fail to find SP register for arch %s, returns 0 Couldn't bump rlimit(MEMLOCK), failures may take place when creating BPF maps, etc this should not happen, your vsnprintf is broken ............................................................................................................................................................................................................... --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PerfTop:%8.0f irqs/sec kernel:%4.1f%% exact: %4.1f%% lost: %lu/%lu drop: %lu/%lu [ PerfTop:%8.0f irqs/sec kernel:%4.1f%% us:%4.1f%% guest kernel:%4.1f%% guest us:%4.1f%% exact: %4.1f%% [ DSO data fd counter out of bounds. Internal error: passing unmasked cpumode (%x) to is_kernel_module Failed to check whether %s is a kernel module or not. Assume it is. DSO %s is still in rbtree when being deleted! %s/sys/module/%.*s/notes/.note.gnu.build-id Internal tools/perf/ library error acpi_processor_ffh_cstate_enter mwait_idle_with_hints.constprop.0 %s/proc/{kallsyms,modules} inconsistency while looking for "%s" module! Failed to open %s. Note /proc/kcore requires CAP_SYS_RAWIO capability to access. Using %s for kernel object code Looking at the vmlinux_path (%d entries long) No kallsyms or vmlinux with build-id %s was found Annotation needs to be init before symbol__init() '.' is the only non valid --field-separator argument /proc/sys/kernel/kptr_restrict /usr/lib/debug/boot/vmlinux-%s /usr/lib/debug/lib/modules/%s/vmlinux /usr/lib/debug/boot/vmlinux-%s.debug Bad metric-id encoding in: '%s' Cannot find metric or group `%s' Try disabling the NMI watchdog to comply NO_NMI_WATCHDOG metric constraint: echo 0 > /proc/sys/kernel/nmi_watchdog perf stat ... echo 1 > /proc/sys/kernel/nmi_watchdog Events in '%s' fully contained within '%s' Cannot resolve IDs for %s: %s failed: recursion detected for %s Not grouping metric %s's events. copying metric event for cgroup '%s': %s (idx=%d) devices/system/cpu/cpu%d/cache/index%d/ # directory data version : %lu # contains samples with branch stack # contains AUX area data (e.g. instruction trace) # compressed : %s, level = %d, ratio = %d # CPU %d: Core ID %d, Die ID %d, Socket ID %d # Core ID, Die ID and Socket ID information is not available # CPU %d: Core ID %d, Socket ID %d # Core ID and Socket ID information is not available # memory nodes (nr %d, block size 0x%llx): # sample duration : %10.3f ms # pmu mappings: not available # pmu mappings: unable to read # node%u meminfo : total = %lu kB, free = %lu kB Error: calling %s in pipe-mode. failed to write buildid table cannot find event format for %d # %s pmu capabilities: not available # reference time: %s = %ld.%06d (TOD) = %ld.%09ld (%s) Failed to process auxtrace index Failed to write auxtrace index Pipe ABI%d perf.data file detected ABI%d perf.data file detected, need_swap=%d build id event received for %s: %s [%zu] Failed to read buildids, continuing... %s: couldn't read %s, does this arch have topology information? Failed to write MEM_TOPOLOGY, size %zd nodes %s/devices/system/node/node%lu failed: can't open memory sysfs data # AMD systems uses ibs_op// PMU for some precise events, e.g.: cycles:p, see the 'perf list' man page for further details. devices/system/memory/block_size_bytes cpu pmu capabilities not available pmu capabilities not available %s pmu capabilities not available interpreting btf from systems with endianness is not yet supported interpreting bpf_prog_info from systems with endianness is not yet supported detected invalid bpf_prog_info Reserved bits are set unexpectedly. Please update perf tool. Unknown sample type (0x%llx) is detected. Please update perf tool. Unknown read format (0x%llx) is detected. Please update perf tool. Unknown branch sample type (0x%llx) is detected. Please update perf tool. # event desc: not available or unable to read socket_id number is too big.You may need to upgrade the perf tool. failed to write perf header attribute failed to write feature section Invalid regular expression %s /sys/devices/system/cpu/cpu%d/online devices/system/cpu/cpu%d/online Failed to lseek to %lu offset for feature %d, continuing... # %s info available, use -I to display failed to write perf pipe header In-place update not supported when byte-swapping is required WARNING: The %s file's data size field is 0 which is unexpected. Was the 'perf record' command properly terminated? ERROR: The %s file's attr size field is 0 which is unexpected. Was the 'perf record' command properly terminated? cannot read %d bytes of header attr file uses a more recent and unsupported ABI (%zu bytes extra) invalid record type %d in pipe-mode failed to get event_update cpus %s: repiping tracing data padding %s: tracing data size mismatch not enough memory to create child for code path tree Warning: empty node in callchain tree not enough memory for the code path tree not enough memory for the code path branch statistics callchain cursor creation failed callchain: Incorrect stack dump size (max %ld): %s callchain: No more arguments needed for --call-graph lbr callchain: Unknown --call-graph option value: %s Can't register callchain params Invalid callchain sort key: %s Invalid callchain threshold: %s Invalid callchain print limit: %s failed to allocate read_values threads arrays failed to allocate read_values counters arrays failed to enlarge read_values threads arrays failed to allocate read_values counters array failed to enlarge read_values rawid array failed to enlarge read_values ->values array INTERNAL ERROR: Failed to allocate counterwidth array . ... raw event: size %d bytes Discarding thread maps for %d:%d Failed to join map groups for %d:%d Problems setting modules path maps, continuing anyway... Failed to allocate space for stitched LBRs. Disable LBR stitch corrupted branch chain. skipping... problem inserting idle task for machine pid %d problem processing PERF_RECORD_COMM, skipping event. WARNING: kernel seems to support more namespaces than perf tool. Try updating the perf tool.. WARNING: perf tool seems to support more namespaces than the kernel. Try updating the kernel.. problem processing PERF_RECORD_NAMESPACES, skipping event. %s: unsupported cpumode - ignoring Failed to write kernel text poke at %#llx Failed to find kernel text poke address map for %#llx Added extra kernel map %s %lx-%lx Problems creating module maps, continuing anyway... Problems creating module maps for guest %d, continuing anyway... Problems creating extra kernel maps, continuing anyway... invalid directory (%s). Skipping. problem processing PERF_RECORD_MMAP2, skipping event. problem processing PERF_RECORD_MMAP, skipping event. removing erroneous parent thread %d/%d problem processing PERF_RECORD_FORK, skipping event. %.*s/platforms/%.*s/arch-%s/usr/lib/%s Internal error: map__kmaps with a non-kernel map %.*s was updated (is prelink enabled?). Restart the long running apps that use it! no symbols found in %s, maybe install a debug package? Internal error: map__kmap with a non-kernel map Internal error: kernel dso with non kernel map overlapping maps in %s (disable tui for more info) Couldn't allocate memory for decompression Reloading kvm_intel module with vmm_exclusive=0 will reduce the gaps to only guest's timeslices. Processed %d events and lost %d chunks! Check IO/CPU overload! Processed %lu samples and lost %3.2f%%! AUX data lost %lu times out of %u! module/kvm_intel/parameters/vmm_exclusive AUX data had gaps in it %lu times out of %u! Are you running a KVM guest in the background?%s AUX data detected collision %lu times out of %u! Found %u unknown events! Is this an older tool processing a perf.data file generated by a more recent tool? If that is not the case, consider reporting to linux-kernel@vger.kernel.org. %u samples with id not present in the header Found invalid callchains! %u out of %u events were discarded for this reason. Consider reporting to linux-kernel@vger.kernel.org. %u unprocessable samples recorded. Do you have a KVM guest running and not using 'perf kvm'? %u out of order events recorded. %d map information files for pre-existing threads were not processed, if there are samples for addresses they will not be resolved, you may find out which are these threads by running with -v and redirecting the output to a file. The time limit to process proc map is too short? Increase it by --proc-map-timeout cpu_map swap: unsupported long size ... %s regs: mask 0x%lx ABI %s (IP, 0x%x): %d/%d: %#lx period: %lu addr: %#lx ..... %2lu: %016lx ..... %2lu: %016lx ..... %2lu: %016lx -> %016lx %hu cycles %s%s%s%s %x %s %s ... branch stack counters: nr:%lu (counter width: %u max counter nr:%u) ... ustack: size %lu, offset 0x%x %s: head=%#lx event->header.size=%#x, mmap_size=%#zx: fuzzed or compressed perf.data? %#lx [%#x]: failed to process type: %d %#lx [%#x]: failed to process type: %d [%s] incompatible file format (rerun with -v to learn more) failed to allocate memory to read event unexpected end of event stream No trace sample to read. Did you call 'perf %s'? (excludes AUX area (e.g. instruction trace) decoded / synthesized events) File does not contain CPU events. Remove -C option to proceed. Requested CPU %d too large. Consider raising MAX_NR_CPUS Invalid counter set entry at %zd Invalid counter set data encountered [%#08zx] Trailer:%c%c%c%c%c Cfvn:%d Csvn:%d Speed:%d TOD:%#llx 1:%lx 2:%lx 3:%lx TOD-Base:%#llx Type:%x [%#08zx] Counterset:%d Counters:%d Counter:%03d %s Value:%#018lx Invalid %s raw data encountered Invalid raw IBS Fetch MSR data encountered L3MissOnly %d FetchOcMiss %d FetchL3Miss %d ibs_fetch_ctl: %016llx MaxCnt %7d Cnt %7d Lat %5d En %d Val %d Comp %d%s PhyAddrValid %d%s L1TlbMiss %d L2TlbMiss %d RandEn %d%s%s ic_ibs_ext_ctl: %016llx IbsItlbRefillLat %3d ibs_op_ctl: %016llx MaxCnt %9d%s En %d Val %d CntCtl %d=%s CurCnt %9d ibs_op_data: %016llx CompToRetCtr %5d TagToRetCtr %5d%s%s%s BrnRet %d RipInvalid %d BrnFuse %d Microcode %d ibs_op_data2: %016llx %sRmtNode %d%s ibs_op_data3: %016llx LdOp %d StOp %d DcL1TlbMiss %d DcL2TlbMiss %d DcL1TlbHit2M %d DcL1TlbHit1G %d DcL2TlbHit2M %d DcMiss %d DcMisAcc %d DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d DcLinAddrValid %d DcPhyAddrValid %d DcL2TlbHit1G %d%s SwPf %d%s%s DcMissLat %5d TlbRefillLat %5d Invalid raw IBS Op MSR data encountered DataSrc 1=Local L3 or other L1/L2 in CCX DataSrc 2=Another CCX cache in the same NUMA node DataSrc 5=Another CCX cache in a different NUMA node DataSrc 7=MMIO/Config/PCI/APIC DataSrc 12=Coherent Memory of a different processor type next_flush - ordered_events__flush PRE %s, nr_events %u Processing time ordered events... next_flush - ordered_events__flush POST %s, nr_events %u last flush, last_flush_type %d alloc size %luB (+%zu), max %luB allocation limit reached %luB broken map groups on thread %d/%d parent %d/%d Couldn't resolve comm name for pid %d out of dynamic memory in yyensure_buffer_stack() out of dynamic memory in yy_create_buffer() out of dynamic memory in yylex() flex scanner push-back overflow fatal flex scanner internal error--end of buffer missed input buffer overflow, can't enlarge buffer because scanner uses REJECT out of dynamic memory in yy_get_next_buffer() fatal flex scanner internal error--no action found out of dynamic memory in yy_scan_buffer() out of dynamic memory in yy_scan_bytes() yyset_lineno called with no buffer yyset_column called with no buffer Unable to find PMU or event on a PMU of '%s' Unable to find event on a PMU of '%s' alias %s differs in field '%s' ('%s' != '%s') unknown term '%s' for pmu '%s' Required parameter '%s' not specified value too big for format, maximum is %llu WARNING: '%s' format '%s' requires 'perf_event_attr::config%d'which is not supported by this version of perf! Attempt to set event's unit twice Attempt to set event's scale twice Attempt to set event snapshot twice WARNING: event '%s' not valid (bits %s of %s '%llx' not supported by kernel)! Failure to set up any core PMUs FATAL: not enough memory to print PMU events fatal error - scanner input buffer overflow <?xml version="1.0" standalone="no"?> <!DOCTYPE svg SYSTEM "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"> <svg width="%i" height="%lu" version="1.1" xmlns="http://www.w3.org/2000/svg"> <defs> <style type="text/css"> <![CDATA[ rect { stroke-width: 1; } rect.process { fill:rgb(180,180,180); fill-opacity:0.9; stroke-width:1; stroke:rgb( 0, 0, 0); } rect.process2 { fill:rgb(180,180,180); fill-opacity:0.9; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.process3 { fill:rgb(180,180,180); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.sample { fill:rgb( 0, 0,255); fill-opacity:0.8; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.sample_hi{ fill:rgb(255,128, 0); fill-opacity:0.8; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.error { fill:rgb(255, 0, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.net { fill:rgb( 0,128, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.disk { fill:rgb( 0, 0,255); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.sync { fill:rgb(128,128, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.poll { fill:rgb( 0,128,128); fill-opacity:0.2; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.blocked { fill:rgb(255, 0, 0); fill-opacity:0.5; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.waiting { fill:rgb(224,214, 0); fill-opacity:0.8; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.WAITING { fill:rgb(255,214, 48); fill-opacity:0.6; stroke-width:0; stroke:rgb( 0, 0, 0); } rect.cpu { fill:rgb(192,192,192); fill-opacity:0.2; stroke-width:0.5; stroke:rgb(128,128,128); } rect.pstate { fill:rgb(128,128,128); fill-opacity:0.8; stroke-width:0; } rect.c1 { fill:rgb(255,214,214); fill-opacity:0.5; stroke-width:0; } rect.c2 { fill:rgb(255,172,172); fill-opacity:0.5; stroke-width:0; } rect.c3 { fill:rgb(255,130,130); fill-opacity:0.5; stroke-width:0; } rect.c4 { fill:rgb(255, 88, 88); fill-opacity:0.5; stroke-width:0; } rect.c5 { fill:rgb(255, 44, 44); fill-opacity:0.5; stroke-width:0; } rect.c6 { fill:rgb(255, 0, 0); fill-opacity:0.5; stroke-width:0; } line.pstate { stroke:rgb(255,255, 0); stroke-opacity:0.8; stroke-width:2; } <title>fd=%d error=%d merges=%d</title> <rect x="%.8f" width="%.8f" y="%.1f" height="%.1f" class="%s"/> <title>#%d blocked %s</title> <title>#%d running %s</title> <desc>Switched because: %s</desc> <text x="%.8f" y="%.8f" font-size="%.8fpt">%i</text> <g transform="translate(%.8f,%.8f)"> <title>#%d waiting %s</title> <rect x="0" width="%.8f" y="0" height="%.1f" class="%s"/> <text transform="rotate(90)" font-size="%.8fpt"> %s</text> <rect x="%.8f" width="%.8f" y="%.1f" height="%.1f" class="cpu"/> <text x="%.8f" y="%.8f">%s</text> /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies <text transform="translate(%.8f,%.8f)" font-size="1.25pt">%s</text> <title>%d %s running %s</title> <text transform="rotate(90)" font-size="%.8fpt">%s</text> <rect class="%s" x="%.8f" width="%.8f" y="%.1f" height="%.1f"/> <text x="%.8f" y="%.8f" font-size="%.8fpt">C%i</text> <line x1="%.8f" x2="%.8f" y1="%.1f" y2="%.1f" class="pstate"/> <text x="%.8f" y="%.8f" font-size="0.25pt">%s</text> <title>%s wakes up %s</title> <line x1="%.8f" y1="%.2f" x2="%.8f" y2="%.2f" style="stroke:rgb(32,255,32);stroke-width:0.009"/> <g transform="translate(%.8f,%.8f)"><text transform="rotate(90)" font-size="0.02pt">%s ></text></g> <g transform="translate(%.8f,%.8f)"><text transform="rotate(90)" font-size="0.02pt">%s <</text></g> <circle cx="%.8f" cy="%.2f" r = "0.01" style="fill:rgb(32,255,32)"/> <title>Wakeup from interrupt</title> <circle cx="%.8f" cy="%.2f" r = "0.01" style="fill:rgb(255,128,128)"/> <rect x="%i" width="%.8f" y="0" height="%.1f" class="%s"/> <text transform="translate(%.8f, %.8f)" font-size="%.8fpt">%s</text> <line x1="%.8f" y1="%.2f" x2="%.8f" y2="%lu" style="stroke:rgb(%i,%i,%i);stroke-width:%.3f"/> topology: can't parse siblings map No memory to alloc tracepoints list can't get tracing/events/header_page can't record header_page file can't get tracing/events/header_event can't record header_event file can't get tracing/events/ftrace can't get tracing/printk_formats can't get tracing/saved_cmdline Python scripting not supported. Install libpython and rebuild perf to enable it. For example: # apt-get install python-dev (ubuntu) # yum install python-devel (Fedora) etc. Perl scripting not supported. Install libperl and rebuild perf to enable it. For example: # apt-get install libperl-dev (ubuntu) # yum install 'perl(ExtUtils::Embed)' (Fedora) etc. Error registering Python script extension: disabling it Error registering Perl script extension: disabling it printk format with empty entry reading input file (size expected=%d received=%d) not a trace file (missing 'tracing' tag) '%s' event is ambiguous: it can be %s or %s Cannot find event field for %s.%s Not enough memory to set up --sort Not enough memory to setup sort keys Not enough memory to setup overhead keys The "dcacheline" --sort key needs to know the cacheline size and it couldn't be determined on this system Not enough memory to setup output fields Samples: %lu%c of event%s '%s',%s%sEvent count (approx.): %lu FATAL ERROR: Couldn't setup hists class kernel/perf_event_max_contexts_per_stack Open /proc/version_signature failed: %s Reading from /proc/version_signature failed: %s Parsing /proc/version_signature failed: %s Unable to get kernel version from /proc/version_signature '%s' Unable to get kernel version from uname '%s' WARNING: debuginfod support requested, but perf is not built with it devices/system/cpu/cpu%d/topology/%s %s/devices/system/cpu/possible sysfs path crossed PATH_MAX(%d) size Failed to read max cpus, using default of %d %s/devices/system/node/possible Failed to read max nodes, using default of %d cpu_map__new_data unknown type %d %s/devices/system/cpu/cpu%d/topology/die_cpus_list %s/devices/system/cpu/cpu%d/topology/package_cpus_list %s/devices/system/cpu/cpu%d/topology/core_siblings_list %s/devices/system/cpu/cpu%d/topology/core_cpus_list %s/devices/system/cpu/cpu%d/topology/thread_siblings_list %s/devices/system/node/node%d/meminfo %s/devices/system/node/node%d/cpulist must define events before cgroups PID/TID switch overriding SYSTEM SYSTEM/CPU switch overriding PER-THREAD Problems obtaining information for user %s failed to read per-pkg counter Unmatched aggregation mode between aliases Failed to resolve counter for stat event. Failed to find perf count for CPU %d thread %d on event %s. ... id %llu, cpu %d, thread %d ... value %llu, enabled %llu, running %llu "core" : "S%d-D%d-C%d", "aggregate-number" : %d, "cache" : "S%d-D%d-L%d-ID%d", "aggregate-number" : %d, "die" : "S%d-D%d", "aggregate-number" : %d, "socket" : "S%d", "aggregate-number" : %d, "node" : "N%d", "aggregate-number" : %d, "event-runtime" : %lu, "pcnt-running" : %.2f, Performance counter stats for Cannot allocate per-core aggr map for display %*s# Table of individual measurements: %17.*f +- %.*f seconds time elapsed Some events weren't counted. Try disabling the NMI watchdog: echo 0 > /proc/sys/kernel/nmi_watchdog perf stat ... echo 1 > /proc/sys/kernel/nmi_watchdog The events in group usually have to be from the same PMU. Try reorganizing the group. cannot set frequency and period at the same time frequency and count are zero, aborting error: Maximum frequency rate (%'u Hz) exceeded. Please use -F freq option with a lower value or consider tweaking /proc/sys/kernel/perf_event_max_sample_rate. warning: Maximum frequency rate (%'u Hz) exceeded, throttling from %'u Hz to %'u Hz. The limit can be raised via /proc/sys/kernel/perf_event_max_sample_rate. The kernel will lower it when perf's interrupts take too long. Use --strict-freq to disable this throttling, refusing to record. Lowering default frequency rate from %u to %u. Please consider tweaking /proc/sys/kernel/perf_event_max_sample_rate. couldn't read /proc/sys/kernel/perf_event_max_sample_rate info: Using a maximum frequency rate of %'d Hz %s %s: addr2line read address for sentinel: %s %s %s: addr2line read line: %s %s %s: addr2line filename:number : %s addr2line missing ':' in filename split Failed to allocate memory for addr2line could not start addr2line (%s) for %s: start_command return code %d %s %s: addr2line_subprocess_init failed Detected LLVM addr2line style Detected binutils addr2line style %s %s: addr2line configuration failed Unknown/broken addr2line style %s %s: could not send request %s %s: could not read first record %s %s: could not read sentinel record %s %s: unexpected record instead of sentinel not enough memory for the srcline node not enough memory for the inline node Failed to read build ID for %s Couldn't get COMM, tigd and ppid for pid %d Name: string not found for pid %d Tgid: string not found for pid %d PPid: string not found for pid %d Reading %s/proc/%d/task/%d/maps time out. You may want to increase the time limit by --proc-map-timeout cannot find cgroup mount point Not enough memory synthesizing mmap event for kernel modules Perf runs in non-root PID namespace but it tries to gather process info from its parent PID namespace. Please mount the proc file system properly, e.g. add the option '--mount-proc' for unshare command. failed to create perf header attribute Couldn't synthesize evsel unit. Couldn't synthesize evsel evsel. Couldn't synthesize evsel cpus. Couldn't synthesize evsel name. No record header feature for header :%d Couldn't synthesize features. Couldn't record tracing data. Can't remove old data: %s (%s) Can't move data: %s (%s to %s) File %s not owned by current user or root (use -f to override) zero-sized data (%s), nothing to do! failed to get perf_event_mmap_page lock Synthesizing TSC conversion information perf_event_open(..., PERF_FLAG_FD_CLOEXEC) failed with unexpected error %d (%s) perf_event_open(..., 0) failed unexpectedly with error %d (%s) Out of memory: no thread stack Out of memory: discarding thread stack iostat mode is not supported on current platform [ Hot streams in old perf data only ] [ Hot streams in new perf data only ] auxtrace idx %d old %#lx head %#lx diff %#lx Multiple symbols with name '%s' Disambiguate symbol name by inserting #n after the name e.g. %s #2 Or select a global symbol by inserting #0 or #g or #G N'th occurrence (N=%d) of symbol '%s' not found. Global symbol '%s' not found. Note that symbols must be functions. Failed to parse /proc/kallsyms Multiple kernel symbols with name '%s' AUX area tracing is not supported on this architecture No AUX area tracing to snapshot Bad AUX area sampling option: '%s' Cannot add AUX area sampling to an AUX area event Cannot add AUX area sampling to a group leader AUX area sample size %u too big, max. %d Cannot add AUX area sampling because group leader is not an AUX area event AUX area sampling requires an AUX area event group leader plus other events to which to add samples AUX area sampling is not supported by kernel Synthesizing auxtrace information size: %#llx offset: %#llx ref: %#llx idx: %u tid: %d cpu: %d Bad Instruction Tracing options '%s' cpu %d pid %d tid %d ip %#llx code %u: %s Error: number of address filters (%d) exceeds maximum (%d) Kernel addresses are restricted. Unable to resolve kernel symbols. Symbol '%s' (0x%lx) comes before '%s' (0x%lx) Symbol '%s' (0x%lx) comes before address 0x%lx) Cannot determine size of symbol '%s' Failed to load symbols from: %s File '%s' not found or has no symbols. Failed to determine filter for %s Cannot determine file size. Failed to parse address filter: '%s' Filter format is: filter|start|stop|tracestop <start symbol or address> [/ <end symbol or size>] [@<file name>] Where multiple filters are separated by space or comma. %s 0x%llx Hints 0x%x Extensions 0x%x %s 0x%llx HW:%u CState:%u Sub-CState:%u %s 0x%llx Last CState:%u Deepest CState:%u Wake Reason 0x%x %s IP:%d Type 0x%02x Vector 0x%llx Suppressing CYC timestamp 0x%lx less than current timestamp 0x%lx CTC timestamp 0x%lx last MTC %#x CTC rem %#x Timestamp: calculated %g TSC ticks per cycle too big (c.f. CBR-based value %g), pos 0x%lx Timestamp: calculated %g TSC ticks per cycle c.f. CBR-based value %g, pos 0x%lx Timestamp: calculated %g TSC ticks per cycle c.f. unknown CBR-based value, pos 0x%lx ERROR: Failed to get instruction ERROR: Conditional branch when expecting indirect branch ERROR: Unexpected branch at FUP instruction ERROR: Unexpected indirect branch ERROR: Unexpected conditional branch Buffer 1st timestamp 0x%lx ref timestamp 0x%lx Suppressing MTC timestamp 0x%lx less than current timestamp 0x%lx Suppressing backwards timestamp ERROR: RET when expecting conditional branch ERROR: Bad RET compression (stack empty) ERROR: Bad RET compression (TNT=N) ERROR: Missing deferred TIP for indirect branch ERROR: Missing FUP after MODE.TSX ERROR: Missing FUP after PTWRITE ERROR: Missing FUP after EXSTOP WARNING: Unknown block type %u WARNING: Duplicate block type %u WARNING: Unknown block item %u type %d WARNING: Duplicate block item %u type %d timestamp: tsc_ctc_ratio_n %u timestamp: tsc_ctc_ratio_d %u Hop mode: decoding FUP and TIPs, but not TNT ERROR: First TSC is not in PSB+ Translated VM TSC %#lx -> %#lx VMCS %#lx TSC Offset %#lx ERROR: First TSC, unknown TSC Offset ERROR: First TSC, no PIP, unknown TSC Offset %s: intel_pt_ctc_to_tsc(decoder, new_ctc_delta) %#lx ERROR: Unknown TSC Offset for VMCS %#lx Fast forward towards timestamp 0x%lx Fast forward to next PSB timestamp 0x%lx Trace doesn't match instruction Never-ending loop (refer perf config intel-pt.max-loops) TIP.PGD ip %#lx offset %#lx in %s hit filter: %s offset %#lx size %#lx TIP.PGD ip %#lx offset %#lx in %s is not in a filter region Intel Processor Trace: failed to deliver error event, error %d Intel PT: failed to deliver event, error %d . ... Intel Processor Trace data: size %zu bytes ERROR: cpu %d expecting switch ip ERROR: guest sideband but no guest machine ERROR: thread has no dso for %#lx ERROR: thread has no map for %#lx ERROR: failed to read at offset %#lx Emulated ptwrite signature found Emulated ptwrite signature not found queue %u decoding cpu %d pid %d tid %d PEBS-via-PT record with no applicable_counters PEBS-via-PT record with no matching event, hw_id %d queue %u processing 0x%lx to 0x%lx Intel Processor Trace requires ordered events queue %u cpu %d pid %d tid %d sched_switch: cpu %d tid %d time %lu tsc %#lx itrace_start: cpu %d pid %d tid %d time %lu tsc %#lx Expecting CPU-wide context switch event context_switch event has no tid Invalidated instruction cache for %s at %#lx event %u: cpu %d time %lu tsc %#lx There are no selected events with Intel Processor Trace data Synthesizing '%s' event with id %lu sample type %#lx %s: failed to synthesize '%s' event type %s: filter string not null terminated Intel PT has no time information for VM Time Correlation Time ranges cannot be specified with VM Time Correlation MTC packets must have been enabled for VM Time Correlation Failed to parse VM Time Correlation options %s: missing sched_switch event %s: missing context_switch attribute flag range %d: perf time interval: %lu to %lu range %d: TSC time interval: %#lx to %#lx WARNING: Intel PT with pipe mode is not recommended. The output cannot relied upon. In particular, timestamps and the order of events may be incorrect. Intel PT decoding without timestamps Intel BTS: failed to deliver error event, error %d Intel BTS: failed to deliver branch event, error %d There are no selected events with Intel BTS data Synthesizing 'branches' event with id %lu sample type %#lx %s: failed to synthesize 'branches' event type Intel BTS requires ordered events . ... Intel BTS data: size %zu bytes ARM SPE: failed to deliver event, error %d . ... ARM SPE data: size %#zx bytes No data or all data has been processed. SPE trace requires ordered events Arm SPE CONTEXT packets not found in the traces. Matching of TIDs to SPE events could be inaccurate. No selected events with SPE trace data Only instruction-based sampling period is currently supported by Arm SPE. Arm SPE has a hardware-based sample period. Additional instruction events will be discarded by --itrace ignoring unsupported address packet index: 0x%x . ... HISI PTT data: size %zu bytes %s %x %s %x %s %x %s %x %s %x %s %x %s %x %s %x %s pos:%#zx ip:%#lx P:%d CL:%d pid:%d.%d cpumode:%d cpu:%d s390 Auxiliary Trace: failed to deliver event Failed to find auxtrace log directory %s, continue with current directory... Missing auxtrace log directory %s, continue with current directory... s390 Auxiliary Trace: failed to deliver error event,error %d . ... s390 AUX data: size %zu bytes Invalid AUX trace data block size:%zu (type:%d bsdes:%hd dsdes:%hd) Invalid AUX trace basic entry [%#08zx] [%#08zx] Basic Def:%04x Inst:%#04x %c%c%c%c AS:%d ASN:%#04x IA:%#018llx CL:%d HPP:%#018llx GPP:%#018llx Invalid AUX trace diagnostic entry [%#08zx] [%#08zx] Diag Def:%04x %c Invalid AUX trace trailer entry [%#08zx] [%#08zx] Trailer %c%c%c bsdes:%d dsdes:%d Overflow:%lld Time:%#llx C:%d TOD:%#lx s390 Auxiliary Trace requires ordered events Failed to open counter set log file %s, continue... Failed to write counter set data Failed to open auxiliary log file %s,continue... Failed to write auxiliary data %s queue_nr:%d buffer:%ld offset:%#lx size:%#zx rest:%#zx [%#08lx] Invalid AUX trailer entry TOD clock base Unsupported --itrace options specified CS ETM Trace: Unknown Header Version = %#lx Magic number Unknown %lx Unknown parameter [%d] %lx CS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1 TRCDEVARCH %llx TS_SOURCE %lld PMU type/num cpus %llx unknown branch filter %s, check man page Error: Can't use --branch-any (-b) with --branch-filter (-j). Unknown register "%s", check man page or run "perf record %s?" ERROR: Failed to allocate command list for unknown command. WARNING: You called a perf program named '%s', which does not exist. Continuing under the assumption that you meant '%s' in %0.1f seconds automatically... perf: '%s' is not a perf-command. See 'perf --help'. failed: event '%s' not found, use '-e list' to get list of available events failed: event '%s' not supported HINT: no first/last sample time found in perf data. Please use latest perf binary to execute 'perf record' (if '--buildid-all' is enabled, please set '--timestamp-boundary'). lookup(%s): ref metric name %s processing metric: %s EXIT: %f lookup(%s): ref val %f metric name %s No memory nodes, is CONFIG_MEMORY_HOTPLUG enabled? mem2node %03lu [0x%016lx-0x%016lx] WARNING: Failed to determine specified clock resolution. unknown clockid %s, check man page Missing PLT entry size for %s %s: problems reading %s PLT info. Failed to decompress (error %d) %s %s: truncating reading of build id in sysfs file %s: n_namesz=%u, n_descsz=%u. unrecognized DSO data encoding %d %s: build id mismatch for %s. %s: failed to find program header for symbol: %s st_value: %#lx %s: adjusting symbol: st_value: %#lx sh_addr: %#lx sh_offset: %#lx %s: adjusting symbol: st_value: %#lx p_vaddr: %#lx p_offset: %#lx Failed to get build-id from %s. Failed to add build-id cache: %s strlist__add failed with -ENOMEM run this command again with sudo. try 'sudo mount -o remount,mode=755 /sys/kernel/tracing/' No permission to %s tracefs. Please %s Debugfs or tracefs is not mounted Please try 'sudo mount -t tracefs nodev /sys/kernel/tracing/' %s/%s does not exist. Please rebuild kernel with %s. Failed to open %s/%cprobe_events: %s CONFIG_KPROBE_EVENTS=y and CONFIG_UPROBE_EVENTS=y Failed to open %s/kprobe_events: %s. Failed to open %s/uprobe_events: %s. Failed to synthesize probe trace event. Internal error: %s should have ':' but not. Failed to get a valid sdt type Module %s is not loaded, please specify its full path name. Failed to find the path for the kernel: %s Rebuild with CONFIG_DEBUG_INFO=y, or install an appropriate debuginfo package. The %s file has no debug information. %s is blacklisted function, skip it. Warning: The probe function (%s) is a GNU indirect function. Consider identifying the final function used at run time and set the probe directly on that. Symbol %s address found : %lx Specified source line is not found. Failed to find source file path. Source file is shorter than expected. Semantic error :%s is bad for event name -it must follow C symbol-naming rule. Error: event "%s" already exists. Hint: Remove existing event by 'perf probe -d' or force duplicates by 'perf probe -f' or set 'force=yes' in BPF source. Internal error: "%s" is an invalid event name. Too many events are on the same function. Failed to find the address of %s Semantic error :'%s' is not a valid number. Semantic error :Start line must be smaller than end line. Semantic error :Tailing with invalid str '%s'. Semantic error :'%s' is not a valid function name. Semantic error :Too many probe arguments (%d). Semantic error :%s must be an SDT name. Semantic error :Invalid absolute address. Semantic error :There is non-digit char in line number. Semantic error :There is non-digit character in offset. Semantic error :SRC@SRC is not allowed. Semantic error :%%%s is not supported. This program has a bug at %s:%d. Semantic error :Lazy pattern can't be used with line number. Semantic error :Lazy pattern can't be used with offset. Semantic error :Offset can't be used with line number. Semantic error :File always requires line number or lazy pattern. Semantic error :Offset requires an entry function. Semantic error :Offset/Line/Lazy pattern can't be used with return probe. symbol:%s file:%s line:%d offset:%lu return:%d lazy:%s Semantic error :ftrace does not support user access Semantic error :Array index must be a number. Semantic error :Argument parse error: %s Semantic error :You can't specify local variable for kretprobe. Semantic error :Too few probe arguments. Semantic error :Failed to parse event name: %s try to find information at %lx in %s Failed to find corresponding probes from debuginfo. Failed to find probe point from both of dwarf and map. No kprobe blacklist support, ignored Too many entries matched in the cache of %s Could not open debuginfo. Try to use symbols. Try to find probe point from debuginfo. Failed to get ELF symbols for %s Relocated base symbol is not found! Check /proc/sys/kernel/kptr_restrict and /proc/sys/kernel/perf_event_paranoid. Or run as privileged perf user. Post processing failed or all events are skipped. (%d) An error occurred in debuginfo analysis (%d). Warning: No dwarf info found in the vmlinux - please rebuild kernel with CONFIG_DEBUG_INFO=y. Failed to load symbols from %s Please ensure the file is not stripped. Please ensure you can read the /proc/kallsyms symbol addresses. If /proc/sys/kernel/kptr_restrict is '2', you can not read kernel symbol addresses even if you are a superuser. Please change it to '1'. If kptr_restrict is '1', the superuser can read the symbol addresses. In that case, please run this command again with sudo. Failed to find symbol %s in %s Too many functions matched in %s Found duplicated symbol %s @ %lx Too many symbols are listed. Skip it. Offset %ld is bigger than the size of %s WARN: Group name %s is ignored ERROR: Bootconfig doesn't support uprobes %sftrace.event.kprobes.%s.probe = Failed to get current event list. A semaphore is associated with %s:%s and seems your kernel doesn't support it. %s accesses a variable by symbol name, but that is not supported for user application probe. Please upgrade your kernel to at least 3.14 to have access to feature %s Failed to add event to probe cache Failed to find symbols matched to "%s" Specified offset is out of %s Failed to find symbol at 0x%lx Failed to find "%s%%return", because %s is an inlined function and has no return point. Mapping for the register number %u missing on this architecture. Failed to get the type of %s. Semantic error: %s must be referred by '->' %s is not a data structure nor a union. Semantic error: %s is not a pointer nor array. Semantic error: %s must be referred by '.' Structure on a register is not supported yet. %s(type:%s) has no member %s. Failed to get the offset of %s. Too many( > %d) probe point found. Searching '%s' variable in context. Failed to find '%s' in this function. Converting variable %s into trace event. Failed to find the location of the '%s' variable at this address. Perhaps it has been optimized out. Use -V with the --range option to show '%s' location range. Sorry, we don't support this variable location yet. Failed to get a type information of %s. Failed to cast into string: %s(%s) is not a pointer nor array. Failed to get a type information. Failed to cast into string: %s is not (unsigned) char *. %s exceeds max-bitwidth. Cut down to %d bits. Failed to convert variable type: %s Caller must pass a scope DIE. Program error. Failed to find probe point in any functions. Failed to get call frame on 0x%jx Probe line found: line:%d addr:0x%llx Failed to find scope of probe point. This line is sharing the address with other lines. Please try to probe at %s:%d instead. Failed to find debug information for address %#lx No matched lines found in %s. A function DIE doesn't have decl_line. Maybe broken DWARF? Target program is compiled without optimization. Skipping prologue. Probe on address 0x%lx to force probing at the function entry. Failed to get entry address of %s. %s has no valid entry address. skipped. Unable to get offset:Unexpected OP %x (%zd) Failed to get the declared file name of %s Failed to get CU from given DIE. Failed to get source lines on this CU. Failed to get line info. Possible error in debuginfo. Failed to get type, make it unknown. ELF MACHINE %x is not supported. offset: %d is bigger than size: %lu cannot find CU for address %lx unwind: get_proc_name unsupported unwind: access_fpreg unsupported unwind: put_unwind_info called unwind: Register unavailable. unwind: %s:ip = 0x%lx (0x%lx) unwind: access_mem %p not inside range 0x%lx-0x%lx unwind: access_mem addr %p val %lx, offset %d unwind: Can't create unwind address space. unwind: find_proc_info dso %s unwind: thread map already set, dso=%s unwind: target platform=%s is not supported --all is currently unsupported for JSON output. --tod is currently unsupported for JSON output. Output file exists. Use --force to overwrite it. Failed to get mtime of source file, not writing captured-on [ perf data convert: Converted '%s' into JSON data '%s' ] [ perf data convert: Converted and wrote %.3f MB (%lu samples) ] # perf script event handlers, generated by perf script -g python # Licensed under the terms of the GNU GPL License version 2 # The common_* event handler fields are the most useful fields common to # all events. They don't necessarily correspond to the 'common_*' fields # in the format files. Those fields not available as handler params can # be retrieved using Python functions of the form common_*(context). # See the perf-script-python Documentation for the list of available functions. from __future__ import print_function sys.path.append(os.environ['PERF_EXEC_PATH'] + \ '/scripts/python/Perf-Trace-Util/lib/Perf/Trace') from perf_trace_context import * print_header(event_name, common_cpu, common_secs, common_nsecs, common_pid, common_comm) print('Sample: {'+get_dict_as_string(perf_sample_dict['sample'], ', ')+'}') for node in common_callchain: print(" [%%x] %%s%%s%%s%%s" %% ( node['ip'], node['sym']['name'], "+0x{:x}".format(node['sym_off']) if 'sym_off' in node else "", " ({})".format(node['dso']) if 'dso' in node else "", " " + node['sym_srcline'] if 'sym_srcline' in node else "")) print(" [%%x]" %% (node['ip'])) def trace_unhandled(event_name, context, event_fields_dict, perf_sample_dict): print(get_dict_as_string(event_fields_dict)) def print_header(event_name, cpu, secs, nsecs, pid, comm): print("%%-20s %%5u %%05u.%%09u %%8u %%-20s " %% \ (event_name, cpu, secs, nsecs, pid, comm), end="") def get_dict_as_string(a_dict, delimiter=' '): return delimiter.join(['%%s=%%s'%%(k,str(v))for k,v in sorted(a_dict.items())]) problem in Python trace event handler couldn't create Python dictionary Error running python script %s Error starting python script %s failed to create calls processor failed to create call path root Failed to setting regs in dict ug! no event found for type %lu Unsupported decompressor flags The input is not in the .xz format Compressed file is truncated or otherwise corrupt lzma: fopen failed on %s: '%s' lzma: lzma_stream_decoder failed %s (%d) Couldn't create compression stream. Failed to initialize compression stream: %s failed to compress %ld bytes: %s Couldn't create decompression stream. Failed to initialize decompression stream: %s failed to decompress (B): %zd -> %zd, dst_size %zd : %s demangle-rust: unexpected escape sequence demangle-rust: unexpected character '%c' in symbol problem processing JIT mmap event, skipping it. version=%u hdr.size=%u ts=0x%llx pid=%d elf_mach=%d use_arch_timestamp=%d wrong jitdump version %u, expected 1 jitdump file contains invalid or unsupported flags 0x%llx jitdump file uses arch timestamps but there is no timestamp conversion next_entry: unknown record type %d, skipping %s: thread %d not found or created error, jitted code must be sampled with perf record -k 1 Fatal error (SEGFAULT) in perf hook '%s' %s: failed to get BPF program info. aborting %s: failed to get BTF of id %u, aborting unexpected bpf event type of %d %s: can't get next program: %s%s %s: failed to get fd for prog_id %u %s: the kernel is too old, aborting %s: mismatch in BPF sub program count and BTF function info count, aborting %s: failed to synthesize bpf images: %s # bpf_prog_info %u: %s addr 0x%llx size %u # sub_prog %u: %s addr 0x%llx size %u %s: mismatch in element count binutils for %s not supported. Please install %s for %s. You can add it to PATH, set CROSS_COMPILE or override the default using --%s. Invalid CPUID %s. Full CPUID is required, vendor-family-model-stepping Failed to read /proc/cpuinfo for TSC frequency Failed to find TSC frequency in /proc/cpuinfo ^([+\-]?)([0-9]*)(\(?)(%[a-z][a-z0-9]+)(\)?)$ Skipping unsupported SDT argument: %s Not enough memory synthesizing mmap event for extra kernel maps {%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled and tagged operation does not cause L3 Miss. This causes sampling period skew. AMD IBS doesn't support privilege filtering. Try again without the privilege modifiers (like 'k') at the end. Invalid mapping data: iio_%d; die%d The -e and -M options are not supported.All chosen events/metrics will be dropped {uncore_iio_%x/event=0x83,umask=0x04,ch_mask=0xF,fc_mask=0x07/, uncore_iio_%x/event=0x83,umask=0x01,ch_mask=0xF,fc_mask=0x07/, uncore_iio_%x/event=0xc0,umask=0x04,ch_mask=0xF,fc_mask=0x07/, uncore_iio_%x/event=0xc0,umask=0x01,ch_mask=0xF,fc_mask=0x07/} Unsupported uncore pmu configuration ^([a-f0-9A-F]{1,}):([a-f0-9A-F]{1,2}) Root port %04x:%02x were not found Requested root ports were not found Unrecognized root port format: %s Please use the following format: [domain]:[bus] for example: 0000:3d # time port intel_pt and intel_bts may not be used together Invalid %s for %s. Valid values are: %s %s: mmap index %d old head %zu new head %zu %s: wrap-around %sdetected, adjusted old head %zu adjusted new head %zu Intel Processor Trace: TSC not available There may be only one intel_pt event module/kvm_intel/parameters/pt_mode Snapshot mode (-S option) requires intel_pt PMU event (-e intel_pt) Snapshot mode (intel_pt PMU) and sample trace cannot be used together Cannot use clockid (-k option) with intel_pt intel_pt supports at most one event with aux-output pt=0 doesn't make sense, forcing pt=1 Snapshot size %zu must not be greater than AUX area tracing mmap size %zu Failed to calculate default snapshot size and/or AUX area tracing mmap pages Intel PT snapshot size (%zu) may be too small for PSB period (%zu) Sample size %zu must not be greater than AUX area tracing mmap size %zu Intel PT min. sample size: %zu max. sample size: %zu Intel PT sample size (%zu) may be too small for PSB period (%zu) Invalid mmap size for Intel Processor Trace: must be at least %zuKiB and a power of 2 %s: failed to create %s, error = %d Unable to select sched:sched_switch Intel Processor Trace decoding will not be possible except for kernel tracing! Intel BTS does not support AUX area sampling There may be only one intel_bts event Snapshot mode (-S option) requires intel_bts PMU event (-e intel_bts) intel_bts does not support per-cpu recording Invalid mmap size for Intel BTS: must be at least %zuKiB and a power of 2 failed to allocate sample uregs data Intel PT hybrid CPU compatibility Samples differ at 'retire_lat' {cpu_core/cycles/,cpu_core/branches/} {cpu_core/cycles/k,cpu_core/branches/u} cpu_core/config=10,config1,config2=3,period=1000/u {cpu_core/cycles/,cpu_core/cpu-cycles/} sched_setaffinity() failed for CPU %d CPU %d CPUID leaf 20 subleaf %d intel_pt_get_packet returned %d Expected length: %d Decoded length %d Expected type: %d Decoded type %d Expected count: %d Decoded count %d Expected payload: 0x%llx Decoded payload 0x%llx Expected packet context: %d Decoded packet context %d CPU %d same caps as previous CPU CPU %d subleaf %d reg %d FAIL %#x vs %#x CPU %d subleaf 1 reg 0 FAIL address filter count %#x vs %#x Is %shybrid : CPUID leaf 7 subleaf 0 edx %#x (bit-15 indicates hybrid) failed to set breakpoint, 1st time: %s failed to set breakpoint, 2nd time: %s failed to PTRACE_PEEKUSER: %s failed, breakpoint set to bogus address type: 0x%x, config: 0x%lx, fd: %d - GTK browser requested but could not find %s Not enough memory to display remaining hits WARN: jump target inconsistency, press 'o', notes->offsets[%#x] = NULL Press 'h' for help on key bindings ui/browsers/../../util/annotate.h UP/DOWN/PGUP PGDN/SPACE Navigate </> Move to prev/next symbol q/ESC/CTRL+C Exit ENTER Go to target H Go to hottest instruction TAB/shift+TAB Cycle thru hottest instructions j Toggle showing jump to target arrows J Toggle showing number of jump sources on targets n Search next string o Toggle disassembler output/simplified view O Bump offset level (jump targets -> +call -> all -> cycle thru) s Toggle source code view t Circulate percent, total period, samples view c Show min/max cycle / Search string k Toggle line numbers l Show full source file location P Print to [symbol_name].annotation file. r Run available scripts p Toggle percent type [local/global] b Toggle percent base [period/hits] ? Search string backwards f Toggle showing offsets to full address Only available for source code lines. %d: nr_ent=%d, height=%d, idx=%d, top_idx=%d, nr_asm_entries=%d Huh? No selection. Report to linux-kernel@vger.kernel.org Actions are only available for assembly lines. Actions are only available for function call/return & jump/branch instructions. The called function was not found. Can't search all data files due to memory shortage. Too many perf data files in PWD! Only the first 32 files will be listed. Data switch failed due to memory shortage! Won't switch the data files due to no valid data file get selected! Run scripts for samples of thread [%s]%s Run scripts for samples of symbol [%s]%s To zoom out press ESC or ENTER + "Zoom out of %s DSO" To zoom out press ESC or ENTER + "Zoom out of %s(%d) thread" To zoom out press ESC or ENTER + "Zoom out of %s thread" Events are being lost, check IO/CPU overload! You may want to run 'perf' using a RT scheduler policy: perf top -r 80 Or reduce the sampling frequency. %d: nr_ent=(%d,%d), etl: %d, rows=%d, idx=%d, fve: idx=%d, row_off=%d, nrows=%d Press '?' for help on key bindings Press 'f' again to re-enable the events Press 'f' to disable the events or 'h' to see other hotkeys Max event group index to sort is %d (index from 0 to %d) Annotation is only available for symbolic views, include "sym*" in --sort to use it. No samples for the "%s" symbol. Probably appeared just in a callchain Too many perf.hist.N files, nothing written! Please enter the name of symbol you want to see. To remove the filter later, press / + ENTER. Please enter the value you want to hide entries under that percent. Zoom %s %s DSO (use the 'k' hotkey to zoom directly into the kernel) %s [%s] callchain (one level, same as '+' hotkey, use 'e'/'c' for the whole main level entry) Show context for individual samples %s Switch to another data file in PWD ESC: exit, ENTER|->: Browse histograms Press ESC to exit, %s / to search Prefix with 0x to search by address Show individual samples with assembler Show individual samples with source Show samples with custom perf script arguments Enter perf script command line (without perf script prefix) --show-switch-events --show-task-events %s script %s%s --time %s %s%s %s%s --ns %s %s %s %s %s | less +/%s ESC: exit, ENTER|->: Select option maximum size of symbol name reached! Get the common preempt count event field value. Get the common flags event field value. Get the common lock depth event field value. Get the machine code instruction. Get source file name and line number. Get source file name, line number and line. GenuineIntel-6-(97|9A|B7|BA|BF) GenuineIntel-6-(1C|26|27|35|36) GenuineIntel-6-55-[56789ABCDEF] GenuineIntel-6-(37|4A|4C|4D|5A) GenuineIntel-6-(4E|5E|8E|9E|A5|A6) AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]) AuthenticAMD-25-([245][[:xdigit:]]|[[:xdigit:]]) Cannot determine the current working directory Error: too many args to run %s %s available from elsewhere on your $PATH --------------------------------------- cannot be used with switch `%c' expects an unsigned numerical value should not happen, someone must be hit on the forehead STOP_AT_NON_OPTION and KEEP_UNKNOWN don't go together Error: did you mean `--%s` (with two dashes ?) Error: Ambiguous option: %s (could be --%s%s or --%s%s) SUBCMD_HAS_NOT_BEEN_INITIALIZED /sys/kernel/debug/tracing/kprobe_events /sys/kernel/tracing/kprobe_events /sys/kernel/debug/tracing/uprobe_events /sys/kernel/tracing/uprobe_events libbpf: failed to open %s: %d. No procfs support? libbpf: failed to open '%s': %s libbpf: failed to parse '%s': %s /sys/bus/event_source/devices/uprobe/type /sys/bus/event_source/devices/kprobe/type libbpf: failed to determine %s perf type: %s /sys/bus/event_source/devices/uprobe/format/retprobe /sys/bus/event_source/devices/kprobe/format/retprobe libbpf: failed to determine %s retprobe bit: %s libbpf: Error in %s():%s(%d). Couldn't create simple array map. libbpf: elf: init internal error libbpf: elf: failed to open %s: %s libbpf: elf: failed to open %s as ELF file: %s libbpf: elf: '%s' is not a proper ELF object libbpf: elf: '%s' is not a 64-bit ELF object libbpf: elf: failed to get ELF header from %s: %s libbpf: elf: failed to get section names section index for %s: %s libbpf: elf: failed to get section names strings from %s: %s libbpf: elf: %s is not a valid eBPF object file libbpf: elf: failed to get section(%zu) header from %s: %s libbpf: failed to dup FD %d to FD > 2: %d libbpf: map '%s': found type = %u. libbpf: map '%s': found key [%u], sz = %u. libbpf: map '%s': found key_size = %u. libbpf: map '%s': found value [%u], sz = %u. libbpf: map '%s': found value_size = %u. libbpf: map '%s': found max_entries = %u. libbpf: map '%s': found map_flags = 0x%x. libbpf: map '%s': found map_extra = 0x%llx. libbpf: map '%s': found pinning = %u. libbpf: map '%s': found numa_node = %u. libbpf: map '%s': found inner map definition. libbpf: struct_ops init: DATASEC %s not found libbpf: struct_ops init: Cannot resolve var type_id %u in DATASEC %s libbpf: struct_ops init: anonymous type is not supported libbpf: struct_ops init: %s is not a struct libbpf: struct_ops init: var %s is beyond the end of DATASEC %s libbpf: struct_ops init: struct %s(type_id=%u) %s found at offset %u libbpf: extern (kcfg) '%s': value '%llu' implies integer, char, or boolean type libbpf: extern (kcfg) '%s': value '%llu' isn't boolean compatible libbpf: extern (kcfg) '%s': value '%llu' doesn't fit in %d bytes libbpf: failed to parse '%s': no separator libbpf: failed to parse '%s': no value libbpf: extern (kcfg) '%s': value '%c' implies tristate or char type libbpf: extern (kcfg) '%s': value '%c' implies bool, tristate, or char type libbpf: extern (kcfg) '%s': value '%s' implies char array type libbpf: extern (kcfg) '%s': invalid string config '%s' libbpf: extern (kcfg) '%s': long string '%s' of (%zu bytes) truncated to %d bytes libbpf: failed to parse '%s' as integer: %d libbpf: failed to parse '%s' as integer completely libbpf: extern (kcfg) '%s': value '%s' isn't a valid integer libbpf: extern (kcfg) '%s': value '%s' implies integer type libbpf: extern (kcfg) '%s': set to %s libbpf: failed to open in-memory Kconfig: %d libbpf: error parsing in-memory Kconfig line '%s': %d libbpf: failed to open system Kconfig libbpf: error parsing system Kconfig line '%s': %d libbpf: extern (ksym) '%s': resolution is ambiguous: 0x%llx or 0x%llx libbpf: extern (ksym) '%s': set to 0x%llx libbpf: permission error while running as root; try raising 'ulimit -l'? current value: %s libbpf: failed to mkdir %s: %s libbpf: failed to statfs %s: %s libbpf: specified path %s is not on BPF FS libbpf: error in %s: map handler doesn't belong to object libbpf: resolved '%s' to '%s' libbpf: tracepoint %s/%s path is too long libbpf: failed to munmap cpu_buf #%d libbpf: unknown perf sample type %d libbpf: Detection of kernel %s support failed: %d libbpf: prog '%s': can't attach before loaded libbpf: prog '%s': failed to attach to %s: %s libbpf: map '%s' (global data): at sec_idx %d, offset %zu, flags %x. libbpf: failed to alloc map '%s' content buffer: %d libbpf: failed bpf_prog_get_info_by_fd for FD %d: %d libbpf: The target program doesn't have BTF libbpf: Failed to get BTF %d of the program: %d libbpf: %s is not found in prog's BTF libbpf: prog '%s': failed to realloc prog code libbpf: prog '%s': added %zu insns from sub-prog '%s' libbpf: elf: failed to get section name string at offset %zu from %s: %s libbpf: elf: failed to get section(%zu) name from %s: %s libbpf: elf: failed to get section(%zu) %s data from %s: %s libbpf: %s size (%zu) is too small libbpf: prog '%s': failed to attach: %s libbpf: %s has non-zero extra bytes libbpf: map '%s': attr '%s': expected PTR, got %s. libbpf: map '%s': attr '%s': type [%u] not found. libbpf: map '%s': attr '%s': expected ARRAY, got %s. libbpf: map '%s': invalid field #%d. libbpf: map '%s': conflicting key size %u != %u. libbpf: map '%s': key type [%d] not found. libbpf: map '%s': key spec is not PTR: %s. libbpf: map '%s': can't determine key size for type [%u]: %zd. libbpf: map '%s': conflicting key size %u != %zd. libbpf: map '%s': conflicting value size %u != %u. libbpf: map '%s': value type [%d] not found. libbpf: map '%s': value spec is not PTR: %s. libbpf: map '%s': can't determine value size for type [%u]: %zd. libbpf: map '%s': conflicting value size %u != %zd. libbpf: map '%s': multi-level inner maps not supported. libbpf: map '%s': '%s' member should be last. libbpf: map '%s': should be map-in-map or prog-array. libbpf: map '%s': conflicting value size %u != 4. libbpf: map '%s': %s type [%d] not found. libbpf: map '%s': %s spec is not a zero-sized array. libbpf: map '%s': %s def is of unexpected kind %s. libbpf: map '%s': prog-array value def is of unexpected kind %s. libbpf: map '%s': map-in-map inner def is of unexpected kind %s. libbpf: map '%s': inner def can't be pinned. libbpf: map '%s': invalid pinning value %u. libbpf: map '%s': unknown field '%s'. libbpf: map '%s': ignoring unknown field '%s'. libbpf: map '%s': map type isn't specified. libbpf: prog '%s': error relocating .BTF.ext function info: %d libbpf: prog '%s': missing .BTF.ext function info. libbpf: prog '%s': missing .BTF.ext function info for the main program, skipping all of .BTF.ext func info. libbpf: prog '%s': error relocating .BTF.ext line info: %d libbpf: prog '%s': missing .BTF.ext line info. libbpf: prog '%s': missing .BTF.ext line info for the main program, skipping all of .BTF.ext line info. libbpf: prog '%s': unexpected relo for insn #%zu, type %d libbpf: prog '%s': missing subprog addr relo for insn #%zu libbpf: prog '%s': no .text section found yet sub-program call exists libbpf: prog '%s': insn #%zu relocated, imm %d points to subprog '%s' (now at %zu offset) libbpf: prog '%s': missing BPF prog type, check ELF section name '%s' libbpf: prog '%s': failed to prepare load attributes: %d libbpf: prog '%s': failed to bind map '%s': %s invalid func unknown#195896080 %d: (%*d) call unknown#195896080 %d: <invalid CO-RE relocation> failed to resolve CO-RE relocation %s%s %d: <invalid BPF map reference> BPF map '%s' is referenced but wasn't created %d: <invalid kfunc call> kfunc '%s' is referenced but wasn't resolved libbpf: prog '%s': BPF program load failed: %s libbpf: prog '%s': -- BEGIN PROG LOAD LOG -- %s-- END PROG LOAD LOG -- libbpf: skipping module BTFs loading, missing privileges libbpf: failed to iterate BTF objects: %d libbpf: failed to get BTF object #%d FD: %d libbpf: failed to get BTF object #%d info: %d libbpf: failed to load module [%s]'s BTF object #%d: %d libbpf: prog '%s': no BTF-based attach target is specified, use bpf_program__set_attach_target() libbpf: prog '%s': attach program FD is not set libbpf: prog '%s': failed to find BPF program (FD %d) BTF ID for '%s': %d libbpf: prog '%s': failed to find kernel BTF type ID of '%s': %d libbpf: CO-RE relocating [%d] %s %s: found target candidate [%d] %s %s in [%s] libbpf: prog '%s': relo #%d: target candidate search failed for [%d] %s %s: %ld libbpf: failed to open /proc/kallsyms: %d libbpf: failed to read kallsyms entry: %d libbpf: prog '%s': can't pin program that wasn't loaded libbpf: prog '%s': failed to pin at '%s': %s libbpf: prog '%s': pinned at '%s' libbpf: prog '%s': can't unpin program that wasn't loaded libbpf: prog '%s': unpinned from '%s' libbpf: error: program handler doesn't match object libbpf: object not yet loaded; load it first libbpf: failed to guess program type from ELF section '%s' libbpf: supported section(type) names are:%s libbpf: vmlinux BTF is not found libbpf: %s is not found in vmlinux BTF libbpf: failed to guess attach type based on ELF section name '%s' libbpf: attachable section(type) names are:%s libbpf: elf: failed to get section(%zu) from %s: %s libbpf: elf: failed to get %s map definitions for %s libbpf: DATASEC '%s' not found. libbpf: map '%s' BTF data is corrupted. libbpf: map '%s': unexpected var kind %s. libbpf: map '%s': unsupported map linkage %s. libbpf: map '%s': unexpected def kind %s. libbpf: map '%s': invalid def size. libbpf: map '%s': failed to alloc map name. libbpf: map '%s': at sec_idx %d, offset %zu. libbpf: map '%s': couldn't build pin path. libbpf: map '%s' already has pin path '%s' different from '%s' libbpf: map '%s' already pinned at '%s'; not re-pinning libbpf: missing a path to pin map '%s' at libbpf: map '%s' already pinned libbpf: failed to pin map: %s libbpf: no path to unpin map '%s' from libbpf: unpinned map '%s' from '%s' libbpf: map '%s': failed to resize memory-mapped region: %d libbpf: map '%s': cannot be resized, map value type is not a datasec libbpf: map '%s': cannot be resized, map value datasec is empty libbpf: map '%s': cannot be resized, last var must be an array libbpf: map '%s': cannot be resized, element size (%d) doesn't align with new total size (%u) libbpf: map '%s': failed to adjust resized BTF, clearing BTF key/value info: %d libbpf: error: unsupported map type libbpf: error: inner_map_fd already specified libbpf: Error loading vmlinux BTF: %d libbpf: .maps relo #%d: failed to get ELF relo libbpf: .maps relo #%d: symbol %zx not found libbpf: .maps relo #%d: for %zd value %zd rel->r_offset %zu name %d ('%s') libbpf: .maps relo #%d: cannot find map '%s' at rel->r_offset %zu libbpf: .maps relo #%d: '%s' isn't a BTF-defined map libbpf: .maps relo #%d: hash-of-maps '%s' should have key size %zu. libbpf: .maps relo #%d: '%s' isn't a valid map reference libbpf: .maps relo #%d: '%s' isn't a valid program reference libbpf: .maps relo #%d: '%s' isn't an entry-point program libbpf: .maps relo #%d: map '%s' slot [%d] points to %s '%s' libbpf: failed to init libelf for %s libbpf: loading object '%s' from buffer libbpf: loading object from %s libbpf: alloc memory failed for %s libbpf: elf: endianness mismatch in %s. libbpf: elf: failed to get the number of sections for %s: %s libbpf: elf: multiple symbol tables in %s libbpf: elf: couldn't find symbol table in %s, stripped object file? libbpf: elf: section(%d) %s, size %ld, link %d, flags %lx, type=%d libbpf: invalid license section in %s libbpf: invalid kver section in %s libbpf: kernel version of %s is %x libbpf: elf: legacy map definitions in 'maps' section are not supported by libbpf v1.0+ libbpf: sec '%s': failed to get symbol name for offset %zu libbpf: sec '%s': program at offset %zu crosses section boundary libbpf: sec '%s': program '%s' is static and not supported libbpf: sec '%s': found program '%s' at insn offset %zu (%zu bytes), code size %zu insns (%zu bytes) libbpf: sec '%s': failed to alloc memory for new program '%s' libbpf: sec '%s': corrupted program '%s', offset %zu, size %zu libbpf: sec '%s': failed to allocate memory for prog '%s' libbpf: elf: skipping unrecognized data section(%d) %s libbpf: elf: skipping relo section(%d) %s for section(%d) %s libbpf: elf: skipping section(%d) %s (size %zu) libbpf: elf: symbol strings section missing or invalid in %s libbpf: Error loading ELF section %s: %d. libbpf: Error loading ELF section %s: %d. Ignored and continue. libbpf: BTF is required, but is missing or corrupted. libbpf: cannot create a dummy_ksym var libbpf: looking for externs among %d symbols... libbpf: failed to find BTF for extern '%s': %d libbpf: failed to find BTF for extern '%s' [%d] section: %d libbpf: extern function %s is unsupported under %s section libbpf: failed to resolve size of extern (kcfg) '%s': %d libbpf: failed to determine alignment of extern (kcfg) '%s': %d libbpf: extern (kcfg) '%s': type is unsupported libbpf: unrecognized extern section '%s' libbpf: collected %d externs total libbpf: extern (ksym) #%d: symbol %d, name %s libbpf: failed to find extern definition for BTF %s '%s' libbpf: extern (kcfg) #%d: symbol %d, off %u, name %s libbpf: failed to find extern definition for BTF var '%s' libbpf: No name found in string section for DATASEC kind. libbpf: sec '%s': failed to determine size from ELF: size %u, err %d libbpf: sec '%s': unexpected non-VAR type found libbpf: sec '%s': failed to find name of DATASEC's member #%d libbpf: failed to get sym name string for var %s libbpf: sec '%s': failed to find ELF symbol for VAR '%s' libbpf: prog '%s': unrecognized ELF section name '%s' libbpf: prog '%s': failed to initialize: %d libbpf: struct_ops reloc: failed to get %d reloc libbpf: struct_ops reloc: symbol %zx not found libbpf: struct_ops reloc: cannot find map at rel->r_offset %zu libbpf: struct_ops reloc %s: for %lld value %lld shdr_idx %u rel->r_offset %zu map->sec_offset %zu name %d ('%s') libbpf: struct_ops reloc %s: rel->r_offset %zu shdr_idx %u unsupported non-static function libbpf: struct_ops reloc %s: invalid target program offset %llu libbpf: struct_ops reloc %s: cannot find member at moff %u libbpf: struct_ops reloc %s: cannot relocate non func ptr %s libbpf: struct_ops reloc %s: cannot find prog at shdr_idx %u to relocate func ptr %s libbpf: struct_ops reloc %s: prog %s is not struct_ops BPF program libbpf: struct_ops reloc %s: cannot use prog %s in sec %s with type %u attach_btf_id %u expected_attach_type %u for func ptr %s libbpf: sec '%s': collecting relocation for section(%zu) '%s' libbpf: sec '%s': failed to get relo #%d libbpf: sec '%s': symbol #%zu not found for relo #%d libbpf: sec '%s': corrupted symbol #%zu pointing to invalid section #%zu for relo #%d libbpf: sec '%s': invalid offset 0x%zx for relo #%d libbpf: sec '%s': relo #%d: insn #%u against '%s' libbpf: sec '%s': relo #%d: couldn't find program in section '%s' for insn #%u, probably overridden weak function, skipping... libbpf: prog '%s': invalid relo against '%s' for insns[%d].code 0x%x libbpf: prog '%s': extern relo failed to find extern for '%s' (%d) libbpf: prog '%s': found extern #%d '%s' (sym %d) for insn #%u libbpf: prog '%s': incorrect bpf_call opcode libbpf: prog '%s': bad call relo against '%s' in section '%s' libbpf: prog '%s': bad call relo against '%s' at offset %zu libbpf: prog '%s': invalid relo against '%s' in special section 0x%x; forgot to initialize global var?.. libbpf: prog '%s': bad subprog addr relo against '%s' at offset %zu+%d libbpf: prog '%s': bad map relo against '%s' in section '%s' libbpf: prog '%s': found map %zd (%s, sec %d, off %zu) for insn #%u libbpf: prog '%s': bad data relo against section '%s' libbpf: prog '%s': found data map %zd (%s, sec %d, off %zu) for insn %u libbpf: prog '%s': map relo failed to find map for section '%s', off %zu libbpf: prog '%s': data relo failed to find map for section '%s' libbpf: Ignore ELF section %s because its depending ELF section %s is not found. libbpf: failed to find skeleton map '%s' libbpf: failed to open link at %s: %d libbpf: link fd=%d: pinned at %s libbpf: link fd=%d: unpinned from %s libbpf: prog '%s': invalid perf event FD %d libbpf: prog '%s': can't attach BPF program w/o FD (did you load it?) libbpf: prog '%s': failed to create BPF link for perf_event FD %d: %d (%s) libbpf: prog '%s': user context value is not supported libbpf: prog '%s': failed to attach to perf_event FD %d: %s libbpf: prog '%s': try add PERF_SAMPLE_CALLCHAIN to or remove exclude_callchain_[kernel|user] from pfd %d libbpf: prog '%s': failed to enable perf_event FD %d: %s libbpf: failed to add legacy kprobe event for '%s+0x%zx': %s libbpf: failed to determine legacy kprobe event id for '%s+0x%zx': %s libbpf: legacy kprobe perf_event_open() failed: %s libbpf: prog '%s': failed to create %s '%s+0x%zx' perf event: %s libbpf: prog '%s': failed to attach to %s '%s+0x%zx': %s libbpf: kprobe name is invalid: %s libbpf: kretprobes do not support offset specification /sys/kernel/debug/tracing/available_filter_functions_addrs /sys/kernel/tracing/available_filter_functions_addrs /sys/kernel/debug/tracing/available_filter_functions /sys/kernel/tracing/available_filter_functions libbpf: failed to open %s: %d libbpf: failed to parse available_filter_functions_addrs entry: %d libbpf: failed to parse available_filter_functions entry: %d libbpf: kprobe multi pattern is invalid: %s libbpf: prog '%s': failed to resolve full path for '%s': %d libbpf: prog '%s': failed to attach multi-uprobe: %s libbpf: prog '%s': invalid format of section definition '%s' libbpf: zip: failed to open %s: %ld libbpf: zip: could not find archive member %s in %s: %ld libbpf: zip: found entry for %s in %s at 0x%lx libbpf: zip: entry %s of %s is compressed and cannot be handled libbpf: elf: could not read elf file %s from %s: %s libbpf: elf: symbol address match for %s of %s in %s: 0x%x + 0x%lx = 0x%lx libbpf: failed to add legacy uprobe event for %s:0x%zx: %d libbpf: failed to determine legacy uprobe event id for %s:0x%zx: %d libbpf: legacy uprobe perf_event_open() failed: %d libbpf: prog '%s': failed to create %s '%s:0x%zx' perf event: %s libbpf: prog '%s': failed to attach to %s '%s:0x%zx': %s libbpf: prog '%s': section '%s' missing ':function[+offset]' specification libbpf: prog '%s': uretprobes do not support offset specification libbpf: invalid section '%s', expected SEC("usdt/<path>:<provider>:<name>") libbpf: failed to determine tracepoint '%s/%s' perf event ID: %s libbpf: tracepoint '%s/%s' perf_event_open() failed: %s libbpf: prog '%s': failed to create tracepoint '%s/%s' perf event: %s libbpf: prog '%s': failed to attach to tracepoint '%s/%s': %s libbpf: prog '%s': failed to attach to raw tracepoint '%s': %s libbpf: prog '%s': invalid section name '%s' libbpf: prog '%s': target netdevice ifindex cannot be zero libbpf: prog '%s': relative_fd and relative_id cannot be set at the same time libbpf: prog '%s': supply none or both of target_fd and attach_func_name libbpf: prog '%s': only BPF_PROG_TYPE_EXT can attach as freplace libbpf: prog '%s': failed to attach to iterator: %s libbpf: prog '%s': failed to attach to netfilter: %s libbpf: error while processing records: %d libbpf: perf_buffer: failed to process records in buffer #%d: %d libbpf: Failed to get CPU range %s: %d libbpf: Invalid CPU range [%d,%d] in %s libbpf: Failed to open cpu mask file %s: %d libbpf: Failed to read cpu mask from %s: %d libbpf: CPU mask is too big in file %s /sys/devices/system/cpu/possible libbpf: map '%s': failed to determine number of system CPUs: %d libbpf: map '%s': setting size to %d libbpf: map '%s': failed to create inner map: %d libbpf: Error in bpf_create_map_xattr(%s):%s(%d). Retrying without BTF. libbpf: map '%s': skipped auto-creating... libbpf: found no pinned map to reuse at '%s' libbpf: couldn't retrieve pinned map '%s': %s libbpf: failed to get map info for map FD %d: %s libbpf: couldn't reuse pinned map at '%s': parameter mismatch libbpf: reused pinned map at '%s' libbpf: map '%s': error reusing pinned map libbpf: map '%s': cannot find pinned map libbpf: map '%s': skipping creation (preset fd=%d) libbpf: map '%s': created successfully, fd=%d libbpf: Error setting initial map(%s) contents: %s libbpf: Error freezing map(%s) as read-only: %s libbpf: map '%s': failed to initialize slot [%d] to map '%s' fd=%d: %d libbpf: map '%s': slot [%d] set to map '%s' fd=%d libbpf: map '%s': failed to auto-pin at '%s': %d libbpf: map '%s': failed to create: %s(%d) libbpf: object '%s': load can't be attempted twice libbpf: Failed to bump RLIMIT_MEMLOCK (err = %d), you might need to do it explicitly! libbpf: Error in %s():%s(%d). Couldn't load trivial BPF program. Make sure your kernel supports BPF (CONFIG_BPF_SYSCALL=y) and/or that RLIMIT_MEMLOCK is set to big enough value. libbpf: extern (kcfg) '%s': failed to get kernel version libbpf: extern (kcfg) '%s': unrecognized virtual extern libbpf: extern (kcfg) '%s': set to 0x%llx libbpf: extern '%s': unrecognized extern kind libbpf: extern (var ksym) '%s': not found in kernel BTF libbpf: extern (var ksym) '%s': incompatible types, expected [%d] %s %s, but kernel has [%d] %s %s libbpf: extern (var ksym) '%s': resolved to [%d] %s %s libbpf: extern (func ksym) '%s': not found in kernel or module BTFs libbpf: extern (func ksym) '%s': func_proto [%d] incompatible with %s [%d] libbpf: extern (func ksym) '%s': module BTF fd index %d too big to fit in bpf_insn offset libbpf: extern (func ksym) '%s': resolved to %s [%d] libbpf: extern '%s' (strong): not resolved libbpf: extern '%s' (weak): not resolved, defaulting to zero libbpf: struct_ops init_kern: struct %s is not found in kernel BTF libbpf: struct_ops init_kern: struct %s%s is not found in kernel BTF libbpf: struct_ops init_kern %s: type_id:%u kern_type_id:%u kern_vtype_id:%u libbpf: struct_ops init_kern: struct %s data is not found in struct %s%s libbpf: struct_ops init_kern %s: Cannot find member %s in kernel BTF libbpf: struct_ops init_kern %s: bitfield %s is not supported libbpf: struct_ops init_kern %s: Unmatched member type %s %u != %u(kernel) libbpf: struct_ops init_kern %s: kernel member %s is not a func ptr libbpf: struct_ops init_kern %s: func ptr %s is set to prog %s from data(+%u) to kern_data(+%u) libbpf: struct_ops init_kern %s: Error in size of member %s: %zd != %zd(kernel) libbpf: struct_ops init_kern %s: copy %s %u bytes from data(+%u) to kern_data(+%u) libbpf: failed to parse target BTF: %d libbpf: sec '%s': found %d CO-RE relocations libbpf: sec '%s': skipping CO-RE relocation #%d for insn #%d belonging to eliminated weak subprogram libbpf: prog '%s': relo #%d: failed to record relocation: %d libbpf: prog '%s': relo #%d: failed to relocate: %d libbpf: prog '%s': relo #%d: failed to patch insn #%u: %d libbpf: failed to perform CO-RE relocations: %d libbpf: prog '%s': failed to relocate calls: %d libbpf: prog '%s': exception_callback:<value> decl tag not applied to the main program libbpf: prog '%s': exception_callback:<value> decl tag contains empty value libbpf: prog '%s': exception callback %s must be a global non-hidden function libbpf: prog '%s': relo #%d: poisoning insn #%d that loads map #%d '%s' libbpf: prog '%s': relo #%d: poisoning insn #%d that calls kfunc '%s' libbpf: prog '%s': relo #%d: bad insn libbpf: prog '%s': relo #%d: bad relo type %d libbpf: prog '%s': failed to relocate data references: %d libbpf: prog '%s': subprog '%s' arg#%d is expected to be of `struct %s *` type libbpf: prog '%s': failed to perform .BTF.ext fix ups: %d libbpf: Kernel doesn't support BTF, skipping uploading it. libbpf: Error loading .BTF into kernel: %d. %s BTF is mandatory, can't proceed. libbpf: prog '%s': skipped loading libbpf: prog '%s': failed to load: %d libbpf: map '%s': failed to initialize slot [%d] to prog '%s' fd=%d: %d libbpf: map '%s': slot [%d] set to prog '%s' fd=%d libbpf: failed to load object '%s' libbpf: prog '%s': cannot find exception callback '%s' libbpf: map '%s': unexpected key size %zu provided, expected %u libbpf: map '%s': unexpected value size %zu provided for per-CPU map, expected %d * %zu = %zd libbpf: map '%s': unexpected value size %zu provided, expected %u libbpf: page count should be power of two, but is %zu libbpf: failed to get map info for FD %d; API not supported? Ignoring... libbpf: map '%s' should be BPF_MAP_TYPE_PERF_EVENT_ARRAY libbpf: failed to create epoll instance: %s libbpf: failed to allocate events: out of memory libbpf: failed to allocate buffers: out of memory /sys/devices/system/cpu/online libbpf: failed to get online CPU mask: %d libbpf: failed to open perf buffer event on cpu #%d: %s libbpf: failed to mmap perf buffer on cpu #%d: %s libbpf: failed to enable perf buffer event on cpu #%d: %s libbpf: failed to set cpu #%d, key %d -> perf FD %d: %s libbpf: failed to epoll_ctl cpu #%d perf FD %d: %s libbpf: failed to initialize skeleton BPF object '%s': %d libbpf: failed to populate skeleton maps for '%s': %d libbpf: failed to find skeleton program '%s' libbpf: failed to populate skeleton progs for '%s': %d libbpf: subskeletons require BTF at runtime (object %s) libbpf: failed to populate subskeleton maps: %d libbpf: type for map '%1$s' is not a datasec: %2$s libbpf: failed to load BPF skeleton '%s': %d libbpf: failed to re-mmap() map '%s': %d libbpf: prog '%s': failed to auto-attach: %d BPF_PROG_LOAD expected_attach_type attribute bpf_probe_read_kernel() helper sk_reuseport_select_or_migrate libbpf: Attribute of type %#x found multiple times in message, previous attribute is being ignored. libbpf: Failed to parse extended error attributes libbpf: Kernel error message: %s libbpf: .BTF.ext %s section is not aligned to 4 bytes libbpf: %s section (off:%u len:%u) is beyond the end of the ELF section .BTF.ext libbpf: .BTF.ext %s record size not found libbpf: %s section in .BTF.ext has invalid record size %u libbpf: %s section in .BTF.ext has no records libbpf: %s section header is not found in .BTF.ext libbpf: %s section has incorrect num_records in .BTF.ext libbpf: Unsupported BTF_KIND:%u libbpf: btf: type [%u]: invalid referenced type ID %u libbpf: BTF loading error: %d libbpf: -- BEGIN BTF LOAD LOG --- %s -- END BTF LOAD LOG -- libbpf: unsupported BTF_KIND:%u libbpf: Can't load BTF with non-native endianness due to unsupported header length %u libbpf: Invalid BTF magic: %x libbpf: BTF header len %u larger than data size %u libbpf: Invalid BTF total size: %u libbpf: Invalid BTF data sections layout: type data at %u + %u, strings data at %u + %u libbpf: BTF type section is not aligned to 4 bytes libbpf: Invalid BTF string section libbpf: BTF type [%d] is malformed libbpf: BTF types data is malformed libbpf: btf: type [%u]: invalid %s (string offset %u) libbpf: btf: type [%u]: referenced type [%u] is not FUNC_PROTO libbpf: btf: type [%u]: unrecognized kind %u libbpf: BTF.ext header not found libbpf: BTF.ext in non-native endianness is not supported libbpf: Invalid BTF.ext magic:%x libbpf: Unsupported BTF.ext version:%u libbpf: Unsupported BTF.ext flags:%x libbpf: failed to open %s: %s libbpf: failed to open %s as ELF file libbpf: failed to get EHDR from %s libbpf: failed to get section names section index for %s libbpf: failed to get e_shstrndx from %s libbpf: failed to get section(%d) header from %s libbpf: failed to get section(%d) name from %s libbpf: failed to get section(%d, %s) data from %s libbpf: failed to find '%s' ELF section in %s libbpf: failed to get ELF class (bitness) for %s /lib/modules/%1$s/vmlinux-%1$s /lib/modules/%1$s/build/vmlinux /usr/lib/modules/%1$s/kernel/vmlinux /usr/lib/debug/boot/vmlinux-%1$s /usr/lib/debug/boot/vmlinux-%1$s.debug /usr/lib/debug/lib/modules/%1$s/vmlinux libbpf: loading kernel BTF '%s': %d libbpf: failed to find valid kernel BTF libbpf: btf_dedup_new failed: %ld libbpf: unknown kind %d for type [%d] libbpf: btf_dedup_prep failed:%d libbpf: btf_dedup_strings failed:%d libbpf: btf_dedup_resolve_fwds failed:%d libbpf: btf_dedup_ref_types failed:%d libbpf: btf_dedup_compact_types failed:%d libbpf: btf_dedup_remap_types failed:%d libbpf: btf_dedup_struct_types failed:%d libbpf: btf_dedup_prim_types failed:%d 'version' section incorrect or lost Kernel verifier blocks program loading Kernel doesn't support this program type Incorrect netlink message parsing libbpf: Netlink error reporting not supported Cannot replace kernel functions attach_btf_id 1 is not a function libbpf: unsatisfiable type cycle, id:[%u] libbpf: unexpected size %d for id [%u] libbpf: unexpected bitfield size %d libbpf: unexpected size %d for enum, id:[%u] __attribute__((btf_type_tag("%s"))) libbpf: unexpected type in decl chain, kind:%u, id:[%u] libbpf: not enough memory for decl stack:%d typedef __builtin_va_list __gnuc_va_list libbpf: anonymous struct/union loop, id:[%u] libbpf: unexpected size [%zu] for id [%u] libbpf: unexpected error skipping mods/typedefs for id [%u] libbpf: unexpected sz %d for id [%u] libbpf: unexpected elem size %zd for array type [%u] libbpf: unexpected kind [%u] for id [%u] libbpf: ringbuf: failed to get map info for fd=%d: %d libbpf: ringbuf: map fd=%d is not BPF_MAP_TYPE_RINGBUF libbpf: ringbuf: failed to mmap consumer page for map fd=%d: %d libbpf: ringbuf: failed to mmap data pages for map fd=%d: %d libbpf: ringbuf: failed to epoll add map fd=%d: %d libbpf: ringbuf: failed to create epoll instance: %d libbpf: user ringbuf: failed to create epoll instance: %d libbpf: user ringbuf: failed to get map info for fd=%d: %d libbpf: user ringbuf: map fd=%d is not BPF_MAP_TYPE_USER_RINGBUF libbpf: user ringbuf: failed to mmap consumer page for map fd=%d: %d libbpf: user ringbuf: failed to mmap data pages for map fd=%d: %d libbpf: user ringbuf: failed to epoll add map fd=%d: %d libbpf: failed to find new ID mapping for original BTF type ID %u libbpf: global '%s': incompatible forward declaration names '%s' and '%s' libbpf: global '%s': incompatible %s forward declaration and concrete kind %s libbpf: global '%s': incompatible BTF kinds %s and %s libbpf: global '%s': incompatible %s names '%s' and '%s' libbpf: global '%s': incompatible %s '%s' size %u and %u libbpf: global '%s': incompatible func '%s' linkage libbpf: global '%s': incompatible var '%s' linkage libbpf: global '%s': incompatible number of %s fields %u and %u libbpf: global '%s': incompatible field #%d names '%s' and '%s' libbpf: global '%s': incompatible field #%d ('%s') offsets libbpf: global '%s': incompatible number of %s params %u and %u libbpf: global '%s': unsupported BTF kind %s libbpf: global '%s': map %s mismatch libbpf: sec %s types mismatch libbpf: sec %s flags mismatch libbpf: sec %s entsize mismatch libbpf: libelf initialization failed: %s libbpf: failed to create '%s': %d libbpf: failed to create ELF object: %s libbpf: failed to create ELF header: %s libbpf: failed to create STRTAB section: %s libbpf: failed to create STRTAB data: %s libbpf: failed to create SYMTAB section: %s libbpf: failed to create SYMTAB data: %s libbpf: linker: adding object file '%s'... libbpf: failed to open file '%s': %d libbpf: failed to parse ELF file '%s': %s libbpf: failed to get ELF header for %s: %s libbpf: unsupported byte order of ELF file %s: %s libbpf: unsupported kind of ELF file %s: %s libbpf: failed to get SHSTRTAB section index for %s: %s libbpf: failed to get section #%zu header for %s: %s libbpf: failed to get section #%zu name for %s: %s libbpf: failed to get section #%zu (%s) data from %s: %s libbpf: multiple SYMTAB sections found, not supported libbpf: failed to parse .BTF from %s: %d libbpf: failed to parse .BTF.ext from '%s': %d libbpf: unrecognized section #%zu (%s) in %s libbpf: ELF is missing SYMTAB section in %s libbpf: ELF is missing section headers STRTAB section in %s libbpf: ELF section #%zu has empty name in %s libbpf: ELF section #%zu alignment %llu is non pow-of-2 alignment in %s libbpf: ELF section #%zu has inconsistent alignment addr=%llu != d=%llu in %s libbpf: ELF section #%zu has inconsistent section size sh=%llu != d=%llu in %s libbpf: ELF SYMTAB section #%zu points to missing STRTAB section #%zu in %s libbpf: ELF SYMTAB section #%zu points to invalid STRTAB section #%zu in %s libbpf: ELF sym #0 is invalid in %s libbpf: ELF sym #%d in section #%zu has unsupported symbol binding %d libbpf: ELF sym #%d in section #%zu has unsupported symbol visibility %d libbpf: ELF sym #%d is invalid extern symbol in %s libbpf: ELF sym #%d in section #%zu points to missing section #%zu in %s libbpf: ELF section #%zu has unexpected size alignment %llu in %s libbpf: ELF relo section #%zu points to invalid SYMTAB section #%zu in %s libbpf: ELF relo section #%zu points to missing section #%zu in %s libbpf: ELF relo section #%zu name has invalid name in %s libbpf: ELF relo section #%zu points to invalid section #%zu in %s libbpf: ELF relo #%d in section #%zu has unexpected type %zu in %s libbpf: ELF relo #%d in section #%zu points to invalid symbol #%zu in %s libbpf: ELF relo #%d in section #%zu points to missing symbol #%zu in %s libbpf: ELF section #%zu (%s) has unrecognized type %zu in %s libbpf: failed to init section '%s' libbpf: ELF sections %s are incompatible libbpf: non-identical contents of section '%s' are not supported libbpf: can't fetch symbol name for symbol #%d in '%s' libbpf: externs without BTF info are not supported libbpf: failed to find BTF info for object '%s' libbpf: failed to find BTF info for global/extern symbol '%s' libbpf: global/extern '%s' BTF is ambiguous: both types #%d and #%u match libbpf: failed to find matching ELF sec '%s' libbpf: conflicting non-weak symbol #%d (%s) definition in '%s' libbpf: BTF info is missing for global symbol '%s' libbpf: only extern variables and functions are supported, but got '%s' for '%s' libbpf: global '%s': invalid map definition type [%d] libbpf: global '%s': invalid map definition libbpf: global '%s': invalid dst map definition libbpf: sections %s are not compatible libbpf: relocation against STT_SECTION in non-exec section is not supported! libbpf: failed to append BTF type #%d from file '%s' libbpf: global '%s': section mismatch %d vs %d libbpf: global '%s': failed to resolve size of underlying type: %d libbpf: can't find section '%s' referenced from .BTF.ext libbpf: incompatible .BTF.ext record sizes for section '%s' libbpf: failed to find symbol for variable '%s' in section '%s' libbpf: failed to add consolidated BTF type for datasec '%s': %d libbpf: mismatch in func_info record size %zu != %u libbpf: .BTF.ext generation failed: %d libbpf: mismatch in line_info record size %zu != %u libbpf: mismatch in core_relo_info record size %zu != %u libbpf: failed to parse final .BTF.ext data: %d libbpf: failed to write out .BTF ELF section: %d libbpf: failed to write out .BTF.ext ELF section: %d libbpf: failed to finalize ELF layout: %s libbpf: failed to write ELF contents: %s var t=%d w=%d (%s:count=%d): imm[0]: %%d, imm[1]: %%d var t=%d w=%d (%s:count=%d): insn.reg libbpf: nr_progs %d/%d nr_maps %d/%d mismatch libbpf: gen: load_btf: size %d libbpf: gen: map_create: %s idx %d type %d value_type_id %d map_create %s idx %d type %d value_size %d value_btf_id %d libbpf: Total maps exceeds %d libbpf: gen: prog_load: type %d insns_cnt %zd progi_idx %d libbpf: gen: find_attach_tgt %s %d libbpf: gen: emit_relo (%d): %s at %d %s libbpf: BTF fd off %d for kfunc %s exceeds INT16_MAX, cannot process relocation func (%s:count=%d): imm: %%d, off: %%d libbpf: gen: map_update_elem: idx %d update_elem idx %d value_size %d libbpf: gen: populate_outer_map: outer %d key %d inner %d populate_outer_map outer %d key %d inner %d libbpf: gen: map_freeze: idx %d libbpf: prog '%s': relo %d at insn #%d can't be applied to array access libbpf: prog '%s': relo %d at insn #%d can't be satisfied for bitfield libbpf: prog '%s': relo #%d: unrecognized CO-RE relocation %s (%d) at insn #%d libbpf: unexpected kind %s relocated, local [%d], target [%d] libbpf: prog '%s': relo for [%u] %s (at idx %d) captures type [%d] of unexpected kind %s libbpf: prog '%s': relo #%d: substituting insn #%d w/ invalid insn libbpf: prog '%s': relo #%d: unexpected insn #%d (ALU/ALU64) value: got %u, exp %llu -> %llu libbpf: prog '%s': relo #%d: patched insn #%d (ALU/ALU64) imm %llu -> %llu libbpf: prog '%s': relo #%d: unexpected insn #%d (LDX/ST/STX) value: got %u, exp %llu -> %llu libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) value too big: %llu libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) accesses field incorrectly. Make sure you are accessing pointers, unsigned integers, or fields of matching type and size. libbpf: prog '%s': relo #%d: patched insn #%d (LDX/ST/STX) off %llu -> %llu libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) unexpected mem size: got %d, exp %u libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) invalid new mem size: %u libbpf: prog '%s': relo #%d: patched insn #%d (LDX/ST/STX) mem_sz %u -> %u libbpf: prog '%s': relo #%d: insn #%d (LDIMM64) has unexpected form libbpf: prog '%s': relo #%d: unexpected insn #%d (LDIMM64) value: got %llu, exp %llu -> %llu libbpf: prog '%s': relo #%d: patched insn #%d (LDIMM64) imm64 %llu -> %llu libbpf: prog '%s': relo #%d: trying to relocate unrecognized insn #%d, code:0x%x, src:0x%x, dst:0x%x, off:0x%x, imm:0x%x libbpf: prog '%s': relo #%d: parsing [%d] %s %s + %s failed: %d libbpf: prog '%s': relo #%d: %s libbpf: prog '%s': relo #%d: no matching targets found libbpf: prog '%s': relo #%d: <%s> (%d) relocation doesn't support anonymous types libbpf: prog '%s': relo #%d: error matching candidate #%d %s: %d libbpf: prog '%s': relo #%d: field offset ambiguity: %u != %u libbpf: prog '%s': relo #%d: relocation decision ambiguity: %s %llu != %s %llu libbpf: prog '%s': relo #%d: %s candidate #%d %s libbpf: usdt: unrecognized register '%s' libbpf: usdt: failed to get absolute path of '%s' (err %d), using path as is... libbpf: usdt: failed to open '%s' to get base addr of '%s': %d libbpf: usdt: discovered segment for lib '%s': addrs %zx-%zx mode %s offset %zx libbpf: usdt: failed to find '%s' (resolved to '%s') within PID %d memory mappings libbpf: usdt: failed to find USDT support BPF maps, did you forget to include bpf/usdt.bpf.h? /sys/bus/event_source/devices/uprobe/format/ref_ctr_offset libbpf: usdt: unrecognized ELF kind %d for '%s' libbpf: usdt: attaching to 32-bit ELF binary '%s' is not supported libbpf: usdt: unsupported ELF class for '%s' libbpf: usdt: unsupported type of ELF binary '%s' (%d), only ET_EXEC and ET_DYN are supported libbpf: usdt: ELF endianness mismatch for '%s' libbpf: usdt: no USDT notes section (%s) found in '%s' libbpf: usdt: invalid USDT notes section (%s) in '%s' libbpf: usdt: discovered PHDR #%d in '%s': vaddr 0x%lx memsz 0x%lx offset 0x%lx type 0x%lx flags 0x%lx libbpf: usdt: failed to find PT_LOAD program headers in '%s' libbpf: usdt: failed to process ELF program segments for '%s': %d libbpf: usdt: failed to find ELF program segment for '%s:%s' in '%s' at IP 0x%lx libbpf: usdt: matched ELF binary '%s' segment [0x%lx, 0x%lx) for '%s:%s' at IP 0x%lx is not executable libbpf: usdt: attaching to shared libraries without specific PID is not supported on current kernel libbpf: usdt: failed to get memory segments in PID %d for shared library '%s': %d libbpf: usdt: failed to find shared lib memory segment for '%s:%s' in '%s' at relative IP 0x%lx libbpf: usdt: probe for '%s:%s' in %s '%s': addr 0x%lx base 0x%lx (resolved abs_ip 0x%lx rel_ip 0x%lx) args '%s' in segment [0x%lx, 0x%lx) at offset 0x%lx libbpf: usdt: kernel doesn't support USDT semaphore refcounting for '%s:%s' in '%s' libbpf: usdt: failed to find ELF loadable segment with semaphore of '%s:%s' in '%s' at 0x%lx libbpf: usdt: matched ELF binary '%s' segment [0x%lx, 0x%lx] for semaphore of '%s:%s' at 0x%lx is executable libbpf: usdt: sema for '%s:%s' in %s '%s': addr 0x%lx base 0x%lx (resolved 0x%lx) in segment [0x%lx, 0x%lx] at offset 0x%lx libbpf: usdt: too many USDT arguments (> %d) for '%s:%s' with args spec '%s' libbpf: usdt: unrecognized arg #%d spec '%s' libbpf: usdt: unsupported arg #%d (spec '%s') size: %d libbpf: usdt: failed to set USDT spec #%d for '%s:%s' in '%s': %d libbpf: usdt: IP collision detected for spec #%d for '%s:%s' in '%s' libbpf: usdt: failed to map IP 0x%lx to spec #%d for '%s:%s' in '%s': %d libbpf: usdt: failed to attach uprobe #%d for '%s:%s' in '%s': %d libbpf: usdt: failed to attach uprobe multi for '%s:%s' in '%s': %d libbpf: elf: failed to get ehdr from %s: %s libbpf: elf: failed to find symbol table ELF sections in '%s' libbpf: elf: failed to get symbols for symtab section in '%s': %s libbpf: elf: failed to get verdef ELF section in '%s' libbpf: elf: failed to init libelf for %s libbpf: elf: could not read elf from %s: %s should not be 0 in a shared library try using shared library path instead libbpf: elf: ambiguous match for '%s', '%s' in '%s' libbpf: elf: symbol address match for '%s' in '%s': 0x%lx libbpf: elf: '%s' is 0 in symtab for '%s': %s libbpf: elf: failed to find symbol '%s' in '%s' libbpf: elf: ambiguous match found '%s@%lu' in '%s' previous offset %lu ? Y@ C @@ ? P? MbP? .A @ eA{Gz? 0A A N@ f g n rh|? @ @ @ i@ r@ @ @ ??333333?ffffff?{Gz? ?90 :0 ?? j@ư> 0C ? >@ ? )@ 9@ $@ K@ @ @ @? ?? ? ? 1@ `]@ 0k@ s@ z@ v@ @ ܄@ @333333? .@333333? & .> 4@ I@ R@ @ h Z ! 4 @ L > > + .. ############################### @B InvalidTimestamp graph,0.5,caller,function,percen /tmp/perf-inject-guest_session-X--sort=mem,sym,dso,symbol_daddr,dso_daddr,tlb,lo--sort=local_weight,mem,sym,dso,symbol_daddr,dso_daddr,snoop,tlb,locked,blocked ' Need privilege Have a try with with -f option @B <>>< < >< SSSSSSSSSSSSSSSS@B gfffgfffgfffgfff /tmp/perf-test-X/tmp/perf-pmu-test-format-XXXXXXd xV4 wUf3D" Z h i j k l m o q s t ާdY Sj xc d , X , X L d & : p L Sb Sb Sb Sb 1 ,1 4&k 4&k 1 -1 3&k 4&k 3|1 d3|1 3|1 3|1 3|1 3|1 3|1 3|1 3|1 3|1 Oh' dOh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' Oh' ZOh' dOh' Oh' Oh' Oh' Oh' YOh' eOh' {cycles,instruct @ test-prog with build id /tmp/perf-kmod-XPERFILE2h PERFILE2 /proc/self/ns/mn/tmp/perf-XXXXXX show reference e callgraph, 0000000000000000 Lost Auxiliary Trace Buffer /tmp/perf-kcore-perf_trace_conte Sort by index only available with group events! -F +brstackinsn is not availableis being ignored bpf_spin_lock v_lock val cnt l default_core bp_l1_btb_correct branch L1 BTB Correction event=0x8a 00 bp_l2_btb_correct branch L2 BTB Correction event=0x8b 00 l3_cache_rd cache L3 cache access, read event=0x40 00 Attributable Level 3 cache access, read segment_reg_loads.any other Number of segment register loads event=0x6,period=200000,umask=0x80 00 dispatch_blocked.any other Memory cluster signals to block micro-op dispatch for any reason event=0x9,period=200000,umask=0x20 00 eist_trans other Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions event=0x3a,period=200000,umask=0x0 00 hisi_sccl,ddrc uncore_hisi_ddrc.flux_wcmd uncore DDRC write commands event=0x2 00 DDRC write commands uncore_cbox unc_cbo_xsnp_response.miss_eviction uncore A cross-core snoop resulted from L3 Eviction which misses in some processor core event=0x22,umask=0x81 00 A cross-core snoop resulted from L3 Eviction which misses in some processor core event-hyphen uncore UNC_CBO_HYPHEN event=0xe0,umask=0x00 00 UNC_CBO_HYPHEN event-two-hyph uncore UNC_CBO_TWO_HYPH event=0xc0,umask=0x00 00 UNC_CBO_TWO_HYPH hisi_sccl,l3c uncore_hisi_l3c.rd_hit_cpipe uncore Total read hits event=0x7 00 Total read hits uncore_imc_free_running uncore_imc_free_running.cache_miss uncore Total cache misses event=0x12 00 Total cache misses uncore_imc uncore_imc.cache_hits uncore Total cache hits event=0x34 00 Total cache hits uncore_sys_ddr_pmu sys_ddr_pmu.write_cycles uncore ddr write-cycles event event=0x2b v8 00 uncore_sys_ccn_pmu sys_ccn_pmu.read_cycles uncore ccn read-cycles event config=0x2c 0x01 00 uncore_sys_cmn_pmu sys_cmn_pmu.hnf_cache_miss uncore Counts total cache misses in first lookup result (high priority) eventid=0x1,type=0x5 (434|436|43c|43a).* 00 l1d.hwpf_miss cache L1D.HWPF_MISS event=0x51,period=1000003,umask=0x20 00 l1d.replacement cache Counts the number of cache lines replaced in L1 data cache event=0x51,period=100003,umask=0x1 00 Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability event=0x48,period=1000003,umask=0x2 00 Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.fb_full_periods cache Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability event=0x48,cmask=1,edge=1,period=1000003,umask=0x2 00 Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.l2_stall cache This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS event=0x48,period=1000003,umask=0x4 10 l1d_pend_miss.l2_stalls cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources event=0x48,period=1000003,umask=0x4 00 Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.pending cache Number of L1D misses that are outstanding event=0x48,period=1000003,umask=0x1 00 Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=1000003,umask=0x1 00 Counts duration of L1D miss outstanding in cycles l2_lines_in.all cache L2 cache lines filling L2 event=0x25,period=100003,umask=0x1f 00 Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.useless_hwpf cache Cache lines that have been L2 hardware prefetched but not used by demand accesses event=0x26,period=200003,umask=0x4 00 Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache l2_request.all cache All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES] event=0x24,period=200003,umask=0xff 00 Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES] l2_request.miss cache Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4 00 Counts the total number of L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read access L2 cache event=0x24,period=200003,umask=0xe1 00 Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27 00 Counts demand requests that miss L2 cache l2_rqsts.all_hwpf cache L2_RQSTS.ALL_HWPF event=0x24,period=200003,umask=0xf0 00 l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2 00 Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4 00 Counts L2 cache hits when fetching instructions, code reads l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24 00 Counts L2 cache misses when fetching instructions l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0xc1 00 Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2 cache event=0x24,period=200003,umask=0x21 00 Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once l2_rqsts.hwpf_miss cache L2_RQSTS.HWPF_MISS event=0x24,period=200003,umask=0x30 00 l2_rqsts.miss cache Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] l2_rqsts.references cache All accesses to L2 cache [This event is alias to L2_REQUEST.ALL] event=0x24,period=200003,umask=0xff 00 Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL] l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2 00 Counts the RFO (Read-for-Ownership) requests that hit L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22 00 Counts the RFO (Read-for-Ownership) requests that miss L2 cache l2_rqsts.swpf_hit cache SW prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xc8 00 Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full l2_rqsts.swpf_miss cache SW prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x28 00 Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full longest_lat_cache.miss cache Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x41 00 Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.miss cache Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3) event=0x2e,period=100003,umask=0x41 00 Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 longest_lat_cache.reference cache Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x4f 00 Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.reference cache Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3) event=0x2e,period=100003,umask=0x4f 00 Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 mem_bound_stalls.ifetch cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x38 00 Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) mem_bound_stalls.ifetch_dram_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x20 00 Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM) mem_bound_stalls.ifetch_l2_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache event=0x34,period=200003,umask=0x8 00 Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache mem_bound_stalls.ifetch_llc_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M event=0x34,period=200003,umask=0x10 00 Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M mem_bound_stalls.load cache Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x7 00 mem_bound_stalls.load_dram_hit cache Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x4 00 mem_bound_stalls.load_l2_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=200003,umask=0x1 00 mem_bound_stalls.load_llc_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M event=0x34,period=200003,umask=0x2 00 Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M mem_inst_retired.all_loads cache Retired load instructions Supports address when precise (Precise event) event=0xd0,period=1000003,umask=0x81 00 Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise (Precise event) mem_inst_retired.all_stores cache Retired store instructions Supports address when precise (Precise event) event=0xd0,period=1000003,umask=0x82 00 Counts all retired store instructions Supports address when precise (Precise event) mem_inst_retired.any cache All retired memory instructions Supports address when precise (Precise event) event=0xd0,period=1000003,umask=0x83 00 Counts all retired memory instructions - loads and stores Supports address when precise (Precise event) mem_inst_retired.lock_loads cache Retired load instructions with locked access Supports address when precise (Precise event) event=0xd0,period=100007,umask=0x21 00 Counts retired load instructions with locked access Supports address when precise (Precise event) mem_inst_retired.split_loads cache Retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x41 00 Counts retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) mem_inst_retired.split_stores cache Retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x42 00 Counts retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) mem_inst_retired.stlb_miss_loads cache Retired load instructions that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x11 00 Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB) Supports address when precise (Precise event) mem_inst_retired.stlb_miss_stores cache Retired store instructions that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x12 00 Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB) Supports address when precise (Precise event) mem_load_completed.l1_miss_any cache Completed demand load uops that miss the L1 d-cache event=0x43,period=1000003,umask=0xfd 00 Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss) mem_load_l3_hit_retired.xsnp_fwd cache Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x4 00 Counts retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hit cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x2 00 Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x4 00 Counts retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x1 00 Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_none cache Retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) event=0xd2,period=100003,umask=0x8 00 Counts retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_no_fwd cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x2 00 Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_miss_retired.local_dram cache Retired load instructions which data sources missed L3 but serviced from local dram Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x1 00 Retired load instructions which data sources missed L3 but serviced from local DRAM Supports address when precise (Precise event) mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=0x4 00 Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock) Supports address when precise (Precise event) mem_load_retired.fb_hit cache Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1 Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x40 00 Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=1000003,umask=0x1 00 Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source Supports address when precise (Precise event) mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x8 00 Counts retired load instructions with at least one uop that missed in the L1 cache Supports address when precise (Precise event) mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x2 00 Counts retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100021,umask=0x10 00 Counts retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=100021,umask=0x4 00 Counts retired load instructions with at least one uop that hit in the L3 cache Supports address when precise (Precise event) mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x20 00 Counts retired load instructions with at least one uop that missed in the L3 cache Supports address when precise (Precise event) mem_load_uops_retired.dram_hit cache Counts the number of load uops retired that hit in DRAM Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x80 00 mem_load_uops_retired.l2_hit cache Counts the number of load uops retired that hit in the L2 cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x2 00 mem_load_uops_retired.l3_hit cache Counts the number of load uops retired that hit in the L3 cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x4 00 mem_scheduler_block.all cache Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full event=0x4,period=20003,umask=0x7 00 mem_scheduler_block.ld_buf cache Counts the number of cycles that uops are blocked due to a load buffer full condition event=0x4,period=20003,umask=0x2 00 mem_scheduler_block.rsv cache Counts the number of cycles that uops are blocked due to an RSV full condition event=0x4,period=20003,umask=0x4 00 mem_scheduler_block.st_buf cache Counts the number of cycles that uops are blocked due to a store buffer full condition event=0x4,period=20003,umask=0x1 00 mem_store_retired.l2_hit cache MEM_STORE_RETIRED.L2_HIT event=0x44,period=200003,umask=0x1 00 mem_uops_retired.all_loads cache Counts the number of load uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x81 00 Counts the total number of load uops retired Supports address when precise (Precise event) mem_uops_retired.all_stores cache Counts the number of store uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x82 00 Counts the total number of store uops retired Supports address when precise (Precise event) mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x80 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x10 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x100 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x20 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x4 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x200 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x40 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x8 00 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uops_retired.split_loads cache Counts the number of retired split load uops Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x41 00 mem_uops_retired.store_latency cache Counts the number of stores uops retired. Counts with or without PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x6 00 Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly Supports address when precise (Must be precise) mem_uop_retired.any cache Retired memory uops for any access event=0xe5,period=1000003,umask=0x3 00 Number of retired micro-operations (uops) for load or store memory accesses ocr.demand_data_rd.l3_hit cache Counts demand data reads that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 offcore_requests.all_requests cache OFFCORE_REQUESTS.ALL_REQUESTS event=0x21,period=100003,umask=0x80 00 offcore_requests.data_rd cache Demand and prefetch data reads event=0x21,period=100003,umask=0x8 00 Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0x21,period=100003,umask=0x1 00 Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests_outstanding.all_data_rd cache This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD Spec update: ADL038 event=0x20,period=1000003,umask=0x8 10 offcore_requests_outstanding.cycles_with_data_rd cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Spec update: ADL038 event=0x20,cmask=1,period=1000003,umask=0x8 00 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles where at least 1 outstanding demand data read request is pending event=0x20,cmask=1,period=2000003,umask=0x1 00 offcore_requests_outstanding.cycles_with_demand_rfo cache For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1 event=0x20,cmask=1,period=1000003,umask=0x4 00 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO offcore_requests_outstanding.data_rd cache OFFCORE_REQUESTS_OUTSTANDING.DATA_RD Spec update: ADL038 event=0x20,period=1000003,umask=0x8 00 offcore_requests_outstanding.demand_data_rd cache For every cycle, increments by the number of outstanding demand data read requests pending event=0x20,period=1000003,umask=0x1 00 For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor sq_misc.bus_lock cache Counts bus locks, accounts for cache line split locks and UC locks event=0x2c,period=100003,umask=0x10 00 Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x40,period=100003,umask=0x1 00 Counts the number of PREFETCHNTA instructions executed sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x40,period=100003,umask=0x8 00 Counts the number of PREFETCHW instructions executed sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x40,period=100003,umask=0x2 00 Counts the number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x40,period=100003,umask=0x4 00 Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed topdown_fe_bound.icache cache Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses event=0x71,period=1000003,umask=0x20 00 arith.fpdiv_active floating point ARITH.FPDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=0x1 00 assists.fp floating point Counts all microcode FP assists event=0xc1,period=100003,umask=0x2 00 Counts all microcode Floating Point assists assists.sse_avx_mix floating point ASSISTS.SSE_AVX_MIX event=0xc1,period=1000003,umask=0x10 00 fp_arith_dispatched.port_0 floating point FP_ARITH_DISPATCHED.PORT_0 event=0xb3,period=2000003,umask=0x1 00 fp_arith_dispatched.port_1 floating point FP_ARITH_DISPATCHED.PORT_1 event=0xb3,period=2000003,umask=0x2 00 fp_arith_dispatched.port_5 floating point FP_ARITH_DISPATCHED.PORT_5 event=0xb3,period=2000003,umask=0x4 00 fp_arith_inst_retired.128b_packed_double floating point Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x4 00 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x8 00 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x10 00 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x20 00 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x18 00 Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=1000003,umask=0x3 00 Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x1 00 Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x2 00 Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=1000003,umask=0xfc 00 Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events machine_clears.fp_assist floating point Counts the number of floating point operations retired that required microcode assist event=0xc3,period=20003,umask=0x4 00 Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event) event=0xc2,period=2000003,umask=0x8 00 baclears.any frontend Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xe6,period=100003,umask=0x1 00 Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches baclears.any frontend Clears due to Unknown Branches event=0x60,period=100003,umask=0x1 00 Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore decode.lcp frontend Stalls caused by changing prefix length of the instruction event=0x87,period=500009,umask=0x1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk decode.ms_busy frontend Cycles the Microcode Sequencer is busy event=0x87,period=500009,umask=0x2 00 dsb2mite_switches.penalty_cycles frontend DSB-to-MITE switch true penalty cycles event=0x61,period=100003,umask=0x2 00 Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x1 00 Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x11 00 Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss (Precise event) frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x14 00 Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x12 00 Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event) frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x13 00 Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event) frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x600106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x608006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x601006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x600206 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x610006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x100206 00 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x602006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x600406 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x620006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x604006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x600806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.ms_flows frontend FRONTEND_RETIRED.MS_FLOWS (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x8 00 frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x15 00 Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) frontend_retired.unknown_branch frontend FRONTEND_RETIRED.UNKNOWN_BRANCH (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x17 00 icache.accesses frontend Counts the number of requests to the instruction cache for one or more bytes of a cache line event=0x80,period=200003,umask=0x3 00 Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line icache.misses frontend Counts the number of instruction cache misses event=0x80,period=200003,umask=0x2 00 Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line icache_data.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache miss event=0x80,period=500009,umask=0x4 00 Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss event=0x83,period=200003,umask=0x4 00 Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss idq.dsb_cycles_any frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x8 00 Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.dsb_cycles_ok frontend Cycles DSB is delivering optimal number of Uops event=0x79,cmask=6,period=2000003,umask=0x8 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=0x8 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.mite_cycles_any frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x4 00 Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles_ok frontend Cycles MITE is delivering optimal number of Uops event=0x79,cmask=6,period=2000003,umask=0x4 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x4 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles_any frontend Cycles when uops are being delivered to IDQ while MS is busy event=0x79,cmask=1,period=2000003,umask=0x20 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_switches frontend Number of switches from DSB or MITE to the MS event=0x79,cmask=1,edge=1,period=100003,umask=0x20 00 Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to IDQ while MS is busy event=0x79,period=1000003,umask=0x20 00 Counts the total number of uops delivered by the Microcode Sequencer (MS) idq_bubbles.core frontend Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE] event=0x9c,period=1000003,umask=0x1 00 Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE] idq_bubbles.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] event=0x9c,cmask=6,period=1000003,umask=0x1 00 Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] idq_bubbles.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK] event=0x9c,cmask=1,inv=1,period=1000003,umask=0x1 00 Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK] idq_uops_not_delivered.core frontend Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE] event=0x9c,period=1000003,umask=0x1 00 Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE] idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] event=0x9c,cmask=6,period=1000003,umask=0x1 00 Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] idq_uops_not_delivered.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK] event=0x9c,cmask=1,inv=1,period=1000003,umask=0x1 00 Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK] cycle_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand load is outstanding event=0xa3,cmask=6,period=1000003,umask=0x6 00 ld_head.any_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires event=0x5,period=1000003,umask=0xff 00 ld_head.l1_bound_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring event=0x5,period=1000003,umask=0xf4 00 ld_head.l1_miss_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss event=0x5,period=1000003,umask=0x81 00 ld_head.other_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases event=0x5,period=1000003,umask=0xc0 00 Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc ld_head.pgwalk_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk event=0x5,period=1000003,umask=0xa0 00 ld_head.st_addr_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match event=0x5,period=1000003,umask=0x84 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation event=0xc3,period=20003,umask=0x2 00 machine_clears.memory_ordering memory Number of machine clears due to memory ordering conflicts event=0xc3,period=100003,umask=0x2 00 Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture memory_activity.cycles_l1d_miss memory Cycles while L1 cache miss demand load is outstanding event=0x47,cmask=2,period=1000003,umask=0x2 00 memory_activity.stalls_l1d_miss memory Execution stalls while L1 cache miss demand load is outstanding event=0x47,cmask=3,period=1000003,umask=0x3 00 memory_activity.stalls_l2_miss memory Execution stalls while L2 cache miss demand cacheable load request is outstanding event=0x47,cmask=5,period=1000003,umask=0x5 00 Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock) memory_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand cacheable load request is outstanding event=0x47,cmask=9,period=1000003,umask=0x9 00 Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock) mem_trans_retired.load_latency_gt_128 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles Supports address when precise (Must be precise) event=0xcd,period=1009,umask=0x1,ldlat=0x80 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_16 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles Supports address when precise (Must be precise) event=0xcd,period=20011,umask=0x1,ldlat=0x10 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_256 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles Supports address when precise (Must be precise) event=0xcd,period=503,umask=0x1,ldlat=0x100 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_32 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles Supports address when precise (Must be precise) event=0xcd,period=100007,umask=0x1,ldlat=0x20 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_4 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles Supports address when precise (Must be precise) event=0xcd,period=100003,umask=0x1,ldlat=0x4 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_512 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles Supports address when precise (Must be precise) event=0xcd,period=101,umask=0x1,ldlat=0x200 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_64 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles Supports address when precise (Must be precise) event=0xcd,period=2003,umask=0x1,ldlat=0x40 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_8 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles Supports address when precise (Must be precise) event=0xcd,period=50021,umask=0x1,ldlat=0x8 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.store_sample memory Retired memory store access operations. A PDist event for PEBS Store Latency Facility Supports address when precise (Must be precise) event=0xcd,period=1000003,umask=0x2 00 Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Supports address when precise (Must be precise) ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400001 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 00 ocr.demand_data_rd.l3_miss_local memory Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400002 00 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002 00 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400002 00 offcore_requests.l3_miss_demand_data_rd memory Counts demand data read requests that miss the L3 cache event=0x21,period=100003,umask=0x10 00 offcore_requests_outstanding.l3_miss_demand_data_rd memory For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache event=0x20,period=2000003,umask=0x10 00 For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache assists.hardware other ASSISTS.HARDWARE event=0xc1,period=100003,umask=0x4 00 assists.page_fault other ASSISTS.PAGE_FAULT event=0xc1,period=1000003,umask=0x8 00 core_power.license_1 other CORE_POWER.LICENSE_1 event=0x28,period=200003,umask=0x2 00 core_power.license_2 other CORE_POWER.LICENSE_2 event=0x28,period=200003,umask=0x4 00 core_power.license_3 other CORE_POWER.LICENSE_3 event=0x28,period=200003,umask=0x8 00 ocr.corewb_m.any_response other Counts modified writebacks from L1 cache and L2 cache that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10008 00 ocr.demand_data_rd.any_response other Counts demand data reads that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 00 ocr.demand_data_rd.any_response other Counts demand data reads that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10001 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x184000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 00 ocr.demand_rfo.any_response other Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10002 00 ocr.streaming_wr.any_response other Counts streaming stores that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10800 00 ocr.streaming_wr.any_response other Counts streaming stores that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10800 00 rs.empty other Cycles when Reservation Station (RS) is empty for the thread event=0xa5,period=1000003,umask=0x7 00 Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) rs.empty_count other Counts end of periods where the Reservation Station (RS) was empty event=0xa5,cmask=1,edge=1,inv=1,period=100003,umask=0x7 00 Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) rs_empty.count other This event is deprecated. Refer to new event RS.EMPTY_COUNT event=0xa5,cmask=1,edge=1,inv=1,period=100003,umask=0x7 10 rs_empty.cycles other This event is deprecated. Refer to new event RS.EMPTY event=0xa5,period=1000003,umask=0x7 10 xq.full_cycles other Cycles the uncore cannot take further requests event=0x2d,cmask=1,period=1000003,umask=0x1 00 number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache) arith.divider_active pipeline This event is deprecated. Refer to new event ARITH.DIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=0x9 10 arith.div_active pipeline Cycles when divide unit is busy executing divide or square root operations event=0xb0,cmask=1,period=1000003,umask=0x9 00 Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations arith.fp_divider_active pipeline This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=0x1 10 arith.idiv_active pipeline This event counts the cycles the integer divider is busy event=0xb0,cmask=1,period=1000003,umask=0x8 00 arith.int_divider_active pipeline This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=0x8 10 assists.any pipeline Number of occurrences where a microcode assist is invoked by hardware event=0xc1,period=100003,umask=0x1b 00 Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types (Precise event) event=0xc4,period=200003 00 Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for (Precise event) br_inst_retired.all_branches pipeline All branch instructions retired (Precise event) event=0xc4,period=400009 00 Counts all branch instructions retired (Precise event) br_inst_retired.call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL (Precise event) event=0xc4,period=200003,umask=0xf9 10 br_inst_retired.cond pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event) event=0xc4,period=200003,umask=0x7e 00 br_inst_retired.cond pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x11 00 Counts conditional branch instructions retired (Precise event) br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x10 00 Counts not taken branch instructions retired (Precise event) br_inst_retired.cond_taken pipeline Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe 00 br_inst_retired.cond_taken pipeline Taken conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x1 00 Counts taken conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return (Precise event) event=0xc4,period=200003,umask=0xbf 00 br_inst_retired.far_branch pipeline Far branch instructions retired (Precise event) event=0xc4,period=100007,umask=0x40 00 Counts far branch instructions retired (Precise event) br_inst_retired.indirect pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb 00 br_inst_retired.indirect pipeline Indirect near branch instructions retired (excluding returns) (Precise event) event=0xc4,period=100003,umask=0x80 00 Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event) br_inst_retired.indirect_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb 00 br_inst_retired.ind_call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL (Precise event) event=0xc4,period=200003,umask=0xfb 10 br_inst_retired.jcc pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.COND (Precise event) event=0xc4,period=200003,umask=0x7e 10 br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9 00 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=0x2 00 Counts both direct and indirect near call instructions retired (Precise event) br_inst_retired.near_return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7 00 br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=0x8 00 Counts return instructions retired (Precise event) br_inst_retired.near_taken pipeline Counts the number of near taken branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xc0 00 br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 Counts taken branch instructions retired (Precise event) br_inst_retired.non_return_ind pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT (Precise event) event=0xc4,period=200003,umask=0xeb 10 br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfd 00 br_inst_retired.return pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN (Precise event) event=0xc4,period=200003,umask=0xf7 10 br_inst_retired.taken_jcc pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN (Precise event) event=0xc4,period=200003,umask=0xfe 10 br_misp_retired.all_branches pipeline Counts the total number of mispredicted branch instructions retired for all branch types (Precise event) event=0xc5,period=200003 00 Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path (Precise event) br_misp_retired.all_branches pipeline All mispredicted branch instructions retired (Precise event) event=0xc5,period=400009 00 Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.cond pipeline Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e 00 br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x11 00 Counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x10 00 Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken (Precise event) br_misp_retired.cond_taken pipeline Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe 00 br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x1 00 Counts taken conditional mispredicted branch instructions retired (Precise event) br_misp_retired.indirect pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb 00 br_misp_retired.indirect pipeline Miss-predicted near indirect branch instructions retired (excluding returns) (Precise event) event=0xc5,period=100003,umask=0x80 00 Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event) br_misp_retired.indirect_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb 00 br_misp_retired.indirect_call pipeline Mispredicted indirect CALL retired (Precise event) event=0xc5,period=400009,umask=0x2 00 Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect (Precise event) br_misp_retired.ind_call pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL (Precise event) event=0xc5,period=200003,umask=0xfb 10 br_misp_retired.jcc pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.COND (Precise event) event=0xc5,period=200003,umask=0x7e 10 br_misp_retired.near_taken pipeline Counts the number of mispredicted near taken branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x80 00 br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 Counts number of near branch instructions retired that were mispredicted and taken (Precise event) br_misp_retired.non_return_ind pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT (Precise event) event=0xc5,period=200003,umask=0xeb 10 br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=100007,umask=0x8 00 This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired (Precise event) br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xf7 00 br_misp_retired.taken_jcc pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN (Precise event) event=0xc5,period=200003,umask=0xfe 10 cpu_clk_unhalted.c01 pipeline Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state event=0xec,period=2000003,umask=0x10 00 Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions cpu_clk_unhalted.c02 pipeline Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state event=0xec,period=2000003,umask=0x20 00 Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions cpu_clk_unhalted.c0_wait pipeline Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state event=0xec,period=2000003,umask=0x70 00 Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction cpu_clk_unhalted.core pipeline Counts the number of unhalted core clock cycles. (Fixed event) event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter cpu_clk_unhalted.distributed pipeline Cycle counts are evenly distributed between active threads in the Core event=0xec,period=2000003,umask=0x2 00 This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread cpu_clk_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=0x2 00 Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted cpu_clk_unhalted.pause pipeline CPU_CLK_UNHALTED.PAUSE event=0xec,period=2000003,umask=0x40 00 cpu_clk_unhalted.pause_inst pipeline CPU_CLK_UNHALTED.PAUSE_INST event=0xec,cmask=1,edge=1,period=2000003,umask=0x40 00 cpu_clk_unhalted.ref_distributed pipeline Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core event=0x3c,period=2000003,umask=0x8 00 This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread cpu_clk_unhalted.ref_tsc pipeline Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event) event=0,period=2000003,umask=0x3 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_tsc_p pipeline Counts the number of unhalted reference clock cycles at TSC frequency event=0x3c,period=2000003,umask=0x1 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc_p pipeline Reference cycles when the core is not in halt state event=0x3c,period=2000003,umask=0x1 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.thread pipeline Counts the number of unhalted core clock cycles. (Fixed event) event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003 00 This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time cycle_activity.cycles_l1d_miss pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=1000003,umask=0x8 00 cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=1000003,umask=0x1 00 cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=16,period=1000003,umask=0x10 00 cycle_activity.stalls_l1d_miss pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=1000003,umask=0xc 00 cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=1000003,umask=0x5 00 cycle_activity.stalls_total pipeline Total execution stalls event=0xa3,cmask=4,period=1000003,umask=0x4 00 exe_activity.1_ports_util pipeline Cycles total of 1 uop is executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=0x2 00 Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty exe_activity.2_ports_util pipeline Cycles total of 2 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=0x4 00 Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty exe_activity.3_ports_util pipeline Cycles total of 3 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=0x8 00 Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.4_ports_util pipeline Cycles total of 4 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=0x10 00 Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.bound_on_loads pipeline Execution stalls while memory subsystem has an outstanding load event=0xa6,cmask=5,period=2000003,umask=0x21 00 exe_activity.bound_on_stores pipeline Cycles where the Store Buffer was full and no loads caused an execution stall event=0xa6,cmask=2,period=1000003,umask=0x40 00 Counts cycles where the Store Buffer was full and no loads caused an execution stall exe_activity.exe_bound_0_ports pipeline Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load event=0xa6,period=1000003,umask=0x80 00 Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load inst_decoded.decoders pipeline Instruction decoders utilized in a cycle event=0x75,period=2000003,umask=0x1 00 Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions inst_retired.any pipeline Counts the total number of instructions retired. (Fixed event) (Precise event) event=0xc0,period=2000003 00 Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0 (Precise event) inst_retired.any pipeline Number of instructions retired. Fixed Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.any_p pipeline Counts the total number of instructions retired (Precise event) event=0xc0,period=2000003 00 Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter (Precise event) inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.macro_fused pipeline INST_RETIRED.MACRO_FUSED event=0xc0,period=2000003,umask=0x10 00 inst_retired.nop pipeline Retired NOP instructions event=0xc0,period=2000003,umask=0x2 00 Counts all retired NOP or ENDBR32/64 instructions inst_retired.prec_dist pipeline Precise instruction retired with PEBS precise-distribution (Precise event) event=0,period=2000003,umask=0x1 00 A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event) inst_retired.rep_iteration pipeline Iterations of Repeat string retired instructions event=0xc0,period=2000003,umask=0x8 00 Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent int_misc.clears_count pipeline Clears speculative count event=0xad,cmask=1,edge=1,period=500009,umask=0x1 00 Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path event=0xad,period=500009,umask=0x80 00 Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread event=0xad,period=500009,umask=0x1 00 Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.unknown_branch_cycles pipeline Bubble cycles of BAClear (Unknown Branch) event=0xad,period=1000003,umask=0x40,frontend=0x7 00 int_misc.uop_dropping pipeline TMA slots where uops got dropped event=0xad,period=1000003,umask=0x10 00 Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons int_vec_retired.128bit pipeline INT_VEC_RETIRED.128BIT event=0xe7,period=1000003,umask=0x13 00 int_vec_retired.256bit pipeline INT_VEC_RETIRED.256BIT event=0xe7,period=1000003,umask=0xac 00 int_vec_retired.add_128 pipeline integer ADD, SUB, SAD 128-bit vector instructions event=0xe7,period=1000003,umask=0x3 00 Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions int_vec_retired.add_256 pipeline integer ADD, SUB, SAD 256-bit vector instructions event=0xe7,period=1000003,umask=0xc 00 Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions int_vec_retired.mul_256 pipeline INT_VEC_RETIRED.MUL_256 event=0xe7,period=1000003,umask=0x80 00 int_vec_retired.shuffles pipeline INT_VEC_RETIRED.SHUFFLES event=0xe7,period=1000003,umask=0x40 00 int_vec_retired.vnni_128 pipeline INT_VEC_RETIRED.VNNI_128 event=0xe7,period=1000003,umask=0x10 00 int_vec_retired.vnni_256 pipeline INT_VEC_RETIRED.VNNI_256 event=0xe7,period=1000003,umask=0x20 00 ld_blocks.4k_alias pipeline This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS (Precise event) event=0x3,period=1000003,umask=0x4 10 ld_blocks.address_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event) event=0x3,period=1000003,umask=0x4 00 ld_blocks.address_alias pipeline False dependencies in MOB due to partial compare on address event=0x3,period=100003,umask=0x4 00 Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address ld_blocks.data_unknown pipeline Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready (Precise event) event=0x3,period=1000003,umask=0x1 00 ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=0x3,period=100003,umask=0x88 00 Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Loads blocked due to overlapping with a preceding store that cannot be forwarded event=0x3,period=100003,umask=0x82 00 Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide load_hit_prefetch.swpf pipeline Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=0x1 00 Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=0x1 00 Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector) lsd.cycles_ok pipeline Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder event=0xa8,cmask=6,period=2000003,umask=0x1 00 Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=0x1 00 Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector) machine_clears.count pipeline Number of machine clears (nukes) of any type event=0xc3,cmask=1,edge=1,period=100003,umask=0x1 00 Counts the number of machine clears (nukes) of any type machine_clears.disambiguation pipeline Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU event=0xc3,period=20003,umask=0x8 00 machine_clears.mrn_nuke pipeline Counts the number of machines clears due to memory renaming event=0xc3,period=1000003,umask=0x80 00 machine_clears.page_fault pipeline Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs event=0xc3,period=20003,umask=0x20 00 machine_clears.slow pipeline Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP event=0xc3,period=20003,umask=0x6f 00 machine_clears.smc pipeline Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page event=0xc3,period=20003,umask=0x1 00 machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=0x4 00 Counts self-modifying code (SMC) detected, which causes a machine clear misc2_retired.lfence pipeline LFENCE instructions retired event=0xe0,period=400009,umask=0x20 00 number of LFENCE retired instructions misc_retired.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=100003,umask=0x20 00 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=100003,umask=0x8 00 Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end resource_stalls.scoreboard pipeline Counts cycles where the pipeline is stalled due to serializing operations event=0xa2,period=100003,umask=0x2 00 serialization.non_c01_ms_scb pipeline Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires event=0x75,period=200003,umask=0x2 00 Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE topdown.backend_bound_slots pipeline TMA slots where no uops were being issued due to lack of back-end resources event=0xa4,period=10000003,umask=0x2 00 Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources topdown.bad_spec_slots pipeline TMA slots wasted due to incorrect speculations event=0xa4,period=10000003,umask=0x4 00 Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations topdown.br_mispredict_slots pipeline TMA slots wasted due to incorrect speculation by branch mispredictions event=0xa4,period=10000003,umask=0x8 00 Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction topdown.memory_bound_slots pipeline TOPDOWN.MEMORY_BOUND_SLOTS event=0xa4,period=10000003,umask=0x10 00 topdown.slots pipeline TMA slots available for an unhalted logical processor. Fixed counter - architectural event event=0,period=10000003,umask=0x4 00 Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3) topdown.slots_p pipeline TMA slots available for an unhalted logical processor. General counter - architectural event event=0xa4,period=10000003,umask=0x1 00 Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core topdown_bad_speculation.all pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003 00 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.fastnuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears event=0x73,period=1000003,umask=0x2 00 topdown_bad_speculation.machine_clears pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation event=0x73,period=1000003,umask=0x3 00 topdown_bad_speculation.mispredict pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts event=0x73,period=1000003,umask=0x4 00 topdown_bad_speculation.nuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke) event=0x73,period=1000003,umask=0x1 00 topdown_be_bound.all pipeline Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls event=0x74,period=1000003 00 topdown_be_bound.alloc_restrictions pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions event=0x74,period=1000003,umask=0x1 00 topdown_be_bound.mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops event=0x74,period=1000003,umask=0x2 00 topdown_be_bound.non_mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops event=0x74,period=1000003,umask=0x8 00 topdown_be_bound.register pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) event=0x74,period=1000003,umask=0x20 00 topdown_be_bound.reorder_buffer pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls) event=0x74,period=1000003,umask=0x40 00 topdown_be_bound.serialization pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) event=0x74,period=1000003,umask=0x10 00 topdown_fe_bound.all pipeline Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls event=0x71,period=1000003 00 topdown_fe_bound.branch_detect pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS event=0x71,period=1000003,umask=0x2 00 Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches topdown_fe_bound.branch_resteer pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS event=0x71,period=1000003,umask=0x40 00 Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch topdown_fe_bound.cisc pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS) event=0x71,period=1000003,umask=0x1 00 topdown_fe_bound.decode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls event=0x71,period=1000003,umask=0x8 00 topdown_fe_bound.frontend_bandwidth pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations event=0x71,period=1000003,umask=0x8d 00 topdown_fe_bound.frontend_latency pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses event=0x71,period=1000003,umask=0x72 00 topdown_fe_bound.itlb pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses event=0x71,period=1000003,umask=0x10 00 Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses topdown_fe_bound.other pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized event=0x71,period=1000003,umask=0x80 00 topdown_fe_bound.predecode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes event=0x71,period=1000003,umask=0x4 00 topdown_retiring.all pipeline Counts the total number of consumed retirement slots (Precise event) event=0xc2,period=1000003 00 uops_decoded.dec0_uops pipeline UOPS_DECODED.DEC0_UOPS event=0x76,period=1000003,umask=0x1 00 uops_dispatched.port_0 pipeline Uops executed on port 0 event=0xb2,period=2000003,umask=0x1 00 Number of uops dispatch to execution port 0 uops_dispatched.port_1 pipeline Uops executed on port 1 event=0xb2,period=2000003,umask=0x2 00 Number of uops dispatch to execution port 1 uops_dispatched.port_2_3_10 pipeline Uops executed on ports 2, 3 and 10 event=0xb2,period=2000003,umask=0x4 00 Number of uops dispatch to execution ports 2, 3 and 10 uops_dispatched.port_4_9 pipeline Uops executed on ports 4 and 9 event=0xb2,period=2000003,umask=0x10 00 Number of uops dispatch to execution ports 4 and 9 uops_dispatched.port_5_11 pipeline Uops executed on ports 5 and 11 event=0xb2,period=2000003,umask=0x20 00 Number of uops dispatch to execution ports 5 and 11 uops_dispatched.port_6 pipeline Uops executed on port 6 event=0xb2,period=2000003,umask=0x40 00 Number of uops dispatch to execution port 6 uops_dispatched.port_7_8 pipeline Uops executed on ports 7 and 8 event=0xb2,period=2000003,umask=0x80 00 Number of uops dispatch to execution ports 7 and 8 uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=0x2 00 Counts cycles when at least 1 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=0x2 00 Counts cycles when at least 2 micro-ops are executed from any thread on physical core uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=0x2 00 Counts cycles when at least 3 micro-ops are executed from any thread on physical core uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=0x2 00 Counts cycles when at least 4 micro-ops are executed from any thread on physical core uops_executed.cycles_ge_1 pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=0x1 00 Cycles where at least 1 uop was executed per-thread uops_executed.cycles_ge_2 pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=0x1 00 Cycles where at least 2 uops were executed per-thread uops_executed.cycles_ge_3 pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=0x1 00 Cycles where at least 3 uops were executed per-thread uops_executed.cycles_ge_4 pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=0x1 00 Cycles where at least 4 uops were executed per-thread uops_executed.stalls pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=0x1 00 Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.stall_cycles pipeline This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS event=0xb1,cmask=1,inv=1,period=2000003,umask=0x1 10 uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=0x1 00 uops_executed.x87 pipeline Counts the number of x87 uops dispatched event=0xb1,period=2000003,umask=0x10 00 Counts the number of x87 uops executed uops_issued.any pipeline Uops that RAT issues to RS event=0xae,period=2000003,umask=0x1 00 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_retired.all pipeline Counts the total number of uops retired (Precise event) event=0xc2,period=2000003 00 uops_retired.cycles pipeline Cycles with retired uop(s) event=0xc2,cmask=1,period=1000003,umask=0x2 00 Counts cycles where at least one uop has retired uops_retired.heavy pipeline Retired uops except the last uop of each instruction event=0xc2,period=2000003,umask=0x1 00 Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count uops_retired.idiv pipeline Counts the number of integer divide uops retired (Precise event) event=0xc2,period=2000003,umask=0x10 00 uops_retired.ms pipeline Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event) event=0xc2,period=2000003,umask=0x1 00 Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows (Precise event) uops_retired.ms pipeline UOPS_RETIRED.MS event=0xc2,period=2000003,umask=0x4,frontend=0x8 00 uops_retired.slots pipeline Retirement slots used event=0xc2,period=2000003,umask=0x2 00 Counts the retirement slots used each cycle uops_retired.stalls pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=1000003,umask=0x2 00 This event counts cycles without actually retired uops uops_retired.stall_cycles pipeline This event is deprecated. Refer to new event UOPS_RETIRED.STALLS event=0xc2,cmask=1,inv=1,period=1000003,umask=0x2 10 uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in MS flows (Precise event) event=0xc2,period=2000003,umask=0x2 00 uncore_arb unc_arb_coh_trk_requests.all uncore interconnect Number of requests allocated in Coherency Tracker event=0x84,umask=0x1 01 unc_arb_dat_occupancy.all uncore interconnect Each cycle counts number of any coherent request at memory controller that were issued by any core event=0x85,umask=0x1 01 unc_arb_dat_occupancy.rd uncore interconnect Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core event=0x85,umask=0x2 01 unc_arb_dat_requests.rd uncore interconnect This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD event=0x81,umask=0x2 11 unc_arb_ifa_occupancy.all uncore interconnect This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL event=0x85,umask=0x1 11 unc_arb_req_trk_occupancy.drd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD] event=0x80,umask=0x2 01 unc_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD] event=0x81,umask=0x2 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=0x1 01 unc_arb_trk_occupancy.rd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD] event=0x80,umask=0x2 01 unc_arb_trk_requests.all uncore interconnect Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC event=0x81,umask=0x1 01 unc_arb_trk_requests.rd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD] event=0x81,umask=0x2 01 uncore_imc_free_running_0 unc_mc0_rdcas_count_freerun uncore memory Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels) unc_mc0_wrcas_count_freerun uncore memory Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x30 01 uncore_imc_free_running_1 unc_mc1_rdcas_count_freerun uncore memory Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels) unc_mc1_wrcas_count_freerun uncore memory Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x30 01 unc_m_act_count_rd uncore memory ACT command for a read request sent to DRAM event=0x24 01 unc_m_act_count_total uncore memory ACT command sent to DRAM event=0x26 01 unc_m_act_count_wr uncore memory ACT command for a write request sent to DRAM event=0x25 01 unc_m_cas_count_rd uncore memory Read CAS command sent to DRAM event=0x22 01 unc_m_cas_count_wr uncore memory Write CAS command sent to DRAM event=0x23 01 unc_m_clockticks uncore memory Number of clocks event=0x1 01 unc_m_dram_page_empty_rd uncore memory incoming read request page status is Page Empty event=0x1d 01 unc_m_dram_page_empty_wr uncore memory incoming write request page status is Page Empty event=0x20 01 unc_m_dram_page_hit_rd uncore memory incoming read request page status is Page Hit event=0x1c 01 unc_m_dram_page_hit_wr uncore memory incoming write request page status is Page Hit event=0x1f 01 unc_m_dram_page_miss_rd uncore memory incoming read request page status is Page Miss event=0x1e 01 unc_m_dram_page_miss_wr uncore memory incoming write request page status is Page Miss event=0x21 01 unc_m_dram_thermal_hot uncore memory Any Rank at Hot state event=0x19 01 unc_m_dram_thermal_warm uncore memory Any Rank at Warm state event=0x1a 01 unc_m_prefetch_rd uncore memory Incoming read prefetch request from IA event=0xa 01 unc_m_pre_count_idle uncore memory PRE command sent to DRAM due to page table idle timer expiration event=0x28 01 unc_m_pre_count_page_miss uncore memory PRE command sent to DRAM for a read/write request event=0x27 01 unc_m_vc0_requests_rd uncore memory Incoming VC0 read request event=0x2 01 unc_m_vc0_requests_wr uncore memory Incoming VC0 write request event=0x3 01 unc_m_vc1_requests_rd uncore memory Incoming VC1 read request event=0x4 01 unc_m_vc1_requests_wr uncore memory Incoming VC1 write request event=0x5 01 uncore_clock unc_clock.socket uncore other This 48-bit fixed counter counts the UCLK cycles event=0xff 01 dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=0x12,period=100003,umask=0x20 00 Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a demand load event=0x12,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses to any page size event=0x8,period=200003,umask=0xe 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_load_misses.walk_completed virtual memory Load miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x12,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_1g virtual memory Page walks completed due to a demand data load to a 1G page event=0x12,period=100003,umask=0x8 00 Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data load to a 2M/4M page event=0x12,period=100003,umask=0x4 00 Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walks completed due to a demand data load to a 4K page event=0x12,period=100003,umask=0x2 00 Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Number of page walks outstanding for a demand load in the PMH each cycle event=0x12,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x13,period=100003,umask=0x20 00 Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store event=0x13,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to any page size event=0x49,period=2000003,umask=0xe 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_store_misses.walk_completed virtual memory Store misses in all TLB levels causes a page walk that completes. (All page sizes) event=0x13,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walks completed due to a demand data store to a 1G page event=0x13,period=100003,umask=0x8 00 Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x13,period=100003,umask=0x4 00 Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x13,period=100003,umask=0x2 00 Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Number of page walks outstanding for a store in the PMH each cycle event=0x13,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle itlb_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs event=0x85,period=1000003,umask=0x1 00 itlb_misses.pde_cache_miss virtual memory Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache event=0x85,period=2000003,umask=0x80 00 itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x11,period=100003,umask=0x20 00 Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request event=0x11,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request itlb_misses.walk_completed virtual memory Counts the number of page walks completed due to instruction fetch misses to any page size event=0x85,period=200003,umask=0xe 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault itlb_misses.walk_completed virtual memory Code miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x11,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x11,period=100003,umask=0x4 00 Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x11,period=100003,umask=0x2 00 Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_pending virtual memory Number of page walks outstanding for an outstanding code request in the PMH each cycle event=0x11,period=100003,umask=0x10 00 Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle ld_head.dtlb_miss_at_ret virtual memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss event=0x5,period=1000003,umask=0x90 00 bp_dyn_ind_pred branch Dynamic Indirect Predictions event=0x8e 00 Indirect Branch Prediction for potential multi-target branch (speculative) bp_de_redirect branch Decoder Overrides Existing Branch Prediction (speculative) event=0x91 00 bp_l1_tlb_fetch_hit branch The number of instruction fetches that hit in the L1 ITLB event=0x94 00 ic_fw32 cache The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses) event=0x80 00 ic_fw32_miss cache The number of 32B fetch windows tried to read the L1 IC and missed in the full tag event=0x81 00 ic_cache_fill_l2 cache The number of 64 byte instruction cache line was fulfilled from the L2 cache event=0x82 00 ic_cache_fill_sys cache The number of 64 byte instruction cache line fulfilled from system memory or another cache event=0x83 00 bp_l1_tlb_miss_l2_hit cache The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84 00 bp_l1_tlb_miss_l2_miss cache The number of instruction fetches that miss in both the L1 and L2 TLBs event=0x85 00 bp_snp_re_sync cache The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event event=0x86 00 ic_fetch_stall.ic_stall_any cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1) event=0x87,umask=0x04 00 ic_fetch_stall.ic_stall_dq_empty cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty event=0x87,umask=0x02 00 ic_fetch_stall.ic_stall_back_pressure cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure event=0x87,umask=0x01 00 ic_cache_inval.l2_invalidating_probe cache IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core event=0x8c,umask=0x02 00 ic_cache_inval.fill_invalidated cache IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core event=0x8c,umask=0x01 00 bp_tlb_rel cache The number of ITLB reload requests event=0x99 00 l2_request_g1.rd_blk_l cache All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch) event=0x60,umask=0x80 00 l2_request_g1.rd_blk_x cache All L2 Cache Requests (Breakdown 1 - Common). Data cache stores event=0x60,umask=0x40 00 l2_request_g1.ls_rd_blk_c_s cache All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads event=0x60,umask=0x20 00 l2_request_g1.cacheable_ic_read cache All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads event=0x60,umask=0x10 00 l2_request_g1.change_to_x cache All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state event=0x60,umask=0x08 00 l2_request_g1.prefetch_l2_cmd cache All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd event=0x60,umask=0x04 00 l2_request_g1.l2_hw_pf cache All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event event=0x60,umask=0x02 00 l2_request_g1.group2 cache Miscellaneous events covered in more detail by l2_request_g2 (PMCx061) event=0x60,umask=0x01 00 l2_request_g1.all_no_prefetch cache event=0x60,umask=0xf9 00 l2_request_g2.group1 cache Miscellaneous events covered in more detail by l2_request_g1 (PMCx060) event=0x61,umask=0x80 00 l2_request_g2.ls_rd_sized cache All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized event=0x61,umask=0x40 00 l2_request_g2.ls_rd_sized_nc cache All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable event=0x61,umask=0x20 00 l2_request_g2.ic_rd_sized cache All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized event=0x61,umask=0x10 00 l2_request_g2.ic_rd_sized_nc cache All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable event=0x61,umask=0x08 00 l2_request_g2.smc_inval cache All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates event=0x61,umask=0x04 00 l2_request_g2.bus_locks_originator cache All L2 Cache Requests (Breakdown 2 - Rare). Bus locks event=0x61,umask=0x02 00 l2_request_g2.bus_locks_responses cache All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response event=0x61,umask=0x01 00 l2_latency.l2_cycles_waiting_on_fills cache Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used event=0x62,umask=0x01 00 l2_wcb_req.wcb_write cache LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests event=0x63,umask=0x40 00 l2_wcb_req.wcb_close cache LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests event=0x63,umask=0x20 00 l2_wcb_req.zero_byte_store cache LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests event=0x63,umask=0x04 00 l2_wcb_req.cl_zero cache LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests event=0x63,umask=0x01 00 l2_cache_req_stat.ls_rd_blk_cs cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2 event=0x64,umask=0x80 00 l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2 event=0x64,umask=0x40 00 l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2 event=0x64,umask=0x20 00 l2_cache_req_stat.ls_rd_blk_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2 event=0x64,umask=0x10 00 l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types) event=0x64,umask=0x08 00 l2_cache_req_stat.ic_fill_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2 event=0x64,umask=0x04 00 l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2 event=0x64,umask=0x02 00 l2_cache_req_stat.ic_fill_miss cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 event=0x64,umask=0x01 00 l2_cache_req_stat.ic_access_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2 event=0x64,umask=0x07 00 l2_cache_req_stat.ic_dc_miss_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types) event=0x64,umask=0x09 00 l2_cache_req_stat.ic_dc_hit_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types) event=0x64,umask=0xf6 00 l2_fill_pending.l2_fill_busy cache Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2 event=0x6d,umask=0x01 00 l2_pf_hit_l2 cache L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead event=0x70,umask=0xff 00 l2_pf_miss_l2_hit_l3 cache L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3 event=0x71,umask=0xff 00 l2_pf_miss_l2_l3 cache L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches event=0x72,umask=0xff 00 amd_l3 l3_request_g1.caching_l3_cache_accesses cache Caching: L3 cache accesses event=0x1,umask=0x80 00 l3_lookup_state.all_l3_req_typs cache All L3 Request Types event=0x4,umask=0xff 00 l3_comb_clstr_state.other_l3_miss_typs cache Other L3 Miss Request Types event=0x6,umask=0xfe 00 l3_comb_clstr_state.request_miss cache L3 cache misses event=0x6,umask=0x01 00 xi_sys_fill_latency cache L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask event=0x90,umask=0x00 00 xi_ccx_sdp_req1.all_l3_miss_req_typs cache All L3 Miss Request Types. Ignores SliceMask and ThreadMask event=0x9a,umask=0x3f 00 ex_ret_instr core Retired Instructions event=0xc0 00 ex_ret_cops core Retired Uops event=0xc1 00 The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4 ex_ret_brn core Retired Branch Instructions event=0xc2 00 The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_misp core Retired Branch Instructions Mispredicted event=0xc3 00 The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts) ex_ret_brn_tkn core Retired Taken Branch Instructions event=0xc4 00 The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_tkn_misp core Retired Taken Branch Instructions Mispredicted event=0xc5 00 The number of retired taken branch instructions that were mispredicted ex_ret_brn_far core Retired Far Control Transfers event=0xc6 00 The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction ex_ret_brn_resync core Retired Branch Resyncs event=0xc7 00 The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare ex_ret_near_ret core Retired Near Returns event=0xc8 00 The number of near return instructions (RET or RET Iw) retired ex_ret_near_ret_mispred core Retired Near Returns Mispredicted event=0xc9 00 The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction ex_ret_brn_ind_misp core Retired Indirect Branch Instructions Mispredicted event=0xca 00 ex_ret_mmx_fp_instr.sse_instr core SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) event=0xcb,umask=0x04 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) ex_ret_mmx_fp_instr.mmx_instr core MMX instructions event=0xcb,umask=0x02 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions ex_ret_mmx_fp_instr.x87_instr core x87 instructions event=0xcb,umask=0x01 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions ex_ret_cond core Retired Conditional Branch Instructions event=0xd1 00 ex_div_busy core Div Cycles Busy count event=0xd3 00 ex_div_count core Div Op Count event=0xd4 00 ex_tagged_ibs_ops.ibs_count_rollover core Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired event=0x1cf,umask=0x04 00 ex_tagged_ibs_ops.ibs_tagged_ops_ret core Tagged IBS Ops. Number of Ops tagged by IBS that retired event=0x1cf,umask=0x02 00 ex_tagged_ibs_ops.ibs_tagged_ops core Tagged IBS Ops. Number of Ops tagged by IBS event=0x1cf,umask=0x01 00 ex_ret_fus_brnch_inst core The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3 event=0x1d0 00 amd_df remote_outbound_data_controller_0 data fabric event=0x7c7,umask=0x02 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0 remote_outbound_data_controller_1 data fabric event=0x807,umask=0x02 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1 remote_outbound_data_controller_2 data fabric event=0x847,umask=0x02 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2 remote_outbound_data_controller_3 data fabric event=0x887,umask=0x02 01 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3 dram_channel_data_controller_0 data fabric event=0x7,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_1 data fabric event=0x47,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_2 data fabric event=0x87,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_3 data fabric event=0xc7,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_4 data fabric event=0x107,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_5 data fabric event=0x147,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_6 data fabric event=0x187,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_7 data fabric event=0x1c7,umask=0x38 01 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 fpu_pipe_assignment.dual floating point Total number multi-pipe uOps assigned to all pipes event=0,umask=0xf0 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes fpu_pipe_assignment.dual3 floating point Total number multi-pipe uOps assigned to pipe 3 event=0,umask=0x80 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3 fpu_pipe_assignment.dual2 floating point Total number multi-pipe uOps assigned to pipe 2 event=0,umask=0x40 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2 fpu_pipe_assignment.dual1 floating point Total number multi-pipe uOps assigned to pipe 1 event=0,umask=0x20 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1 fpu_pipe_assignment.dual0 floating point Total number multi-pipe uOps assigned to pipe 0 event=0,umask=0x10 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0 fpu_pipe_assignment.total floating point Total number uOps assigned to all fpu pipes event=0,umask=0x0f 00 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipes fpu_pipe_assignment.total3 floating point Total number of fp uOps on pipe 3 event=0,umask=0x08 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total2 floating point Total number of fp uOps on pipe 2 event=0,umask=0x04 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fpu_pipe_assignment.total1 floating point Total number of fp uOps on pipe 1 event=0,umask=0x02 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fpu_pipe_assignment.total0 floating point Total number of fp uOps on pipe 0 event=0,umask=0x01 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0 fp_sched_empty floating point This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler event=0x1 00 fp_retx87_fp_ops.all floating point All Ops event=0x2,umask=0x07 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8 fp_retx87_fp_ops.div_sqr_r_ops floating point Divide and square root Ops event=0x2,umask=0x04 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Ops fp_retx87_fp_ops.mul_ops floating point Multiply Ops event=0x2,umask=0x02 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Ops fp_retx87_fp_ops.add_sub_ops floating point Add/subtract Ops event=0x2,umask=0x01 00 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops fp_ret_sse_avx_ops.all floating point All FLOPS event=0x3,umask=0xff 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.dp_mult_add_flops floating point Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS event=0x3,umask=0x80 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.dp_div_flops floating point Double precision divide/square root FLOPS event=0x3,umask=0x40 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPS fp_ret_sse_avx_ops.dp_mult_flops floating point Double precision multiply FLOPS event=0x3,umask=0x20 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPS fp_ret_sse_avx_ops.dp_add_sub_flops floating point Double precision add/subtract FLOPS event=0x3,umask=0x10 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPS fp_ret_sse_avx_ops.sp_mult_add_flops floating point Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS event=0x3,umask=0x08 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.sp_div_flops floating point Single-precision divide/square root FLOPS event=0x3,umask=0x04 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPS fp_ret_sse_avx_ops.sp_mult_flops floating point Single-precision multiply FLOPS event=0x3,umask=0x02 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPS fp_ret_sse_avx_ops.sp_add_sub_flops floating point Single-precision add/subtract FLOPS event=0x3,umask=0x01 00 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPS fp_num_mov_elim_scal_op.optimized floating point Number of Scalar Ops optimized event=0x4,umask=0x08 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimized fp_num_mov_elim_scal_op.opt_potential floating point Number of Ops that are candidates for optimization (have Z-bit either set or pass) event=0x4,umask=0x04 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass) fp_num_mov_elim_scal_op.sse_mov_ops_elim floating point Number of SSE Move Ops eliminated event=0x4,umask=0x02 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminated fp_num_mov_elim_scal_op.sse_mov_ops floating point Number of SSE Move Ops event=0x4,umask=0x01 00 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops fp_retired_ser_ops.x87_ctrl_ret floating point x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits event=0x5,umask=0x08 00 The number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing uOps retired event=0x5,umask=0x04 00 The number of serializing Ops retired. x87 bottom-executing uOps retired fp_retired_ser_ops.sse_ctrl_ret floating point SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits event=0x5,umask=0x02 00 The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits fp_retired_ser_ops.sse_bot_ret floating point SSE bottom-executing uOps retired event=0x5,umask=0x01 00 The number of serializing Ops retired. SSE bottom-executing uOps retired ls_locks.bus_lock memory Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type event=0x25,umask=0x01 00 ls_dispatch.ld_st_dispatch memory Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores event=0x29,umask=0x04 00 ls_dispatch.store_dispatch memory Counts the number of stores dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=0x02 00 ls_dispatch.ld_dispatch memory Counts the number of loads dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=0x01 00 ls_stlf memory Number of STLF hits event=0x35 00 ls_dc_accesses memory The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event event=0x40 00 ls_mab_alloc.dc_prefetcher memory LS MAB allocates by type - DC prefetcher event=0x41,umask=0x08 00 ls_mab_alloc.stores memory LS MAB allocates by type - stores event=0x41,umask=0x02 00 ls_mab_alloc.loads memory LS MAB allocates by type - loads event=0x41,umask=0x01 00 ls_l1_d_tlb_miss.all memory L1 DTLB Miss or Reload off all sizes event=0x45,umask=0xff 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss of a page of 1G size event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss of a page of 2M size event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss memory L1 DTLB Miss of a page of 32K size event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss of a page of 4K size event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB Reload of a page of 1G size event=0x45,umask=0x08 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB Reload of a page of 2M size event=0x45,umask=0x04 00 ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit memory L1 DTLB Reload of a page of 32K size event=0x45,umask=0x02 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB Reload of a page of 4K size event=0x45,umask=0x01 00 ls_tablewalker.iside memory Total Page Table Walks on I-side event=0x46,umask=0x0c 00 ls_tablewalker.ic_type1 memory Total Page Table Walks IC Type 1 event=0x46,umask=0x08 00 ls_tablewalker.ic_type0 memory Total Page Table Walks IC Type 0 event=0x46,umask=0x04 00 ls_tablewalker.dside memory Total Page Table Walks on D-side event=0x46,umask=0x03 00 ls_tablewalker.dc_type1 memory Total Page Table Walks DC Type 1 event=0x46,umask=0x02 00 ls_tablewalker.dc_type0 memory Total Page Table Walks DC Type 0 event=0x46,umask=0x01 00 ls_misal_accesses memory Misaligned loads event=0x47 00 ls_pref_instr_disp.prefetch_nta memory Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched event=0x4b,umask=0x04 00 ls_pref_instr_disp.store_prefetch_w memory Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched event=0x4b,umask=0x02 00 ls_pref_instr_disp.load_prefetch_w memory Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2 event=0x4b,umask=0x01 00 ls_inef_sw_pref.mab_mch_cnt memory The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer event=0x52,umask=0x02 00 ls_inef_sw_pref.data_pipe_sw_pf_dc_hit memory The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit event=0x52,umask=0x01 00 ls_not_halted_cyc memory Cycles not in Halt event=0x76 00 ic_oc_mode_switch.oc_ic_mode_switch other OC Mode Switch. OC to IC mode switch event=0x28a,umask=0x02 00 ic_oc_mode_switch.ic_oc_mode_switch other OC Mode Switch. IC to OC mode switch event=0x28a,umask=0x01 00 de_dis_dispatch_token_stalls0.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable event=0xaf,umask=0x40 00 de_dis_dispatch_token_stalls0.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x20 00 de_dis_dispatch_token_stalls0.alu_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable event=0xaf,umask=0x10 00 de_dis_dispatch_token_stalls0.alsq3_0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable event=0xaf,umask=0x08 00 de_dis_dispatch_token_stalls0.alsq3_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable event=0xaf,umask=0x04 00 de_dis_dispatch_token_stalls0.alsq2_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable event=0xaf,umask=0x02 00 de_dis_dispatch_token_stalls0.alsq1_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable event=0xaf,umask=0x01 00 all_dc_accesses recommended All L1 Data Cache Accesses event=0x29,umask=0x07 00 l2_cache_accesses_from_ic_misses recommended L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch) event=0x60,umask=0x10 00 l2_cache_accesses_from_dc_misses recommended L2 Cache Accesses from L1 Data Cache Misses (including prefetch) event=0x60,umask=0xc8 00 l2_cache_misses_from_ic_miss recommended L2 Cache Misses from L1 Instruction Cache Misses event=0x64,umask=0x01 00 l2_cache_misses_from_dc_misses recommended L2 Cache Misses from L1 Data Cache Misses event=0x64,umask=0x08 00 l2_cache_hits_from_ic_misses recommended L2 Cache Hits from L1 Instruction Cache Misses event=0x64,umask=0x06 00 l2_cache_hits_from_dc_misses recommended L2 Cache Hits from L1 Data Cache Misses event=0x64,umask=0x70 00 l2_cache_hits_from_l2_hwpf recommended L2 Cache Hits from L2 HWPF event=0x70,umask=0xff 00 l3_accesses recommended L3 Accesses event=0x4,umask=0xff 00 l3_misses recommended L3 Misses (includes Chg2X) event=0x4,umask=0x01 00 l2_itlb_misses recommended L2 ITLB Misses & Instruction page walks event=0x85,umask=0x07 00 l1_dtlb_misses recommended L1 DTLB Misses event=0x45,umask=0xff 00 l2_dtlb_misses recommended L2 DTLB Misses & Data page walks event=0x45,umask=0xf0 00 all_tlbs_flushed recommended All TLBs Flushed event=0x78,umask=0xdf 00 uops_dispatched recommended Micro-ops Dispatched event=0xaa,umask=0x03 00 sse_avx_stalls recommended Mixed SSE/AVX Stalls event=0xe,umask=0x0e 00 uops_retired recommended Micro-ops Retired event=0xc1 00 bp_l1_btb_correct branch L1 Branch Prediction Overrides Existing Prediction (speculative) event=0x8a 00 bp_l2_btb_correct branch L2 Branch Prediction Overrides Existing Prediction (speculative) event=0x8b 00 bp_l1_tlb_fetch_hit branch The number of instruction fetches that hit in the L1 ITLB event=0x94,umask=0xff 00 bp_l1_tlb_fetch_hit.if1g branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB page event=0x94,umask=0x04 00 bp_l1_tlb_fetch_hit.if2m branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB page event=0x94,umask=0x02 00 bp_l1_tlb_fetch_hit.if4k branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB page event=0x94,umask=0x01 00 bp_tlb_rel branch The number of ITLB reload requests event=0x99 00 bp_l1_tlb_miss_l2_tlb_miss cache The number of instruction fetches that miss in both the L1 and L2 TLBs event=0x85,umask=0xff 00 bp_l1_tlb_miss_l2_tlb_miss.if1g cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB page event=0x85,umask=0x04 00 bp_l1_tlb_miss_l2_tlb_miss.if2m cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB page event=0x85,umask=0x02 00 bp_l1_tlb_miss_l2_tlb_miss.if4k cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB page event=0x85,umask=0x01 00 ic_oc_mode_switch.oc_ic_mode_switch cache OC Mode Switch. OC to IC mode switch event=0x28a,umask=0x02 00 ic_oc_mode_switch.ic_oc_mode_switch cache OC Mode Switch. IC to OC mode switch event=0x28a,umask=0x01 00 ex_ret_cops core Retired Uops event=0xc1 00 The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8 ex_ret_cond_misp core Retired Conditional Branch Instructions Mispredicted event=0xd2 00 ex_ret_fus_brnch_inst core Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8 event=0x1d0 00 fpu_pipe_assignment.total floating point Total number of fp uOps event=0,umask=0x0f 00 Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS fpu_pipe_assignment.total3 floating point Total number uOps assigned to pipe 3 event=0,umask=0x08 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total2 floating point Total number uOps assigned to pipe 2 event=0,umask=0x04 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fpu_pipe_assignment.total1 floating point Total number uOps assigned to pipe 1 event=0,umask=0x02 00 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fp_ret_sse_avx_ops.all floating point All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=0x3,umask=0xff 00 fp_ret_sse_avx_ops.mac_flops floating point Multiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=0x3,umask=0x08 00 fp_ret_sse_avx_ops.div_flops floating point Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=0x3,umask=0x04 00 fp_ret_sse_avx_ops.mult_flops floating point Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=0x3,umask=0x02 00 fp_ret_sse_avx_ops.add_sub_flops floating point Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=0x3,umask=0x01 00 fp_num_mov_elim_scal_op.optimized floating point Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=0x4,umask=0x08 00 fp_num_mov_elim_scal_op.opt_potential floating point Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=0x4,umask=0x04 00 fp_num_mov_elim_scal_op.sse_mov_ops_elim floating point Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=0x4,umask=0x02 00 fp_num_mov_elim_scal_op.sse_mov_ops floating point Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=0x4,umask=0x01 00 fp_retired_ser_ops.sse_bot_ret floating point SSE bottom-executing uOps retired. The number of serializing Ops retired event=0x5,umask=0x08 00 fp_retired_ser_ops.sse_ctrl_ret floating point The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits event=0x5,umask=0x04 00 fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing uOps retired. The number of serializing Ops retired event=0x5,umask=0x02 00 fp_retired_ser_ops.x87_ctrl_ret floating point x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired event=0x5,umask=0x01 00 fp_disp_faults.ymm_spill_fault floating point Floating Point Dispatch Faults. YMM spill fault event=0xe,umask=0x08 00 fp_disp_faults.ymm_fill_fault floating point Floating Point Dispatch Faults. YMM fill fault event=0xe,umask=0x04 00 fp_disp_faults.xmm_fill_fault floating point Floating Point Dispatch Faults. XMM fill fault event=0xe,umask=0x02 00 fp_disp_faults.x87_fill_fault floating point Floating Point Dispatch Faults. x87 fill fault event=0xe,umask=0x01 00 ls_bad_status2.stli_other memory Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason event=0x24,umask=0x02 00 Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores ls_locks.spec_lock_hi_spec memory Retired lock instructions. High speculative cacheable lock speculation succeeded event=0x25,umask=0x08 00 ls_locks.spec_lock_lo_spec memory Retired lock instructions. Low speculative cacheable lock speculation succeeded event=0x25,umask=0x04 00 ls_locks.non_spec_lock memory Retired lock instructions. Non-speculative lock succeeded event=0x25,umask=0x02 00 ls_locks.bus_lock memory Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock event=0x25,umask=0x01 00 ls_ret_cl_flush memory Number of retired CLFLUSH instructions event=0x26 00 ls_ret_cpuid memory Number of retired CPUID instructions event=0x27 00 ls_dispatch.ld_st_dispatch memory Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address event=0x29,umask=0x04 00 ls_dispatch.store_dispatch memory Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=0x02 00 ls_dispatch.ld_dispatch memory Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=0x01 00 ls_smi_rx memory Number of SMIs received event=0x2b 00 ls_int_taken memory Number of interrupts taken event=0x2c 00 ls_rdtsc memory Number of reads of the TSC (RDTSC instructions). The count is speculative event=0x2d 00 ls_st_commit_cancel2.st_commit_cancel_wcb_full memory A non-cacheable store and the non-cacheable commit buffer is full event=0x37 00 ls_dc_accesses memory Number of accesses to the dcache for load/store references event=0x40 00 The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event ls_mab_alloc.dc_prefetcher memory LS MAB Allocates by Type. DC prefetcher event=0x41,umask=0x08 00 ls_mab_alloc.stores memory LS MAB Allocates by Type. Stores event=0x41,umask=0x02 00 ls_mab_alloc.loads memory LS MAB Allocates by Type. Loads event=0x41,umask=0x01 00 ls_refills_from_sys.ls_mabresp_rmt_dram memory Demand Data Cache Fills by Data Source. DRAM or IO from different die event=0x43,umask=0x40 00 ls_refills_from_sys.ls_mabresp_rmt_cache memory Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die event=0x43,umask=0x10 00 ls_refills_from_sys.ls_mabresp_lcl_dram memory Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die event=0x43,umask=0x08 00 ls_refills_from_sys.ls_mabresp_lcl_cache memory Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die event=0x43,umask=0x02 00 ls_refills_from_sys.ls_mabresp_lcl_l2 memory Demand Data Cache Fills by Data Source. Local L2 hit event=0x43,umask=0x01 00 ls_l1_d_tlb_miss.all memory All L1 DTLB Misses or Reloads event=0x45,umask=0xff 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB Miss. DTLB reload coalesced page miss event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB event=0x45,umask=0x08 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB event=0x45,umask=0x04 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB Miss. DTLB reload hit a coalesced page event=0x45,umask=0x02 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB event=0x45,umask=0x01 00 ls_pref_instr_disp memory Software Prefetch Instructions Dispatched (Speculative) event=0x4b,umask=0xff 00 ls_pref_instr_disp.prefetch_nta memory Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel event=0x4b,umask=0x04 00 ls_pref_instr_disp.prefetch_w memory Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW event=0x4b,umask=0x02 00 ls_pref_instr_disp.prefetch memory Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel event=0x4b,umask=0x01 00 ls_sw_pf_dc_fill.ls_mabresp_rmt_dram memory Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0x59,umask=0x40 00 ls_sw_pf_dc_fill.ls_mabresp_rmt_cache memory Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote) event=0x59,umask=0x10 00 ls_sw_pf_dc_fill.ls_mabresp_lcl_dram memory Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local) event=0x59,umask=0x08 00 ls_sw_pf_dc_fill.ls_mabresp_lcl_cache memory Software Prefetch Data Cache Fills by Data Source. From another cache (home node local) event=0x59,umask=0x02 00 ls_sw_pf_dc_fill.ls_mabresp_lcl_l2 memory Software Prefetch Data Cache Fills by Data Source. Local L2 hit event=0x59,umask=0x01 00 ls_hw_pf_dc_fill.ls_mabresp_rmt_dram memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0x5a,umask=0x40 00 ls_hw_pf_dc_fill.ls_mabresp_rmt_cache memory Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote) event=0x5a,umask=0x10 00 ls_hw_pf_dc_fill.ls_mabresp_lcl_dram memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local) event=0x5a,umask=0x08 00 ls_hw_pf_dc_fill.ls_mabresp_lcl_cache memory Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local) event=0x5a,umask=0x02 00 ls_hw_pf_dc_fill.ls_mabresp_lcl_l2 memory Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit event=0x5a,umask=0x01 00 ls_tlb_flush memory All TLB Flushes event=0x78 00 de_dis_uop_queue_empty_di0 other Cycles where the Micro-Op Queue is empty event=0xa9 00 de_dis_uops_from_decoder other Ops dispatched from either the decoders, OpCache or both event=0xaa,umask=0xff 00 de_dis_uops_from_decoder.opcache_dispatched other Count of dispatched Ops from OpCache event=0xaa,umask=0x02 00 de_dis_uops_from_decoder.decoder_dispatched other Count of dispatched Ops from Decoder event=0xaa,umask=0x01 00 de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops event=0xae,umask=0x80 00 de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP scheduler event=0xae,umask=0x40 00 de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination register event=0xae,umask=0x20 00 de_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stall event=0xae,umask=0x10 00 de_dis_dispatch_token_stalls1.int_sched_misc_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall event=0xae,umask=0x08 00 de_dis_dispatch_token_stalls1.store_queue_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semantics event=0xae,umask=0x04 00 de_dis_dispatch_token_stalls1.load_queue_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semantics event=0xae,umask=0x02 00 de_dis_dispatch_token_stalls1.int_phy_reg_file_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination register event=0xae,umask=0x01 00 de_dis_dispatch_token_stalls0.sc_agu_dispatch_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stall event=0xaf,umask=0x40 00 de_dis_dispatch_token_stalls0.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable event=0xaf,umask=0x20 00 de_dis_dispatch_token_stalls0.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x10 00 de_dis_dispatch_token_stalls0.alu_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable event=0xaf,umask=0x08 00 de_dis_dispatch_token_stalls0.alsq3_0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStall event=0xaf,umask=0x04 00 bp_dyn_ind_pred branch Dynamic Indirect Predictions event=0x8e 00 The number of times a branch used the indirect predictor to make a prediction bp_de_redirect branch Decode Redirects event=0x91 00 The number of times the instruction decoder overrides the predicted target bp_l1_tlb_fetch_hit.if1g branch The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size) event=0x94,umask=0x04 00 bp_l1_tlb_fetch_hit.if2m branch The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size) event=0x94,umask=0x02 00 bp_l1_tlb_fetch_hit.if4k branch The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size) event=0x94,umask=0x01 00 l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable event=0x64,umask=0x40 00 l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2 event=0x64,umask=0x20 00 l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses instead event=0x64,umask=0x08 00 l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2 event=0x64,umask=0x02 00 l2_cache_req_stat.ic_fill_miss cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss instead event=0x64,umask=0x01 00 l2_pf_miss_l2_l3 cache L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches event=0x72,umask=0xff 00 ic_cache_fill_l2 cache Instruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cache event=0x82 00 ic_cache_fill_sys cache Instruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cache event=0x83 00 bp_l1_tlb_miss_l2_tlb_hit cache L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84 00 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced page event=0x85,umask=0x08 00 bp_l1_tlb_miss_l2_tlb_miss.if1g cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G page event=0x85,umask=0x04 00 bp_l1_tlb_miss_l2_tlb_miss.if2m cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M page event=0x85,umask=0x02 00 bp_l1_tlb_miss_l2_tlb_miss.if4k cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K page event=0x85,umask=0x01 00 ic_tag_hit_miss.all_instruction_cache_accesses cache All Instruction Cache Accesses. Counts various IC tag related hit and miss events event=0x18e,umask=0x1f 00 ic_tag_hit_miss.instruction_cache_miss cache Instruction Cache Miss. Counts various IC tag related hit and miss events event=0x18e,umask=0x18 00 ic_tag_hit_miss.instruction_cache_hit cache Instruction Cache Hit. Counts various IC tag related hit and miss events event=0x18e,umask=0x07 00 op_cache_hit_miss.all_op_cache_accesses cache All Op Cache accesses. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=0x07 00 op_cache_hit_miss.op_cache_miss cache Op Cache Miss. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=0x04 00 op_cache_hit_miss.op_cache_hit cache Op Cache Hit. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=0x03 00 l3_lookup_state.all_l3_req_typs cache All L3 Request Types. All L3 cache Requests event=0x4,umask=0xff 00 xi_sys_fill_latency cache L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask event=0x90 00 xi_ccx_sdp_req1 cache L3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting event=0x9a,umask=0xff 00 ex_ret_ops core Retired Ops. Use macro_ops_retired instead event=0xc1 00 The number of macro-ops retired ex_ret_brn_misp core Retired Branch Instructions Mispredicted event=0xc3 00 The number of retired branch instructions, that were mispredicted ex_ret_brn_ind_misp core Retired Indirect Branch Instructions Mispredicted event=0xca 00 The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted ex_ret_mmx_fp_instr.sse_instr core SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) event=0xcb,umask=0x04 00 The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS ex_ret_ind_brch_instr core Retired Indirect Branch Instructions. The number of indirect branches retired event=0xcc 00 ex_ret_msprd_brnch_instr_dir_msmtch core Retired Mispredicted Branch Instructions due to Direction Mismatch event=0x1c7 00 The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch ex_ret_fused_instr core Counts retired Fused Instructions event=0x1d0 00 fp_ret_sse_avx_ops.mac_flops floating point Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=0x3,umask=0x08 00 fp_ret_sse_avx_ops.div_flops floating point Divide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=0x3,umask=0x04 00 fp_ret_sse_avx_ops.mult_flops floating point Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=0x3,umask=0x02 00 fp_ret_sse_avx_ops.add_sub_flops floating point Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=0x3,umask=0x01 00 fp_retired_ser_ops.sse_bot_ret floating point SSE/AVX bottom-executing ops retired. The number of serializing Ops retired event=0x5,umask=0x08 00 fp_retired_ser_ops.sse_ctrl_ret floating point SSE/AVX control word mispredict traps. The number of serializing Ops retired event=0x5,umask=0x04 00 fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing ops retired. The number of serializing Ops retired event=0x5,umask=0x02 00 ls_locks.bus_lock memory Retired lock instructions. Comparable to legacy bus lock event=0x25,umask=0x01 00 ls_ret_cl_flush memory The number of retired CLFLUSH instructions. This is a non-speculative event event=0x26 00 ls_ret_cpuid memory The number of CPUID instructions retired event=0x27 00 ls_dispatch.ld_st_dispatch memory Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=0x04 00 ls_dispatch.store_dispatch memory Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=0x02 00 ls_dispatch.ld_dispatch memory Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=0x01 00 ls_smi_rx memory Counts the number of SMIs received event=0x2b 00 ls_int_taken memory Counts the number of interrupts taken event=0x2c 00 ls_st_commit_cancel2.st_commit_cancel_wcb_full memory A non-cacheable store and the non-cacheable commit buffer is full event=0x37,umask=0x01 00 ls_mab_alloc.all_allocations memory All Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x7f 00 ls_mab_alloc.hardware_prefetcher_allocations memory Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x40 00 ls_mab_alloc.load_store_allocations memory Load Store Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x3f 00 ls_dmnd_fills_from_sys.mem_io_remote memory Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x43,umask=0x40 00 ls_dmnd_fills_from_sys.ext_cache_remote memory Demand Data Cache Fills by Data Source. From CCX Cache in different Node event=0x43,umask=0x10 00 ls_dmnd_fills_from_sys.mem_io_local memory Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x43,umask=0x08 00 ls_dmnd_fills_from_sys.ext_cache_local memory Demand Data Cache Fills by Data Source. From cache of different CCX in same node event=0x43,umask=0x04 00 ls_dmnd_fills_from_sys.int_cache memory Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x43,umask=0x02 00 ls_dmnd_fills_from_sys.lcl_l2 memory Demand Data Cache Fills by Data Source. From Local L2 to the core event=0x43,umask=0x01 00 ls_any_fills_from_sys.mem_io_remote memory Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x44,umask=0x40 00 ls_any_fills_from_sys.ext_cache_remote memory Any Data Cache Fills by Data Source. From CCX Cache in different Node event=0x44,umask=0x10 00 ls_any_fills_from_sys.mem_io_local memory Any Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x44,umask=0x08 00 ls_any_fills_from_sys.ext_cache_local memory Any Data Cache Fills by Data Source. From cache of different CCX in same node event=0x44,umask=0x04 00 ls_any_fills_from_sys.int_cache memory Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x44,umask=0x02 00 ls_any_fills_from_sys.lcl_l2 memory Any Data Cache Fills by Data Source. From Local L2 to the core event=0x44,umask=0x01 00 ls_l1_d_tlb_miss.all memory All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead event=0x45,umask=0xff 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB event=0x45,umask=0x02 00 ls_misal_loads.ma4k memory The number of 4KB misaligned (i.e., page crossing) loads event=0x47,umask=0x02 00 ls_misal_loads.ma64 memory The number of 64B misaligned (i.e., cacheline crossing) loads event=0x47,umask=0x01 00 ls_pref_instr_disp.prefetch_w memory Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW event=0x4b,umask=0x02 00 ls_pref_instr_disp.prefetch memory Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel event=0x4b,umask=0x01 00 ls_sw_pf_dc_fills.mem_io_remote memory Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x59,umask=0x40 00 ls_sw_pf_dc_fills.ext_cache_remote memory Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node event=0x59,umask=0x10 00 ls_sw_pf_dc_fills.mem_io_local memory Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x59,umask=0x08 00 ls_sw_pf_dc_fills.ext_cache_local memory Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node event=0x59,umask=0x04 00 ls_sw_pf_dc_fills.int_cache memory Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x59,umask=0x02 00 ls_sw_pf_dc_fills.lcl_l2 memory Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core event=0x59,umask=0x01 00 ls_hw_pf_dc_fills.mem_io_remote memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x5a,umask=0x40 00 ls_hw_pf_dc_fills.ext_cache_remote memory Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node event=0x5a,umask=0x10 00 ls_hw_pf_dc_fills.mem_io_local memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x5a,umask=0x08 00 ls_hw_pf_dc_fills.ext_cache_local memory Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node event=0x5a,umask=0x04 00 ls_hw_pf_dc_fills.int_cache memory Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x5a,umask=0x02 00 ls_hw_pf_dc_fills.lcl_l2 memory Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core event=0x5a,umask=0x01 00 ls_alloc_mab_count memory Count of Allocated Mabs event=0x5f 00 This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events] ls_tlb_flush.all_tlb_flushes memory All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead event=0x78,umask=0xff 00 de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch other Any Integer dispatch. Types of Oops Dispatched from Decoder event=0xab,umask=0x08 00 de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch other Any FP dispatch. Types of Oops Dispatched from Decoder event=0xab,umask=0x04 00 de_dis_dispatch_token_stalls1.fp_flush_recovery_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stall event=0xae,umask=0x80 00 de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP scheduler event=0xae,umask=0x40 00 de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination register event=0xae,umask=0x20 00 de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stall event=0xae,umask=0x10 00 de_dis_dispatch_token_stalls1.store_queue_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semantics event=0xae,umask=0x04 00 de_dis_dispatch_token_stalls1.load_queue_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semantics event=0xae,umask=0x02 00 de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register event=0xae,umask=0x01 00 de_dis_dispatch_token_stalls2.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens available event=0xaf,umask=0x20 00 de_dis_dispatch_token_stalls2.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x10 00 de_dis_dispatch_token_stalls2.int_sch3_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 available event=0xaf,umask=0x08 00 de_dis_dispatch_token_stalls2.int_sch2_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 available event=0xaf,umask=0x04 00 de_dis_dispatch_token_stalls2.int_sch1_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 available event=0xaf,umask=0x02 00 de_dis_dispatch_token_stalls2.int_sch0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 available event=0xaf,umask=0x01 00 all_data_cache_accesses recommended All L1 Data Cache Accesses event=0x29,umask=0x07 00 l2_cache_accesses_from_dc_misses recommended L2 Cache Accesses from L1 Data Cache Misses (including prefetch) event=0x60,umask=0xe8 00 l2_cache_hits_from_dc_misses recommended L2 Cache Hits from L1 Data Cache Misses event=0x64,umask=0xf0 00 l2_cache_hits_from_l2_hwpf recommended L2 Cache Hits from L2 Cache HWPF event=0x70,umask=0xff 00 l3_cache_accesses recommended L3 Cache Accesses event=0x4,umask=0xff 00 l3_misses recommended L3 Misses (includes cacheline state change requests) event=0x4,umask=0x01 00 l1_data_cache_fills_from_memory recommended L1 Data Cache Fills: From Memory event=0x44,umask=0x48 00 l1_data_cache_fills_from_remote_node recommended L1 Data Cache Fills: From Remote Node event=0x44,umask=0x50 00 l1_data_cache_fills_from_within_same_ccx recommended L1 Data Cache Fills: From within same CCX event=0x44,umask=0x03 00 l1_data_cache_fills_from_external_ccx_cache recommended L1 Data Cache Fills: From External CCX Cache event=0x44,umask=0x14 00 l1_data_cache_fills_all recommended L1 Data Cache Fills: All event=0x44,umask=0xff 00 all_tlbs_flushed recommended All TLBs Flushed event=0x78,umask=0xff 00 macro_ops_retired recommended Macro-ops Retired event=0xc1 00 bp_l2_btb_correct branch L2 branch prediction overrides existing prediction (speculative) event=0x8b 00 bp_dyn_ind_pred branch Dynamic indirect predictions (branch used the indirect predictor to make a prediction) event=0x8e 00 bp_de_redirect branch Instruction decoder corrects the predicted target and resteers the branch predictor event=0x91 00 ex_ret_brn branch Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc2 00 ex_ret_brn_misp branch Retired branch instructions mispredicted event=0xc3 00 ex_ret_brn_tkn branch Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc4 00 ex_ret_brn_tkn_misp branch Retired taken branch instructions mispredicted event=0xc5 00 ex_ret_brn_far branch Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction event=0xc6 00 ex_ret_near_ret branch Retired near returns (RET or RET Iw) event=0xc8 00 ex_ret_near_ret_mispred branch Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xc9 00 ex_ret_brn_ind_misp branch Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xca 00 ex_ret_ind_brch_instr branch Retired indirect branch instructions event=0xcc 00 ex_ret_cond branch Retired conditional branch instructions event=0xd1 00 ex_ret_msprd_brnch_instr_dir_msmtch branch Retired branch instructions mispredicted due to direction mismatch event=0x1c7 00 ex_ret_uncond_brnch_instr_mispred branch Retired unconditional indirect branch instructions mispredicted event=0x1c8 00 ex_ret_uncond_brnch_instr branch Retired unconditional branch instructions event=0x1c9 00 ls_mab_alloc.load_store_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations event=0x41,umask=0x3f 00 ls_mab_alloc.hardware_prefetcher_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations event=0x41,umask=0x40 00 ls_mab_alloc.all_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations event=0x41,umask=0x7f 00 ls_dmnd_fills_from_sys.local_l2 cache Demand data cache fills from local L2 cache event=0x43,umask=0x01 00 ls_dmnd_fills_from_sys.local_ccx cache Demand data cache fills from L3 cache or different L2 cache in the same CCX event=0x43,umask=0x02 00 ls_dmnd_fills_from_sys.near_cache cache Demand data cache fills from cache of another CCX when the address was in the same NUMA node event=0x43,umask=0x04 00 ls_dmnd_fills_from_sys.dram_io_near cache Demand data cache fills from either DRAM or MMIO in the same NUMA node event=0x43,umask=0x08 00 ls_dmnd_fills_from_sys.far_cache cache Demand data cache fills from cache of another CCX when the address was in a different NUMA node event=0x43,umask=0x10 00 ls_dmnd_fills_from_sys.dram_io_far cache Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x43,umask=0x40 00 ls_dmnd_fills_from_sys.alternate_memories cache Demand data cache fills from extension memory event=0x43,umask=0x80 00 ls_dmnd_fills_from_sys.all cache Demand data cache fills from all types of data sources event=0x43,umask=0xff 00 ls_any_fills_from_sys.local_l2 cache Any data cache fills from local L2 cache event=0x44,umask=0x01 00 ls_any_fills_from_sys.local_ccx cache Any data cache fills from L3 cache or different L2 cache in the same CCX event=0x44,umask=0x02 00 ls_any_fills_from_sys.local_all cache Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX event=0x44,umask=0x03 00 ls_any_fills_from_sys.near_cache cache Any data cache fills from cache of another CCX when the address was in the same NUMA node event=0x44,umask=0x04 00 ls_any_fills_from_sys.dram_io_near cache Any data cache fills from either DRAM or MMIO in the same NUMA node event=0x44,umask=0x08 00 ls_any_fills_from_sys.far_cache cache Any data cache fills from cache of another CCX when the address was in a different NUMA node event=0x44,umask=0x10 00 ls_any_fills_from_sys.remote_cache cache Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x44,umask=0x14 00 ls_any_fills_from_sys.dram_io_far cache Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x44,umask=0x40 00 ls_any_fills_from_sys.dram_io_all cache Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48 00 ls_any_fills_from_sys.far_all cache Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x44,umask=0x50 00 ls_any_fills_from_sys.all_dram_io cache Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48 00 ls_any_fills_from_sys.alternate_memories cache Any data cache fills from extension memory event=0x44,umask=0x80 00 ls_any_fills_from_sys.all cache Any data cache fills from all types of data sources event=0x44,umask=0xff 00 ls_pref_instr_disp.prefetch cache Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2) event=0x4b,umask=0x01 00 ls_pref_instr_disp.prefetch_w cache Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable) event=0x4b,umask=0x02 00 ls_pref_instr_disp.prefetch_nta cache Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access) event=0x4b,umask=0x04 00 ls_pref_instr_disp.all cache Software prefetch instructions dispatched (speculative) of all types event=0x4b,umask=0x07 00 ls_inef_sw_pref.data_pipe_sw_pf_dc_hit cache Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit event=0x52,umask=0x01 00 ls_inef_sw_pref.mab_mch_cnt cache Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB) event=0x52,umask=0x02 00 ls_inef_sw_pref.all cache event=0x52,umask=0x03 00 ls_sw_pf_dc_fills.local_l2 cache Software prefetch data cache fills from local L2 cache event=0x59,umask=0x01 00 ls_sw_pf_dc_fills.local_ccx cache Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x59,umask=0x02 00 ls_sw_pf_dc_fills.near_cache cache Software prefetch data cache fills from cache of another CCX in the same NUMA node event=0x59,umask=0x04 00 ls_sw_pf_dc_fills.dram_io_near cache Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x59,umask=0x08 00 ls_sw_pf_dc_fills.far_cache cache Software prefetch data cache fills from cache of another CCX in a different NUMA node event=0x59,umask=0x10 00 ls_sw_pf_dc_fills.dram_io_far cache Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x59,umask=0x40 00 ls_sw_pf_dc_fills.alternate_memories cache Software prefetch data cache fills from extension memory event=0x59,umask=0x80 00 ls_sw_pf_dc_fills.all cache Software prefetch data cache fills from all types of data sources event=0x59,umask=0xdf 00 ls_hw_pf_dc_fills.local_l2 cache Hardware prefetch data cache fills from local L2 cache event=0x5a,umask=0x01 00 ls_hw_pf_dc_fills.local_ccx cache Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x5a,umask=0x02 00 ls_hw_pf_dc_fills.near_cache cache Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node event=0x5a,umask=0x04 00 ls_hw_pf_dc_fills.dram_io_near cache Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x5a,umask=0x08 00 ls_hw_pf_dc_fills.far_cache cache Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node event=0x5a,umask=0x10 00 ls_hw_pf_dc_fills.dram_io_far cache Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x5a,umask=0x40 00 ls_hw_pf_dc_fills.alternate_memories cache Hardware prefetch data cache fills from extension memory event=0x5a,umask=0x80 00 ls_hw_pf_dc_fills.all cache Hardware prefetch data cache fills from all types of data sources event=0x5a,umask=0xdf 00 ls_alloc_mab_count cache In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle event=0x5f 00 l2_request_g1.group2 cache L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks) event=0x60,umask=0x01 00 l2_request_g1.l2_hw_pf cache L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss) event=0x60,umask=0x02 00 l2_request_g1.prefetch_l2_cmd cache L2 cache requests: prefetch directly into L2 event=0x60,umask=0x04 00 l2_request_g1.change_to_x cache L2 cache requests: data cache state change to writable, check L2 for current state event=0x60,umask=0x08 00 l2_request_g1.cacheable_ic_read cache L2 cache requests: instruction cache reads event=0x60,umask=0x10 00 l2_request_g1.ls_rd_blk_c_s cache L2 cache requests: data cache shared reads event=0x60,umask=0x20 00 l2_request_g1.rd_blk_x cache L2 cache requests: data cache stores event=0x60,umask=0x40 00 l2_request_g1.rd_blk_l cache L2 cache requests: data cache reads including hardware and software prefetch event=0x60,umask=0x80 00 l2_request_g1.all_dc cache L2 cache requests of common types from L1 data cache (including prefetches) event=0x60,umask=0xe8 00 l2_request_g1.all_no_prefetch cache L2 cache requests of common types not including prefetches event=0x60,umask=0xf9 00 l2_request_g1.all cache L2 cache requests of all types event=0x60,umask=0xff 00 l2_cache_req_stat.ic_fill_miss cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2 event=0x64,umask=0x01 00 l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2 event=0x64,umask=0x02 00 l2_cache_req_stat.ic_fill_hit_x cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2 event=0x64,umask=0x04 00 l2_cache_req_stat.ic_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache hits event=0x64,umask=0x06 00 l2_cache_req_stat.ic_access_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache access event=0x64,umask=0x07 00 l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2 event=0x64,umask=0x08 00 l2_cache_req_stat.ic_dc_miss_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses event=0x64,umask=0x09 00 l2_cache_req_stat.ls_rd_blk_x cache Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2 event=0x64,umask=0x10 00 l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2 event=0x64,umask=0x20 00 l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2 event=0x64,umask=0x40 00 l2_cache_req_stat.ls_rd_blk_cs cache Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2 event=0x64,umask=0x80 00 l2_cache_req_stat.dc_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache hits event=0x64,umask=0xf0 00 l2_cache_req_stat.ic_dc_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits event=0x64,umask=0xf6 00 l2_cache_req_stat.dc_access_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache access event=0x64,umask=0xf8 00 l2_cache_req_stat.all cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access event=0x64,umask=0xff 00 l2_pf_hit_l2.l2_stream cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache) event=0x70,umask=0x01 00 l2_pf_hit_l2.l2_next_line cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache) event=0x70,umask=0x02 00 l2_pf_hit_l2.l2_up_down cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x70,umask=0x04 00 l2_pf_hit_l2.l2_burst cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x70,umask=0x08 00 l2_pf_hit_l2.l2_stride cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous) event=0x70,umask=0x10 00 l2_pf_hit_l2.l1_stream cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache) event=0x70,umask=0x20 00 l2_pf_hit_l2.l1_stride cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x70,umask=0x40 00 l2_pf_hit_l2.l1_region cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x70,umask=0x80 00 l2_pf_hit_l2.all cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all types event=0x70,umask=0xff 00 l2_pf_miss_l2_hit_l3.l2_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache) event=0x71,umask=0x01 00 l2_pf_miss_l2_hit_l3.l2_next_line cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache) event=0x71,umask=0x02 00 l2_pf_miss_l2_hit_l3.l2_up_down cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x71,umask=0x04 00 l2_pf_miss_l2_hit_l3.l2_burst cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x71,umask=0x08 00 l2_pf_miss_l2_hit_l3.l2_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) event=0x71,umask=0x10 00 l2_pf_miss_l2_hit_l3.l1_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache) event=0x71,umask=0x20 00 l2_pf_miss_l2_hit_l3.l1_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x71,umask=0x40 00 l2_pf_miss_l2_hit_l3.l1_region cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x71,umask=0x80 00 l2_pf_miss_l2_hit_l3.all cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all types event=0x71,umask=0xff 00 l2_pf_miss_l2_l3.l2_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache) event=0x72,umask=0x01 00 l2_pf_miss_l2_l3.l2_next_line cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache) event=0x72,umask=0x02 00 l2_pf_miss_l2_l3.l2_up_down cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x72,umask=0x04 00 l2_pf_miss_l2_l3.l2_burst cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x72,umask=0x08 00 l2_pf_miss_l2_l3.l2_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) event=0x72,umask=0x10 00 l2_pf_miss_l2_l3.l1_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache) event=0x72,umask=0x20 00 l2_pf_miss_l2_l3.l1_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x72,umask=0x40 00 l2_pf_miss_l2_l3.l1_region cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x72,umask=0x80 00 l2_pf_miss_l2_l3.all cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all types event=0x72,umask=0xff 00 ic_cache_fill_l2 cache Instruction cache lines (64 bytes) fulfilled from the L2 cache event=0x82 00 ic_cache_fill_sys cache Instruction cache lines (64 bytes) fulfilled from system memory or another cache event=0x83 00 ic_tag_hit_miss.instruction_cache_hit cache Instruction cache hits event=0x18e,umask=0x07 00 ic_tag_hit_miss.instruction_cache_miss cache Instruction cache misses event=0x18e,umask=0x18 00 ic_tag_hit_miss.all_instruction_cache_accesses cache Instruction cache accesses of all types event=0x18e,umask=0x1f 00 op_cache_hit_miss.op_cache_hit cache Op cache hits event=0x28f,umask=0x03 00 op_cache_hit_miss.op_cache_miss cache Op cache misses event=0x28f,umask=0x04 00 op_cache_hit_miss.all_op_cache_accesses cache Op cache accesses of all types event=0x28f,umask=0x07 00 l3_lookup_state.l3_miss cache L3 cache misses event=0x4,umask=0x01 00 l3_lookup_state.l3_hit cache L3 cache hits event=0x4,umask=0xfe 00 l3_lookup_state.all_coherent_accesses_to_l3 cache L3 cache requests for all coherent accesses event=0x4,umask=0xff 00 l3_xi_sampled_latency.dram_near cache Average sampled latency when data is sourced from DRAM in the same NUMA node event=0xac,umask=0x01,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency.dram_far cache Average sampled latency when data is sourced from DRAM in a different NUMA node event=0xac,umask=0x02,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency.near_cache cache Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node event=0xac,umask=0x04,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency.far_cache cache Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node event=0xac,umask=0x08,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency.ext_near cache Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node event=0xac,umask=0x10,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency.ext_far cache Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node event=0xac,umask=0x20,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency.all cache Average sampled latency from all data sources event=0xac,umask=0x3f,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency_requests.dram_near cache L3 cache fill requests sourced from DRAM in the same NUMA node event=0xad,umask=0x01,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency_requests.dram_far cache L3 cache fill requests sourced from DRAM in a different NUMA node event=0xad,umask=0x02,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency_requests.near_cache cache L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node event=0xad,umask=0x04,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency_requests.far_cache cache L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node event=0xad,umask=0x08,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency_requests.ext_near cache L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node event=0xad,umask=0x10,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency_requests.ext_far cache L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node event=0xad,umask=0x20,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 l3_xi_sampled_latency_requests.all cache L3 cache fill requests sourced from all data sources event=0xad,umask=0x3f,enallcores=0x1,enallslices=0x1,sliceid=0x3,threadmask=0x3 00 ls_locks.bus_lock core Retired Lock instructions which caused a bus lock event=0x25,umask=0x01 00 ls_ret_cl_flush core Retired CLFLUSH instructions event=0x26 00 ls_ret_cpuid core Retired CPUID instructions event=0x27 00 ls_smi_rx core SMIs received event=0x2b 00 ls_int_taken core Interrupts taken event=0x2c 00 ls_not_halted_cyc core Core cycles not in halt event=0x76 00 ex_ret_instr core Retired instructions event=0xc0 00 ex_ret_ops core Retired macro-ops event=0xc1 00 ex_div_busy core Number of cycles the divider is busy event=0xd3 00 ex_div_count core Divide ops executed event=0xd4 00 ex_no_retire.empty core Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects) event=0xd6,umask=0x01 00 ex_no_retire.not_complete core Cycles with no retire while the oldest op is waiting to be executed event=0xd6,umask=0x02 00 ex_no_retire.other core Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.) event=0xd6,umask=0x08 00 ex_no_retire.thread_not_selected core Cycles with no retire because thread arbitration did not select the thread event=0xd6,umask=0x10 00 ex_no_retire.load_not_complete core Cycles with no retire while the oldest op is waiting for load data event=0xd6,umask=0xa2 00 ex_no_retire.all core Cycles with no retire for any reason event=0xd6,umask=0x1b 00 ls_not_halted_p0_cyc.p0_freq_cyc core Reference cycles (P0 frequency) not in halt event=0x120,umask=0x1 00 ex_ret_ucode_instr core Retired microcoded instructions event=0x1c1 00 ex_ret_ucode_ops core Retired microcode ops event=0x1c2 00 ex_tagged_ibs_ops.ibs_tagged_ops core Ops tagged by IBS event=0x1cf,umask=0x01 00 ex_tagged_ibs_ops.ibs_tagged_ops_ret core Ops tagged by IBS that retired event=0x1cf,umask=0x02 00 ex_ret_fused_instr core Retired fused instructions event=0x1d0 00 local_processor_read_data_beats_cs0 data fabric event=0x1f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 0 local_processor_read_data_beats_cs1 data fabric event=0x5f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 1 local_processor_read_data_beats_cs2 data fabric event=0x9f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 2 local_processor_read_data_beats_cs3 data fabric event=0xdf,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 3 local_processor_read_data_beats_cs4 data fabric event=0x11f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 4 local_processor_read_data_beats_cs5 data fabric event=0x15f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 5 local_processor_read_data_beats_cs6 data fabric event=0x19f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 6 local_processor_read_data_beats_cs7 data fabric event=0x1df,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_read_data_beats_cs8 data fabric event=0x21f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 8 local_processor_read_data_beats_cs9 data fabric event=0x25f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 9 local_processor_read_data_beats_cs10 data fabric event=0x29f,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 10 local_processor_read_data_beats_cs11 data fabric event=0x2df,umask=0x7fe 01 Read data beats (64 bytes) for local processor at Coherent Station (CS) 11 local_processor_write_data_beats_cs0 data fabric event=0x1f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 0 local_processor_write_data_beats_cs1 data fabric event=0x5f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 1 local_processor_write_data_beats_cs2 data fabric event=0x9f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 2 local_processor_write_data_beats_cs3 data fabric event=0xdf,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 3 local_processor_write_data_beats_cs4 data fabric event=0x11f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 4 local_processor_write_data_beats_cs5 data fabric event=0x15f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 5 local_processor_write_data_beats_cs6 data fabric event=0x19f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 6 local_processor_write_data_beats_cs7 data fabric event=0x1df,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_write_data_beats_cs8 data fabric event=0x21f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 8 local_processor_write_data_beats_cs9 data fabric event=0x25f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 9 local_processor_write_data_beats_cs10 data fabric event=0x29f,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 10 local_processor_write_data_beats_cs11 data fabric event=0x2df,umask=0x7ff 01 Write data beats (64 bytes) for local processor at Coherent Station (CS) 11 remote_processor_read_data_beats_cs0 data fabric event=0x1f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 0 remote_processor_read_data_beats_cs1 data fabric event=0x5f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_read_data_beats_cs2 data fabric event=0x9f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 2 remote_processor_read_data_beats_cs3 data fabric event=0xdf,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 3 remote_processor_read_data_beats_cs4 data fabric event=0x11f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 4 remote_processor_read_data_beats_cs5 data fabric event=0x15f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 5 remote_processor_read_data_beats_cs6 data fabric event=0x19f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_read_data_beats_cs7 data fabric event=0x1df,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 7 remote_processor_read_data_beats_cs8 data fabric event=0x21f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 8 remote_processor_read_data_beats_cs9 data fabric event=0x25f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 9 remote_processor_read_data_beats_cs10 data fabric event=0x29f,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 10 remote_processor_read_data_beats_cs11 data fabric event=0x2df,umask=0xbfe 01 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 11 remote_processor_write_data_beats_cs0 data fabric event=0x1f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 0 remote_processor_write_data_beats_cs1 data fabric event=0x5f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_write_data_beats_cs2 data fabric event=0x9f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 2 remote_processor_write_data_beats_cs3 data fabric event=0xdf,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 3 remote_processor_write_data_beats_cs4 data fabric event=0x11f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 4 remote_processor_write_data_beats_cs5 data fabric event=0x15f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 5 remote_processor_write_data_beats_cs6 data fabric event=0x19f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_write_data_beats_cs7 data fabric event=0x1df,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 7 remote_processor_write_data_beats_cs8 data fabric event=0x21f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 8 remote_processor_write_data_beats_cs9 data fabric event=0x25f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 9 remote_processor_write_data_beats_cs10 data fabric event=0x29f,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 10 remote_processor_write_data_beats_cs11 data fabric event=0x2df,umask=0xbff 01 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 11 local_socket_upstream_read_beats_iom0 data fabric event=0x81f,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 local_socket_upstream_read_beats_iom1 data fabric event=0x85f,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 local_socket_upstream_read_beats_iom2 data fabric event=0x89f,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 local_socket_upstream_read_beats_iom3 data fabric event=0x8df,umask=0x7fe 01 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 local_socket_upstream_write_beats_iom0 data fabric event=0x81f,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 local_socket_upstream_write_beats_iom1 data fabric event=0x85f,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 local_socket_upstream_write_beats_iom2 data fabric event=0x89f,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 local_socket_upstream_write_beats_iom3 data fabric event=0x8df,umask=0x7ff 01 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 remote_socket_upstream_read_beats_iom0 data fabric event=0x81f,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 remote_socket_upstream_read_beats_iom1 data fabric event=0x85f,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 remote_socket_upstream_read_beats_iom2 data fabric event=0x89f,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 remote_socket_upstream_read_beats_iom3 data fabric event=0x8df,umask=0xbfe 01 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 remote_socket_upstream_write_beats_iom0 data fabric event=0x81f,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 remote_socket_upstream_write_beats_iom1 data fabric event=0x85f,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 remote_socket_upstream_write_beats_iom2 data fabric event=0x89f,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 remote_socket_upstream_write_beats_iom3 data fabric event=0x8df,umask=0xbff 01 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 local_socket_inf0_inbound_data_beats_ccm0 data fabric event=0x41e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 0 local_socket_inf0_inbound_data_beats_ccm1 data fabric event=0x45e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 1 local_socket_inf0_inbound_data_beats_ccm2 data fabric event=0x49e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 2 local_socket_inf0_inbound_data_beats_ccm3 data fabric event=0x4de,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 3 local_socket_inf0_inbound_data_beats_ccm4 data fabric event=0x51e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 4 local_socket_inf0_inbound_data_beats_ccm5 data fabric event=0x55e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf0_inbound_data_beats_ccm6 data fabric event=0x59e,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 6 local_socket_inf0_inbound_data_beats_ccm7 data fabric event=0x5de,umask=0x7fe 01 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 7 local_socket_inf1_inbound_data_beats_ccm0 data fabric event=0x41f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 0 local_socket_inf1_inbound_data_beats_ccm1 data fabric event=0x45f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 1 local_socket_inf1_inbound_data_beats_ccm2 data fabric event=0x49f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 2 local_socket_inf1_inbound_data_beats_ccm3 data fabric event=0x4df,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 3 local_socket_inf1_inbound_data_beats_ccm4 data fabric event=0x51f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 4 local_socket_inf1_inbound_data_beats_ccm5 data fabric event=0x55f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf1_inbound_data_beats_ccm6 data fabric event=0x59f,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 6 local_socket_inf1_inbound_data_beats_ccm7 data fabric event=0x5df,umask=0x7fe 01 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 7 local_socket_inf0_outbound_data_beats_ccm0 data fabric event=0x41e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 0 local_socket_inf0_outbound_data_beats_ccm1 data fabric event=0x45e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 1 local_socket_inf0_outbound_data_beats_ccm2 data fabric event=0x49e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 2 local_socket_inf0_outbound_data_beats_ccm3 data fabric event=0x4de,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 3 local_socket_inf0_outbound_data_beats_ccm4 data fabric event=0x51e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 4 local_socket_inf0_outbound_data_beats_ccm5 data fabric event=0x55e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 5 local_socket_inf0_outbound_data_beats_ccm6 data fabric event=0x59e,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 6 local_socket_inf0_outbound_data_beats_ccm7 data fabric event=0x5de,umask=0x7ff 01 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 7 local_socket_inf1_outbound_data_beats_ccm0 data fabric event=0x41f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 0 local_socket_inf1_outbound_data_beats_ccm1 data fabric event=0x45f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 1 local_socket_inf1_outbound_data_beats_ccm2 data fabric event=0x49f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 2 local_socket_inf1_outbound_data_beats_ccm3 data fabric event=0x4df,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 3 local_socket_inf1_outbound_data_beats_ccm4 data fabric event=0x51f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 4 local_socket_inf1_outbound_data_beats_ccm5 data fabric event=0x55f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 5 local_socket_inf1_outbound_data_beats_ccm6 data fabric event=0x59f,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 6 local_socket_inf1_outbound_data_beats_ccm7 data fabric event=0x5df,umask=0x7ff 01 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 7 remote_socket_inf0_inbound_data_beats_ccm0 data fabric event=0x41e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 0 remote_socket_inf0_inbound_data_beats_ccm1 data fabric event=0x45e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 1 remote_socket_inf0_inbound_data_beats_ccm2 data fabric event=0x49e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 2 remote_socket_inf0_inbound_data_beats_ccm3 data fabric event=0x4de,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 3 remote_socket_inf0_inbound_data_beats_ccm4 data fabric event=0x51e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf0_inbound_data_beats_ccm5 data fabric event=0x55e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 5 remote_socket_inf0_inbound_data_beats_ccm6 data fabric event=0x59e,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 6 remote_socket_inf0_inbound_data_beats_ccm7 data fabric event=0x5de,umask=0xbfe 01 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 7 remote_socket_inf1_inbound_data_beats_ccm0 data fabric event=0x41f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 0 remote_socket_inf1_inbound_data_beats_ccm1 data fabric event=0x45f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 1 remote_socket_inf1_inbound_data_beats_ccm2 data fabric event=0x49f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 2 remote_socket_inf1_inbound_data_beats_ccm3 data fabric event=0x4df,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 3 remote_socket_inf1_inbound_data_beats_ccm4 data fabric event=0x51f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf1_inbound_data_beats_ccm5 data fabric event=0x55f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 5 remote_socket_inf1_inbound_data_beats_ccm6 data fabric event=0x59f,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 6 remote_socket_inf1_inbound_data_beats_ccm7 data fabric event=0x5df,umask=0xbfe 01 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 7 remote_socket_inf0_outbound_data_beats_ccm0 data fabric event=0x41e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 0 remote_socket_inf0_outbound_data_beats_ccm1 data fabric event=0x45e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 1 remote_socket_inf0_outbound_data_beats_ccm2 data fabric event=0x49e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 2 remote_socket_inf0_outbound_data_beats_ccm3 data fabric event=0x4de,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 3 remote_socket_inf0_outbound_data_beats_ccm4 data fabric event=0x51e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf0_outbound_data_beats_ccm5 data fabric event=0x55e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 5 remote_socket_inf0_outbound_data_beats_ccm6 data fabric event=0x59e,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 6 remote_socket_inf0_outbound_data_beats_ccm7 data fabric event=0x5de,umask=0xbff 01 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 7 remote_socket_inf1_outbound_data_beats_ccm0 data fabric event=0x41f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 0 remote_socket_inf1_outbound_data_beats_ccm1 data fabric event=0x45f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 1 remote_socket_inf1_outbound_data_beats_ccm2 data fabric event=0x49f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 2 remote_socket_inf1_outbound_data_beats_ccm3 data fabric event=0x4df,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 3 remote_socket_inf1_outbound_data_beats_ccm4 data fabric event=0x51f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf1_outbound_data_beats_ccm5 data fabric event=0x55f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 5 remote_socket_inf1_outbound_data_beats_ccm6 data fabric event=0x59f,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 6 remote_socket_inf1_outbound_data_beats_ccm7 data fabric event=0x5df,umask=0xbff 01 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 7 local_socket_outbound_data_beats_link0 data fabric event=0xb5f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 0 local_socket_outbound_data_beats_link1 data fabric event=0xb9f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 1 local_socket_outbound_data_beats_link2 data fabric event=0xbdf,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 2 local_socket_outbound_data_beats_link3 data fabric event=0xc1f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 3 local_socket_outbound_data_beats_link4 data fabric event=0xc5f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 4 local_socket_outbound_data_beats_link5 data fabric event=0xc9f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 5 local_socket_outbound_data_beats_link6 data fabric event=0xcdf,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 6 local_socket_outbound_data_beats_link7 data fabric event=0xd1f,umask=0xf3e 01 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 7 fp_ret_x87_fp_ops.add_sub_ops floating point Retired x87 floating-point add and subtract ops event=0x2,umask=0x01 00 fp_ret_x87_fp_ops.mul_ops floating point Retired x87 floating-point multiply ops event=0x2,umask=0x02 00 fp_ret_x87_fp_ops.div_sqrt_ops floating point Retired x87 floating-point divide and square root ops event=0x2,umask=0x04 00 fp_ret_x87_fp_ops.all floating point Retired x87 floating-point ops of all types event=0x2,umask=0x07 00 fp_ret_sse_avx_ops.add_sub_flops floating point Retired SSE and AVX floating-point add and subtract ops event=0x3,umask=0x01 00 fp_ret_sse_avx_ops.mult_flops floating point Retired SSE and AVX floating-point multiply ops event=0x3,umask=0x02 00 fp_ret_sse_avx_ops.div_flops floating point Retired SSE and AVX floating-point divide and square root ops event=0x3,umask=0x04 00 fp_ret_sse_avx_ops.mac_flops floating point Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops) event=0x3,umask=0x08 00 fp_ret_sse_avx_ops.bfloat_mac_flops floating point Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops) event=0x3,umask=0x10 00 fp_ret_sse_avx_ops.all floating point Retired SSE and AVX floating-point ops of all types event=0x3,umask=0x1f 00 fp_retired_ser_ops.x87_ctrl_ret floating point Retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bits event=0x5,umask=0x01 00 fp_retired_ser_ops.x87_bot_ret floating point Retired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing event=0x5,umask=0x02 00 fp_retired_ser_ops.sse_ctrl_ret floating point Retired SSE and AVX control word mispredict traps event=0x5,umask=0x04 00 fp_retired_ser_ops.sse_bot_ret floating point Retired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing event=0x5,umask=0x08 00 fp_retired_ser_ops.all floating point Retired SSE and AVX serializing ops of all types event=0x5,umask=0x0f 00 fp_ops_retired_by_width.x87_uops_retired floating point Retired x87 floating-point ops event=0x8,umask=0x01 00 fp_ops_retired_by_width.mmx_uops_retired floating point Retired MMX floating-point ops event=0x8,umask=0x02 00 fp_ops_retired_by_width.scalar_uops_retired floating point Retired scalar floating-point ops event=0x8,umask=0x04 00 fp_ops_retired_by_width.pack_128_uops_retired floating point Retired packed 128-bit floating-point ops event=0x8,umask=0x08 00 fp_ops_retired_by_width.pack_256_uops_retired floating point Retired packed 256-bit floating-point ops event=0x8,umask=0x10 00 fp_ops_retired_by_width.pack_512_uops_retired floating point Retired packed 512-bit floating-point ops event=0x8,umask=0x20 00 fp_ops_retired_by_width.all floating point Retired floating-point ops of all widths event=0x8,umask=0x3f 00 fp_ops_retired_by_type.scalar_add floating point Retired scalar floating-point add ops event=0xa,umask=0x01 00 fp_ops_retired_by_type.scalar_sub floating point Retired scalar floating-point subtract ops event=0xa,umask=0x02 00 fp_ops_retired_by_type.scalar_mul floating point Retired scalar floating-point multiply ops event=0xa,umask=0x03 00 fp_ops_retired_by_type.scalar_mac floating point Retired scalar floating-point multiply-accumulate ops event=0xa,umask=0x04 00 fp_ops_retired_by_type.scalar_div floating point Retired scalar floating-point divide ops event=0xa,umask=0x05 00 fp_ops_retired_by_type.scalar_sqrt floating point Retired scalar floating-point square root ops event=0xa,umask=0x06 00 fp_ops_retired_by_type.scalar_cmp floating point Retired scalar floating-point compare ops event=0xa,umask=0x07 00 fp_ops_retired_by_type.scalar_cvt floating point Retired scalar floating-point convert ops event=0xa,umask=0x08 00 fp_ops_retired_by_type.scalar_blend floating point Retired scalar floating-point blend ops event=0xa,umask=0x09 00 fp_ops_retired_by_type.scalar_other floating point Retired scalar floating-point ops of other types event=0xa,umask=0x0e 00 fp_ops_retired_by_type.scalar_all floating point Retired scalar floating-point ops of all types event=0xa,umask=0x0f 00 fp_ops_retired_by_type.vector_add floating point Retired vector floating-point add ops event=0xa,umask=0x10 00 fp_ops_retired_by_type.vector_sub floating point Retired vector floating-point subtract ops event=0xa,umask=0x20 00 fp_ops_retired_by_type.vector_mul floating point Retired vector floating-point multiply ops event=0xa,umask=0x30 00 fp_ops_retired_by_type.vector_mac floating point Retired vector floating-point multiply-accumulate ops event=0xa,umask=0x40 00 fp_ops_retired_by_type.vector_div floating point Retired vector floating-point divide ops event=0xa,umask=0x50 00 fp_ops_retired_by_type.vector_sqrt floating point Retired vector floating-point square root ops event=0xa,umask=0x60 00 fp_ops_retired_by_type.vector_cmp floating point Retired vector floating-point compare ops event=0xa,umask=0x70 00 fp_ops_retired_by_type.vector_cvt floating point Retired vector floating-point convert ops event=0xa,umask=0x80 00 fp_ops_retired_by_type.vector_blend floating point Retired vector floating-point blend ops event=0xa,umask=0x90 00 fp_ops_retired_by_type.vector_shuffle floating point Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xa,umask=0xb0 00 fp_ops_retired_by_type.vector_logical floating point Retired vector floating-point logical ops event=0xa,umask=0xd0 00 fp_ops_retired_by_type.vector_other floating point Retired vector floating-point ops of other types event=0xa,umask=0xe0 00 fp_ops_retired_by_type.vector_all floating point Retired vector floating-point ops of all types event=0xa,umask=0xf0 00 fp_ops_retired_by_type.all floating point Retired floating-point ops of all types event=0xa,umask=0xff 00 sse_avx_ops_retired.mmx_add floating point Retired MMX integer add event=0xb,umask=0x01 00 sse_avx_ops_retired.mmx_sub floating point Retired MMX integer subtract ops event=0xb,umask=0x02 00 sse_avx_ops_retired.mmx_mul floating point Retired MMX integer multiply ops event=0xb,umask=0x03 00 sse_avx_ops_retired.mmx_mac floating point Retired MMX integer multiply-accumulate ops event=0xb,umask=0x04 00 sse_avx_ops_retired.mmx_cmp floating point Retired MMX integer compare ops event=0xb,umask=0x07 00 sse_avx_ops_retired.mmx_shift floating point Retired MMX integer shift ops event=0xb,umask=0x09 00 sse_avx_ops_retired.mmx_mov floating point Retired MMX integer MOV ops event=0xb,umask=0x0a 00 sse_avx_ops_retired.mmx_shuffle floating point Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0x0b 00 sse_avx_ops_retired.mmx_pack floating point Retired MMX integer pack ops event=0xb,umask=0x0c 00 sse_avx_ops_retired.mmx_logical floating point Retired MMX integer logical ops event=0xb,umask=0x0d 00 sse_avx_ops_retired.mmx_other floating point Retired MMX integer multiply ops of other types event=0xb,umask=0x0e 00 sse_avx_ops_retired.mmx_all floating point Retired MMX integer ops of all types event=0xb,umask=0x0f 00 sse_avx_ops_retired.sse_avx_add floating point Retired SSE and AVX integer add ops event=0xb,umask=0x10 00 sse_avx_ops_retired.sse_avx_sub floating point Retired SSE and AVX integer subtract ops event=0xb,umask=0x20 00 sse_avx_ops_retired.sse_avx_mul floating point Retired SSE and AVX integer multiply ops event=0xb,umask=0x30 00 sse_avx_ops_retired.sse_avx_mac floating point Retired SSE and AVX integer multiply-accumulate ops event=0xb,umask=0x40 00 sse_avx_ops_retired.sse_avx_aes floating point Retired SSE and AVX integer AES ops event=0xb,umask=0x50 00 sse_avx_ops_retired.sse_avx_sha floating point Retired SSE and AVX integer SHA ops event=0xb,umask=0x60 00 sse_avx_ops_retired.sse_avx_cmp floating point Retired SSE and AVX integer compare ops event=0xb,umask=0x70 00 sse_avx_ops_retired.sse_avx_clm floating point Retired SSE and AVX integer CLM ops event=0xb,umask=0x80 00 sse_avx_ops_retired.sse_avx_shift floating point Retired SSE and AVX integer shift ops event=0xb,umask=0x90 00 sse_avx_ops_retired.sse_avx_mov floating point Retired SSE and AVX integer MOV ops event=0xb,umask=0xa0 00 sse_avx_ops_retired.sse_avx_shuffle floating point Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0xb0 00 sse_avx_ops_retired.sse_avx_pack floating point Retired SSE and AVX integer pack ops event=0xb,umask=0xc0 00 sse_avx_ops_retired.sse_avx_logical floating point Retired SSE and AVX integer logical ops event=0xb,umask=0xd0 00 sse_avx_ops_retired.sse_avx_other floating point Retired SSE and AVX integer ops of other types event=0xb,umask=0xe0 00 sse_avx_ops_retired.sse_avx_all floating point Retired SSE and AVX integer ops of all types event=0xb,umask=0xf0 00 sse_avx_ops_retired.all floating point Retired SSE, AVX and MMX integer ops of all types event=0xb,umask=0xff 00 fp_pack_ops_retired.fp128_add floating point Retired 128-bit packed floating-point add ops event=0xc,umask=0x01 00 fp_pack_ops_retired.fp128_sub floating point Retired 128-bit packed floating-point subtract ops event=0xc,umask=0x02 00 fp_pack_ops_retired.fp128_mul floating point Retired 128-bit packed floating-point multiply ops event=0xc,umask=0x03 00 fp_pack_ops_retired.fp128_mac floating point Retired 128-bit packed floating-point multiply-accumulate ops event=0xc,umask=0x04 00 fp_pack_ops_retired.fp128_div floating point Retired 128-bit packed floating-point divide ops event=0xc,umask=0x05 00 fp_pack_ops_retired.fp128_sqrt floating point Retired 128-bit packed floating-point square root ops event=0xc,umask=0x06 00 fp_pack_ops_retired.fp128_cmp floating point Retired 128-bit packed floating-point compare ops event=0xc,umask=0x07 00 fp_pack_ops_retired.fp128_cvt floating point Retired 128-bit packed floating-point convert ops event=0xc,umask=0x08 00 fp_pack_ops_retired.fp128_blend floating point Retired 128-bit packed floating-point blend ops event=0xc,umask=0x09 00 fp_pack_ops_retired.fp128_shuffle floating point Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0x0b 00 fp_pack_ops_retired.fp128_logical floating point Retired 128-bit packed floating-point logical ops event=0xc,umask=0x0d 00 fp_pack_ops_retired.fp128_other floating point Retired 128-bit packed floating-point ops of other types event=0xc,umask=0x0e 00 fp_pack_ops_retired.fp128_all floating point Retired 128-bit packed floating-point ops of all types event=0xc,umask=0x0f 00 fp_pack_ops_retired.fp256_add floating point Retired 256-bit packed floating-point add ops event=0xc,umask=0x10 00 fp_pack_ops_retired.fp256_sub floating point Retired 256-bit packed floating-point subtract ops event=0xc,umask=0x20 00 fp_pack_ops_retired.fp256_mul floating point Retired 256-bit packed floating-point multiply ops event=0xc,umask=0x30 00 fp_pack_ops_retired.fp256_mac floating point Retired 256-bit packed floating-point multiply-accumulate ops event=0xc,umask=0x40 00 fp_pack_ops_retired.fp256_div floating point Retired 256-bit packed floating-point divide ops event=0xc,umask=0x50 00 fp_pack_ops_retired.fp256_sqrt floating point Retired 256-bit packed floating-point square root ops event=0xc,umask=0x60 00 fp_pack_ops_retired.fp256_cmp floating point Retired 256-bit packed floating-point compare ops event=0xc,umask=0x70 00 fp_pack_ops_retired.fp256_cvt floating point Retired 256-bit packed floating-point convert ops event=0xc,umask=0x80 00 fp_pack_ops_retired.fp256_blend floating point Retired 256-bit packed floating-point blend ops event=0xc,umask=0x90 00 fp_pack_ops_retired.fp256_shuffle floating point Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0xb0 00 fp_pack_ops_retired.fp256_logical floating point Retired 256-bit packed floating-point logical ops event=0xc,umask=0xd0 00 fp_pack_ops_retired.fp256_other floating point Retired 256-bit packed floating-point ops of other types event=0xc,umask=0xe0 00 fp_pack_ops_retired.fp256_all floating point Retired 256-bit packed floating-point ops of all types event=0xc,umask=0xf0 00 fp_pack_ops_retired.all floating point Retired packed floating-point ops of all types event=0xc,umask=0xff 00 packed_int_op_type.int128_add floating point Retired 128-bit packed integer add ops event=0xd,umask=0x01 00 packed_int_op_type.int128_sub floating point Retired 128-bit packed integer subtract ops event=0xd,umask=0x02 00 packed_int_op_type.int128_mul floating point Retired 128-bit packed integer multiply ops event=0xd,umask=0x03 00 packed_int_op_type.int128_mac floating point Retired 128-bit packed integer multiply-accumulate ops event=0xd,umask=0x04 00 packed_int_op_type.int128_aes floating point Retired 128-bit packed integer AES ops event=0xd,umask=0x05 00 packed_int_op_type.int128_sha floating point Retired 128-bit packed integer SHA ops event=0xd,umask=0x06 00 packed_int_op_type.int128_cmp floating point Retired 128-bit packed integer compare ops event=0xd,umask=0x07 00 packed_int_op_type.int128_clm floating point Retired 128-bit packed integer CLM ops event=0xd,umask=0x08 00 packed_int_op_type.int128_shift floating point Retired 128-bit packed integer shift ops event=0xd,umask=0x09 00 packed_int_op_type.int128_mov floating point Retired 128-bit packed integer MOV ops event=0xd,umask=0x0a 00 packed_int_op_type.int128_shuffle floating point Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0x0b 00 packed_int_op_type.int128_pack floating point Retired 128-bit packed integer pack ops event=0xd,umask=0x0c 00 packed_int_op_type.int128_logical floating point Retired 128-bit packed integer logical ops event=0xd,umask=0x0d 00 packed_int_op_type.int128_other floating point Retired 128-bit packed integer ops of other types event=0xd,umask=0x0e 00 packed_int_op_type.int128_all floating point Retired 128-bit packed integer ops of all types event=0xd,umask=0x0f 00 packed_int_op_type.int256_add floating point Retired 256-bit packed integer add ops event=0xd,umask=0x10 00 packed_int_op_type.int256_sub floating point Retired 256-bit packed integer subtract ops event=0xd,umask=0x20 00 packed_int_op_type.int256_mul floating point Retired 256-bit packed integer multiply ops event=0xd,umask=0x30 00 packed_int_op_type.int256_mac floating point Retired 256-bit packed integer multiply-accumulate ops event=0xd,umask=0x40 00 packed_int_op_type.int256_cmp floating point Retired 256-bit packed integer compare ops event=0xd,umask=0x70 00 packed_int_op_type.int256_shift floating point Retired 256-bit packed integer shift ops event=0xd,umask=0x90 00 packed_int_op_type.int256_mov floating point Retired 256-bit packed integer MOV ops event=0xd,umask=0xa0 00 packed_int_op_type.int256_shuffle floating point Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0xb0 00 packed_int_op_type.int256_pack floating point Retired 256-bit packed integer pack ops event=0xd,umask=0xc0 00 packed_int_op_type.int256_logical floating point Retired 256-bit packed integer logical ops event=0xd,umask=0xd0 00 packed_int_op_type.int256_other floating point Retired 256-bit packed integer ops of other types event=0xd,umask=0xe0 00 packed_int_op_type.int256_all floating point Retired 256-bit packed integer ops of all types event=0xd,umask=0xf0 00 packed_int_op_type.all floating point Retired packed integer ops of all types event=0xd,umask=0xff 00 fp_disp_faults.x87_fill_fault floating point Floating-point dispatch faults for x87 fills event=0xe,umask=0x01 00 fp_disp_faults.xmm_fill_fault floating point Floating-point dispatch faults for XMM fills event=0xe,umask=0x02 00 fp_disp_faults.ymm_fill_fault floating point Floating-point dispatch faults for YMM fills event=0xe,umask=0x04 00 fp_disp_faults.ymm_spill_fault floating point Floating-point dispatch faults for YMM spills event=0xe,umask=0x08 00 fp_disp_faults.sse_avx_all floating point Floating-point dispatch faults of all types for SSE and AVX ops event=0xe,umask=0x0e 00 fp_disp_faults.all floating point Floating-point dispatch faults of all types event=0xe,umask=0x0f 00 amd_umc umc_mem_clk memory controller event=0 01 Number of memory clock cycles umc_act_cmd.all memory controller event=0x5 01 Number of ACTIVATE commands sent umc_act_cmd.rd memory controller event=0x5,rdwrmask=0x1 01 Number of ACTIVATE commands sent for reads umc_act_cmd.wr memory controller event=0x5,rdwrmask=0x2 01 Number of ACTIVATE commands sent for writes umc_pchg_cmd.all memory controller event=0x6 01 Number of PRECHARGE commands sent umc_pchg_cmd.rd memory controller event=0x6,rdwrmask=0x1 01 Number of PRECHARGE commands sent for reads umc_pchg_cmd.wr memory controller event=0x6,rdwrmask=0x2 01 Number of PRECHARGE commands sent for writes umc_cas_cmd.all memory controller event=0xa 01 Number of CAS commands sent umc_cas_cmd.rd memory controller event=0xa,rdwrmask=0x1 01 Number of CAS commands sent for reads umc_cas_cmd.wr memory controller event=0xa,rdwrmask=0x2 01 Number of CAS commands sent for writes umc_data_slot_clks.all memory controller event=0x14 01 Number of clocks used by the data bus umc_data_slot_clks.rd memory controller event=0x14,rdwrmask=0x1 01 Number of clocks used by the data bus for reads umc_data_slot_clks.wr memory controller event=0x14,rdwrmask=0x2 01 Number of clocks used by the data bus for writes ls_bad_status2.stli_other memory Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store) event=0x24,umask=0x02 00 ls_dispatch.ld_dispatch memory Number of memory load operations dispatched to the load-store unit event=0x29,umask=0x01 00 ls_dispatch.store_dispatch memory Number of memory store operations dispatched to the load-store unit event=0x29,umask=0x02 00 ls_dispatch.ld_st_dispatch memory Number of memory load-store operations dispatched to the load-store unit event=0x29,umask=0x04 00 ls_stlf memory Store-to-load-forward (STLF) hits event=0x35 00 ls_st_commit_cancel2.st_commit_cancel_wcb_full memory Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full event=0x37,umask=0x01 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB misses with L2 DTLB hits for 4k pages event=0x45,umask=0x01 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=0x02 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB misses with L2 DTLB hits for 2M pages event=0x45,umask=0x04 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB misses with L2 DTLB hits for 1G pages event=0x45,umask=0x08 00 ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages event=0x45,umask=0x10 00 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=0x20 00 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages event=0x45,umask=0x40 00 ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages event=0x45,umask=0x80 00 ls_l1_d_tlb_miss.all_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes event=0x45,umask=0xf0 00 ls_l1_d_tlb_miss.all memory L1 DTLB misses for all page sizes event=0x45,umask=0xff 00 ls_misal_loads.ma64 memory 64B misaligned (cacheline crossing) loads event=0x47,umask=0x01 00 ls_misal_loads.ma4k memory 4kB misaligned (page crossing) loads event=0x47,umask=0x02 00 ls_tlb_flush.all memory All TLB Flushes event=0x78,umask=0xff 00 bp_l1_tlb_miss_l2_tlb_hit memory Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84 00 bp_l1_tlb_miss_l2_tlb_miss.if4k memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages event=0x85,umask=0x01 00 bp_l1_tlb_miss_l2_tlb_miss.if2m memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages event=0x85,umask=0x02 00 bp_l1_tlb_miss_l2_tlb_miss.if1g memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages event=0x85,umask=0x04 00 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x85,umask=0x08 00 bp_l1_tlb_miss_l2_tlb_miss.all memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes event=0x85,umask=0x0f 00 bp_l1_tlb_fetch_hit.if4k memory Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x94,umask=0x01 00 bp_l1_tlb_fetch_hit.if2m memory Instruction fetches that hit in the L1 ITLB for 2M pages event=0x94,umask=0x02 00 bp_l1_tlb_fetch_hit.if1g memory Instruction fetches that hit in the L1 ITLB for 1G pages event=0x94,umask=0x04 00 bp_l1_tlb_fetch_hit.all memory Instruction fetches that hit in the L1 ITLB for all page sizes event=0x94,umask=0x07 00 resyncs_or_nc_redirects other Pipeline restarts not caused by branch mispredicts event=0x96 00 de_op_queue_empty other Cycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough event=0xa9 00 de_src_op_disp.decoder other Ops fetched from instruction cache and dispatched event=0xaa,umask=0x01 00 de_src_op_disp.op_cache other Ops fetched from op cache and dispatched event=0xaa,umask=0x02 00 de_src_op_disp.loop_buffer other Ops dispatched from loop buffer event=0xaa,umask=0x04 00 de_src_op_disp.all other Ops dispatched from any source event=0xaa,umask=0x07 00 de_dis_ops_from_decoder.any_fp_dispatch other Number of ops dispatched to the floating-point unit event=0xab,umask=0x04 00 de_dis_ops_from_decoder.disp_op_type.any_integer_dispatch other Number of ops dispatched to the integer execution unit event=0xab,umask=0x08 00 de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall other Number of cycles dispatch is stalled for integer physical register file tokens event=0xae,umask=0x01 00 de_dis_dispatch_token_stalls1.load_queue_rsrc_stall other Number of cycles dispatch is stalled for Load queue token event=0xae,umask=0x02 00 de_dis_dispatch_token_stalls1.store_queue_rsrc_stall other Number of cycles dispatch is stalled for store queue tokens event=0xae,umask=0x04 00 de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc other Number of cycles dispatch is stalled for taken branch buffer tokens event=0xae,umask=0x10 00 de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Number of cycles dispatch is stalled for floating-point register file tokens event=0xae,umask=0x20 00 de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Number of cycles dispatch is stalled for floating-point scheduler tokens event=0xae,umask=0x40 00 de_dis_dispatch_token_stalls1.fp_flush_recovery_stall other Number of cycles dispatch is stalled for floating-point flush recovery event=0xae,umask=0x80 00 de_dis_dispatch_token_stalls2.int_sch0_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 0 tokens event=0xaf,umask=0x01 00 de_dis_dispatch_token_stalls2.int_sch1_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 1 tokens event=0xaf,umask=0x02 00 de_dis_dispatch_token_stalls2.int_sch2_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 2 tokens event=0xaf,umask=0x04 00 de_dis_dispatch_token_stalls2.int_sch3_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 3 tokens event=0xaf,umask=0x08 00 de_dis_dispatch_token_stalls2.retire_token_stall other Number of cycles dispatch is stalled for retire queue tokens event=0xaf,umask=0x20 00 de_no_dispatch_per_slot.no_ops_from_frontend other In each cycle counts dispatch slots left empty because the front-end did not supply ops event=0x1a0,umask=0x01 00 de_no_dispatch_per_slot.backend_stalls other In each cycle counts ops unable to dispatch because of back-end stalls event=0x1a0,umask=0x1e 00 de_no_dispatch_per_slot.smt_contention other In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread event=0x1a0,umask=0x60 00 all_data_cache_accesses recommended All data cache accesses event=0x29,umask=0x07 00 l1d_cache.all_cache_ref cache L1 Data Cacheable reads and writes event=0x40,period=2000000,umask=0xa3 00 l1d_cache.all_ref cache L1 Data reads and writes event=0x40,period=2000000,umask=0x83 00 l1d_cache.evict cache Modified cache lines evicted from the L1 data cache event=0x40,period=200000,umask=0x10 00 l1d_cache.ld cache L1 Cacheable Data Reads event=0x40,period=2000000,umask=0xa1 00 l1d_cache.repl cache L1 Data line replacements event=0x40,period=200000,umask=0x8 00 l1d_cache.replm cache Modified cache lines allocated in the L1 data cache event=0x40,period=200000,umask=0x48 00 l1d_cache.st cache L1 Cacheable Data Writes event=0x40,period=2000000,umask=0xa2 00 l2_ads.self cache Cycles L2 address bus is in use event=0x21,period=200000,umask=0x40 00 l2_data_rqsts.self.e_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x44 00 l2_data_rqsts.self.i_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x41 00 l2_data_rqsts.self.mesi cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x4f 00 l2_data_rqsts.self.m_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x48 00 l2_data_rqsts.self.s_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x42 00 l2_dbus_busy.self cache Cycles the L2 cache data bus is busy event=0x22,period=200000,umask=0x40 00 l2_dbus_busy_rd.self cache Cycles the L2 transfers data to the core event=0x23,period=200000,umask=0x40 00 l2_ifetch.self.e_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x44 00 l2_ifetch.self.i_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x41 00 l2_ifetch.self.mesi cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x4f 00 l2_ifetch.self.m_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x48 00 l2_ifetch.self.s_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x42 00 l2_ld.self.any.e_state cache L2 cache reads event=0x29,period=200000,umask=0x74 00 l2_ld.self.any.i_state cache L2 cache reads event=0x29,period=200000,umask=0x71 00 l2_ld.self.any.mesi cache L2 cache reads event=0x29,period=200000,umask=0x7f 00 l2_ld.self.any.m_state cache L2 cache reads event=0x29,period=200000,umask=0x78 00 l2_ld.self.any.s_state cache L2 cache reads event=0x29,period=200000,umask=0x72 00 l2_ld.self.demand.e_state cache L2 cache reads event=0x29,period=200000,umask=0x44 00 l2_ld.self.demand.i_state cache L2 cache reads event=0x29,period=200000,umask=0x41 00 l2_ld.self.demand.mesi cache L2 cache reads event=0x29,period=200000,umask=0x4f 00 l2_ld.self.demand.m_state cache L2 cache reads event=0x29,period=200000,umask=0x48 00 l2_ld.self.demand.s_state cache L2 cache reads event=0x29,period=200000,umask=0x42 00 l2_ld.self.prefetch.e_state cache L2 cache reads event=0x29,period=200000,umask=0x54 00 l2_ld.self.prefetch.i_state cache L2 cache reads event=0x29,period=200000,umask=0x51 00 l2_ld.self.prefetch.mesi cache L2 cache reads event=0x29,period=200000,umask=0x5f 00 l2_ld.self.prefetch.m_state cache L2 cache reads event=0x29,period=200000,umask=0x58 00 l2_ld.self.prefetch.s_state cache L2 cache reads event=0x29,period=200000,umask=0x52 00 l2_ld_ifetch.self.e_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x44 00 l2_ld_ifetch.self.i_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x41 00 l2_ld_ifetch.self.mesi cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x4f 00 l2_ld_ifetch.self.m_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x48 00 l2_ld_ifetch.self.s_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x42 00 l2_lines_in.self.any cache L2 cache misses event=0x24,period=200000,umask=0x70 00 l2_lines_in.self.demand cache L2 cache misses event=0x24,period=200000,umask=0x40 00 l2_lines_in.self.prefetch cache L2 cache misses event=0x24,period=200000,umask=0x50 00 l2_lines_out.self.any cache L2 cache lines evicted event=0x26,period=200000,umask=0x70 00 l2_lines_out.self.demand cache L2 cache lines evicted event=0x26,period=200000,umask=0x40 00 l2_lines_out.self.prefetch cache L2 cache lines evicted event=0x26,period=200000,umask=0x50 00 l2_lock.self.e_state cache L2 locked accesses event=0x2b,period=200000,umask=0x44 00 l2_lock.self.i_state cache L2 locked accesses event=0x2b,period=200000,umask=0x41 00 l2_lock.self.mesi cache L2 locked accesses event=0x2b,period=200000,umask=0x4f 00 l2_lock.self.m_state cache L2 locked accesses event=0x2b,period=200000,umask=0x48 00 l2_lock.self.s_state cache L2 locked accesses event=0x2b,period=200000,umask=0x42 00 l2_m_lines_in.self cache L2 cache line modifications event=0x25,period=200000,umask=0x40 00 l2_m_lines_out.self.any cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x70 00 l2_m_lines_out.self.demand cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x40 00 l2_m_lines_out.self.prefetch cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x50 00 l2_no_req.self cache Cycles no L2 cache requests are pending event=0x32,period=200000,umask=0x40 00 l2_reject_busq.self.any.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x74 00 l2_reject_busq.self.any.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x71 00 l2_reject_busq.self.any.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x7f 00 l2_reject_busq.self.any.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x78 00 l2_reject_busq.self.any.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x72 00 l2_reject_busq.self.demand.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x44 00 l2_reject_busq.self.demand.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x41 00 l2_reject_busq.self.demand.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x4f 00 l2_reject_busq.self.demand.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x48 00 l2_reject_busq.self.demand.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x42 00 l2_reject_busq.self.prefetch.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x54 00 l2_reject_busq.self.prefetch.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x51 00 l2_reject_busq.self.prefetch.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x5f 00 l2_reject_busq.self.prefetch.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x58 00 l2_reject_busq.self.prefetch.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x52 00 l2_rqsts.self.any.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x74 00 l2_rqsts.self.any.i_state cache L2 cache requests event=0x2e,period=200000,umask=0x71 00 l2_rqsts.self.any.mesi cache L2 cache requests event=0x2e,period=200000,umask=0x7f 00 l2_rqsts.self.any.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x78 00 l2_rqsts.self.any.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x72 00 l2_rqsts.self.demand.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x44 00 l2_rqsts.self.demand.i_state cache L2 cache demand requests from this core that missed the L2 event=0x2e,period=200000,umask=0x41 00 l2_rqsts.self.demand.mesi cache L2 cache demand requests from this core event=0x2e,period=200000,umask=0x4f 00 l2_rqsts.self.demand.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x48 00 l2_rqsts.self.demand.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x42 00 l2_rqsts.self.prefetch.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x54 00 l2_rqsts.self.prefetch.i_state cache L2 cache requests event=0x2e,period=200000,umask=0x51 00 l2_rqsts.self.prefetch.mesi cache L2 cache requests event=0x2e,period=200000,umask=0x5f 00 l2_rqsts.self.prefetch.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x58 00 l2_rqsts.self.prefetch.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x52 00 l2_st.self.e_state cache L2 store requests event=0x2a,period=200000,umask=0x44 00 l2_st.self.i_state cache L2 store requests event=0x2a,period=200000,umask=0x41 00 l2_st.self.mesi cache L2 store requests event=0x2a,period=200000,umask=0x4f 00 l2_st.self.m_state cache L2 store requests event=0x2a,period=200000,umask=0x48 00 l2_st.self.s_state cache L2 store requests event=0x2a,period=200000,umask=0x42 00 mem_load_retired.l2_hit cache Retired loads that hit the L2 cache (precise event) event=0xcb,period=200000,umask=0x1 00 mem_load_retired.l2_miss cache Retired loads that miss the L2 cache event=0xcb,period=10000,umask=0x2 00 fp_assist.ar floating point Floating point assists for retired operations event=0x11,period=10000,umask=0x81 00 fp_assist.s floating point Floating point assists event=0x11,period=10000,umask=0x1 00 simd_assist floating point SIMD assists invoked event=0xcd,period=100000 00 simd_comp_inst_retired.packed_single floating point Retired computational Streaming SIMD Extensions (SSE) packed-single instructions event=0xca,period=2000000,umask=0x1 00 simd_comp_inst_retired.scalar_double floating point Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions event=0xca,period=2000000,umask=0x8 00 simd_comp_inst_retired.scalar_single floating point Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions event=0xca,period=2000000,umask=0x2 00 simd_instr_retired floating point SIMD Instructions retired event=0xce,period=2000000 00 simd_inst_retired.packed_single floating point Retired Streaming SIMD Extensions (SSE) packed-single instructions event=0xc7,period=2000000,umask=0x1 00 simd_inst_retired.scalar_double floating point Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions event=0xc7,period=2000000,umask=0x8 00 simd_inst_retired.scalar_single floating point Retired Streaming SIMD Extensions (SSE) scalar-single instructions event=0xc7,period=2000000,umask=0x2 00 simd_inst_retired.vector floating point Retired Streaming SIMD Extensions 2 (SSE2) vector instructions event=0xc7,period=2000000,umask=0x10 00 simd_sat_instr_retired floating point Saturated arithmetic instructions retired event=0xcf,period=2000000 00 simd_sat_uop_exec.ar floating point SIMD saturated arithmetic micro-ops retired event=0xb1,period=2000000,umask=0x80 00 simd_sat_uop_exec.s floating point SIMD saturated arithmetic micro-ops executed event=0xb1,period=2000000 00 simd_uops_exec.ar floating point SIMD micro-ops retired (excluding stores) (Must be precise) event=0xb0,period=2000000,umask=0x80 00 simd_uops_exec.s floating point SIMD micro-ops executed (excluding stores) event=0xb0,period=2000000 00 simd_uop_type_exec.arithmetic.ar floating point SIMD packed arithmetic micro-ops retired event=0xb3,period=2000000,umask=0xa0 00 simd_uop_type_exec.arithmetic.s floating point SIMD packed arithmetic micro-ops executed event=0xb3,period=2000000,umask=0x20 00 simd_uop_type_exec.logical.ar floating point SIMD packed logical micro-ops retired event=0xb3,period=2000000,umask=0x90 00 simd_uop_type_exec.logical.s floating point SIMD packed logical micro-ops executed event=0xb3,period=2000000,umask=0x10 00 simd_uop_type_exec.mul.ar floating point SIMD packed multiply micro-ops retired event=0xb3,period=2000000,umask=0x81 00 simd_uop_type_exec.mul.s floating point SIMD packed multiply micro-ops executed event=0xb3,period=2000000,umask=0x1 00 simd_uop_type_exec.pack.ar floating point SIMD packed micro-ops retired event=0xb3,period=2000000,umask=0x84 00 simd_uop_type_exec.pack.s floating point SIMD packed micro-ops executed event=0xb3,period=2000000,umask=0x4 00 simd_uop_type_exec.shift.ar floating point SIMD packed shift micro-ops retired event=0xb3,period=2000000,umask=0x82 00 simd_uop_type_exec.shift.s floating point SIMD packed shift micro-ops executed event=0xb3,period=2000000,umask=0x2 00 simd_uop_type_exec.unpack.ar floating point SIMD unpacked micro-ops retired event=0xb3,period=2000000,umask=0x88 00 simd_uop_type_exec.unpack.s floating point SIMD unpacked micro-ops executed event=0xb3,period=2000000,umask=0x8 00 x87_comp_ops_exe.any.ar floating point Floating point computational micro-ops retired (Must be precise) event=0x10,period=2000000,umask=0x81 00 x87_comp_ops_exe.any.s floating point Floating point computational micro-ops executed event=0x10,period=2000000,umask=0x1 00 x87_comp_ops_exe.fxch.ar floating point FXCH uops retired (Must be precise) event=0x10,period=2000000,umask=0x82 00 x87_comp_ops_exe.fxch.s floating point FXCH uops executed event=0x10,period=2000000,umask=0x2 00 baclears.any frontend BACLEARS asserted event=0xe6,period=2000000,umask=0x1 00 cycles_icache_mem_stalled.icache_mem_stalled frontend Cycles during which instruction fetches are stalled event=0x86,period=2000000,umask=0x1 00 decode_stall.iq_full frontend Decode stall due to IQ full event=0x87,period=2000000,umask=0x2 00 decode_stall.pfb_empty frontend Decode stall due to PFB empty event=0x87,period=2000000,umask=0x1 00 icache.accesses frontend Instruction fetches event=0x80,period=200000,umask=0x3 00 icache.hit frontend Icache hit event=0x80,period=200000,umask=0x1 00 icache.misses frontend Icache miss event=0x80,period=200000,umask=0x2 00 macro_insts.all_decoded frontend All Instructions decoded event=0xaa,period=2000000,umask=0x3 00 macro_insts.cisc_decoded frontend CISC macro instructions decoded event=0xaa,period=2000000,umask=0x2 00 macro_insts.non_cisc_decoded frontend Non-CISC macro instructions decoded event=0xaa,period=2000000,umask=0x1 00 uops.ms_cycles frontend This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ event=0xa9,cmask=1,period=2000000,umask=0x1 00 misalign_mem_ref.bubble memory Nonzero segbase 1 bubble event=0x5,period=200000,umask=0x97 00 misalign_mem_ref.ld_bubble memory Nonzero segbase load 1 bubble event=0x5,period=200000,umask=0x91 00 misalign_mem_ref.ld_split memory Load splits event=0x5,period=200000,umask=0x9 00 misalign_mem_ref.ld_split.ar memory Load splits (At Retirement) event=0x5,period=200000,umask=0x89 00 misalign_mem_ref.rmw_bubble memory Nonzero segbase ld-op-st 1 bubble event=0x5,period=200000,umask=0x94 00 misalign_mem_ref.rmw_split memory ld-op-st splits event=0x5,period=200000,umask=0x8c 00 misalign_mem_ref.split memory Memory references that cross an 8-byte boundary event=0x5,period=200000,umask=0xf 00 misalign_mem_ref.split.ar memory Memory references that cross an 8-byte boundary (At Retirement) event=0x5,period=200000,umask=0x8f 00 misalign_mem_ref.st_bubble memory Nonzero segbase store 1 bubble event=0x5,period=200000,umask=0x92 00 misalign_mem_ref.st_split memory Store splits event=0x5,period=200000,umask=0xa 00 misalign_mem_ref.st_split.ar memory Store splits (Ar Retirement) event=0x5,period=200000,umask=0x8a 00 prefetch.hw_prefetch memory L1 hardware prefetch request event=0x7,period=2000000,umask=0x10 00 prefetch.prefetchnta memory Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed event=0x7,period=200000,umask=0x88 00 prefetch.prefetcht0 memory Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed event=0x7,period=200000,umask=0x81 00 prefetch.prefetcht1 memory Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed event=0x7,period=200000,umask=0x82 00 prefetch.prefetcht2 memory Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed event=0x7,period=200000,umask=0x84 00 prefetch.software_prefetch memory Any Software prefetch event=0x7,period=200000,umask=0xf 00 prefetch.software_prefetch.ar memory Any Software prefetch event=0x7,period=200000,umask=0x8f 00 prefetch.sw_l2 memory Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed event=0x7,period=200000,umask=0x86 00 busq_empty.self other Bus queue is empty event=0x7d,period=200000,umask=0x40 00 bus_bnr_drv.all_agents other Number of Bus Not Ready signals asserted event=0x61,period=200000,umask=0x20 00 bus_bnr_drv.this_agent other Number of Bus Not Ready signals asserted event=0x61,period=200000 00 bus_data_rcv.self other Bus cycles while processor receives data event=0x64,period=200000,umask=0x40 00 bus_drdy_clocks.all_agents other Bus cycles when data is sent on the bus event=0x62,period=200000,umask=0x20 00 bus_drdy_clocks.this_agent other Bus cycles when data is sent on the bus event=0x62,period=200000 00 bus_hitm_drv.all_agents other HITM signal asserted event=0x7b,period=200000,umask=0x20 00 bus_hitm_drv.this_agent other HITM signal asserted event=0x7b,period=200000 00 bus_hit_drv.all_agents other HIT signal asserted event=0x7a,period=200000,umask=0x20 00 bus_hit_drv.this_agent other HIT signal asserted event=0x7a,period=200000 00 bus_io_wait.self other IO requests waiting in the bus queue event=0x7f,period=200000,umask=0x40 00 bus_lock_clocks.all_agents other Bus cycles when a LOCK signal is asserted event=0x63,period=200000,umask=0xe0 00 bus_lock_clocks.self other Bus cycles when a LOCK signal is asserted event=0x63,period=200000,umask=0x40 00 bus_request_outstanding.all_agents other Outstanding cacheable data read bus requests duration event=0x60,period=200000,umask=0xe0 00 bus_request_outstanding.self other Outstanding cacheable data read bus requests duration event=0x60,period=200000,umask=0x40 00 bus_trans_any.all_agents other All bus transactions event=0x70,period=200000,umask=0xe0 00 bus_trans_any.self other All bus transactions event=0x70,period=200000,umask=0x40 00 bus_trans_brd.all_agents other Burst read bus transactions event=0x65,period=200000,umask=0xe0 00 bus_trans_brd.self other Burst read bus transactions event=0x65,period=200000,umask=0x40 00 bus_trans_burst.all_agents other Burst (full cache-line) bus transactions event=0x6e,period=200000,umask=0xe0 00 bus_trans_burst.self other Burst (full cache-line) bus transactions event=0x6e,period=200000,umask=0x40 00 bus_trans_def.all_agents other Deferred bus transactions event=0x6d,period=200000,umask=0xe0 00 bus_trans_def.self other Deferred bus transactions event=0x6d,period=200000,umask=0x40 00 bus_trans_ifetch.all_agents other Instruction-fetch bus transactions event=0x68,period=200000,umask=0xe0 00 bus_trans_ifetch.self other Instruction-fetch bus transactions event=0x68,period=200000,umask=0x40 00 bus_trans_inval.all_agents other Invalidate bus transactions event=0x69,period=200000,umask=0xe0 00 bus_trans_inval.self other Invalidate bus transactions event=0x69,period=200000,umask=0x40 00 bus_trans_io.all_agents other IO bus transactions event=0x6c,period=200000,umask=0xe0 00 bus_trans_io.self other IO bus transactions event=0x6c,period=200000,umask=0x40 00 bus_trans_mem.all_agents other Memory bus transactions event=0x6f,period=200000,umask=0xe0 00 bus_trans_mem.self other Memory bus transactions event=0x6f,period=200000,umask=0x40 00 bus_trans_p.all_agents other Partial bus transactions event=0x6b,period=200000,umask=0xe0 00 bus_trans_p.self other Partial bus transactions event=0x6b,period=200000,umask=0x40 00 bus_trans_pwr.all_agents other Partial write bus transaction event=0x6a,period=200000,umask=0xe0 00 bus_trans_pwr.self other Partial write bus transaction event=0x6a,period=200000,umask=0x40 00 bus_trans_rfo.all_agents other RFO bus transactions event=0x66,period=200000,umask=0xe0 00 bus_trans_rfo.self other RFO bus transactions event=0x66,period=200000,umask=0x40 00 bus_trans_wb.all_agents other Explicit writeback bus transactions event=0x67,period=200000,umask=0xe0 00 bus_trans_wb.self other Explicit writeback bus transactions event=0x67,period=200000,umask=0x40 00 cycles_int_masked.cycles_int_masked other Cycles during which interrupts are disabled event=0xc6,period=2000000,umask=0x1 00 cycles_int_masked.cycles_int_pending_and_masked other Cycles during which interrupts are pending and disabled event=0xc6,period=2000000,umask=0x2 00 eist_trans other Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions event=0x3a,period=200000 00 ext_snoop.all_agents.any other External snoops event=0x77,period=200000,umask=0x2b 00 ext_snoop.all_agents.clean other External snoops event=0x77,period=200000,umask=0x21 00 ext_snoop.all_agents.hit other External snoops event=0x77,period=200000,umask=0x22 00 ext_snoop.all_agents.hitm other External snoops event=0x77,period=200000,umask=0x28 00 ext_snoop.this_agent.any other External snoops event=0x77,period=200000,umask=0xb 00 ext_snoop.this_agent.clean other External snoops event=0x77,period=200000,umask=0x1 00 ext_snoop.this_agent.hit other External snoops event=0x77,period=200000,umask=0x2 00 ext_snoop.this_agent.hitm other External snoops event=0x77,period=200000,umask=0x8 00 hw_int_rcv other Hardware interrupts received event=0xc8,period=200000 00 snoop_stall_drv.all_agents other Bus stalled for snoops event=0x7e,period=200000,umask=0xe0 00 snoop_stall_drv.self other Bus stalled for snoops event=0x7e,period=200000,umask=0x40 00 thermal_trip other Number of thermal trips event=0x3b,period=200000,umask=0xc0 00 bogus_br pipeline Bogus branches event=0xe4,period=2000000,umask=0x1 00 br_inst_decoded pipeline Branch instructions decoded event=0xe0,period=2000000,umask=0x1 00 br_inst_retired.any pipeline Retired branch instructions event=0xc4,period=2000000 00 br_inst_retired.any1 pipeline Retired branch instructions event=0xc4,period=2000000,umask=0xf 00 br_inst_retired.mispred pipeline Retired mispredicted branch instructions (precise event) (Precise event) event=0xc5,period=200000 00 br_inst_retired.mispred_not_taken pipeline Retired branch instructions that were mispredicted not-taken event=0xc4,period=200000,umask=0x2 00 br_inst_retired.mispred_taken pipeline Retired branch instructions that were mispredicted taken event=0xc4,period=200000,umask=0x8 00 br_inst_retired.pred_not_taken pipeline Retired branch instructions that were predicted not-taken event=0xc4,period=2000000,umask=0x1 00 br_inst_retired.pred_taken pipeline Retired branch instructions that were predicted taken event=0xc4,period=2000000,umask=0x4 00 br_inst_retired.taken pipeline Retired taken branch instructions event=0xc4,period=2000000,umask=0xc 00 br_inst_type_retired.cond pipeline All macro conditional branch instructions event=0x88,period=2000000,umask=0x1 00 br_inst_type_retired.cond_taken pipeline Only taken macro conditional branch instructions event=0x88,period=2000000,umask=0x41 00 br_inst_type_retired.dir_call pipeline All non-indirect calls event=0x88,period=2000000,umask=0x10 00 br_inst_type_retired.ind pipeline All indirect branches that are not calls event=0x88,period=2000000,umask=0x4 00 br_inst_type_retired.ind_call pipeline All indirect calls, including both register and memory indirect event=0x88,period=2000000,umask=0x20 00 br_inst_type_retired.ret pipeline All indirect branches that have a return mnemonic event=0x88,period=2000000,umask=0x8 00 br_inst_type_retired.uncond pipeline All macro unconditional branch instructions, excluding calls and indirects event=0x88,period=2000000,umask=0x2 00 br_missp_type_retired.cond pipeline Mispredicted cond branch instructions retired event=0x89,period=200000,umask=0x1 00 br_missp_type_retired.cond_taken pipeline Mispredicted and taken cond branch instructions retired event=0x89,period=200000,umask=0x11 00 br_missp_type_retired.ind pipeline Mispredicted ind branches that are not calls event=0x89,period=200000,umask=0x2 00 br_missp_type_retired.ind_call pipeline Mispredicted indirect calls, including both register and memory indirect event=0x89,period=200000,umask=0x8 00 br_missp_type_retired.return pipeline Mispredicted return branches event=0x89,period=200000,umask=0x4 00 cpu_clk_unhalted.bus pipeline Bus cycles when core is not halted event=0x3c,period=200000,umask=0x1 00 cpu_clk_unhalted.core pipeline Core cycles when core is not halted event=0x3c,period=2000003 00 cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000000 00 cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 div.ar pipeline Divide operations retired event=0x13,period=2000000,umask=0x81 00 div.s pipeline Divide operations executed event=0x13,period=2000000,umask=0x1 00 inst_retired.any pipeline Instructions retired event=0xc0,period=2000003 00 inst_retired.any_p pipeline Instructions retired (precise event) (Must be precise) event=0xc0,period=2000003 00 machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200000,umask=0x1 00 mul.ar pipeline Multiply operations retired event=0x12,period=2000000,umask=0x81 00 mul.s pipeline Multiply operations executed event=0x12,period=2000000,umask=0x1 00 reissue.any pipeline Micro-op reissues for any cause event=0x3,period=200000,umask=0x7f 00 reissue.any.ar pipeline Micro-op reissues for any cause (At Retirement) event=0x3,period=200000,umask=0xff 00 reissue.overlap_store pipeline Micro-op reissues on a store-load collision event=0x3,period=200000,umask=0x1 00 reissue.overlap_store.ar pipeline Micro-op reissues on a store-load collision (At Retirement) event=0x3,period=200000,umask=0x81 00 resource_stalls.div_busy pipeline Cycles issue is stalled due to div busy event=0xdc,period=2000000,umask=0x2 00 store_forwards.any pipeline All store forwards event=0x2,period=200000,umask=0x83 00 store_forwards.good pipeline Good store forwards event=0x2,period=200000,umask=0x81 00 uops_retired.any pipeline Micro-ops retired event=0xc2,period=2000000,umask=0x10 00 uops_retired.stalled_cycles pipeline Cycles no micro-ops retired event=0xc2,period=2000000,umask=0x10 00 uops_retired.stalls pipeline Periods no micro-ops retired event=0xc2,period=2000000,umask=0x10 00 data_tlb_misses.dtlb_miss virtual memory Memory accesses that missed the DTLB event=0x8,period=200000,umask=0x7 00 data_tlb_misses.dtlb_miss_ld virtual memory DTLB misses due to load operations event=0x8,period=200000,umask=0x5 00 data_tlb_misses.dtlb_miss_st virtual memory DTLB misses due to store operations event=0x8,period=200000,umask=0x6 00 data_tlb_misses.l0_dtlb_miss_ld virtual memory L0 DTLB misses due to load operations event=0x8,period=200000,umask=0x9 00 data_tlb_misses.l0_dtlb_miss_st virtual memory L0 DTLB misses due to store operations event=0x8,period=200000,umask=0xa 00 itlb.flush virtual memory ITLB flushes event=0x82,period=200000,umask=0x4 00 itlb.hit virtual memory ITLB hits event=0x82,period=200000,umask=0x1 00 itlb.misses virtual memory ITLB misses (Must be precise) event=0x82,period=200000,umask=0x2 00 mem_load_retired.dtlb_miss virtual memory Retired loads that miss the DTLB (precise event) (Precise event) event=0xcb,period=200000,umask=0x4 00 page_walks.cycles virtual memory Duration of page-walks in core cycles event=0xc,period=2000000,umask=0x3 00 page_walks.d_side_cycles virtual memory Duration of D-side only page walks event=0xc,period=2000000,umask=0x1 00 page_walks.d_side_walks virtual memory Number of D-side only page walks event=0xc,period=200000,umask=0x1 00 page_walks.i_side_cycles virtual memory Duration of I-Side page walks event=0xc,period=2000000,umask=0x2 00 page_walks.i_side_walks virtual memory Number of I-Side page walks event=0xc,period=200000,umask=0x2 00 page_walks.walks virtual memory Number of page-walks executed event=0xc,period=200000,umask=0x3 00 l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=0x1 00 This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Cycles a demand request was blocked due to Fill Buffers unavailability event=0x48,cmask=1,period=2000003,umask=0x2 00 l1d_pend_miss.pending cache L1D miss outstandings duration in cycles event=0x48,period=2000003,umask=0x1 00 This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=0x1 00 This event counts duration of L1D miss outstanding in cycles l1d_pend_miss.pending_cycles_any cache Cycles with L1D load Misses outstanding from any thread on physical core event=0x48,any=1,cmask=1,period=2000003,umask=0x1 00 l2_demand_rqsts.wb_hit cache Not rejected writebacks that hit L2 cache event=0x27,period=200003,umask=0x50 00 This event counts the number of WB requests that hit L2 cache l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=0x7 00 This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=0x4 00 This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=0x1 00 This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=0x2 00 This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=0x5 00 l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4 00 This event counts the total number of L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0xe1 00 This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27 00 l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7 00 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xf8 00 This event counts the total number of requests from the L2 hardware prefetchers l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2 00 This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4 00 l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24 00 l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0xc1 00 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects event=0x24,period=200003,umask=0x21 00 This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_rqsts.l2_pf_hit cache L2 prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xd0 00 This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types l2_rqsts.l2_pf_miss cache L2 prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x30 00 This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f 00 l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff 00 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2 00 l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22 00 l2_trans.all_pf cache L2 or L3 HW prefetches that access L2 cache event=0xf0,period=200003,umask=0x8 00 This event counts L2 or L3 HW prefetches that access L2 cache including rejects l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80 00 This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=0x4 00 This event counts the number of L2 cache accesses when fetching instructions l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=0x1 00 This event counts Demand Data Read requests that access L2 cache, including rejects l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10 00 This event counts L1D writebacks that access L2 cache l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20 00 This event counts L2 fill requests that access L2 cache l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 This event counts L2 writebacks that access L2 cache l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=0x2 00 This event counts Read for Ownership (RFO) requests that access L2 cache lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=0x2 00 This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 event=0x2e,period=100003,umask=0x41 00 This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 event=0x2e,period=100003,umask=0x4f 00 This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU mem_load_uops_l3_hit_retired.xsnp_hit cache Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=0x2 00 This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=0x4 00 This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_miss cache Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=0x1 00 This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_none cache Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) event=0xd2,period=100003,umask=0x8 00 This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) event=0xd3,period=100007,umask=0x1 00 Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x40 00 This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=2000003,umask=0x1 00 This event counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) mem_load_uops_retired.l1_miss cache Retired load uops misses in L1 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x8 00 This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: BDM35 (Precise event) event=0xd1,period=100003,umask=0x2 00 This event counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) mem_load_uops_retired.l2_miss cache Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x10 00 This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) mem_load_uops_retired.l3_hit cache Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) event=0xd1,period=50021,umask=0x4 00 This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_retired.l3_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: BDM100, BDE70 (Precise event) event=0xd1,period=100007,umask=0x20 00 mem_uops_retired.all_loads cache Retired load uops Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x81 00 Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise (Precise event) mem_uops_retired.all_stores cache Retired store uops Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x82 00 Counts all retired store uops Supports address when precise (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access Supports address when precise. Spec update: BDM35 (Precise event) event=0xd0,period=100007,umask=0x21 00 This event counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x41 00 This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x42 00 This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x11 00 This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x12 00 This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=0x8 00 This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0xb0,period=100003,umask=0x80 00 This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=0x2 00 This event counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=0x1 00 This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=0x4 00 This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=0x1 00 This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,period=2000003,umask=0x8 00 This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=0x8 00 This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=0x1 00 This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=0x4 00 This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 event=0x60,period=2000003,umask=0x2 00 This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 event=0x60,period=2000003,umask=0x1 00 This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point Spec update: BDM76 offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 event=0x60,cmask=6,period=2000003,umask=0x1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0x60,period=2000003,umask=0x4 00 This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100003,umask=0x1 00 offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10091 00 offcore_response.all_data_rd.l3_hit.any_snoop cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0091 00 offcore_response.all_data_rd.l3_hit.snoop_hitm cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0091 00 offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0091 00 offcore_response.all_data_rd.l3_hit.snoop_miss cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0091 00 offcore_response.all_data_rd.l3_hit.snoop_none cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0091 00 offcore_response.all_data_rd.l3_hit.snoop_not_needed cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0091 00 offcore_response.all_data_rd.supplier_none.any_snoop cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020091 00 offcore_response.all_data_rd.supplier_none.snoop_hitm cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020091 00 offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020091 00 offcore_response.all_data_rd.supplier_none.snoop_miss cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020091 00 offcore_response.all_data_rd.supplier_none.snoop_none cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020091 00 offcore_response.all_data_rd.supplier_none.snoop_not_needed cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020091 00 offcore_response.all_pf_code_rd.any_response cache Counts all prefetch code reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10240 00 offcore_response.all_pf_code_rd.l3_hit.any_snoop cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_hitm cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_miss cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_none cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0240 00 offcore_response.all_pf_code_rd.l3_hit.snoop_not_needed cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0240 00 offcore_response.all_pf_code_rd.supplier_none.any_snoop cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_hitm cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_miss cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_none cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_not_needed cache Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020240 00 offcore_response.all_pf_data_rd.any_response cache Counts all prefetch data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10090 00 offcore_response.all_pf_data_rd.l3_hit.any_snoop cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_hitm cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_miss cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_none cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0090 00 offcore_response.all_pf_data_rd.l3_hit.snoop_not_needed cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0090 00 offcore_response.all_pf_data_rd.supplier_none.any_snoop cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_hitm cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_miss cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_none cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_not_needed cache Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020090 00 offcore_response.all_pf_rfo.any_response cache Counts prefetch RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10120 00 offcore_response.all_pf_rfo.l3_hit.any_snoop cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_hitm cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwd cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_miss cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_none cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_not_needed cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0120 00 offcore_response.all_pf_rfo.supplier_none.any_snoop cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_hitm cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwd cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_miss cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_none cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020120 00 offcore_response.all_pf_rfo.supplier_none.snoop_not_needed cache Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020120 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10122 00 offcore_response.all_rfo.l3_hit.any_snoop cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0122 00 offcore_response.all_rfo.l3_hit.snoop_hitm cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122 00 offcore_response.all_rfo.l3_hit.snoop_miss cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0122 00 offcore_response.all_rfo.l3_hit.snoop_none cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0122 00 offcore_response.all_rfo.l3_hit.snoop_not_needed cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0122 00 offcore_response.all_rfo.supplier_none.any_snoop cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020122 00 offcore_response.all_rfo.supplier_none.snoop_hitm cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020122 00 offcore_response.all_rfo.supplier_none.snoop_hit_no_fwd cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020122 00 offcore_response.all_rfo.supplier_none.snoop_miss cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020122 00 offcore_response.all_rfo.supplier_none.snoop_none cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020122 00 offcore_response.all_rfo.supplier_none.snoop_not_needed cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020122 00 offcore_response.corewb.any_response cache Counts writebacks (modified to exclusive) have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10008 00 offcore_response.corewb.l3_hit.any_snoop cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0008 00 offcore_response.corewb.l3_hit.snoop_hitm cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0008 00 offcore_response.corewb.l3_hit.snoop_hit_no_fwd cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0008 00 offcore_response.corewb.l3_hit.snoop_miss cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0008 00 offcore_response.corewb.l3_hit.snoop_none cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0008 00 offcore_response.corewb.l3_hit.snoop_not_needed cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0008 00 offcore_response.corewb.supplier_none.any_snoop cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020008 00 offcore_response.corewb.supplier_none.snoop_hitm cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020008 00 offcore_response.corewb.supplier_none.snoop_hit_no_fwd cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020008 00 offcore_response.corewb.supplier_none.snoop_miss cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020008 00 offcore_response.corewb.supplier_none.snoop_none cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020008 00 offcore_response.corewb.supplier_none.snoop_not_needed cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020008 00 offcore_response.demand_code_rd.any_response cache Counts all demand code reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10004 00 offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004 00 offcore_response.demand_code_rd.supplier_none.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020004 00 offcore_response.demand_code_rd.supplier_none.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020004 00 offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020004 00 offcore_response.demand_code_rd.supplier_none.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020004 00 offcore_response.demand_code_rd.supplier_none.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020004 00 offcore_response.demand_code_rd.supplier_none.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020004 00 offcore_response.demand_data_rd.any_response cache Counts demand data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 00 offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 00 offcore_response.demand_data_rd.supplier_none.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020001 00 offcore_response.demand_data_rd.supplier_none.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020001 00 offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020001 00 offcore_response.demand_data_rd.supplier_none.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020001 00 offcore_response.demand_data_rd.supplier_none.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020001 00 offcore_response.demand_data_rd.supplier_none.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020001 00 offcore_response.demand_rfo.any_response cache Counts all demand data writes (RFOs) have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 00 offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0002 00 offcore_response.demand_rfo.l3_hit.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002 00 offcore_response.other.any_response cache Counts any other requests have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000 00 offcore_response.other.l3_hit.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8000 00 offcore_response.other.l3_hit.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C8000 00 offcore_response.other.l3_hit.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C8000 00 offcore_response.other.l3_hit.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C8000 00 offcore_response.other.l3_hit.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C8000 00 offcore_response.other.l3_hit.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C8000 00 offcore_response.other.supplier_none.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80028000 00 offcore_response.other.supplier_none.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000028000 00 offcore_response.other.supplier_none.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400028000 00 offcore_response.other.supplier_none.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200028000 00 offcore_response.other.supplier_none.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80028000 00 offcore_response.other.supplier_none.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100028000 00 offcore_response.pf_l2_code_rd.any_response cache Counts all prefetch (that bring data to LLC only) code reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040 00 offcore_response.pf_l2_code_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0040 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0040 00 offcore_response.pf_l2_code_rd.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020040 00 offcore_response.pf_l2_data_rd.any_response cache Counts prefetch (that bring data to L2) data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010 00 offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_hitm cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_not_needed cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010 00 offcore_response.pf_l2_data_rd.supplier_none.any_snoop cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_hitm cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_not_needed cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020010 00 offcore_response.pf_l2_rfo.any_response cache Counts all prefetch (that bring data to L2) RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020 00 offcore_response.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020 00 offcore_response.pf_l2_rfo.supplier_none.any_snoop cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020020 00 offcore_response.pf_l3_code_rd.any_response cache Counts prefetch (that bring data to LLC only) code reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10200 00 offcore_response.pf_l3_code_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_hitm cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwd cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0200 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_not_needed cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0200 00 offcore_response.pf_l3_code_rd.supplier_none.any_snoop cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_hitm cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwd cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_none cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_not_needed cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020200 00 offcore_response.pf_l3_data_rd.any_response cache Counts all prefetch (that bring data to LLC only) data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10080 00 offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0080 00 offcore_response.pf_l3_data_rd.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020080 00 offcore_response.pf_l3_rfo.any_response cache Counts all prefetch (that bring data to LLC only) RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100 00 offcore_response.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0100 00 offcore_response.pf_l3_rfo.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020100 00 sq_misc.split_lock cache Split locks in SQ event=0xf4,period=100003,umask=0x10 00 This event counts the number of split locks in the super queue fp_arith_inst_retired.128b_packed_double floating point Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x4 00 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element event=0xc7,period=2000003,umask=0x8 00 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element event=0xc7,period=2000003,umask=0x10 00 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element event=0xc7,period=2000003,umask=0x20 00 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x18 00 Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.double floating point Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000006,umask=0x15 00 fp_arith_inst_retired.packed floating point Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000004,umask=0x3c 00 fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=0x3 00 Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=0x1 00 Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=0x2 00 Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.single floating point Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000005,umask=0x2a 00 fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=2000003,umask=0xfc 00 fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10 00 This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=0x8 00 This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=0x4 00 This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=0x2 00 This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid move_elimination.simd_eliminated floating point Number of SIMD Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=0x2 00 move_elimination.simd_not_eliminated floating point Number of SIMD Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=0x8 00 other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: BDM30 event=0xc1,period=100003,umask=0x8 00 This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable Spec update: BDM30 other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable Spec update: BDM30 event=0xc1,period=100003,umask=0x10 00 This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable Spec update: BDM30 uop_dispatches_cancelled.simd_prf floating point Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports event=0xa0,period=2000003,umask=0x3 00 This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=0x1f 00 dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=0x2 00 This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=0x1 00 This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches icache.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=0x4 00 This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit) icache.misses frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses event=0x80,period=200003,umask=0x2 00 This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18 00 This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18 00 This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=0x8 00 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=0x8 00 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=0x2 00 This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c 00 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=0x4 00 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x4 00 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10 00 This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10 00 This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_switches frontend Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer event=0x79,cmask=1,edge=1,period=2000003,umask=0x30 00 idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=0x1 00 This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread; b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); c. Instruction Decode Queue (IDQ) delivers four uops idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=0x1 00 This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 idq_uops_not_delivered.cycles_fe_was_ok frontend Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE event=0x9c,cmask=1,inv=1,period=2000003,umask=0x1 00 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=0x1 00 This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end event=0x9c,cmask=2,period=2000003,umask=0x1 00 idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end event=0x9c,cmask=1,period=2000003,umask=0x1 00 hle_retired.aborted memory Number of times HLE abort was triggered (Precise event) event=0xc8,period=2000003,umask=0x4 00 Number of times HLE abort was triggered (Precise event) hle_retired.aborted_misc1 memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=0x8 00 Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details) hle_retired.aborted_misc2 memory Number of times an HLE execution aborted due to uncommon conditions event=0xc8,period=2000003,umask=0x10 00 Number of times the TSX watchdog signaled an HLE abort hle_retired.aborted_misc3 memory Number of times an HLE execution aborted due to HLE-unfriendly instructions event=0xc8,period=2000003,umask=0x20 00 Number of times a disallowed operation caused an HLE abort hle_retired.aborted_misc4 memory Number of times an HLE execution aborted due to incompatible memory type event=0xc8,period=2000003,umask=0x40 00 Number of times HLE caused a fault hle_retired.aborted_misc5 memory Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) event=0xc8,period=2000003,umask=0x80 00 Number of times HLE aborted and was not due to the abort conditions in subevents 3-6 hle_retired.commit memory Number of times HLE commit succeeded event=0xc8,period=2000003,umask=0x2 00 Number of times HLE commit succeeded hle_retired.start memory Number of times we entered an HLE region; does not count nested transactions event=0xc8,period=2000003,umask=0x1 00 Number of times we entered an HLE region does not count nested transactions machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=0x2 00 This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer mem_trans_retired.load_latency_gt_128 memory Randomly selected loads with latency value being above 128 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=1009,umask=0x1,ldlat=0x80 00 Counts randomly selected loads with latency value being above 128 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_16 memory Randomly selected loads with latency value being above 16 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=20011,umask=0x1,ldlat=0x10 00 Counts randomly selected loads with latency value being above 16 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_256 memory Randomly selected loads with latency value being above 256 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=503,umask=0x1,ldlat=0x100 00 Counts randomly selected loads with latency value being above 256 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_32 memory Randomly selected loads with latency value being above 32 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=100007,umask=0x1,ldlat=0x20 00 Counts randomly selected loads with latency value being above 32 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_4 memory Randomly selected loads with latency value being above 4 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=100003,umask=0x1,ldlat=0x4 00 Counts randomly selected loads with latency value being above four Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_512 memory Randomly selected loads with latency value being above 512 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=101,umask=0x1,ldlat=0x200 00 Counts randomly selected loads with latency value being above 512 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_64 memory Randomly selected loads with latency value being above 64 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=2003,umask=0x1,ldlat=0x40 00 Counts randomly selected loads with latency value being above 64 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_8 memory Randomly selected loads with latency value being above 8 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=50021,umask=0x1,ldlat=0x8 00 Counts randomly selected loads with latency value being above eight Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=0x5,period=2000003,umask=0x1 00 This event counts speculative cache-line split load uops dispatched to the L1 cache misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=0x5,period=2000003,umask=0x2 00 This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache offcore_response.all_data_rd.l3_hit.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0091 00 offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000091 00 offcore_response.all_data_rd.l3_miss.snoop_miss memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000091 00 offcore_response.all_data_rd.l3_miss.snoop_none memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000091 00 offcore_response.all_data_rd.l3_miss.snoop_not_needed memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000091 00 offcore_response.all_data_rd.l3_miss_local_dram.any_snoop memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_none memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000091 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000091 00 offcore_response.all_data_rd.supplier_none.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020091 00 offcore_response.all_pf_code_rd.l3_hit.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_miss memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_none memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000240 00 offcore_response.all_pf_code_rd.l3_miss.snoop_not_needed memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000240 00 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000240 00 offcore_response.all_pf_code_rd.supplier_none.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020240 00 offcore_response.all_pf_data_rd.l3_hit.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_miss memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_none memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000090 00 offcore_response.all_pf_data_rd.l3_miss.snoop_not_needed memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000090 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000090 00 offcore_response.all_pf_data_rd.supplier_none.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020090 00 offcore_response.all_pf_rfo.l3_hit.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0120 00 offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwd memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000120 00 offcore_response.all_pf_rfo.l3_miss.snoop_miss memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000120 00 offcore_response.all_pf_rfo.l3_miss.snoop_none memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000120 00 offcore_response.all_pf_rfo.l3_miss.snoop_not_needed memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitm memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_needed memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000120 00 offcore_response.all_pf_rfo.supplier_none.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020120 00 offcore_response.all_rfo.l3_hit.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0122 00 offcore_response.all_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000122 00 offcore_response.all_rfo.l3_miss.snoop_miss memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000122 00 offcore_response.all_rfo.l3_miss.snoop_none memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000122 00 offcore_response.all_rfo.l3_miss.snoop_not_needed memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000122 00 offcore_response.all_rfo.l3_miss_local_dram.any_snoop memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_hitm memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_none memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000122 00 offcore_response.all_rfo.supplier_none.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020122 00 offcore_response.corewb.l3_hit.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0008 00 offcore_response.corewb.l3_miss.snoop_hit_no_fwd memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000008 00 offcore_response.corewb.l3_miss.snoop_miss memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000008 00 offcore_response.corewb.l3_miss.snoop_none memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000008 00 offcore_response.corewb.l3_miss.snoop_not_needed memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000008 00 offcore_response.corewb.l3_miss_local_dram.any_snoop memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_hitm memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwd memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_miss memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_none memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000008 00 offcore_response.corewb.l3_miss_local_dram.snoop_not_needed memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000008 00 offcore_response.corewb.supplier_none.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020008 00 offcore_response.demand_code_rd.l3_hit.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0004 00 offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000004 00 offcore_response.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000004 00 offcore_response.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000004 00 offcore_response.demand_code_rd.l3_miss.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000004 00 offcore_response.demand_code_rd.supplier_none.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020004 00 offcore_response.demand_data_rd.l3_hit.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0001 00 offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000001 00 offcore_response.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000001 00 offcore_response.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000001 00 offcore_response.demand_data_rd.l3_miss.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitm memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000001 00 offcore_response.demand_data_rd.supplier_none.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020001 00 offcore_response.demand_rfo.l3_hit.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0002 00 offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000002 00 offcore_response.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000002 00 offcore_response.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000002 00 offcore_response.demand_rfo.l3_miss.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000002 00 offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000002 00 offcore_response.other.l3_hit.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C8000 00 offcore_response.other.l3_miss.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C008000 00 offcore_response.other.l3_miss.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C008000 00 offcore_response.other.l3_miss.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC008000 00 offcore_response.other.l3_miss.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C008000 00 offcore_response.other.l3_miss_local_dram.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84008000 00 offcore_response.other.l3_miss_local_dram.snoop_hitm memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004008000 00 offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404008000 00 offcore_response.other.l3_miss_local_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204008000 00 offcore_response.other.l3_miss_local_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84008000 00 offcore_response.other.l3_miss_local_dram.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004008000 00 offcore_response.other.l3_miss_local_dram.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104008000 00 offcore_response.other.supplier_none.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000028000 00 offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000040 00 offcore_response.pf_l2_code_rd.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000040 00 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000040 00 offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020040 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwd memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_not_needed memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitm memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000010 00 offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020010 00 offcore_response.pf_l2_rfo.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000020 00 offcore_response.pf_l2_rfo.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020020 00 offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwd memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000200 00 offcore_response.pf_l3_code_rd.l3_miss.snoop_not_needed memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitm memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000200 00 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000200 00 offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020200 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000080 00 offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020080 00 offcore_response.pf_l3_rfo.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000100 00 offcore_response.pf_l3_rfo.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020100 00 rtm_retired.aborted memory Number of times RTM abort was triggered (Precise event) event=0xc9,period=2000003,umask=0x4 00 Number of times RTM abort was triggered (Precise event) rtm_retired.aborted_misc1 memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x8 00 Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details) rtm_retired.aborted_misc2 memory Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x10 00 Number of times the TSX watchdog signaled an RTM abort rtm_retired.aborted_misc3 memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20 00 Number of times a disallowed operation caused an RTM abort rtm_retired.aborted_misc4 memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=2000003,umask=0x40 00 Number of times a RTM caused a fault rtm_retired.aborted_misc5 memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80 00 Number of times RTM aborted and was not due to the abort conditions in subevents 3-6 rtm_retired.commit memory Number of times RTM commit succeeded event=0xc9,period=2000003,umask=0x2 00 Number of times RTM commit succeeded rtm_retired.start memory Number of times we entered an RTM region; does not count nested transactions event=0xc9,period=2000003,umask=0x1 00 Number of times we entered an RTM region does not count nested transactions tx_exec.misc1 memory Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort event=0x5d,period=2000003,umask=0x1 00 tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=0x2 00 Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc3 memory Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=2000003,umask=0x4 00 Unfriendly TSX abort triggered by a nest count that is too deep tx_exec.misc4 memory Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region event=0x5d,period=2000003,umask=0x8 00 RTM region detected inside HLE tx_exec.misc5 memory Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region event=0x5d,period=2000003,umask=0x10 00 tx_mem.abort_capacity_write memory Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow event=0x54,period=2000003,umask=0x2 00 Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow tx_mem.abort_conflict memory Number of times a TSX line had a cache conflict event=0x54,period=2000003,umask=0x1 00 Number of times a TSX line had a cache conflict tx_mem.abort_hle_elision_buffer_mismatch memory Number of times a TSX Abort was triggered due to release/commit but data and address mismatch event=0x54,period=2000003,umask=0x10 00 Number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty event=0x54,period=2000003,umask=0x8 00 Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer event=0x54,period=2000003,umask=0x20 00 Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a TSX Abort was triggered due to a non-release/commit store to lock event=0x54,period=2000003,umask=0x4 00 Number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times we could not allocate Lock Buffer event=0x54,period=2000003,umask=0x40 00 Number of times we could not allocate Lock Buffer cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=0x1 00 This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=0x1 00 This event counts when there is a transition from ring 1,2 or 3 to ring0 cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=0x2 00 This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=0x1 00 This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=0x1 00 This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed br_inst_exec.all_branches pipeline Speculative and retired branches event=0x88,period=200003,umask=0xff 00 This event counts both taken and not taken speculative and retired branch instructions br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1 00 This event counts both taken and not taken speculative and retired macro-conditional branch instructions br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2 00 This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0 00 This event counts both taken and not taken speculative and retired direct near calls br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4 00 This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.all_indirect_near_return pipeline Speculative and retired indirect return branches event=0x88,period=200003,umask=0xc8 00 This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41 00 This event counts not taken macro-conditional branch instructions br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81 00 This event counts taken speculative and retired macro-conditional branch instructions br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82 00 This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90 00 This event counts taken speculative and retired direct near calls br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84 00 This event counts taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0 00 This event counts taken speculative and retired indirect calls including both register and memory indirect br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88 00 This event counts taken speculative and retired indirect branches that have a return mnemonic br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009 00 This event counts all (macro) branch instructions retired br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired. (Precise Event - PEBS) Spec update: BDW98 (Must be precise) event=0xc4,period=400009,umask=0x4 00 This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: BDW98 (Must be precise) br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x1 00 This event counts conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Far branch instructions retired Spec update: BDW98 event=0xc4,period=100007,umask=0x40 00 This event counts far branch instructions retired Spec update: BDW98 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=0x2 00 This event counts both direct and indirect near call instructions retired (Precise event) br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100007,umask=0x2 00 This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=0x8 00 This event counts return instructions retired (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 This event counts taken branch instructions retired (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10 00 This event counts not taken branch instructions retired br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff 00 This event counts both taken and not taken speculative and retired mispredicted branch instructions br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1 00 This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4 00 This event counts both taken and not taken mispredicted indirect branches excluding calls and returns br_misp_exec.indirect pipeline Speculative mispredicted indirect branches event=0x89,period=200003,umask=0xe4 00 Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded) br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41 00 This event counts not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81 00 This event counts taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84 00 This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns br_misp_exec.taken_indirect_near_call pipeline Taken speculative and retired mispredicted indirect calls event=0x89,period=200003,umask=0xa0 00 br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88 00 This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 This event counts all mispredicted macro branch instructions retired br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc5,period=400009,umask=0x4 00 This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x1 00 This event counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 Number of near branch instructions retired that were mispredicted and taken (Precise event) br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=100007,umask=0x8 00 This event counts mispredicted return instructions retired (Precise event) cpu_clk_thread_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=100003,umask=0x2 00 cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=0x1 00 This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=0x1 00 cpu_clk_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=100003,umask=0x2 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=0x1 00 Reference cycles when the thread is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=0x1 00 cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.thread_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 cpu_clk_unhalted.thread_p_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 cycle_activity.cycles_l1d_miss pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=2000003,umask=0x8 00 cycle_activity.cycles_l1d_pending pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=2000003,umask=0x8 00 Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=2000003,umask=0x1 00 cycle_activity.cycles_l2_pending pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=2000003,umask=0x1 00 Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache cycle_activity.cycles_ldm_pending pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=2,period=2000003,umask=0x2 00 Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem) cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=2,period=2000003,umask=0x2 00 cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=0x4 00 Counts number of cycles nothing is executed on any execution port cycle_activity.stalls_l1d_miss pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=2000003,umask=0xc 00 cycle_activity.stalls_l1d_pending pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=2000003,umask=0xc 00 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=2000003,umask=0x5 00 cycle_activity.stalls_l2_pending pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=2000003,umask=0x5 00 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands cycle_activity.stalls_ldm_pending pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=6,period=2000003,umask=0x6 00 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=6,period=2000003,umask=0x6 00 cycle_activity.stalls_total pipeline Total execution stalls event=0xa3,cmask=4,period=2000003,umask=0x4 00 ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=0x1 00 This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event Spec update: BDM61 event=0xc0,period=2000003 00 This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: BDM61 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: BDM11, BDM55 (Must be precise) event=0xc0,period=2000003,umask=0x1 00 This is a precise version (that is, uses PEBS) of the event that counts instructions retired Spec update: BDM11, BDM55 (Must be precise) inst_retired.x87 pipeline FP operations retired. X87 FP operations that have no exceptions: event=0xc0,period=2000003,umask=0x2 00 This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling int_misc.rat_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xd,period=2000003,umask=0x8 00 This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,cmask=1,period=2000003,umask=0x3 00 Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,cmask=1,period=2000003,umask=0x3 00 ld_blocks.no_sr pipeline This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=0x3,period=100003,umask=0x8 00 ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=0x3,period=100003,umask=0x2 00 This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: - preceding store conflicts with the load (incomplete overlap); - store forwarding is impossible due to u-arch limitations; - preceding lock RMW operations are not forwarded; - store has the no-forward bit set (uncacheable/page-split/masked stores); - all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare event=0x7,period=100003,umask=0x1 00 This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=0x2 00 This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=0x1 00 This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=4,period=2000003,umask=0x1 00 lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=0x1 00 lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=0x1 00 machine_clears.count pipeline Number of machine clears (nukes) of any type event=0xc3,cmask=1,edge=1,period=100003,umask=0x1 00 machine_clears.cycles pipeline Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes event=0xc3,period=2000003,umask=0x1 00 This event counts both thread-specific (TS) and all-thread (AT) nukes machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20 00 Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=0x4 00 This event counts self-modifying code (SMC) detected, which causes a machine clear move_elimination.int_eliminated pipeline Number of integer Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=0x1 00 move_elimination.int_not_eliminated pipeline Number of integer Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=0x4 00 other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x40 00 resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=0x1 00 This event counts resource-related stall cycles resource_stalls.rob pipeline Cycles stalled due to re-order buffer full event=0xa2,period=2000003,umask=0x10 00 This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.rs pipeline Cycles stalled due to no eligible RS entry available event=0xa2,period=2000003,umask=0x4 00 This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=0x8 00 This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20 00 This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=0x1 00 This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=200003,umask=0x1 00 uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=0x1 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=0x2 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=0x4 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=0x8 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=0x2 00 Number of uops executed from any thread uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=0x2 00 uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=0x2 00 uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=0x2 00 uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=0x2 00 uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,inv=1,period=2000003,umask=0x2 00 uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=0x1 00 uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=0x1 00 uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=0x1 00 uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=0x1 00 uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=0x1 00 This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=0x1 00 Number of uops to be executed per-thread each cycle uops_executed_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=0x1 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 uops_executed_port.port_0_core pipeline Cycles per core when uops are executed in port 0 event=0xa1,any=1,period=2000003,umask=0x1 00 uops_executed_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=0x2 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 uops_executed_port.port_1_core pipeline Cycles per core when uops are executed in port 1 event=0xa1,any=1,period=2000003,umask=0x2 00 uops_executed_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=0x4 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 uops_executed_port.port_2_core pipeline Cycles per core when uops are dispatched to port 2 event=0xa1,any=1,period=2000003,umask=0x4 00 uops_executed_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=0x8 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 uops_executed_port.port_3_core pipeline Cycles per core when uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=0x8 00 uops_executed_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_executed_port.port_4_core pipeline Cycles per core when uops are executed in port 4 event=0xa1,any=1,period=2000003,umask=0x10 00 uops_executed_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_executed_port.port_5_core pipeline Cycles per core when uops are executed in port 5 event=0xa1,any=1,period=2000003,umask=0x20 00 uops_executed_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_executed_port.port_6_core pipeline Cycles per core when uops are executed in port 6 event=0xa1,any=1,period=2000003,umask=0x40 00 uops_executed_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 uops_executed_port.port_7_core pipeline Cycles per core when uops are dispatched to port 7 event=0xa1,any=1,period=2000003,umask=0x80 00 uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=0x1 00 This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) uops_issued.flags_merge pipeline Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch event=0xe,period=2000003,umask=0x10 00 Number of flags-merge uops being allocated. Such uops considered perf sensitive added by GSR u-arch uops_issued.single_mul pipeline Number of Multiply packed/scalar single precision uops allocated event=0xe,period=2000003,umask=0x40 00 uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20 00 uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=0x1 00 This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=0x1 00 This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight (Precise event) uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=0x2 00 This event counts the number of retirement slots used (Precise event) uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=0x1 00 This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=0x1 00 Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event unc_cbo_cache_lookup.any_es uncore cache L3 Lookup any request that access cache and found line in E or S-state event=0x34,umask=0x86 01 L3 Lookup any request that access cache and found line in E or S-state unc_cbo_cache_lookup.any_i uncore cache L3 Lookup any request that access cache and found line in I-state event=0x34,umask=0x88 01 L3 Lookup any request that access cache and found line in I-state unc_cbo_cache_lookup.any_m uncore cache L3 Lookup any request that access cache and found line in M-state event=0x34,umask=0x81 01 L3 Lookup any request that access cache and found line in M-state unc_cbo_cache_lookup.any_mesi uncore cache L3 Lookup any request that access cache and found line in MESI-state event=0x34,umask=0x8f 01 L3 Lookup any request that access cache and found line in MESI-state unc_cbo_cache_lookup.read_es uncore cache L3 Lookup read request that access cache and found line in E or S-state event=0x34,umask=0x16 01 L3 Lookup read request that access cache and found line in E or S-state unc_cbo_cache_lookup.read_i uncore cache L3 Lookup read request that access cache and found line in I-state event=0x34,umask=0x18 01 L3 Lookup read request that access cache and found line in I-state unc_cbo_cache_lookup.read_m uncore cache L3 Lookup read request that access cache and found line in M-state event=0x34,umask=0x11 01 L3 Lookup read request that access cache and found line in M-state unc_cbo_cache_lookup.read_mesi uncore cache L3 Lookup read request that access cache and found line in any MESI-state event=0x34,umask=0x1f 01 L3 Lookup read request that access cache and found line in any MESI-state unc_cbo_cache_lookup.write_es uncore cache L3 Lookup write request that access cache and found line in E or S-state event=0x34,umask=0x26 01 L3 Lookup write request that access cache and found line in E or S-state unc_cbo_cache_lookup.write_m uncore cache L3 Lookup write request that access cache and found line in M-state event=0x34,umask=0x21 01 L3 Lookup write request that access cache and found line in M-state unc_cbo_cache_lookup.write_mesi uncore cache L3 Lookup write request that access cache and found line in MESI-state event=0x34,umask=0x2f 01 L3 Lookup write request that access cache and found line in MESI-state unc_cbo_xsnp_response.hitm_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core event=0x22,umask=0x48 01 unc_cbo_xsnp_response.hit_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core event=0x22,umask=0x44 01 unc_cbo_xsnp_response.miss_eviction uncore cache A cross-core snoop resulted from L3 Eviction which misses in some processor core event=0x22,umask=0x81 01 unc_cbo_xsnp_response.miss_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core event=0x22,umask=0x41 01 unc_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc event=0x84,umask=0x1 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic event=0x80,umask=0x1 01 unc_arb_trk_occupancy.cycles_with_any_request uncore interconnect Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.; event=0x80,cmask=1,umask=0x1 01 unc_arb_trk_occupancy.drd_direct uncore interconnect Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case event=0x80,umask=0x2 01 Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case unc_arb_trk_requests.all uncore interconnect Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=0x1 01 unc_arb_trk_requests.drd_direct uncore interconnect Number of Core coherent Data Read entries allocated in DirectData mode event=0x81,umask=0x2 01 Number of Core coherent Data Read entries allocated in DirectData mode unc_arb_trk_requests.writes uncore interconnect Number of Writes allocated - any write transactions: full/partials writes and evictions event=0x81,umask=0x20 01 unc_clock.socket uncore other This 48-bit fixed counter counts the UCLK cycles event=0xff 01 This 48-bit fixed counter counts the UCLK cycles dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks Spec update: BDM69 event=0x8,period=100003,umask=0x1 00 This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=0x8,period=2000003,umask=0x60 00 dtlb_load_misses.stlb_hit_2m virtual memory Load misses that miss the DTLB and hit the STLB (2M) event=0x8,period=2000003,umask=0x40 00 dtlb_load_misses.stlb_hit_4k virtual memory Load misses that miss the DTLB and hit the STLB (4K) event=0x8,period=2000003,umask=0x20 00 dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size Spec update: BDM69 event=0x8,period=100003,umask=0xe 00 dtlb_load_misses.walk_completed_1g virtual memory Load miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 event=0x8,period=2000003,umask=0x8 00 This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_completed_2m_4m virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Spec update: BDM69 event=0x8,period=2000003,umask=0x4 00 This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_completed_4k virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) Spec update: BDM69 event=0x8,period=2000003,umask=0x2 00 This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks Spec update: BDM69 event=0x8,period=2000003,umask=0x10 00 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks Spec update: BDM69 event=0x49,period=100003,umask=0x1 00 This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x60 00 dtlb_store_misses.stlb_hit_2m virtual memory Store misses that miss the DTLB and hit the STLB (2M) event=0x49,period=100003,umask=0x40 00 dtlb_store_misses.stlb_hit_4k virtual memory Store misses that miss the DTLB and hit the STLB (4K) event=0x49,period=100003,umask=0x20 00 dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks Spec update: BDM69 event=0x49,period=100003,umask=0xe 00 dtlb_store_misses.walk_completed_1g virtual memory Store misses in all DTLB levels that cause completed page walks (1G) Spec update: BDM69 event=0x49,period=100003,umask=0x8 00 This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed_2m_4m virtual memory Store misses in all DTLB levels that cause completed page walks (2M/4M) Spec update: BDM69 event=0x49,period=100003,umask=0x4 00 This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed_4k virtual memory Store miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 event=0x49,period=100003,umask=0x2 00 This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks Spec update: BDM69 event=0x49,period=100003,umask=0x10 00 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 ept.walk_cycles virtual memory Cycle count for an Extended Page table walk event=0x4f,period=2000003,umask=0x10 00 This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=0x1 00 This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks Spec update: BDM69 event=0x85,period=100003,umask=0x1 00 This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x60 00 itlb_misses.stlb_hit_2m virtual memory Code misses that miss the DTLB and hit the STLB (2M) event=0x85,period=100003,umask=0x40 00 itlb_misses.stlb_hit_4k virtual memory Core misses that miss the DTLB and hit the STLB (4K) event=0x85,period=100003,umask=0x20 00 itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks Spec update: BDM69 event=0x85,period=100003,umask=0xe 00 itlb_misses.walk_completed_1g virtual memory Store miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 event=0x85,period=100003,umask=0x8 00 This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) Spec update: BDM69 event=0x85,period=100003,umask=0x4 00 This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 event=0x85,period=100003,umask=0x2 00 This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks Spec update: BDM69 event=0x85,period=100003,umask=0x10 00 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 page_walker_loads.dtlb_l1 virtual memory Number of DTLB page walker hits in the L1+FB Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x11 00 page_walker_loads.dtlb_l2 virtual memory Number of DTLB page walker hits in the L2 Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x12 00 page_walker_loads.dtlb_l3 virtual memory Number of DTLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x14 00 page_walker_loads.dtlb_memory virtual memory Number of DTLB page walker hits in Memory Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x18 00 page_walker_loads.itlb_l1 virtual memory Number of ITLB page walker hits in the L1+FB Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x21 00 page_walker_loads.itlb_l2 virtual memory Number of ITLB page walker hits in the L2 Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x22 00 page_walker_loads.itlb_l3 virtual memory Number of ITLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x24 00 tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=0x1 00 This event counts the number of DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on) mem_load_uops_l3_miss_retired.remote_dram cache Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=0x4 00 mem_load_uops_l3_miss_retired.remote_fwd cache Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=0x20 00 mem_load_uops_l3_miss_retired.remote_hitm cache Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=0x10 00 unc_c_bounce_control uncore cache Bounce Control event=0xa 01 unc_c_clockticks uncore cache Uncore Clocks event=0 01 unc_c_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f 01 Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_c_fast_asserted uncore cache FaST wire asserted event=0x9 01 Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn unc_c_llc_lookup.any uncore cache Cache Lookups; Any Request event=0x34,umask=0x11 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=0x3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions unc_c_llc_lookup.nid uncore cache Cache Lookups; Lookups that Match NID event=0x34,umask=0x41 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_llc_lookup.read uncore cache Cache Lookups; Any Read Request event=0x34,umask=0x21 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=0x9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=0x5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_c_llc_victims.e_state uncore cache Lines Victimized; Lines in E state event=0x37,umask=0x2 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.f_state uncore cache Lines Victimized event=0x37,umask=0x8 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.i_state uncore cache Lines Victimized; Lines in S State event=0x37,umask=0x4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.miss uncore cache Lines Victimized event=0x37,umask=0x10 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.m_state uncore cache Lines Victimized; Lines in M state event=0x37,umask=0x1 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.nid uncore cache Lines Victimized; Victimized Lines that Match NID event=0x37,umask=0x40 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_misc.cvzero_prefetch_miss uncore cache Cbo Misc; DRd hitting non-M with raw CV=0 event=0x39,umask=0x20 01 Miscellaneous events in the Cbo unc_c_misc.cvzero_prefetch_victim uncore cache Cbo Misc; Clean Victim with raw CV=0 event=0x39,umask=0x10 01 Miscellaneous events in the Cbo unc_c_misc.rfo_hit_s uncore cache Cbo Misc; RFO HitS event=0x39,umask=0x8 01 Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB unc_c_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=0x1 01 Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings unc_c_misc.started uncore cache Cbo Misc event=0x39,umask=0x4 01 Miscellaneous events in the Cbo unc_c_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=0x2 01 Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing unc_c_qlru.age0 uncore cache LRU Queue; LRU Age 0 event=0x3c,umask=0x1 01 How often age was set to 0 unc_c_qlru.age1 uncore cache LRU Queue; LRU Age 1 event=0x3c,umask=0x2 01 How often age was set to 1 unc_c_qlru.age2 uncore cache LRU Queue; LRU Age 2 event=0x3c,umask=0x4 01 How often age was set to 2 unc_c_qlru.age3 uncore cache LRU Queue; LRU Age 3 event=0x3c,umask=0x8 01 How often age was set to 3 unc_c_qlru.lru_decrement uncore cache LRU Queue; LRU Bits Decremented event=0x3c,umask=0x10 01 How often all LRU bits were decremented by 1 unc_c_qlru.victim_non_zero uncore cache LRU Queue; Non-0 Aged Victim event=0x3c,umask=0x20 01 How often we picked a victim that had a non-zero age unc_c_ring_ad_used.all uncore cache AD Ring In Use; All event=0x1b,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.ccw uncore cache AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.cw uncore cache AD Ring In Use; Up event=0x1b,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_ak_used.all uncore cache AK Ring In Use; All event=0x1c,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.ccw uncore cache AK Ring In Use; Down event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.cw uncore cache AK Ring In Use; Up event=0x1c,umask=0x3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bl_used.all uncore cache BL Ring in Use; Down event=0x1d,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.ccw uncore cache BL Ring in Use; Down event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.cw uncore cache BL Ring in Use; Up event=0x1d,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bounces.ad uncore cache Number of LLC responses that bounced on the Ring.; AD event=0x5,umask=0x1 01 unc_c_ring_bounces.ak uncore cache Number of LLC responses that bounced on the Ring.; AK event=0x5,umask=0x2 01 unc_c_ring_bounces.bl uncore cache Number of LLC responses that bounced on the Ring.; BL event=0x5,umask=0x4 01 unc_c_ring_bounces.iv uncore cache Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=0x5,umask=0x10 01 unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.dn uncore cache BL Ring in Use; Any event=0x1e,umask=0xc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.down uncore cache BL Ring in Use; Down event=0x1e,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache BL Ring in Use; Any event=0x1e,umask=0x3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_sink_starved.ad uncore cache AD event=0x6,umask=0x1 01 unc_c_ring_sink_starved.ak uncore cache AK event=0x6,umask=0x2 01 unc_c_ring_sink_starved.bl uncore cache BL event=0x6,umask=0x4 01 unc_c_ring_sink_starved.iv uncore cache IV event=0x6,umask=0x8 01 unc_c_ring_src_thrtl uncore cache Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic event=0x7 01 unc_c_rxr_ext_starved.ipq uncore cache Ingress Arbiter Blocking Cycles; IRQ event=0x12,umask=0x2 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ unc_c_rxr_ext_starved.irq uncore cache Ingress Arbiter Blocking Cycles; IPQ event=0x12,umask=0x1 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ unc_c_rxr_ext_starved.ismq_bids uncore cache Ingress Arbiter Blocking Cycles; ISMQ_BID event=0x12,umask=0x8 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid unc_c_rxr_ext_starved.prq uncore cache Ingress Arbiter Blocking Cycles; PRQ event=0x12,umask=0x4 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_inserts.ipq uncore cache Ingress Allocations; IPQ event=0x13,umask=0x4 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.irq uncore cache Ingress Allocations; IRQ event=0x13,umask=0x1 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.irq_rej uncore cache Ingress Allocations; IRQ Rejected event=0x13,umask=0x2 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.prq uncore cache Ingress Allocations; PRQ event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.prq_rej uncore cache Ingress Allocations; PRQ event=0x13,umask=0x20 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_int_starved.ipq uncore cache Ingress Internal Starvation Cycles; IPQ event=0x14,umask=0x4 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation unc_c_rxr_int_starved.irq uncore cache Ingress Internal Starvation Cycles; IRQ event=0x14,umask=0x1 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation unc_c_rxr_int_starved.ismq uncore cache Ingress Internal Starvation Cycles; ISMQ event=0x14,umask=0x8 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation unc_c_rxr_int_starved.prq uncore cache Ingress Internal Starvation Cycles; PRQ event=0x14,umask=0x10 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_ipq_retry.addr_conflict uncore cache Probe Queue Retries; Address Conflict event=0x31,umask=0x4 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics unc_c_rxr_ipq_retry.any uncore cache Probe Queue Retries; Any Reject event=0x31,umask=0x1 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts unc_c_rxr_ipq_retry.full uncore cache Probe Queue Retries; No Egress Credits event=0x31,umask=0x2 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits unc_c_rxr_ipq_retry.qpi_credits uncore cache Probe Queue Retries; No QPI Credits event=0x31,umask=0x10 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry2.ad_sbo uncore cache Probe Queue Retries; No AD Sbo Credits event=0x28,umask=0x1 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_ipq_retry2.target uncore cache Probe Queue Retries; Target Node Filter event=0x28,umask=0x40 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_irq_retry.addr_conflict uncore cache Ingress Request Queue Rejects; Address Conflict event=0x32,umask=0x4 01 Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled unc_c_rxr_irq_retry.any uncore cache Ingress Request Queue Rejects; Any Reject event=0x32,umask=0x1 01 Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request unc_c_rxr_irq_retry.full uncore cache Ingress Request Queue Rejects; No Egress Credits event=0x32,umask=0x2 01 Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried unc_c_rxr_irq_retry.iio_credits uncore cache Ingress Request Queue Rejects; No IIO Credits event=0x32,umask=0x20 01 Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO unc_c_rxr_irq_retry.nid uncore cache Ingress Request Queue Rejects event=0x32,umask=0x40 01 Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_irq_retry.qpi_credits uncore cache Ingress Request Queue Rejects; No QPI Credits event=0x32,umask=0x10 01 Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information unc_c_rxr_irq_retry.rtid uncore cache Ingress Request Queue Rejects; No RTIDs event=0x32,umask=0x8 01 Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case unc_c_rxr_irq_retry2.ad_sbo uncore cache Ingress Request Queue Rejects; No AD Sbo Credits event=0x29,umask=0x1 01 Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_irq_retry2.bl_sbo uncore cache Ingress Request Queue Rejects; No BL Sbo Credits event=0x29,umask=0x2 01 Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo unc_c_rxr_irq_retry2.target uncore cache Ingress Request Queue Rejects; Target Node Filter event=0x29,umask=0x40 01 Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_ismq_retry.any uncore cache ISMQ Retries; Any Reject event=0x33,umask=0x1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here unc_c_rxr_ismq_retry.full uncore cache ISMQ Retries; No Egress Credits event=0x33,umask=0x2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried unc_c_rxr_ismq_retry.iio_credits uncore cache ISMQ Retries; No IIO Credits event=0x33,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO unc_c_rxr_ismq_retry.nid uncore cache ISMQ Retries event=0x33,umask=0x40 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_ismq_retry.qpi_credits uncore cache ISMQ Retries; No QPI Credits event=0x33,umask=0x10 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.rtid uncore cache ISMQ Retries; No RTIDs event=0x33,umask=0x8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried unc_c_rxr_ismq_retry.wb_credits uncore cache ISMQ Retries event=0x33,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_ismq_retry2.ad_sbo uncore cache ISMQ Request Queue Rejects; No AD Sbo Credits event=0x2a,umask=0x1 01 Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_ismq_retry2.bl_sbo uncore cache ISMQ Request Queue Rejects; No BL Sbo Credits event=0x2a,umask=0x2 01 Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo unc_c_rxr_ismq_retry2.target uncore cache ISMQ Request Queue Rejects; Target Node Filter event=0x2a,umask=0x40 01 Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_occupancy.ipq uncore cache Ingress Occupancy; IPQ event=0x11,umask=0x4 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.irq uncore cache Ingress Occupancy; IRQ event=0x11,umask=0x1 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.irq_rej uncore cache Ingress Occupancy; IRQ Rejected event=0x11,umask=0x2 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.prq_rej uncore cache Ingress Occupancy; PRQ Rejects event=0x11,umask=0x20 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_sbo_credits_acquired.ad uncore cache SBo Credits Acquired; For AD Ring event=0x3d,umask=0x1 01 Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credits_acquired.bl uncore cache SBo Credits Acquired; For BL Ring event=0x3d,umask=0x2 01 Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credit_occupancy.ad uncore cache SBo Credits Occupancy; For AD Ring event=0x3e,umask=0x1 01 Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credit_occupancy.bl uncore cache SBo Credits Occupancy; For BL Ring event=0x3e,umask=0x2 01 Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with unc_c_tor_inserts.all uncore cache TOR Inserts; All event=0x35,umask=0x8 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots unc_c_tor_inserts.eviction uncore cache TOR Inserts; Evictions event=0x35,umask=0x4 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory) unc_c_tor_inserts.local uncore cache TOR Inserts; Local Memory event=0x35,umask=0x28 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.local_opcode uncore cache TOR Inserts; Local Memory - Opcode Matched event=0x35,umask=0x21 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_local uncore cache TOR Inserts; Misses to Local Memory event=0x35,umask=0x2a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_local_opcode uncore cache TOR Inserts; Misses to Local Memory - Opcode Matched event=0x35,umask=0x23 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_opcode uncore cache TOR Inserts; Miss Opcode Match event=0x35,umask=0x3 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode unc_c_tor_inserts.miss_remote uncore cache TOR Inserts; Misses to Remote Memory event=0x35,umask=0x8a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.miss_remote_opcode uncore cache TOR Inserts; Misses to Remote Memory - Opcode Matched event=0x35,umask=0x83 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.nid_all uncore cache TOR Inserts; NID Matched event=0x35,umask=0x48 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_tor_inserts.nid_eviction uncore cache TOR Inserts; NID Matched Evictions event=0x35,umask=0x44 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR unc_c_tor_inserts.nid_miss_all uncore cache TOR Inserts; NID Matched Miss All event=0x35,umask=0x4a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR unc_c_tor_inserts.nid_miss_opcode uncore cache TOR Inserts; NID and Opcode Matched Miss event=0x35,umask=0x43 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode unc_c_tor_inserts.nid_opcode uncore cache TOR Inserts; NID and Opcode Matched event=0x35,umask=0x41 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode unc_c_tor_inserts.nid_wb uncore cache TOR Inserts; NID Matched Writebacks event=0x35,umask=0x50 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR unc_c_tor_inserts.opcode uncore cache TOR Inserts; Opcode Match event=0x35,umask=0x1 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_tor_inserts.remote uncore cache TOR Inserts; Remote Memory event=0x35,umask=0x88 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.remote_opcode uncore cache TOR Inserts; Remote Memory - Opcode Matched event=0x35,umask=0x81 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.wb uncore cache TOR Inserts; Writebacks event=0x35,umask=0x10 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core unc_c_tor_occupancy.all uncore cache TOR Occupancy; Any event=0x36,umask=0x8 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots unc_c_tor_occupancy.eviction uncore cache TOR Occupancy; Evictions event=0x36,umask=0x4 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory) unc_c_tor_occupancy.local uncore cache TOR Occupancy event=0x36,umask=0x28 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.local_opcode uncore cache TOR Occupancy; Local Memory - Opcode Matched event=0x36,umask=0x21 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory unc_c_tor_occupancy.miss_all uncore cache TOR Occupancy; Miss All event=0x36,umask=0xa 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO unc_c_tor_occupancy.miss_local uncore cache TOR Occupancy event=0x36,umask=0x2a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_local_opcode uncore cache TOR Occupancy; Misses to Local Memory - Opcode Matched event=0x36,umask=0x23 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory unc_c_tor_occupancy.miss_opcode uncore cache TOR Occupancy; Miss Opcode Match event=0x36,umask=0x3 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO unc_c_tor_occupancy.miss_remote uncore cache TOR Occupancy event=0x36,umask=0x8a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_remote_opcode uncore cache TOR Occupancy; Misses to Remote Memory - Opcode Matched event=0x36,umask=0x83 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory unc_c_tor_occupancy.nid_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x48 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_tor_occupancy.nid_eviction uncore cache TOR Occupancy; NID Matched Evictions event=0x36,umask=0x44 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR unc_c_tor_occupancy.nid_miss_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x4a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID unc_c_tor_occupancy.nid_miss_opcode uncore cache TOR Occupancy; NID and Opcode Matched Miss event=0x36,umask=0x43 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode unc_c_tor_occupancy.nid_opcode uncore cache TOR Occupancy; NID and Opcode Matched event=0x36,umask=0x41 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode unc_c_tor_occupancy.nid_wb uncore cache TOR Occupancy; NID Matched Writebacks event=0x36,umask=0x50 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR unc_c_tor_occupancy.opcode uncore cache TOR Occupancy; Opcode Match event=0x36,umask=0x1 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_tor_occupancy.remote uncore cache TOR Occupancy event=0x36,umask=0x88 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.remote_opcode uncore cache TOR Occupancy; Remote Memory - Opcode Matched event=0x36,umask=0x81 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory unc_c_tor_occupancy.wb uncore cache TOR Occupancy; Writebacks event=0x36,umask=0x10 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core unc_c_txr_ads_used.ad uncore cache Onto AD Ring event=0x4,umask=0x1 01 unc_c_txr_ads_used.ak uncore cache Onto AK Ring event=0x4,umask=0x2 01 unc_c_txr_ads_used.bl uncore cache Onto BL Ring event=0x4,umask=0x4 01 unc_c_txr_inserts.ad_cache uncore cache Egress Allocations; AD - Cachebo event=0x2,umask=0x1 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_c_txr_inserts.ad_core uncore cache Egress Allocations; AD - Corebo event=0x2,umask=0x10 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests unc_c_txr_inserts.ak_cache uncore cache Egress Allocations; AK - Cachebo event=0x2,umask=0x2 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses unc_c_txr_inserts.ak_core uncore cache Egress Allocations; AK - Corebo event=0x2,umask=0x20 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo unc_c_txr_inserts.bl_cache uncore cache Egress Allocations; BL - Cacheno event=0x2,umask=0x4 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_c_txr_inserts.bl_core uncore cache Egress Allocations; BL - Corebo event=0x2,umask=0x40 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_c_txr_inserts.iv_cache uncore cache Egress Allocations; IV - Cachebo event=0x2,umask=0x8 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores unc_c_txr_starved.ad_core uncore cache Injection Starvation; Onto AD Ring (to core) event=0x3,umask=0x10 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation unc_c_txr_starved.ak_both uncore cache Injection Starvation; Onto AK Ring event=0x3,umask=0x2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation unc_c_txr_starved.bl_both uncore cache Injection Starvation; Onto BL Ring event=0x3,umask=0x4 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation unc_c_txr_starved.iv uncore cache Injection Starvation; Onto IV Ring event=0x3,umask=0x8 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation uncore_ha unc_h_bt_cycles_ne uncore cache BT Cycles Not Empty event=0x42 01 Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_to_ht_not_issued.incoming_bl_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=0x4 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bt_to_ht_not_issued.incoming_snp_hazard uncore cache BT to HT Not Issued; Incoming Snoop Hazard event=0x51,umask=0x2 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard unc_h_bt_to_ht_not_issued.rspackcflt_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=0x8 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bt_to_ht_not_issued.wbmdata_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=0x10 01 Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bypass_imc.not_taken uncore cache HA to iMC Bypass; Not Taken event=0x14,umask=0x2 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass unc_h_bypass_imc.taken uncore cache HA to iMC Bypass; Taken event=0x14,umask=0x1 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass unc_h_clockticks uncore cache uclks event=0 01 Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent unc_h_direct2core_count uncore cache Direct2Core Messages Sent event=0x11 01 Number of Direct2Core messages sent unc_h_direct2core_cycles_disabled uncore cache Cycles when Direct2Core was Disabled event=0x12 01 Number of cycles in which Direct2Core was disabled unc_h_direct2core_txn_override uncore cache Number of Reads that had Direct2Core Overridden event=0x13 01 Number of Reads where Direct2Core overridden unc_h_directory_lat_opt uncore cache Directory Lat Opt Return event=0x41 01 Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc) unc_h_directory_lookup.no_snp uncore cache Directory Lookups; Snoop Not Needed event=0xc,umask=0x2 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear unc_h_directory_lookup.snp uncore cache Directory Lookups; Snoop Needed event=0xc,umask=0x1 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set unc_h_directory_update.any uncore cache Directory Updates; Any Directory Update event=0xd,umask=0x3 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.clear uncore cache Directory Updates; Directory Clear event=0xd,umask=0x2 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory clears. This occurs when snoops were sent and all returned with RspI unc_h_directory_update.set uncore cache Directory Updates; Directory Set event=0xd,umask=0x1 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory sets. This occurs when a remote read transaction requests memory, bringing it to a remote cache unc_h_hitme_hit.ackcnfltwbi uncore cache Counts Number of Hits in HitMe Cache; op is AckCnfltWbI event=0x71,umask=0x4 01 unc_h_hitme_hit.all uncore cache Counts Number of Hits in HitMe Cache; All Requests event=0x71,umask=0xff 01 unc_h_hitme_hit.allocs uncore cache Counts Number of Hits in HitMe Cache; Allocations event=0x71,umask=0x70 01 unc_h_hitme_hit.evicts uncore cache Counts Number of Hits in HitMe Cache; Allocations event=0x71,umask=0x42 01 unc_h_hitme_hit.hom uncore cache Counts Number of Hits in HitMe Cache; HOM Requests event=0x71,umask=0xf 01 unc_h_hitme_hit.invals uncore cache Counts Number of Hits in HitMe Cache; Invalidations event=0x71,umask=0x26 01 unc_h_hitme_hit.read_or_invitoe uncore cache Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x71,umask=0x1 01 unc_h_hitme_hit.rsp uncore cache Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x71,umask=0x80 01 unc_h_hitme_hit.rspfwdi_local uncore cache Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request event=0x71,umask=0x20 01 unc_h_hitme_hit.rspfwdi_remote uncore cache Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request event=0x71,umask=0x10 01 unc_h_hitme_hit.rspfwds uncore cache Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb event=0x71,umask=0x40 01 unc_h_hitme_hit.wbmtoe_or_s uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS event=0x71,umask=0x8 01 unc_h_hitme_hit.wbmtoi uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoI event=0x71,umask=0x2 01 unc_h_hitme_hit_pv_bits_set.ackcnfltwbi uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI event=0x72,umask=0x4 01 unc_h_hitme_hit_pv_bits_set.all uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; All Requests event=0x72,umask=0xff 01 unc_h_hitme_hit_pv_bits_set.hom uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests event=0x72,umask=0xf 01 unc_h_hitme_hit_pv_bits_set.read_or_invitoe uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x72,umask=0x1 01 unc_h_hitme_hit_pv_bits_set.rsp uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x72,umask=0x80 01 unc_h_hitme_hit_pv_bits_set.rspfwdi_local uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request event=0x72,umask=0x20 01 unc_h_hitme_hit_pv_bits_set.rspfwdi_remote uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request event=0x72,umask=0x10 01 unc_h_hitme_hit_pv_bits_set.rspfwds uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb event=0x72,umask=0x40 01 unc_h_hitme_hit_pv_bits_set.wbmtoe_or_s uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS event=0x72,umask=0x8 01 unc_h_hitme_hit_pv_bits_set.wbmtoi uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI event=0x72,umask=0x2 01 unc_h_hitme_lookup.ackcnfltwbi uncore cache Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI event=0x70,umask=0x4 01 unc_h_hitme_lookup.all uncore cache Counts Number of times HitMe Cache is accessed; All Requests event=0x70,umask=0xff 01 unc_h_hitme_lookup.allocs uncore cache Counts Number of times HitMe Cache is accessed; Allocations event=0x70,umask=0x70 01 unc_h_hitme_lookup.hom uncore cache Counts Number of times HitMe Cache is accessed; HOM Requests event=0x70,umask=0xf 01 unc_h_hitme_lookup.invals uncore cache Counts Number of times HitMe Cache is accessed; Invalidations event=0x70,umask=0x26 01 unc_h_hitme_lookup.read_or_invitoe uncore cache Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x70,umask=0x1 01 unc_h_hitme_lookup.rsp uncore cache Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x70,umask=0x80 01 unc_h_hitme_lookup.rspfwdi_local uncore cache Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request event=0x70,umask=0x20 01 unc_h_hitme_lookup.rspfwdi_remote uncore cache Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request event=0x70,umask=0x10 01 unc_h_hitme_lookup.rspfwds uncore cache Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb event=0x70,umask=0x40 01 unc_h_hitme_lookup.wbmtoe_or_s uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS event=0x70,umask=0x8 01 unc_h_hitme_lookup.wbmtoi uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoI event=0x70,umask=0x2 01 unc_h_igr_no_credit_cycles.ad_qpi0 uncore cache Cycles without QPI Ingress Credits; AD to QPI Link 0 event=0x22,umask=0x1 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.ad_qpi1 uncore cache Cycles without QPI Ingress Credits; AD to QPI Link 1 event=0x22,umask=0x2 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.ad_qpi2 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 0 event=0x22,umask=0x10 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi0 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 0 event=0x22,umask=0x4 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi1 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 1 event=0x22,umask=0x8 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi2 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 1 event=0x22,umask=0x20 01 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links unc_h_imc_reads.normal uncore cache HA to iMC Normal Priority Reads Issued; Normal Priority event=0x17,umask=0x1 01 Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads unc_h_imc_retry uncore cache Retry Events event=0x1e 01 unc_h_imc_writes.all uncore cache HA to iMC Full Line Writes Issued; All Writes event=0x1a,umask=0xf 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.full uncore cache HA to iMC Full Line Writes Issued; Full Line Non-ISOCH event=0x1a,umask=0x1 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.full_isoch uncore cache HA to iMC Full Line Writes Issued; ISOCH Full Line event=0x1a,umask=0x4 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.partial uncore cache HA to iMC Full Line Writes Issued; Partial Non-ISOCH event=0x1a,umask=0x2 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.partial_isoch uncore cache HA to iMC Full Line Writes Issued; ISOCH Partial event=0x1a,umask=0x8 01 Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_iot_backpressure.hub uncore cache IOT Backpressure event=0x61,umask=0x2 01 unc_h_iot_backpressure.sat uncore cache IOT Backpressure event=0x61,umask=0x1 01 unc_h_iot_cts_east_lo.cts0 uncore cache IOT Common Trigger Sequencer - Lo event=0x64,umask=0x1 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_east_lo.cts1 uncore cache IOT Common Trigger Sequencer - Lo event=0x64,umask=0x2 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_hi.cts2 uncore cache IOT Common Trigger Sequencer - Hi event=0x65,umask=0x1 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_hi.cts3 uncore cache IOT Common Trigger Sequencer - Hi event=0x65,umask=0x2 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_west_lo.cts0 uncore cache IOT Common Trigger Sequencer - Lo event=0x62,umask=0x1 01 Debug Mask/Match Tie-Ins unc_h_iot_cts_west_lo.cts1 uncore cache IOT Common Trigger Sequencer - Lo event=0x62,umask=0x2 01 Debug Mask/Match Tie-Ins unc_h_osb.cancelled uncore cache OSB Snoop Broadcast; Cancelled event=0x53,umask=0x10 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring unc_h_osb.invitoe_local uncore cache OSB Snoop Broadcast; Local InvItoE event=0x53,umask=0x4 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.reads_local uncore cache OSB Snoop Broadcast; Local Reads event=0x53,umask=0x2 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.reads_local_useful uncore cache OSB Snoop Broadcast; Reads Local - Useful event=0x53,umask=0x20 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.remote uncore cache OSB Snoop Broadcast; Remote event=0x53,umask=0x8 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.remote_useful uncore cache OSB Snoop Broadcast; Remote - Useful event=0x53,umask=0x40 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb_edr.all uncore cache OSB Early Data Return; All event=0x54,umask=0x1 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_local_i uncore cache OSB Early Data Return; Reads to Local I event=0x54,umask=0x2 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_local_s uncore cache OSB Early Data Return; Reads to Local S event=0x54,umask=0x8 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_remote_i uncore cache OSB Early Data Return; Reads to Remote I event=0x54,umask=0x4 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_remote_s uncore cache OSB Early Data Return; Reads to Remote S event=0x54,umask=0x10 01 Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_requests.invitoe_local uncore cache Read and Write Requests; Local InvItoEs event=0x1,umask=0x10 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket unc_h_requests.invitoe_remote uncore cache Read and Write Requests; Remote InvItoEs event=0x1,umask=0x20 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets unc_h_requests.reads uncore cache Read and Write Requests; Reads event=0x1,umask=0x3 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests. This is a good proxy for LLC Read Misses (including RFOs) unc_h_requests.reads_local uncore cache Read and Write Requests; Local Reads event=0x1,umask=0x1 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket. This is a good proxy for LLC Read Misses (including RFOs) from the local socket unc_h_requests.reads_remote uncore cache Read and Write Requests; Remote Reads event=0x1,umask=0x2 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket. This is a good proxy for LLC Read Misses (including RFOs) from the remote socket unc_h_requests.writes uncore cache Read and Write Requests; Writes event=0x1,umask=0xc 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests unc_h_requests.writes_local uncore cache Read and Write Requests; Local Writes event=0x1,umask=0x4 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket unc_h_requests.writes_remote uncore cache Read and Write Requests; Remote Writes event=0x1,umask=0x8 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets unc_h_ring_ad_used.ccw uncore cache HA AD Ring in Use; Counterclockwise event=0x3e,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_even uncore cache HA AD Ring in Use; Counterclockwise and Even event=0x3e,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_ad_used.ccw_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd event=0x3e,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_ad_used.cw uncore cache HA AD Ring in Use; Clockwise event=0x3e,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_even uncore cache HA AD Ring in Use; Clockwise and Even event=0x3e,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_ad_used.cw_odd uncore cache HA AD Ring in Use; Clockwise and Odd event=0x3e,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_ring_ak_used.all uncore cache HA AK Ring in Use; All event=0x3f,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw uncore cache HA AK Ring in Use; Counterclockwise event=0x3f,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_even uncore cache HA AK Ring in Use; Counterclockwise and Even event=0x3f,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_ak_used.ccw_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd event=0x3f,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_ak_used.cw uncore cache HA AK Ring in Use; Clockwise event=0x3f,umask=0x3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_even uncore cache HA AK Ring in Use; Clockwise and Even event=0x3f,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_ak_used.cw_odd uncore cache HA AK Ring in Use; Clockwise and Odd event=0x3f,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_ring_bl_used.all uncore cache HA BL Ring in Use; All event=0x40,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw uncore cache HA BL Ring in Use; Counterclockwise event=0x40,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_even uncore cache HA BL Ring in Use; Counterclockwise and Even event=0x40,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_bl_used.ccw_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd event=0x40,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_bl_used.cw uncore cache HA BL Ring in Use; Clockwise event=0x40,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_even uncore cache HA BL Ring in Use; Clockwise and Even event=0x40,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_bl_used.cw_odd uncore cache HA BL Ring in Use; Clockwise and Odd event=0x40,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_rpq_cycles_no_reg_credits.chn0 uncore cache iMC RPQ Credits Empty - Regular; Channel 0 event=0x15,umask=0x1 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_rpq_cycles_no_reg_credits.chn1 uncore cache iMC RPQ Credits Empty - Regular; Channel 1 event=0x15,umask=0x2 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_rpq_cycles_no_reg_credits.chn2 uncore cache iMC RPQ Credits Empty - Regular; Channel 2 event=0x15,umask=0x4 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_rpq_cycles_no_reg_credits.chn3 uncore cache iMC RPQ Credits Empty - Regular; Channel 3 event=0x15,umask=0x8 01 Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_rpq_cycles_no_spec_credits.chn0 uncore cache iMC RPQ Credits Empty - Special; Channel 0 event=0x16,umask=0x1 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_rpq_cycles_no_spec_credits.chn1 uncore cache iMC RPQ Credits Empty - Special; Channel 1 event=0x16,umask=0x2 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_rpq_cycles_no_spec_credits.chn2 uncore cache iMC RPQ Credits Empty - Special; Channel 2 event=0x16,umask=0x4 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_rpq_cycles_no_spec_credits.chn3 uncore cache iMC RPQ Credits Empty - Special; Channel 3 event=0x16,umask=0x8 01 Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_sbo0_credits_acquired.ad uncore cache SBo0 Credits Acquired; For AD Ring event=0x68,umask=0x1 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_h_sbo0_credits_acquired.bl uncore cache SBo0 Credits Acquired; For BL Ring event=0x68,umask=0x2 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_h_sbo0_credit_occupancy.ad uncore cache SBo0 Credits Occupancy; For AD Ring event=0x6a,umask=0x1 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_h_sbo0_credit_occupancy.bl uncore cache SBo0 Credits Occupancy; For BL Ring event=0x6a,umask=0x2 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_h_sbo1_credits_acquired.ad uncore cache SBo1 Credits Acquired; For AD Ring event=0x69,umask=0x1 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_h_sbo1_credits_acquired.bl uncore cache SBo1 Credits Acquired; For BL Ring event=0x69,umask=0x2 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_h_sbo1_credit_occupancy.ad uncore cache SBo1 Credits Occupancy; For AD Ring event=0x6b,umask=0x1 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_h_sbo1_credit_occupancy.bl uncore cache SBo1 Credits Occupancy; For BL Ring event=0x6b,umask=0x2 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_h_snoops_rsp_after_data.local uncore cache Data beat the Snoop Responses; Local Requests event=0xa,umask=0x1 01 Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket unc_h_snoops_rsp_after_data.remote uncore cache Data beat the Snoop Responses; Remote Requests event=0xa,umask=0x2 01 Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets unc_h_snoop_cycles_ne.all uncore cache Cycles with Snoops Outstanding; All Requests event=0x8,umask=0x3 01 Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets unc_h_snoop_cycles_ne.local uncore cache Cycles with Snoops Outstanding; Local Requests event=0x8,umask=0x1 01 Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket unc_h_snoop_cycles_ne.remote uncore cache Cycles with Snoops Outstanding; Remote Requests event=0x8,umask=0x2 01 Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets unc_h_snoop_occupancy.local uncore cache Tracker Snoops Outstanding Accumulator; Local Requests event=0x9,umask=0x1 01 Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket unc_h_snoop_occupancy.remote uncore cache Tracker Snoops Outstanding Accumulator; Remote Requests event=0x9,umask=0x2 01 Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets unc_h_snoop_resp.rspcnflct uncore cache Snoop Responses Received; RSPCNFLCT* event=0x21,umask=0x40 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_h_snoop_resp.rspi uncore cache Snoop Responses Received; RspI event=0x21,umask=0x1 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_h_snoop_resp.rspifwd uncore cache Snoop Responses Received; RspIFwd event=0x21,umask=0x4 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_h_snoop_resp.rsps uncore cache Snoop Responses Received; RspS event=0x21,umask=0x2 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_h_snoop_resp.rspsfwd uncore cache Snoop Responses Received; RspSFwd event=0x21,umask=0x8 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snoop_resp.rsp_fwd_wb uncore cache Snoop Responses Received; Rsp*Fwd*WB event=0x21,umask=0x20 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_h_snoop_resp.rsp_wb uncore cache Snoop Responses Received; Rsp*WB event=0x21,umask=0x10 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_h_snp_resp_recv_local.other uncore cache Snoop Responses Received Local; Other event=0x60,umask=0x80 01 Number of snoop responses received for a Local request; Filters for all other snoop responses unc_h_snp_resp_recv_local.rspcnflct uncore cache Snoop Responses Received Local; RspCnflct event=0x60,umask=0x40 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_h_snp_resp_recv_local.rspi uncore cache Snoop Responses Received Local; RspI event=0x60,umask=0x1 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_h_snp_resp_recv_local.rspifwd uncore cache Snoop Responses Received Local; RspIFwd event=0x60,umask=0x4 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_h_snp_resp_recv_local.rsps uncore cache Snoop Responses Received Local; RspS event=0x60,umask=0x2 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_h_snp_resp_recv_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x60,umask=0x8 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snp_resp_recv_local.rspxfwdxwb uncore cache Snoop Responses Received Local; Rsp*FWD*WB event=0x60,umask=0x20 01 Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_h_snp_resp_recv_local.rspxwb uncore cache Snoop Responses Received Local; Rsp*WB event=0x60,umask=0x10 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_h_stall_no_sbo_credit.sbo0_ad uncore cache Stall on No Sbo Credits; For SBo0, AD Ring event=0x6c,umask=0x1 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo0_bl uncore cache Stall on No Sbo Credits; For SBo0, BL Ring event=0x6c,umask=0x4 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo1_ad uncore cache Stall on No Sbo Credits; For SBo1, AD Ring event=0x6c,umask=0x2 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo1_bl uncore cache Stall on No Sbo Credits; For SBo1, BL Ring event=0x6c,umask=0x8 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_h_tad_requests_g0.region0 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 0 event=0x1b,umask=0x1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0 unc_h_tad_requests_g0.region1 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 1 event=0x1b,umask=0x2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1 unc_h_tad_requests_g0.region2 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 2 event=0x1b,umask=0x4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2 unc_h_tad_requests_g0.region3 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 3 event=0x1b,umask=0x8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3 unc_h_tad_requests_g0.region4 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 4 event=0x1b,umask=0x10 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4 unc_h_tad_requests_g0.region5 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 5 event=0x1b,umask=0x20 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5 unc_h_tad_requests_g0.region6 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 6 event=0x1b,umask=0x40 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6 unc_h_tad_requests_g0.region7 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 7 event=0x1b,umask=0x80 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7 unc_h_tad_requests_g1.region10 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 10 event=0x1c,umask=0x4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10 unc_h_tad_requests_g1.region11 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 11 event=0x1c,umask=0x8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11 unc_h_tad_requests_g1.region8 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 8 event=0x1c,umask=0x1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8 unc_h_tad_requests_g1.region9 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 9 event=0x1c,umask=0x2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9 unc_h_tracker_cycles_full.all uncore cache Tracker Cycles Full; Cycles Completely Used event=0x2,umask=0x2 01 Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries. It will not return valid count when BT is disabled unc_h_tracker_cycles_full.gp uncore cache Tracker Cycles Full; Cycles GP Completely Used event=0x2,umask=0x1 01 Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used. It will not return valid count when BT is disabled unc_h_tracker_cycles_ne.all uncore cache Tracker Cycles Not Empty; All Requests event=0x3,umask=0x3 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets unc_h_tracker_cycles_ne.local uncore cache Tracker Cycles Not Empty; Local Requests event=0x3,umask=0x1 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket unc_h_tracker_cycles_ne.remote uncore cache Tracker Cycles Not Empty; Remote Requests event=0x3,umask=0x2 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets unc_h_tracker_occupancy.invitoe_local uncore cache Tracker Occupancy Accumulator; Local InvItoE Requests event=0x4,umask=0x40 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.invitoe_remote uncore cache Tracker Occupancy Accumulator; Remote InvItoE Requests event=0x4,umask=0x80 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.reads_local uncore cache Tracker Occupancy Accumulator; Local Read Requests event=0x4,umask=0x4 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.reads_remote uncore cache Tracker Occupancy Accumulator; Remote Read Requests event=0x4,umask=0x8 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.writes_local uncore cache Tracker Occupancy Accumulator; Local Write Requests event=0x4,umask=0x10 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.writes_remote uncore cache Tracker Occupancy Accumulator; Remote Write Requests event=0x4,umask=0x20 01 Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_pending_occupancy.local uncore cache Data Pending Occupancy Accumulator; Local Requests event=0x5,umask=0x1 01 Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket unc_h_tracker_pending_occupancy.remote uncore cache Data Pending Occupancy Accumulator; Remote Requests event=0x5,umask=0x2 01 Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets unc_h_txr_ad.hom uncore cache Outbound NDR Ring Transactions; Non-data Responses event=0xf,umask=0x4 01 Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring. NDR stands for non-data response and is generally used for completions that do not include data. AD NDR is used for transactions to remote sockets unc_h_txr_ad_cycles_full.all uncore cache AD Egress Full; All event=0x2a,umask=0x3 01 AD Egress Full; Cycles full from both schedulers unc_h_txr_ad_cycles_full.sched0 uncore cache AD Egress Full; Scheduler 0 event=0x2a,umask=0x1 01 AD Egress Full; Filter for cycles full from scheduler bank 0 unc_h_txr_ad_cycles_full.sched1 uncore cache AD Egress Full; Scheduler 1 event=0x2a,umask=0x2 01 AD Egress Full; Filter for cycles full from scheduler bank 1 unc_h_txr_ad_cycles_ne.all uncore cache AD Egress Not Empty; All event=0x29,umask=0x3 01 AD Egress Not Empty; Cycles full from both schedulers unc_h_txr_ad_cycles_ne.sched0 uncore cache AD Egress Not Empty; Scheduler 0 event=0x29,umask=0x1 01 AD Egress Not Empty; Filter for cycles not empty from scheduler bank 0 unc_h_txr_ad_cycles_ne.sched1 uncore cache AD Egress Not Empty; Scheduler 1 event=0x29,umask=0x2 01 AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_ad_inserts.all uncore cache AD Egress Allocations; All event=0x27,umask=0x3 01 AD Egress Allocations; Allocations from both schedulers unc_h_txr_ad_inserts.sched0 uncore cache AD Egress Allocations; Scheduler 0 event=0x27,umask=0x1 01 AD Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_ad_inserts.sched1 uncore cache AD Egress Allocations; Scheduler 1 event=0x27,umask=0x2 01 AD Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_ak_cycles_full.all uncore cache AK Egress Full; All event=0x32,umask=0x3 01 AK Egress Full; Cycles full from both schedulers unc_h_txr_ak_cycles_full.sched0 uncore cache AK Egress Full; Scheduler 0 event=0x32,umask=0x1 01 AK Egress Full; Filter for cycles full from scheduler bank 0 unc_h_txr_ak_cycles_full.sched1 uncore cache AK Egress Full; Scheduler 1 event=0x32,umask=0x2 01 AK Egress Full; Filter for cycles full from scheduler bank 1 unc_h_txr_ak_cycles_ne.all uncore cache AK Egress Not Empty; All event=0x31,umask=0x3 01 AK Egress Not Empty; Cycles full from both schedulers unc_h_txr_ak_cycles_ne.sched0 uncore cache AK Egress Not Empty; Scheduler 0 event=0x31,umask=0x1 01 AK Egress Not Empty; Filter for cycles not empty from scheduler bank 0 unc_h_txr_ak_cycles_ne.sched1 uncore cache AK Egress Not Empty; Scheduler 1 event=0x31,umask=0x2 01 AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_ak_inserts.all uncore cache AK Egress Allocations; All event=0x2f,umask=0x3 01 AK Egress Allocations; Allocations from both schedulers unc_h_txr_ak_inserts.sched0 uncore cache AK Egress Allocations; Scheduler 0 event=0x2f,umask=0x1 01 AK Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_ak_inserts.sched1 uncore cache AK Egress Allocations; Scheduler 1 event=0x2f,umask=0x2 01 AK Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_bl.drs_cache uncore cache Outbound DRS Ring Transactions to Cache; Data to Cache event=0x10,umask=0x1 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to the cache unc_h_txr_bl.drs_core uncore cache Outbound DRS Ring Transactions to Cache; Data to Core event=0x10,umask=0x2 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent directly to the requesting core unc_h_txr_bl.drs_qpi uncore cache Outbound DRS Ring Transactions to Cache; Data to QPI event=0x10,umask=0x4 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI unc_h_txr_bl_cycles_full.all uncore cache BL Egress Full; All event=0x36,umask=0x3 01 BL Egress Full; Cycles full from both schedulers unc_h_txr_bl_cycles_full.sched0 uncore cache BL Egress Full; Scheduler 0 event=0x36,umask=0x1 01 BL Egress Full; Filter for cycles full from scheduler bank 0 unc_h_txr_bl_cycles_full.sched1 uncore cache BL Egress Full; Scheduler 1 event=0x36,umask=0x2 01 BL Egress Full; Filter for cycles full from scheduler bank 1 unc_h_txr_bl_cycles_ne.all uncore cache BL Egress Not Empty; All event=0x35,umask=0x3 01 BL Egress Not Empty; Cycles full from both schedulers unc_h_txr_bl_cycles_ne.sched0 uncore cache BL Egress Not Empty; Scheduler 0 event=0x35,umask=0x1 01 BL Egress Not Empty; Filter for cycles not empty from scheduler bank 0 unc_h_txr_bl_cycles_ne.sched1 uncore cache BL Egress Not Empty; Scheduler 1 event=0x35,umask=0x2 01 BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_bl_inserts.all uncore cache BL Egress Allocations; All event=0x33,umask=0x3 01 BL Egress Allocations; Allocations from both schedulers unc_h_txr_bl_inserts.sched0 uncore cache BL Egress Allocations; Scheduler 0 event=0x33,umask=0x1 01 BL Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_bl_inserts.sched1 uncore cache BL Egress Allocations; Scheduler 1 event=0x33,umask=0x2 01 BL Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_starved.ak uncore cache Injection Starvation; For AK Ring event=0x6d,umask=0x1 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_txr_starved.bl uncore cache Injection Starvation; For BL Ring event=0x6d,umask=0x2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_wpq_cycles_no_reg_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0 event=0x18,umask=0x1 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_wpq_cycles_no_reg_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1 event=0x18,umask=0x2 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_wpq_cycles_no_reg_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2 event=0x18,umask=0x4 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_wpq_cycles_no_reg_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3 event=0x18,umask=0x8 01 Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_wpq_cycles_no_spec_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 0 event=0x19,umask=0x1 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_wpq_cycles_no_spec_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 1 event=0x19,umask=0x2 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_wpq_cycles_no_spec_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 2 event=0x19,umask=0x4 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_wpq_cycles_no_spec_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 3 event=0x19,umask=0x8 01 Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only uncore_irp unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0x12,umask=0x1 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port unc_i_cache_total_occupancy.source uncore interconnect Total Write Cache Occupancy; Select Source event=0x12,umask=0x2 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_clockticks uncore interconnect Clocks in the IRP event=0 01 Number of clocks in the IRP unc_i_coherent_ops.clflush uncore interconnect Coherent Ops; CLFlush event=0x13,umask=0x80 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.crd uncore interconnect Coherent Ops; CRd event=0x13,umask=0x2 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.drd uncore interconnect Coherent Ops; DRd event=0x13,umask=0x4 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcidcahint uncore interconnect Coherent Ops; PCIDCAHin5t event=0x13,umask=0x20 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcirdcur uncore interconnect Coherent Ops; PCIRdCur event=0x13,umask=0x1 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcitom uncore interconnect Coherent Ops; PCIItoM event=0x13,umask=0x10 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.rfo uncore interconnect Coherent Ops; RFO event=0x13,umask=0x8 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops; WbMtoI event=0x13,umask=0x40 01 Counts the number of coherency related operations servied by the IRP unc_i_misc0.2nd_atomic_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary event=0x14,umask=0x10 01 Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary unc_i_misc0.2nd_rd_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary event=0x14,umask=0x4 01 Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary unc_i_misc0.2nd_wr_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary event=0x14,umask=0x8 01 Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary unc_i_misc0.fast_rej uncore interconnect Misc Events - Set 0; Fastpath Rejects event=0x14,umask=0x2 01 Counts Timeouts - Set 0 : Fastpath Rejects unc_i_misc0.fast_req uncore interconnect Misc Events - Set 0; Fastpath Requests event=0x14,umask=0x1 01 Counts Timeouts - Set 0 : Fastpath Requests unc_i_misc0.fast_xfer uncore interconnect Misc Events - Set 0; Fastpath Transfers From Primary to Secondary event=0x14,umask=0x20 01 Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary unc_i_misc0.pf_ack_hint uncore interconnect Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary event=0x14,umask=0x40 01 Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary unc_i_misc0.pf_timeout uncore interconnect Misc Events - Set 0; Prefetch TimeOut event=0x14,umask=0x80 01 Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut unc_i_misc1.data_throttle uncore interconnect Misc Events - Set 1; Data Throttled event=0x15,umask=0x80 01 IRP throttled switch data unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 event=0x15,umask=0x10 01 Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1; Received Invalid event=0x15,umask=0x20 01 Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1; Received Valid event=0x15,umask=0x40 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1; Slow Transfer of E Line event=0x15,umask=0x4 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1; Slow Transfer of I Line event=0x15,umask=0x1 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1; Slow Transfer of M Line event=0x15,umask=0x8 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1; Slow Transfer of S Line event=0x15,umask=0x2 01 Secondary received a transfer that did not have sufficient MESI state unc_i_rxr_ak_inserts uncore interconnect AK Ingress Occupancy event=0xa 01 Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_bl_drs_cycles_full uncore interconnect UNC_I_RxR_BL_DRS_CYCLES_FULL event=0x4 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_inserts uncore interconnect BL Ingress Occupancy - DRS event=0x1 01 Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_occupancy uncore interconnect UNC_I_RxR_BL_DRS_OCCUPANCY event=0x7 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_cycles_full uncore interconnect UNC_I_RxR_BL_NCB_CYCLES_FULL event=0x5 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_inserts uncore interconnect BL Ingress Occupancy - NCB event=0x2 01 Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_occupancy uncore interconnect UNC_I_RxR_BL_NCB_OCCUPANCY event=0x8 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_cycles_full uncore interconnect UNC_I_RxR_BL_NCS_CYCLES_FULL event=0x6 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_inserts uncore interconnect BL Ingress Occupancy - NCS event=0x3 01 Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_occupancy uncore interconnect UNC_I_RxR_BL_NCS_OCCUPANCY event=0x9 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses; Hit E or S event=0x17,umask=0x4 01 Snoop Responses : Hit E or S unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses; Hit I event=0x17,umask=0x2 01 Snoop Responses : Hit I unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses; Hit M event=0x17,umask=0x8 01 Snoop Responses : Hit M unc_i_snoop_resp.miss uncore interconnect Snoop Responses; Miss event=0x17,umask=0x1 01 Snoop Responses : Miss unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses; SnpCode event=0x17,umask=0x10 01 Snoop Responses : SnpCode unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses; SnpData event=0x17,umask=0x20 01 Snoop Responses : SnpData unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses; SnpInv event=0x17,umask=0x40 01 Snoop Responses : SnpInv unc_i_transactions.atomic uncore interconnect Inbound Transaction Count; Atomic event=0x16,umask=0x10 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count; Other event=0x16,umask=0x20 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions unc_i_transactions.rd_pref uncore interconnect Inbound Transaction Count; Read Prefetches event=0x16,umask=0x4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x16,umask=0x1 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x16,umask=0x2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests unc_i_transactions.wr_pref uncore interconnect Inbound Transaction Count; Write Prefetches event=0x16,umask=0x8 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches unc_i_txr_ad_stall_credit_cycles uncore interconnect No AD Egress Credit Stalls event=0x18 01 Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available unc_i_txr_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x19 01 Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txr_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xe 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txr_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xf 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txr_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xd 01 Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests uncore_ubox unc_u_event_msg.doorbell_rcvd uncore interconnect VLW Received event=0x42,umask=0x8 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.disable uncore interconnect Filter Match event=0x41,umask=0x2 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.enable uncore interconnect Filter Match event=0x41,umask=0x1 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.u2c_disable uncore interconnect Filter Match event=0x41,umask=0x8 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.u2c_enable uncore interconnect Filter Match event=0x41,umask=0x4 01 Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack; Assert to ACK event=0x45,umask=0x1 01 PHOLD cycles. Filter from source CoreID unc_u_racu_requests uncore interconnect RACU Request event=0x46 01 Number outstanding register requests within message channel tracker unc_u_u2c_events.cmc uncore interconnect Monitor Sent to T0; Correctable Machine Check event=0x43,umask=0x10 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.livelock uncore interconnect Monitor Sent to T0; Livelock event=0x43,umask=0x4 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.lterror uncore interconnect Monitor Sent to T0; LTError event=0x43,umask=0x8 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.monitor_t0 uncore interconnect Monitor Sent to T0; Monitor T0 event=0x43,umask=0x1 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.monitor_t1 uncore interconnect Monitor Sent to T0; Monitor T1 event=0x43,umask=0x2 01 Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.other uncore interconnect Monitor Sent to T0; Other event=0x43,umask=0x80 01 Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI unc_u_u2c_events.trap uncore interconnect Monitor Sent to T0; Trap event=0x43,umask=0x40 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.umc uncore interconnect Monitor Sent to T0; Uncorrectable Machine Check event=0x43,umask=0x20 01 Events coming from Uncore can be sent to one or all cores uncore_r2pcie unc_r2_clockticks uncore io Number of uclks in domain event=0x1 01 Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_r2_iio_credit.isoch_qpi0 uncore io UNC_R2_IIO_CREDIT.ISOCH_QPI0 event=0x2d,umask=0x4 01 unc_r2_iio_credit.isoch_qpi1 uncore io UNC_R2_IIO_CREDIT.ISOCH_QPI1 event=0x2d,umask=0x8 01 unc_r2_iio_credit.prq_qpi0 uncore io UNC_R2_IIO_CREDIT.PRQ_QPI0 event=0x2d,umask=0x1 01 unc_r2_iio_credit.prq_qpi1 uncore io UNC_R2_IIO_CREDIT.PRQ_QPI1 event=0x2d,umask=0x2 01 unc_r2_iio_credits_acquired.drs uncore io R2PCIe IIO Credit Acquired; DRS event=0x33,umask=0x8 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_iio_credits_acquired.ncb uncore io R2PCIe IIO Credit Acquired; NCB event=0x33,umask=0x10 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class unc_r2_iio_credits_acquired.ncs uncore io R2PCIe IIO Credit Acquired; NCS event=0x33,umask=0x20 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class unc_r2_iio_credits_used.drs uncore io R2PCIe IIO Credits in Use; DRS event=0x32,umask=0x8 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_iio_credits_used.ncb uncore io R2PCIe IIO Credits in Use; NCB event=0x32,umask=0x10 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class unc_r2_iio_credits_used.ncs uncore io R2PCIe IIO Credits in Use; NCS event=0x32,umask=0x20 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class unc_r2_ring_ad_used.all uncore io R2 AD Ring in Use; All event=0x7,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw uncore io R2 AD Ring in Use; Counterclockwise event=0x7,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_even uncore io R2 AD Ring in Use; Counterclockwise and Even event=0x7,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_ad_used.ccw_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd event=0x7,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_ad_used.cw uncore io R2 AD Ring in Use; Clockwise event=0x7,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_even uncore io R2 AD Ring in Use; Clockwise and Even event=0x7,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_ad_used.cw_odd uncore io R2 AD Ring in Use; Clockwise and Odd event=0x7,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_ak_bounces.dn uncore io AK Ingress Bounced; Dn event=0x12,umask=0x2 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_ring_ak_bounces.up uncore io AK Ingress Bounced; Up event=0x12,umask=0x1 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_ring_ak_used.all uncore io R2 AK Ring in Use; All event=0x8,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw uncore io R2 AK Ring in Use; Counterclockwise event=0x8,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_even uncore io R2 AK Ring in Use; Counterclockwise and Even event=0x8,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_ak_used.ccw_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd event=0x8,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_ak_used.cw uncore io R2 AK Ring in Use; Clockwise event=0x8,umask=0x3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_even uncore io R2 AK Ring in Use; Clockwise and Even event=0x8,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_ak_used.cw_odd uncore io R2 AK Ring in Use; Clockwise and Odd event=0x8,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_bl_used.all uncore io R2 BL Ring in Use; All event=0x9,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw uncore io R2 BL Ring in Use; Counterclockwise event=0x9,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_even uncore io R2 BL Ring in Use; Counterclockwise and Even event=0x9,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_bl_used.ccw_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd event=0x9,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_bl_used.cw uncore io R2 BL Ring in Use; Clockwise event=0x9,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_even uncore io R2 BL Ring in Use; Clockwise and Even event=0x9,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_bl_used.cw_odd uncore io R2 BL Ring in Use; Clockwise and Odd event=0x9,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_ring_iv_used.ccw uncore io R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_ring_iv_used.cw uncore io R2 IV Ring in Use; Clockwise event=0xa,umask=0x3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_rxr_cycles_ne.ncb uncore io Ingress Cycles Not Empty; NCB event=0x10,umask=0x10 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r2_rxr_cycles_ne.ncs uncore io Ingress Cycles Not Empty; NCS event=0x10,umask=0x20 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r2_rxr_inserts.ncb uncore io Ingress Allocations; NCB event=0x11,umask=0x10 01 Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r2_rxr_inserts.ncs uncore io Ingress Allocations; NCS event=0x11,umask=0x20 01 Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r2_rxr_occupancy.drs uncore io Ingress Occupancy Accumulator; DRS event=0x13,umask=0x8 01 Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r2_sbo0_credits_acquired.ad uncore io SBo0 Credits Acquired; For AD Ring event=0x28,umask=0x1 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r2_sbo0_credits_acquired.bl uncore io SBo0 Credits Acquired; For BL Ring event=0x28,umask=0x2 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r2_sbo0_credit_occupancy.ad uncore io SBo0 Credits Occupancy; For AD Ring event=0x2a,umask=0x1 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r2_sbo0_credit_occupancy.bl uncore io SBo0 Credits Occupancy; For BL Ring event=0x2a,umask=0x2 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r2_stall_no_sbo_credit.sbo0_ad uncore io Stall on No Sbo Credits; For SBo0, AD Ring event=0x2c,umask=0x1 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo0_bl uncore io Stall on No Sbo Credits; For SBo0, BL Ring event=0x2c,umask=0x4 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo1_ad uncore io Stall on No Sbo Credits; For SBo1, AD Ring event=0x2c,umask=0x2 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo1_bl uncore io Stall on No Sbo Credits; For SBo1, BL Ring event=0x2c,umask=0x8 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r2_txr_cycles_full.ad uncore io Egress Cycles Full; AD event=0x25,umask=0x1 01 Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue unc_r2_txr_cycles_full.ak uncore io Egress Cycles Full; AK event=0x25,umask=0x2 01 Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue unc_r2_txr_cycles_full.bl uncore io Egress Cycles Full; BL event=0x25,umask=0x4 01 Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue unc_r2_txr_cycles_ne.ad uncore io Egress Cycles Not Empty; AD event=0x23,umask=0x1 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue unc_r2_txr_cycles_ne.ak uncore io Egress Cycles Not Empty; AK event=0x23,umask=0x2 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue unc_r2_txr_cycles_ne.bl uncore io Egress Cycles Not Empty; BL event=0x23,umask=0x4 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue unc_r2_txr_nack_cw.dn_ad uncore io Egress CCW NACK; AD CCW event=0x26,umask=0x1 01 AD CounterClockwise Egress Queue unc_r2_txr_nack_cw.dn_ak uncore io Egress CCW NACK; AK CCW event=0x26,umask=0x4 01 AK CounterClockwise Egress Queue unc_r2_txr_nack_cw.dn_bl uncore io Egress CCW NACK; BL CCW event=0x26,umask=0x2 01 BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.up_ad uncore io Egress CCW NACK; AK CCW event=0x26,umask=0x8 01 BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.up_ak uncore io Egress CCW NACK; BL CW event=0x26,umask=0x20 01 AD Clockwise Egress Queue unc_r2_txr_nack_cw.up_bl uncore io Egress CCW NACK; BL CCW event=0x26,umask=0x10 01 AD CounterClockwise Egress Queue unc_m_act_count.byp uncore memory DRAM Activate Count; Activate due to Write event=0x1,umask=0x8 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.rd uncore memory DRAM Activate Count; Activate due to Read event=0x1,umask=0x1 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.wr uncore memory DRAM Activate Count; Activate due to Write event=0x1,umask=0x2 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_byp_cmds.act uncore memory ACT command issued by 2 cycle bypass event=0xa1,umask=0x1 01 unc_m_byp_cmds.cas uncore memory CAS command issued by 2 cycle bypass event=0xa1,umask=0x2 01 unc_m_byp_cmds.pre uncore memory PRE command issued by 2 cycle bypass event=0xa1,umask=0x4 01 unc_m_cas_count.all uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre) event=0x4,umask=0xf 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.rd uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills) event=0x4,umask=0x3 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills) unc_m_cas_count.rd_reg uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre) event=0x4,umask=0x1 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM event=0x4,umask=0x20 01 unc_m_cas_count.rd_underfill uncore memory DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued event=0x4,umask=0x2 01 DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller. This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ. While it is possible for underfills to be issed in both WMM and RMM, this event counts both unc_m_cas_count.rd_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM event=0x4,umask=0x10 01 unc_m_cas_count.wr uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes) event=0x4,umask=0xc 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel unc_m_cas_count.wr_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=0x4,umask=0x8 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode unc_m_cas_count.wr_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=0x4,umask=0x4 01 DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode unc_m_dclockticks uncore memory DRAM Clockticks event=0 01 unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=0x6 01 Counts the number of times that the precharge all command was sent unc_m_dram_refresh.high uncore memory Number of DRAM Refreshes Issued event=0x5,umask=0x4 01 Counts the number of refreshes issued unc_m_dram_refresh.panic uncore memory Number of DRAM Refreshes Issued event=0x5,umask=0x2 01 Counts the number of refreshes issued unc_m_ecc_correctable_errors uncore memory ECC Correctable Errors event=0x9 01 Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode unc_m_major_modes.isoch uncore memory Cycles in a Major Mode; Isoch Major Mode event=0x7,umask=0x8 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed unc_m_major_modes.partial uncore memory Cycles in a Major Mode; Partial Major Mode event=0x7,umask=0x4 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed unc_m_major_modes.read uncore memory Cycles in a Major Mode; Read Major Mode event=0x7,umask=0x1 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes unc_m_major_modes.write uncore memory Cycles in a Major Mode; Write Major Mode event=0x7,umask=0x2 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth unc_m_power_channel_dlloff uncore memory Channel DLLOFF Cycles event=0x84 01 Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode unc_m_power_channel_ppd uncore memory Channel PPD Cycles event=0x85 01 Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_cke_cycles.rank0 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x1 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank1 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x2 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank2 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x4 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank3 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x8 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank4 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x10 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank5 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x20 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank6 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x40 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank7 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x80 01 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_critical_throttle_cycles uncore memory Critical Throttle Cycles event=0x86 01 Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event unc_m_power_pcu_throttling uncore memory UNC_M_POWER_PCU_THROTTLING event=0x42 01 unc_m_power_self_refresh uncore memory Clock-Enabled Self-Refresh event=0x43 01 Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_power_throttle_cycles.rank0 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x1 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID unc_m_power_throttle_cycles.rank1 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x2 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank2 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x4 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank3 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x8 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank4 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x10 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank5 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x20 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank6 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x40 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank7 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x80 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_preemption.rd_preempt_rd uncore memory Read Preemption Count; Read over Read Preemption event=0x8,umask=0x1 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read unc_m_preemption.rd_preempt_wr uncore memory Read Preemption Count; Read over Write Preemption event=0x8,umask=0x2 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write unc_m_pre_count.byp uncore memory DRAM Precharge commands.; Precharge due to bypass event=0x2,umask=0x10 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_close uncore memory DRAM Precharge commands.; Precharge due to timer expiration event=0x2,umask=0x2 01 Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode unc_m_pre_count.page_miss uncore memory DRAM Precharge commands.; Precharges due to page miss event=0x2,umask=0x1 01 Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses. This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include PRE commands sent as a result of the page close counter expiration unc_m_pre_count.rd uncore memory DRAM Precharge commands.; Precharge due to read event=0x2,umask=0x4 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr uncore memory DRAM Precharge commands.; Precharge due to write event=0x2,umask=0x8 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_rd_cas_prio.high uncore memory Read CAS issued with HIGH priority event=0xa0,umask=0x4 01 unc_m_rd_cas_prio.low uncore memory Read CAS issued with LOW priority event=0xa0,umask=0x1 01 unc_m_rd_cas_prio.med uncore memory Read CAS issued with MEDIUM priority event=0xa0,umask=0x2 01 unc_m_rd_cas_prio.panic uncore memory Read CAS issued with PANIC NON ISOCH priority (starved) event=0xa0,umask=0x8 01 unc_m_rd_cas_rank0.allbanks uncore memory RD_CAS Access to Rank 0; All Banks event=0xb0,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=0x1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank0.bank10 uncore memory RD_CAS Access to Rank 0; Bank 10 event=0xb0,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank0.bank11 uncore memory RD_CAS Access to Rank 0; Bank 11 event=0xb0,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank0.bank12 uncore memory RD_CAS Access to Rank 0; Bank 12 event=0xb0,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank0.bank13 uncore memory RD_CAS Access to Rank 0; Bank 13 event=0xb0,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank0.bank14 uncore memory RD_CAS Access to Rank 0; Bank 14 event=0xb0,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank0.bank15 uncore memory RD_CAS Access to Rank 0; Bank 15 event=0xb0,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=0x2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=0x3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=0x4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=0x5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=0x6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=0x7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank0.bank8 uncore memory RD_CAS Access to Rank 0; Bank 8 event=0xb0,umask=0x8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank0.bank9 uncore memory RD_CAS Access to Rank 0; Bank 9 event=0xb0,umask=0x9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank0.bankg0 uncore memory RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb0,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank0.bankg1 uncore memory RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb0,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank0.bankg2 uncore memory RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb0,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank0.bankg3 uncore memory RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb0,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank1.allbanks uncore memory RD_CAS Access to Rank 1; All Banks event=0xb1,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=0x1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank1.bank10 uncore memory RD_CAS Access to Rank 1; Bank 10 event=0xb1,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank1.bank11 uncore memory RD_CAS Access to Rank 1; Bank 11 event=0xb1,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank1.bank12 uncore memory RD_CAS Access to Rank 1; Bank 12 event=0xb1,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank1.bank13 uncore memory RD_CAS Access to Rank 1; Bank 13 event=0xb1,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank1.bank14 uncore memory RD_CAS Access to Rank 1; Bank 14 event=0xb1,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank1.bank15 uncore memory RD_CAS Access to Rank 1; Bank 15 event=0xb1,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=0x2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=0x3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=0x4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=0x5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=0x6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=0x7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank1.bank8 uncore memory RD_CAS Access to Rank 1; Bank 8 event=0xb1,umask=0x8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank1.bank9 uncore memory RD_CAS Access to Rank 1; Bank 9 event=0xb1,umask=0x9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank1.bankg0 uncore memory RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb1,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank1.bankg1 uncore memory RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb1,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank1.bankg2 uncore memory RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb1,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank1.bankg3 uncore memory RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb1,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank4.allbanks uncore memory RD_CAS Access to Rank 4; All Banks event=0xb4,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=0x1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank4.bank10 uncore memory RD_CAS Access to Rank 4; Bank 10 event=0xb4,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank4.bank11 uncore memory RD_CAS Access to Rank 4; Bank 11 event=0xb4,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank4.bank12 uncore memory RD_CAS Access to Rank 4; Bank 12 event=0xb4,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank4.bank13 uncore memory RD_CAS Access to Rank 4; Bank 13 event=0xb4,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank4.bank14 uncore memory RD_CAS Access to Rank 4; Bank 14 event=0xb4,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank4.bank15 uncore memory RD_CAS Access to Rank 4; Bank 15 event=0xb4,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=0x2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=0x3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=0x4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=0x5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=0x6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=0x7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank4.bank8 uncore memory RD_CAS Access to Rank 4; Bank 8 event=0xb4,umask=0x8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank4.bank9 uncore memory RD_CAS Access to Rank 4; Bank 9 event=0xb4,umask=0x9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank4.bankg0 uncore memory RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xb4,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank4.bankg1 uncore memory RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xb4,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank4.bankg2 uncore memory RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xb4,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank4.bankg3 uncore memory RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xb4,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank5.allbanks uncore memory RD_CAS Access to Rank 5; All Banks event=0xb5,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=0x1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank5.bank10 uncore memory RD_CAS Access to Rank 5; Bank 10 event=0xb5,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank5.bank11 uncore memory RD_CAS Access to Rank 5; Bank 11 event=0xb5,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank5.bank12 uncore memory RD_CAS Access to Rank 5; Bank 12 event=0xb5,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank5.bank13 uncore memory RD_CAS Access to Rank 5; Bank 13 event=0xb5,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank5.bank14 uncore memory RD_CAS Access to Rank 5; Bank 14 event=0xb5,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank5.bank15 uncore memory RD_CAS Access to Rank 5; Bank 15 event=0xb5,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=0x2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=0x3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=0x4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=0x5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=0x6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=0x7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank5.bank8 uncore memory RD_CAS Access to Rank 5; Bank 8 event=0xb5,umask=0x8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank5.bank9 uncore memory RD_CAS Access to Rank 5; Bank 9 event=0xb5,umask=0x9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank5.bankg0 uncore memory RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xb5,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank5.bankg1 uncore memory RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xb5,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank5.bankg2 uncore memory RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xb5,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank5.bankg3 uncore memory RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xb5,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank6.allbanks uncore memory RD_CAS Access to Rank 6; All Banks event=0xb6,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=0x1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank6.bank10 uncore memory RD_CAS Access to Rank 6; Bank 10 event=0xb6,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank6.bank11 uncore memory RD_CAS Access to Rank 6; Bank 11 event=0xb6,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank6.bank12 uncore memory RD_CAS Access to Rank 6; Bank 12 event=0xb6,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank6.bank13 uncore memory RD_CAS Access to Rank 6; Bank 13 event=0xb6,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank6.bank14 uncore memory RD_CAS Access to Rank 6; Bank 14 event=0xb6,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank6.bank15 uncore memory RD_CAS Access to Rank 6; Bank 15 event=0xb6,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=0x2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=0x3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=0x4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=0x5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=0x6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=0x7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank6.bank8 uncore memory RD_CAS Access to Rank 6; Bank 8 event=0xb6,umask=0x8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank6.bank9 uncore memory RD_CAS Access to Rank 6; Bank 9 event=0xb6,umask=0x9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank6.bankg0 uncore memory RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xb6,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank6.bankg1 uncore memory RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xb6,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank6.bankg2 uncore memory RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xb6,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank6.bankg3 uncore memory RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xb6,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank7.allbanks uncore memory RD_CAS Access to Rank 7; All Banks event=0xb7,umask=0x10 01 RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7 01 RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=0x1 01 RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank7.bank10 uncore memory RD_CAS Access to Rank 7; Bank 10 event=0xb7,umask=0xa 01 RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank7.bank11 uncore memory RD_CAS Access to Rank 7; Bank 11 event=0xb7,umask=0xb 01 RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank7.bank12 uncore memory RD_CAS Access to Rank 7; Bank 12 event=0xb7,umask=0xc 01 RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank7.bank13 uncore memory RD_CAS Access to Rank 7; Bank 13 event=0xb7,umask=0xd 01 RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank7.bank14 uncore memory RD_CAS Access to Rank 7; Bank 14 event=0xb7,umask=0xe 01 RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank7.bank15 uncore memory RD_CAS Access to Rank 7; Bank 15 event=0xb7,umask=0xf 01 RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=0x2 01 RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=0x3 01 RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=0x4 01 RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=0x5 01 RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=0x6 01 RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=0x7 01 RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank7.bank8 uncore memory RD_CAS Access to Rank 7; Bank 8 event=0xb7,umask=0x8 01 RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank7.bank9 uncore memory RD_CAS Access to Rank 7; Bank 9 event=0xb7,umask=0x9 01 RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank7.bankg0 uncore memory RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xb7,umask=0x11 01 RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank7.bankg1 uncore memory RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xb7,umask=0x12 01 RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank7.bankg2 uncore memory RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xb7,umask=0x13 01 RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank7.bankg3 uncore memory RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xb7,umask=0x14 01 RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rpq_cycles_ne uncore memory Read Pending Queue Not Empty event=0x11 01 Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_rpq_inserts uncore memory Read Pending Queue Allocations event=0x10 01 Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_m_vmse_mxb_wr_occupancy uncore memory VMSE MXB write buffer occupancy event=0x91 01 unc_m_vmse_wr_push.rmm uncore memory VMSE WR PUSH issued; VMSE write PUSH issued in RMM event=0x90,umask=0x2 01 unc_m_vmse_wr_push.wmm uncore memory VMSE WR PUSH issued; VMSE write PUSH issued in WMM event=0x90,umask=0x1 01 unc_m_wmm_to_rmm.low_thresh uncore memory Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter event=0xc0,umask=0x1 01 unc_m_wmm_to_rmm.starve uncore memory Transition from WMM to RMM because of low threshold event=0xc0,umask=0x2 01 unc_m_wmm_to_rmm.vmse_retry uncore memory Transition from WMM to RMM because of low threshold event=0xc0,umask=0x4 01 unc_m_wpq_cycles_full uncore memory Write Pending Queue Full Cycles event=0x22 01 Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21 01 Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_read_hit uncore memory Write Pending Queue CAM Match event=0x23 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit uncore memory Write Pending Queue CAM Match event=0x24 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wrong_mm uncore memory Not getting the requested Major Mode event=0xc1 01 unc_m_wr_cas_rank0.allbanks uncore memory WR_CAS Access to Rank 0; All Banks event=0xb8,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=0x1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank0.bank10 uncore memory WR_CAS Access to Rank 0; Bank 10 event=0xb8,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank0.bank11 uncore memory WR_CAS Access to Rank 0; Bank 11 event=0xb8,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank0.bank12 uncore memory WR_CAS Access to Rank 0; Bank 12 event=0xb8,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank0.bank13 uncore memory WR_CAS Access to Rank 0; Bank 13 event=0xb8,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank0.bank14 uncore memory WR_CAS Access to Rank 0; Bank 14 event=0xb8,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank0.bank15 uncore memory WR_CAS Access to Rank 0; Bank 15 event=0xb8,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=0x2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=0x3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=0x4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=0x5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=0x6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=0x7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank0.bank8 uncore memory WR_CAS Access to Rank 0; Bank 8 event=0xb8,umask=0x8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank0.bank9 uncore memory WR_CAS Access to Rank 0; Bank 9 event=0xb8,umask=0x9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank0.bankg0 uncore memory WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb8,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank0.bankg1 uncore memory WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb8,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank0.bankg2 uncore memory WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb8,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank0.bankg3 uncore memory WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb8,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank1.allbanks uncore memory WR_CAS Access to Rank 1; All Banks event=0xb9,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=0x1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank1.bank10 uncore memory WR_CAS Access to Rank 1; Bank 10 event=0xb9,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank1.bank11 uncore memory WR_CAS Access to Rank 1; Bank 11 event=0xb9,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank1.bank12 uncore memory WR_CAS Access to Rank 1; Bank 12 event=0xb9,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank1.bank13 uncore memory WR_CAS Access to Rank 1; Bank 13 event=0xb9,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank1.bank14 uncore memory WR_CAS Access to Rank 1; Bank 14 event=0xb9,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank1.bank15 uncore memory WR_CAS Access to Rank 1; Bank 15 event=0xb9,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=0x2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=0x3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=0x4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=0x5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=0x6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=0x7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank1.bank8 uncore memory WR_CAS Access to Rank 1; Bank 8 event=0xb9,umask=0x8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank1.bank9 uncore memory WR_CAS Access to Rank 1; Bank 9 event=0xb9,umask=0x9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank1.bankg0 uncore memory WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb9,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank1.bankg1 uncore memory WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb9,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank1.bankg2 uncore memory WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb9,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank1.bankg3 uncore memory WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb9,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank4.allbanks uncore memory WR_CAS Access to Rank 4; All Banks event=0xbc,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=0x1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank4.bank10 uncore memory WR_CAS Access to Rank 4; Bank 10 event=0xbc,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank4.bank11 uncore memory WR_CAS Access to Rank 4; Bank 11 event=0xbc,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank4.bank12 uncore memory WR_CAS Access to Rank 4; Bank 12 event=0xbc,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank4.bank13 uncore memory WR_CAS Access to Rank 4; Bank 13 event=0xbc,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank4.bank14 uncore memory WR_CAS Access to Rank 4; Bank 14 event=0xbc,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank4.bank15 uncore memory WR_CAS Access to Rank 4; Bank 15 event=0xbc,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=0x2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=0x3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=0x4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=0x5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=0x6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=0x7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank4.bank8 uncore memory WR_CAS Access to Rank 4; Bank 8 event=0xbc,umask=0x8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank4.bank9 uncore memory WR_CAS Access to Rank 4; Bank 9 event=0xbc,umask=0x9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank4.bankg0 uncore memory WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xbc,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank4.bankg1 uncore memory WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xbc,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank4.bankg2 uncore memory WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xbc,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank4.bankg3 uncore memory WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xbc,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank5.allbanks uncore memory WR_CAS Access to Rank 5; All Banks event=0xbd,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=0x1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank5.bank10 uncore memory WR_CAS Access to Rank 5; Bank 10 event=0xbd,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank5.bank11 uncore memory WR_CAS Access to Rank 5; Bank 11 event=0xbd,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank5.bank12 uncore memory WR_CAS Access to Rank 5; Bank 12 event=0xbd,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank5.bank13 uncore memory WR_CAS Access to Rank 5; Bank 13 event=0xbd,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank5.bank14 uncore memory WR_CAS Access to Rank 5; Bank 14 event=0xbd,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank5.bank15 uncore memory WR_CAS Access to Rank 5; Bank 15 event=0xbd,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=0x2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=0x3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=0x4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=0x5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=0x6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=0x7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank5.bank8 uncore memory WR_CAS Access to Rank 5; Bank 8 event=0xbd,umask=0x8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank5.bank9 uncore memory WR_CAS Access to Rank 5; Bank 9 event=0xbd,umask=0x9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank5.bankg0 uncore memory WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xbd,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank5.bankg1 uncore memory WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xbd,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank5.bankg2 uncore memory WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xbd,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank5.bankg3 uncore memory WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xbd,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank6.allbanks uncore memory WR_CAS Access to Rank 6; All Banks event=0xbe,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=0x1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank6.bank10 uncore memory WR_CAS Access to Rank 6; Bank 10 event=0xbe,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank6.bank11 uncore memory WR_CAS Access to Rank 6; Bank 11 event=0xbe,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank6.bank12 uncore memory WR_CAS Access to Rank 6; Bank 12 event=0xbe,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank6.bank13 uncore memory WR_CAS Access to Rank 6; Bank 13 event=0xbe,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank6.bank14 uncore memory WR_CAS Access to Rank 6; Bank 14 event=0xbe,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank6.bank15 uncore memory WR_CAS Access to Rank 6; Bank 15 event=0xbe,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=0x2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=0x3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=0x4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=0x5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=0x6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=0x7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank6.bank8 uncore memory WR_CAS Access to Rank 6; Bank 8 event=0xbe,umask=0x8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank6.bank9 uncore memory WR_CAS Access to Rank 6; Bank 9 event=0xbe,umask=0x9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank6.bankg0 uncore memory WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xbe,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank6.bankg1 uncore memory WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xbe,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank6.bankg2 uncore memory WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xbe,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank6.bankg3 uncore memory WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xbe,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank7.allbanks uncore memory WR_CAS Access to Rank 7; All Banks event=0xbf,umask=0x10 01 WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf 01 WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=0x1 01 WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank7.bank10 uncore memory WR_CAS Access to Rank 7; Bank 10 event=0xbf,umask=0xa 01 WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank7.bank11 uncore memory WR_CAS Access to Rank 7; Bank 11 event=0xbf,umask=0xb 01 WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank7.bank12 uncore memory WR_CAS Access to Rank 7; Bank 12 event=0xbf,umask=0xc 01 WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank7.bank13 uncore memory WR_CAS Access to Rank 7; Bank 13 event=0xbf,umask=0xd 01 WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank7.bank14 uncore memory WR_CAS Access to Rank 7; Bank 14 event=0xbf,umask=0xe 01 WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank7.bank15 uncore memory WR_CAS Access to Rank 7; Bank 15 event=0xbf,umask=0xf 01 WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=0x2 01 WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=0x3 01 WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=0x4 01 WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=0x5 01 WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=0x6 01 WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=0x7 01 WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank7.bank8 uncore memory WR_CAS Access to Rank 7; Bank 8 event=0xbf,umask=0x8 01 WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank7.bank9 uncore memory WR_CAS Access to Rank 7; Bank 9 event=0xbf,umask=0x9 01 WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank7.bankg0 uncore memory WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xbf,umask=0x11 01 WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank7.bankg1 uncore memory WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xbf,umask=0x12 01 WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank7.bankg2 uncore memory WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xbf,umask=0x13 01 WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank7.bankg3 uncore memory WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xbf,umask=0x14 01 WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) uncore_pcu unc_p_clockticks uncore power pclk Cycles event=0 01 The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_core0_transition_cycles uncore power Core C State Transition Cycles event=0x60 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core10_transition_cycles uncore power Core C State Transition Cycles event=0x6a 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core11_transition_cycles uncore power Core C State Transition Cycles event=0x6b 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core12_transition_cycles uncore power Core C State Transition Cycles event=0x6c 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core13_transition_cycles uncore power Core C State Transition Cycles event=0x6d 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core14_transition_cycles uncore power Core C State Transition Cycles event=0x6e 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core15_transition_cycles uncore power Core C State Transition Cycles event=0x6f 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core16_transition_cycles uncore power Core C State Transition Cycles event=0x70 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core17_transition_cycles uncore power Core C State Transition Cycles event=0x71 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core1_transition_cycles uncore power Core C State Transition Cycles event=0x61 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core2_transition_cycles uncore power Core C State Transition Cycles event=0x62 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core3_transition_cycles uncore power Core C State Transition Cycles event=0x63 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core4_transition_cycles uncore power Core C State Transition Cycles event=0x64 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core5_transition_cycles uncore power Core C State Transition Cycles event=0x65 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core6_transition_cycles uncore power Core C State Transition Cycles event=0x66 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core7_transition_cycles uncore power Core C State Transition Cycles event=0x67 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core8_transition_cycles uncore power Core C State Transition Cycles event=0x68 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core9_transition_cycles uncore power Core C State Transition Cycles event=0x69 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_demotions_core0 uncore power Core C State Demotions event=0x30 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core C State Demotions event=0x31 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core10 uncore power Core C State Demotions event=0x3a 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core11 uncore power Core C State Demotions event=0x3b 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core12 uncore power Core C State Demotions event=0x3c 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core13 uncore power Core C State Demotions event=0x3d 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core14 uncore power Core C State Demotions event=0x3e 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core15 uncore power Core C State Demotions event=0x3f 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core16 uncore power Core C State Demotions event=0x40 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core17 uncore power Core C State Demotions event=0x41 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core C State Demotions event=0x32 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core C State Demotions event=0x33 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core C State Demotions event=0x34 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core C State Demotions event=0x35 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core C State Demotions event=0x36 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core C State Demotions event=0x37 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core8 uncore power Core C State Demotions event=0x38 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core9 uncore power Core C State Demotions event=0x39 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_max_limit_thermal_cycles uncore power Thermal Strongest Upper Limit Cycles event=0x4 01 Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input unc_p_freq_max_os_cycles uncore power OS Strongest Upper Limit Cycles event=0x6 01 Counts the number of cycles when the OS is the upper limit on frequency unc_p_freq_max_power_cycles uncore power Power Strongest Upper Limit Cycles event=0x5 01 Counts the number of cycles when power is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x73 01 Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x74 01 Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_memory_phase_shedding_cycles uncore power Memory Phase Shedding Cycles event=0x2f 01 Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency unc_p_pkg_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a 01 Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c1e_cycles uncore power Package C State Residency - C1E event=0x4e 01 Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c2e_cycles uncore power Package C State Residency - C2E event=0x2b 01 Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c 01 Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d 01 Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c7_cycles uncore power Package C7 State Residency event=0x2e 01 Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State; C0 and C1 event=0x80 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State; C3 event=0x80 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State; C6 and C7 event=0x80 01 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_prochot_external_cycles uncore power External Prochot event=0xa 01 Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip unc_p_prochot_internal_cycles uncore power Internal Prochot event=0x9 01 Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x72 01 Number of cycles spent performing core C state transitions across all cores unc_p_ufs_transitions_ring_gv uncore power UNC_P_UFS_TRANSITIONS_RING_GV event=0x79 01 Ring GV with same final and initial frequency unc_p_vr_hot_cycles uncore power VR Hot event=0x42 01 VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0244 00 offcore_response.all_data_rd.llc_hit.hitm_other_core cache Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0091 00 offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0091 00 offcore_response.all_reads.llc_hit.hitm_other_core cache Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C07F7 00 offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C07F7 00 offcore_response.all_requests.llc_hit.any_response cache Counts all requests hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8FFF 00 offcore_response.all_rfo.llc_hit.hitm_other_core cache Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122 00 offcore_response.demand_rfo.llc_hit.any_response cache Counts all demand data writes (RFOs) hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 00 offcore_response.demand_rfo.llc_hit.hitm_other_core cache Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 offcore_response.pf_llc_code_rd.llc_hit.any_response cache Counts prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0200 00 offcore_response.pf_llc_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100 00 offcore_response.all_code_rd.llc_miss.any_response memory Counts all demand & prefetch code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00244 00 offcore_response.all_code_rd.llc_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000244 00 offcore_response.all_data_rd.llc_miss.any_response memory Counts all demand & prefetch data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00091 00 offcore_response.all_data_rd.llc_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000091 00 offcore_response.all_data_rd.llc_miss.remote_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63BC00091 00 offcore_response.all_data_rd.llc_miss.remote_hitm memory Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00091 00 offcore_response.all_data_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87FC00091 00 offcore_response.all_reads.llc_miss.any_response memory Counts all data/code/rfo reads (demand & prefetch) miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC007F7 00 offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6040007F7 00 offcore_response.all_reads.llc_miss.remote_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63BC007F7 00 offcore_response.all_reads.llc_miss.remote_hitm memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC007F7 00 offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87FC007F7 00 offcore_response.all_requests.llc_miss.any_response memory Counts all requests miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC08FFF 00 offcore_response.all_rfo.llc_miss.any_response memory Counts all demand & prefetch RFOs miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00122 00 offcore_response.all_rfo.llc_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000122 00 offcore_response.demand_rfo.llc_miss.any_response memory Counts all demand data writes (RFOs) miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002 00 offcore_response.demand_rfo.llc_miss.remote_hitm memory Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00002 00 offcore_response.pf_llc_code_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00200 00 offcore_response.pf_llc_rfo.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00100 00 llc_misses.code_llc_prefetch uncore cache LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x191 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.data_llc_prefetch uncore cache LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x192 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.data_read uncore cache LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x182 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.mmio_read uncore cache MMIO reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x187,filter_nc=1 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.mmio_write uncore cache MMIO writes. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x18f,filter_nc=1 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_non_snoop_write uncore cache PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x1c8,filter_tid=0x3e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_read uncore cache LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x19e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_write uncore cache ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x1c8 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.rfo_llc_prefetch uncore cache LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x190 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.uncacheable uncore cache LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=0x3,filter_opc=0x187 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_references.code_llc_prefetch uncore cache L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode event=0x35,umask=0x1,filter_opc=0x181 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_ns_partial_write uncore cache PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=0x1,filter_opc=0x180,filter_tid=0x3e 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_read uncore cache PCIe read current. Derived from unc_c_tor_inserts.opcode event=0x35,umask=0x1,filter_opc=0x19e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_write uncore cache PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=0x1,filter_opc=0x1c8,filter_tid=0x3e 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.streaming_full uncore cache Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=0x1,filter_opc=0x18c 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.streaming_partial uncore cache Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=0x1,filter_opc=0x18d 0164Bytes Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_llc_lookup.any uncore cache All LLC Misses (code+ data rd + data wr - including demand and prefetch) event=0x34,umask=0x11,filter_state=0x1 0164Bytes Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_c_llc_victims.m_state uncore cache M line evictions from LLC (writebacks to memory) event=0x37,umask=0x1 0164Bytes Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down uncore cache AK Ring In Use; Down event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up uncore cache AK Ring In Use; Up event=0x1c,umask=0x3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down uncore cache BL Ring in Use; Down event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up uncore cache BL Ring in Use; Up event=0x1d,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_tor_occupancy.llc_data_read uncore cache Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode event=0x36,umask=0x3,filter_opc=0x182 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO unc_h_snoop_resp.rspifwd uncore cache M line forwarded from remote cache with no writeback to memory event=0x21,umask=0x4 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_h_snoop_resp.rsps uncore cache Shared line response from remote cache event=0x21,umask=0x2 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_h_snoop_resp.rspsfwd uncore cache Shared line forwarded from remote cache event=0x21,umask=0x8 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snoop_resp.rsp_fwd_wb uncore cache M line forwarded from remote cache along with writeback to memory event=0x21,umask=0x20 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory uncore_qpi qpi_ctl_bandwidth_tx uncore interconnect Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data event=0,umask=0x4 018Bytes Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets qpi_data_bandwidth_tx uncore interconnect Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data event=0,umask=0x2 018Bytes Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. BDX does not support dynamic link speeds, so this frequency is fixed unc_q_cto_count uncore interconnect Count of CTO Events event=0x38 01 Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered unc_q_direct2core.failure_credits uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress Credits event=0x13,umask=0x2 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched unc_q_direct2core.failure_credits_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss event=0x13,umask=0x20 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set unc_q_direct2core.failure_credits_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid event=0x13,umask=0x8 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched unc_q_direct2core.failure_credits_rbt_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid event=0x13,umask=0x80 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits unc_q_direct2core.failure_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Miss event=0x13,umask=0x10 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits unc_q_direct2core.failure_rbt_hit uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Invalid event=0x13,umask=0x4 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set unc_q_direct2core.failure_rbt_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid event=0x13,umask=0x40 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits unc_q_direct2core.success_rbt_hit uncore interconnect Direct 2 Core Spawning; Spawn Success event=0x13,umask=0x1 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core unc_q_l1_power_cycles uncore interconnect Cycles in L1 event=0x12 01 Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode unc_q_rxl0p_power_cycles uncore interconnect Cycles in L0p event=0x10 01 Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_q_rxl0_power_cycles uncore interconnect Cycles in L0 event=0xf 01 Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_q_rxl_bypassed uncore interconnect Rx Flit Buffer Bypassed event=0x9 01 Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_q_rxl_crc_errors.link_init uncore interconnect CRC Errors Detected; LinkInit event=0x3,umask=0x1 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization unc_q_rxl_crc_errors.normal_op uncore interconnect UNC_Q_RxL_CRC_ERRORS.NORMAL_OP event=0x3,umask=0x2 01 unc_q_rxl_credits_consumed_vn0.drs uncore interconnect VN0 Credit Consumed; DRS event=0x1e,umask=0x1 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class unc_q_rxl_credits_consumed_vn0.hom uncore interconnect VN0 Credit Consumed; HOM event=0x1e,umask=0x8 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class unc_q_rxl_credits_consumed_vn0.ncb uncore interconnect VN0 Credit Consumed; NCB event=0x1e,umask=0x2 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class unc_q_rxl_credits_consumed_vn0.ncs uncore interconnect VN0 Credit Consumed; NCS event=0x1e,umask=0x4 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class unc_q_rxl_credits_consumed_vn0.ndr uncore interconnect VN0 Credit Consumed; NDR event=0x1e,umask=0x20 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class unc_q_rxl_credits_consumed_vn0.snp uncore interconnect VN0 Credit Consumed; SNP event=0x1e,umask=0x10 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class unc_q_rxl_credits_consumed_vn1.drs uncore interconnect VN1 Credit Consumed; DRS event=0x39,umask=0x1 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class unc_q_rxl_credits_consumed_vn1.hom uncore interconnect VN1 Credit Consumed; HOM event=0x39,umask=0x8 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class unc_q_rxl_credits_consumed_vn1.ncb uncore interconnect VN1 Credit Consumed; NCB event=0x39,umask=0x2 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class unc_q_rxl_credits_consumed_vn1.ncs uncore interconnect VN1 Credit Consumed; NCS event=0x39,umask=0x4 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class unc_q_rxl_credits_consumed_vn1.ndr uncore interconnect VN1 Credit Consumed; NDR event=0x39,umask=0x20 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class unc_q_rxl_credits_consumed_vn1.snp uncore interconnect VN1 Credit Consumed; SNP event=0x39,umask=0x10 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class unc_q_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x1d 01 Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_cycles_ne uncore interconnect RxQ Cycles Not Empty event=0xa 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy unc_q_rxl_cycles_ne_drs.vn0 uncore interconnect RxQ Cycles Not Empty - DRS; for VN0 event=0xf,umask=0x1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only unc_q_rxl_cycles_ne_drs.vn1 uncore interconnect RxQ Cycles Not Empty - DRS; for VN1 event=0xf,umask=0x2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only unc_q_rxl_cycles_ne_hom.vn0 uncore interconnect RxQ Cycles Not Empty - HOM; for VN0 event=0x12,umask=0x1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only unc_q_rxl_cycles_ne_hom.vn1 uncore interconnect RxQ Cycles Not Empty - HOM; for VN1 event=0x12,umask=0x2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only unc_q_rxl_cycles_ne_ncb.vn0 uncore interconnect RxQ Cycles Not Empty - NCB; for VN0 event=0x10,umask=0x1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only unc_q_rxl_cycles_ne_ncb.vn1 uncore interconnect RxQ Cycles Not Empty - NCB; for VN1 event=0x10,umask=0x2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only unc_q_rxl_cycles_ne_ncs.vn0 uncore interconnect RxQ Cycles Not Empty - NCS; for VN0 event=0x11,umask=0x1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only unc_q_rxl_cycles_ne_ncs.vn1 uncore interconnect RxQ Cycles Not Empty - NCS; for VN1 event=0x11,umask=0x2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only unc_q_rxl_cycles_ne_ndr.vn0 uncore interconnect RxQ Cycles Not Empty - NDR; for VN0 event=0x14,umask=0x1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only unc_q_rxl_cycles_ne_ndr.vn1 uncore interconnect RxQ Cycles Not Empty - NDR; for VN1 event=0x14,umask=0x2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only unc_q_rxl_cycles_ne_snp.vn0 uncore interconnect RxQ Cycles Not Empty - SNP; for VN0 event=0x13,umask=0x1 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only unc_q_rxl_cycles_ne_snp.vn1 uncore interconnect RxQ Cycles Not Empty - SNP; for VN1 event=0x13,umask=0x2 01 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only unc_q_rxl_flits_g0.idle uncore interconnect Flits Received - Group 0; Idle and Null Flits event=0x1,umask=0x1 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth unc_q_rxl_flits_g1.drs uncore interconnect Flits Received - Group 1; DRS Flits (both Header and Data) event=0x2,umask=0x18 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data unc_q_rxl_flits_g1.drs_data uncore interconnect Flits Received - Group 1; DRS Data Flits event=0x2,umask=0x8 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header) unc_q_rxl_flits_g1.drs_nondata uncore interconnect Flits Received - Group 1; DRS Header Flits event=0x2,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers unc_q_rxl_flits_g1.hom uncore interconnect Flits Received - Group 1; HOM Flits event=0x2,umask=0x6 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel unc_q_rxl_flits_g1.hom_nonreq uncore interconnect Flits Received - Group 1; HOM Non-Request Flits event=0x2,umask=0x4 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that unc_q_rxl_flits_g1.hom_req uncore interconnect Flits Received - Group 1; HOM Request Flits event=0x2,umask=0x2 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses unc_q_rxl_flits_g1.snp uncore interconnect Flits Received - Group 1; SNP Flits event=0x2,umask=0x1 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel unc_q_rxl_flits_g2.ncb uncore interconnect Flits Received - Group 2; Non-Coherent Rx Flits event=0x3,umask=0xc 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI unc_q_rxl_flits_g2.ncb_data uncore interconnect Flits Received - Group 2; Non-Coherent data Rx Flits event=0x3,umask=0x4 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers unc_q_rxl_flits_g2.ncb_nondata uncore interconnect Flits Received - Group 2; Non-Coherent non-data Rx Flits event=0x3,umask=0x8 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers unc_q_rxl_flits_g2.ncs uncore interconnect Flits Received - Group 2; Non-Coherent standard Rx Flits event=0x3,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers unc_q_rxl_flits_g2.ndr_ad uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AD event=0x3,umask=0x1 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring unc_q_rxl_flits_g2.ndr_ak uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AK event=0x3,umask=0x2 01 Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket unc_q_rxl_inserts uncore interconnect Rx Flit Buffer Allocations event=0x8 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_q_rxl_inserts_drs.vn0 uncore interconnect Rx Flit Buffer Allocations - DRS; for VN0 event=0x9,umask=0x1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits unc_q_rxl_inserts_drs.vn1 uncore interconnect Rx Flit Buffer Allocations - DRS; for VN1 event=0x9,umask=0x2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits unc_q_rxl_inserts_hom.vn0 uncore interconnect Rx Flit Buffer Allocations - HOM; for VN0 event=0xc,umask=0x1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits unc_q_rxl_inserts_hom.vn1 uncore interconnect Rx Flit Buffer Allocations - HOM; for VN1 event=0xc,umask=0x2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits unc_q_rxl_inserts_ncb.vn0 uncore interconnect Rx Flit Buffer Allocations - NCB; for VN0 event=0xa,umask=0x1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits unc_q_rxl_inserts_ncb.vn1 uncore interconnect Rx Flit Buffer Allocations - NCB; for VN1 event=0xa,umask=0x2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits unc_q_rxl_inserts_ncs.vn0 uncore interconnect Rx Flit Buffer Allocations - NCS; for VN0 event=0xb,umask=0x1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits unc_q_rxl_inserts_ncs.vn1 uncore interconnect Rx Flit Buffer Allocations - NCS; for VN1 event=0xb,umask=0x2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits unc_q_rxl_inserts_ndr.vn0 uncore interconnect Rx Flit Buffer Allocations - NDR; for VN0 event=0xe,umask=0x1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits unc_q_rxl_inserts_ndr.vn1 uncore interconnect Rx Flit Buffer Allocations - NDR; for VN1 event=0xe,umask=0x2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits unc_q_rxl_inserts_snp.vn0 uncore interconnect Rx Flit Buffer Allocations - SNP; for VN0 event=0xd,umask=0x1 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits unc_q_rxl_inserts_snp.vn1 uncore interconnect Rx Flit Buffer Allocations - SNP; for VN1 event=0xd,umask=0x2 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits unc_q_rxl_occupancy uncore interconnect RxQ Occupancy - All Packets event=0xb 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_q_rxl_occupancy_drs.vn0 uncore interconnect RxQ Occupancy - DRS; for VN0 event=0x15,umask=0x1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only unc_q_rxl_occupancy_drs.vn1 uncore interconnect RxQ Occupancy - DRS; for VN1 event=0x15,umask=0x2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only unc_q_rxl_occupancy_hom.vn0 uncore interconnect RxQ Occupancy - HOM; for VN0 event=0x18,umask=0x1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only unc_q_rxl_occupancy_hom.vn1 uncore interconnect RxQ Occupancy - HOM; for VN1 event=0x18,umask=0x2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only unc_q_rxl_occupancy_ncb.vn0 uncore interconnect RxQ Occupancy - NCB; for VN0 event=0x16,umask=0x1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only unc_q_rxl_occupancy_ncb.vn1 uncore interconnect RxQ Occupancy - NCB; for VN1 event=0x16,umask=0x2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only unc_q_rxl_occupancy_ncs.vn0 uncore interconnect RxQ Occupancy - NCS; for VN0 event=0x17,umask=0x1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only unc_q_rxl_occupancy_ncs.vn1 uncore interconnect RxQ Occupancy - NCS; for VN1 event=0x17,umask=0x2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only unc_q_rxl_occupancy_ndr.vn0 uncore interconnect RxQ Occupancy - NDR; for VN0 event=0x1a,umask=0x1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only unc_q_rxl_occupancy_ndr.vn1 uncore interconnect RxQ Occupancy - NDR; for VN1 event=0x1a,umask=0x2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only unc_q_rxl_occupancy_snp.vn0 uncore interconnect RxQ Occupancy - SNP; for VN0 event=0x19,umask=0x1 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only unc_q_rxl_occupancy_snp.vn1 uncore interconnect RxQ Occupancy - SNP; for VN1 event=0x19,umask=0x2 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only unc_q_rxl_stalls_vn0.bgf_drs uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - HOM event=0x35,umask=0x1 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_hom uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - DRS event=0x35,umask=0x8 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ncb uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - SNP event=0x35,umask=0x2 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ncs uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NDR event=0x35,umask=0x4 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ndr uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NCS event=0x35,umask=0x20 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_snp uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NCB event=0x35,umask=0x10 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.egress_credits uncore interconnect Stalls Sending to R3QPI on VN0; Egress Credits event=0x35,umask=0x40 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events unc_q_rxl_stalls_vn0.gv uncore interconnect Stalls Sending to R3QPI on VN0; GV event=0x35,umask=0x80 01 Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place unc_q_rxl_stalls_vn1.bgf_drs uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - HOM event=0x3a,umask=0x1 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_hom uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - DRS event=0x3a,umask=0x8 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ncb uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - SNP event=0x3a,umask=0x2 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ncs uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NDR event=0x3a,umask=0x4 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ndr uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NCS event=0x3a,umask=0x20 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_snp uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NCB event=0x3a,umask=0x10 01 Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_txl0p_power_cycles uncore interconnect Cycles in L0p event=0xd 01 Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_q_txl0_power_cycles uncore interconnect Cycles in L0 event=0xc 01 Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_q_txl_bypassed uncore interconnect Tx Flit Buffer Bypassed event=0x5 01 Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_q_txl_crc_no_credits.almost_full uncore interconnect Cycles Stalled with no LLR Credits; LLR is almost full event=0x2,umask=0x2 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets unc_q_txl_crc_no_credits.full uncore interconnect Cycles Stalled with no LLR Credits; LLR is full event=0x2,umask=0x1 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets unc_q_txl_cycles_ne uncore interconnect Tx Flit Buffer Cycles not Empty event=0x6 01 Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_q_txl_flits_g0.data uncore interconnect Flits Transferred - Group 0; Data Tx Flits event=0,umask=0x2 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets unc_q_txl_flits_g0.non_data uncore interconnect Flits Transferred - Group 0; Non-Data protocol Tx Flits event=0,umask=0x4 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets unc_q_txl_flits_g1.drs uncore interconnect Flits Transferred - Group 1; DRS Flits (both Header and Data) event=0,umask=0x18 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency unc_q_txl_flits_g1.drs_data uncore interconnect Flits Transferred - Group 1; DRS Data Flits event=0,umask=0x8 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header) unc_q_txl_flits_g1.drs_nondata uncore interconnect Flits Transferred - Group 1; DRS Header Flits event=0,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers unc_q_txl_flits_g1.hom uncore interconnect Flits Transferred - Group 1; HOM Flits event=0,umask=0x6 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel unc_q_txl_flits_g1.hom_nonreq uncore interconnect Flits Transferred - Group 1; HOM Non-Request Flits event=0,umask=0x4 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that unc_q_txl_flits_g1.hom_req uncore interconnect Flits Transferred - Group 1; HOM Request Flits event=0,umask=0x2 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses unc_q_txl_flits_g1.snp uncore interconnect Flits Transferred - Group 1; SNP Flits event=0,umask=0x1 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel unc_q_txl_flits_g2.ncb uncore interconnect Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits event=0x1,umask=0xc 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI unc_q_txl_flits_g2.ncb_data uncore interconnect Flits Transferred - Group 2; Non-Coherent data Tx Flits event=0x1,umask=0x4 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers unc_q_txl_flits_g2.ncb_nondata uncore interconnect Flits Transferred - Group 2; Non-Coherent non-data Tx Flits event=0x1,umask=0x8 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers unc_q_txl_flits_g2.ncs uncore interconnect Flits Transferred - Group 2; Non-Coherent standard Tx Flits event=0x1,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers unc_q_txl_flits_g2.ndr_ad uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AD event=0x1,umask=0x1 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring unc_q_txl_flits_g2.ndr_ak uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AK event=0x1,umask=0x2 01 Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket unc_q_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=0x4 01 Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_q_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=0x7 01 Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_q_txr_ad_hom_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - HOM; for VN0 event=0x26,umask=0x1 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD unc_q_txr_ad_hom_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - HOM; for VN1 event=0x26,umask=0x2 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD unc_q_txr_ad_hom_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD HOM; for VN0 event=0x22,umask=0x1 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD unc_q_txr_ad_hom_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD HOM; for VN1 event=0x22,umask=0x2 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD unc_q_txr_ad_ndr_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN0 event=0x28,umask=0x1 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN1 event=0x28,umask=0x2 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN0 event=0x24,umask=0x1 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN1 event=0x24,umask=0x2 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD unc_q_txr_ad_snp_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - SNP; for VN0 event=0x27,umask=0x1 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - SNP; for VN1 event=0x27,umask=0x2 01 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD SNP; for VN0 event=0x23,umask=0x1 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD SNP; for VN1 event=0x23,umask=0x2 01 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD unc_q_txr_ak_ndr_credit_acquired uncore interconnect R3QPI Egress Credit Occupancy - AK NDR event=0x29 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy uncore interconnect R3QPI Egress Credit Occupancy - AK NDR event=0x25 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress unc_q_txr_bl_drs_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - DRS; for VN0 event=0x2a,umask=0x1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - DRS; for VN1 event=0x2a,umask=0x2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_acquired.vn_shr uncore interconnect R3QPI Egress Credit Occupancy - DRS; for Shared VN event=0x2a,umask=0x4 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for VN0 event=0x1f,umask=0x1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for VN1 event=0x1f,umask=0x2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn_shr uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for Shared VN event=0x1f,umask=0x4 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress unc_q_txr_bl_ncb_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - NCB; for VN0 event=0x2b,umask=0x1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - NCB; for VN1 event=0x2b,umask=0x2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL NCB; for VN0 event=0x20,umask=0x1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL NCB; for VN1 event=0x20,umask=0x2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress unc_q_txr_bl_ncs_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - NCS; for VN0 event=0x2c,umask=0x1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - NCS; for VN1 event=0x2c,umask=0x2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL NCS; for VN0 event=0x21,umask=0x1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL NCS; for VN1 event=0x21,umask=0x2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress unc_q_vna_credit_returns uncore interconnect VNA Credits Returned event=0x1c 01 Number of VNA credits returned unc_q_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x1b 01 Number of VNA credits in the Rx side that are waitng to be returned back across the link uncore_r3qpi unc_r3_clockticks uncore interconnect Number of uclks in domain event=0x1 01 Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_r3_c_hi_ad_credits_empty.cbo10 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x4 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10 unc_r3_c_hi_ad_credits_empty.cbo11 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x8 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11 unc_r3_c_hi_ad_credits_empty.cbo12 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12 unc_r3_c_hi_ad_credits_empty.cbo13 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13 unc_r3_c_hi_ad_credits_empty.cbo14_16 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16 unc_r3_c_hi_ad_credits_empty.cbo8 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x1 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8 unc_r3_c_hi_ad_credits_empty.cbo9 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x2 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9 unc_r3_c_hi_ad_credits_empty.cbo_15_17 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x80 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17 unc_r3_c_lo_ad_credits_empty.cbo0 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x1 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0 unc_r3_c_lo_ad_credits_empty.cbo1 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x2 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1 unc_r3_c_lo_ad_credits_empty.cbo2 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x4 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2 unc_r3_c_lo_ad_credits_empty.cbo3 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x8 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3 unc_r3_c_lo_ad_credits_empty.cbo4 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4 unc_r3_c_lo_ad_credits_empty.cbo5 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5 unc_r3_c_lo_ad_credits_empty.cbo6 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6 unc_r3_c_lo_ad_credits_empty.cbo7 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x80 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7 unc_r3_ha_r2_bl_credits_empty.ha0 uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=0x1 01 No credits available to send to either HA or R2 on the BL Ring; HA0 unc_r3_ha_r2_bl_credits_empty.ha1 uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=0x2 01 No credits available to send to either HA or R2 on the BL Ring; HA1 unc_r3_ha_r2_bl_credits_empty.r2_ncb uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=0x4 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages unc_r3_ha_r2_bl_credits_empty.r2_ncs uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=0x8 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages unc_r3_iot_backpressure.hub uncore interconnect IOT Backpressure event=0xb,umask=0x2 01 unc_r3_iot_backpressure.sat uncore interconnect IOT Backpressure event=0xb,umask=0x1 01 unc_r3_iot_cts_hi.cts2 uncore interconnect IOT Common Trigger Sequencer - Hi event=0xd,umask=0x1 01 Debug Mask/Match Tie-Ins unc_r3_iot_cts_hi.cts3 uncore interconnect IOT Common Trigger Sequencer - Hi event=0xd,umask=0x2 01 Debug Mask/Match Tie-Ins unc_r3_iot_cts_lo.cts0 uncore interconnect IOT Common Trigger Sequencer - Lo event=0xc,umask=0x1 01 Debug Mask/Match Tie-Ins unc_r3_iot_cts_lo.cts1 uncore interconnect IOT Common Trigger Sequencer - Lo event=0xc,umask=0x2 01 Debug Mask/Match Tie-Ins unc_r3_qpi0_ad_credits_empty.vn0_hom uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x2 01 No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages unc_r3_qpi0_ad_credits_empty.vn0_ndr uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x8 01 No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages unc_r3_qpi0_ad_credits_empty.vn0_snp uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x4 01 No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages unc_r3_qpi0_ad_credits_empty.vn1_hom uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x10 01 No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages unc_r3_qpi0_ad_credits_empty.vn1_ndr uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x40 01 No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages unc_r3_qpi0_ad_credits_empty.vn1_snp uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x20 01 No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages unc_r3_qpi0_ad_credits_empty.vna uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x1 01 No credits available to send to QPI0 on the AD Ring; VNA unc_r3_qpi0_bl_credits_empty.vn1_hom uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x10 01 No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages unc_r3_qpi0_bl_credits_empty.vn1_ndr uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x40 01 No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages unc_r3_qpi0_bl_credits_empty.vn1_snp uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x20 01 No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages unc_r3_qpi0_bl_credits_empty.vna uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x1 01 No credits available to send to QPI0 on the BL Ring; VNA unc_r3_qpi1_ad_credits_empty.vn1_hom uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x10 01 No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages unc_r3_qpi1_ad_credits_empty.vn1_ndr uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x40 01 No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages unc_r3_qpi1_ad_credits_empty.vn1_snp uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x20 01 No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages unc_r3_qpi1_ad_credits_empty.vna uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x1 01 No credits available to send to QPI1 on the AD Ring; VNA unc_r3_qpi1_bl_credits_empty.vn0_hom uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x2 01 No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages unc_r3_qpi1_bl_credits_empty.vn0_ndr uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x8 01 No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages unc_r3_qpi1_bl_credits_empty.vn0_snp uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x4 01 No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages unc_r3_qpi1_bl_credits_empty.vn1_hom uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x10 01 No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages unc_r3_qpi1_bl_credits_empty.vn1_ndr uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x40 01 No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages unc_r3_qpi1_bl_credits_empty.vn1_snp uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x20 01 No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages unc_r3_qpi1_bl_credits_empty.vna uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x1 01 No credits available to send to QPI1 on the BL Ring; VNA unc_r3_ring_ad_used.all uncore interconnect R3 AD Ring in Use; All event=0x7,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw uncore interconnect R3 AD Ring in Use; Counterclockwise event=0x7,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even event=0x7,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_ad_used.ccw_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd event=0x7,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_ad_used.cw uncore interconnect R3 AD Ring in Use; Clockwise event=0x7,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_even uncore interconnect R3 AD Ring in Use; Clockwise and Even event=0x7,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_ad_used.cw_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd event=0x7,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_ak_used.all uncore interconnect R3 AK Ring in Use; All event=0x8,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw uncore interconnect R3 AK Ring in Use; Counterclockwise event=0x8,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even event=0x8,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_ak_used.ccw_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd event=0x8,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_ak_used.cw uncore interconnect R3 AK Ring in Use; Clockwise event=0x8,umask=0x3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.cw_even uncore interconnect R3 AK Ring in Use; Clockwise and Even event=0x8,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_ak_used.cw_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd event=0x8,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_bl_used.all uncore interconnect R3 BL Ring in Use; All event=0x9,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw uncore interconnect R3 BL Ring in Use; Counterclockwise event=0x9,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even event=0x9,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_bl_used.ccw_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd event=0x9,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_bl_used.cw uncore interconnect R3 BL Ring in Use; Clockwise event=0x9,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_even uncore interconnect R3 BL Ring in Use; Clockwise and Even event=0x9,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_bl_used.cw_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd event=0x9,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_iv_used.any uncore interconnect R3 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_iv_used.cw uncore interconnect R3 IV Ring in Use; Clockwise event=0xa,umask=0x3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_sink_starved.ak uncore interconnect Ring Stop Starved; AK event=0xe,umask=0x2 01 Number of cycles the ringstop is in starvation (per ring) unc_r3_rxr_cycles_ne.hom uncore interconnect Ingress Cycles Not Empty; HOM event=0x10,umask=0x1 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_cycles_ne.ndr uncore interconnect Ingress Cycles Not Empty; NDR event=0x10,umask=0x4 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_cycles_ne.snp uncore interconnect Ingress Cycles Not Empty; SNP event=0x10,umask=0x2 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_cycles_ne_vn1.drs uncore interconnect VN1 Ingress Cycles Not Empty; DRS event=0x14,umask=0x8 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_cycles_ne_vn1.hom uncore interconnect VN1 Ingress Cycles Not Empty; HOM event=0x14,umask=0x1 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_cycles_ne_vn1.ncb uncore interconnect VN1 Ingress Cycles Not Empty; NCB event=0x14,umask=0x10 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_cycles_ne_vn1.ncs uncore interconnect VN1 Ingress Cycles Not Empty; NCS event=0x14,umask=0x20 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_cycles_ne_vn1.ndr uncore interconnect VN1 Ingress Cycles Not Empty; NDR event=0x14,umask=0x4 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_cycles_ne_vn1.snp uncore interconnect VN1 Ingress Cycles Not Empty; SNP event=0x14,umask=0x2 01 Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_inserts.drs uncore interconnect Ingress Allocations; DRS event=0x11,umask=0x8 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_inserts.hom uncore interconnect Ingress Allocations; HOM event=0x11,umask=0x1 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_inserts.ncb uncore interconnect Ingress Allocations; NCB event=0x11,umask=0x10 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_inserts.ncs uncore interconnect Ingress Allocations; NCS event=0x11,umask=0x20 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_inserts.ndr uncore interconnect Ingress Allocations; NDR event=0x11,umask=0x4 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_inserts.snp uncore interconnect Ingress Allocations; SNP event=0x11,umask=0x2 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_inserts_vn1.drs uncore interconnect VN1 Ingress Allocations; DRS event=0x15,umask=0x8 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_inserts_vn1.hom uncore interconnect VN1 Ingress Allocations; HOM event=0x15,umask=0x1 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_inserts_vn1.ncb uncore interconnect VN1 Ingress Allocations; NCB event=0x15,umask=0x10 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_inserts_vn1.ncs uncore interconnect VN1 Ingress Allocations; NCS event=0x15,umask=0x20 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_inserts_vn1.ndr uncore interconnect VN1 Ingress Allocations; NDR event=0x15,umask=0x4 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_inserts_vn1.snp uncore interconnect VN1 Ingress Allocations; SNP event=0x15,umask=0x2 01 Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_occupancy_vn1.drs uncore interconnect VN1 Ingress Occupancy Accumulator; DRS event=0x13,umask=0x8 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r3_rxr_occupancy_vn1.hom uncore interconnect VN1 Ingress Occupancy Accumulator; HOM event=0x13,umask=0x1 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue unc_r3_rxr_occupancy_vn1.ncb uncore interconnect VN1 Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue unc_r3_rxr_occupancy_vn1.ncs uncore interconnect VN1 Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue unc_r3_rxr_occupancy_vn1.ndr uncore interconnect VN1 Ingress Occupancy Accumulator; NDR event=0x13,umask=0x4 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue unc_r3_rxr_occupancy_vn1.snp uncore interconnect VN1 Ingress Occupancy Accumulator; SNP event=0x13,umask=0x2 01 Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue unc_r3_sbo0_credits_acquired.ad uncore interconnect SBo0 Credits Acquired; For AD Ring event=0x28,umask=0x1 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r3_sbo0_credits_acquired.bl uncore interconnect SBo0 Credits Acquired; For BL Ring event=0x28,umask=0x2 01 Number of Sbo 0 credits acquired in a given cycle, per ring unc_r3_sbo0_credit_occupancy.ad uncore interconnect SBo0 Credits Occupancy; For AD Ring event=0x2a,umask=0x1 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r3_sbo0_credit_occupancy.bl uncore interconnect SBo0 Credits Occupancy; For BL Ring event=0x2a,umask=0x2 01 Number of Sbo 0 credits in use in a given cycle, per ring unc_r3_sbo1_credits_acquired.ad uncore interconnect SBo1 Credits Acquired; For AD Ring event=0x29,umask=0x1 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_r3_sbo1_credits_acquired.bl uncore interconnect SBo1 Credits Acquired; For BL Ring event=0x29,umask=0x2 01 Number of Sbo 1 credits acquired in a given cycle, per ring unc_r3_sbo1_credit_occupancy.ad uncore interconnect SBo1 Credits Occupancy; For AD Ring event=0x2b,umask=0x1 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_r3_sbo1_credit_occupancy.bl uncore interconnect SBo1 Credits Occupancy; For BL Ring event=0x2b,umask=0x2 01 Number of Sbo 1 credits in use in a given cycle, per ring unc_r3_stall_no_sbo_credit.sbo0_ad uncore interconnect Stall on No Sbo Credits; For SBo0, AD Ring event=0x2c,umask=0x1 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo0_bl uncore interconnect Stall on No Sbo Credits; For SBo0, BL Ring event=0x2c,umask=0x4 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo1_ad uncore interconnect Stall on No Sbo Credits; For SBo1, AD Ring event=0x2c,umask=0x2 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo1_bl uncore interconnect Stall on No Sbo Credits; For SBo1, BL Ring event=0x2c,umask=0x8 01 Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring unc_r3_txr_nack.dn_ad uncore interconnect Egress CCW NACK; AD CCW event=0x26,umask=0x1 01 AD CounterClockwise Egress Queue unc_r3_txr_nack.dn_ak uncore interconnect Egress CCW NACK; AK CCW event=0x26,umask=0x4 01 AK CounterClockwise Egress Queue unc_r3_txr_nack.dn_bl uncore interconnect Egress CCW NACK; BL CCW event=0x26,umask=0x2 01 BL CounterClockwise Egress Queue unc_r3_txr_nack.up_ad uncore interconnect Egress CCW NACK; AK CCW event=0x26,umask=0x8 01 BL CounterClockwise Egress Queue unc_r3_txr_nack.up_ak uncore interconnect Egress CCW NACK; BL CW event=0x26,umask=0x20 01 AD Clockwise Egress Queue unc_r3_txr_nack.up_bl uncore interconnect Egress CCW NACK; BL CCW event=0x26,umask=0x10 01 AD CounterClockwise Egress Queue unc_r3_vn0_credits_reject.drs uncore interconnect VN0 Credit Acquisition Failed on DRS; DRS Message Class event=0x37,umask=0x8 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn0_credits_reject.hom uncore interconnect VN0 Credit Acquisition Failed on DRS; HOM Message Class event=0x37,umask=0x1 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn0_credits_reject.ncb uncore interconnect VN0 Credit Acquisition Failed on DRS; NCB Message Class event=0x37,umask=0x10 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn0_credits_reject.ncs uncore interconnect VN0 Credit Acquisition Failed on DRS; NCS Message Class event=0x37,umask=0x20 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn0_credits_reject.ndr uncore interconnect VN0 Credit Acquisition Failed on DRS; NDR Message Class event=0x37,umask=0x4 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn0_credits_reject.snp uncore interconnect VN0 Credit Acquisition Failed on DRS; SNP Message Class event=0x37,umask=0x2 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vn0_credits_used.drs uncore interconnect VN0 Credit Used; DRS Message Class event=0x36,umask=0x8 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn0_credits_used.hom uncore interconnect VN0 Credit Used; HOM Message Class event=0x36,umask=0x1 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; NCB Message Class event=0x36,umask=0x10 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCS Message Class event=0x36,umask=0x20 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn0_credits_used.ndr uncore interconnect VN0 Credit Used; NDR Message Class event=0x36,umask=0x4 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP Message Class event=0x36,umask=0x2 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vn1_credits_reject.drs uncore interconnect VN1 Credit Acquisition Failed on DRS; DRS Message Class event=0x39,umask=0x8 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn1_credits_reject.hom uncore interconnect VN1 Credit Acquisition Failed on DRS; HOM Message Class event=0x39,umask=0x1 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn1_credits_reject.ncb uncore interconnect VN1 Credit Acquisition Failed on DRS; NCB Message Class event=0x39,umask=0x10 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn1_credits_reject.ncs uncore interconnect VN1 Credit Acquisition Failed on DRS; NCS Message Class event=0x39,umask=0x20 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn1_credits_reject.ndr uncore interconnect VN1 Credit Acquisition Failed on DRS; NDR Message Class event=0x39,umask=0x4 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn1_credits_reject.snp uncore interconnect VN1 Credit Acquisition Failed on DRS; SNP Message Class event=0x39,umask=0x2 01 Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vn1_credits_used.drs uncore interconnect VN1 Credit Used; DRS Message Class event=0x38,umask=0x8 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn1_credits_used.hom uncore interconnect VN1 Credit Used; HOM Message Class event=0x38,umask=0x1 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn1_credits_used.ncb uncore interconnect VN1 Credit Used; NCB Message Class event=0x38,umask=0x10 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vn1_credits_used.ncs uncore interconnect VN1 Credit Used; NCS Message Class event=0x38,umask=0x20 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? unc_r3_vn1_credits_used.ndr uncore interconnect VN1 Credit Used; NDR Message Class event=0x38,umask=0x4 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn1_credits_used.snp uncore interconnect VN1 Credit Used; SNP Message Class event=0x38,umask=0x2 01 Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class unc_r3_vna_credits_acquired.ad uncore interconnect VNA credit Acquisitions; HOM Message Class event=0x33,umask=0x1 01 Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_acquired.bl uncore interconnect VNA credit Acquisitions; HOM Message Class event=0x33,umask=0x4 01 Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_reject.drs uncore interconnect VNA Credit Reject; DRS Message Class event=0x34,umask=0x8 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vna_credits_reject.hom uncore interconnect VNA Credit Reject; HOM Message Class event=0x34,umask=0x1 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_reject.ncb uncore interconnect VNA Credit Reject; NCB Message Class event=0x34,umask=0x10 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_r3_vna_credits_reject.ncs uncore interconnect VNA Credit Reject; NCS Message Class event=0x34,umask=0x20 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS) unc_r3_vna_credits_reject.ndr uncore interconnect VNA Credit Reject; NDR Message Class event=0x34,umask=0x4 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vna_credits_reject.snp uncore interconnect VNA Credit Reject; SNP Message Class event=0x34,umask=0x2 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class uncore_sbox unc_s_bounce_control uncore interconnect Bounce Control event=0xa 01 unc_s_clockticks uncore interconnect Uncore Clocks event=0 01 unc_s_fast_asserted uncore interconnect FaST wire asserted event=0x9 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_s_ring_ad_used.all uncore interconnect AD Ring In Use; All event=0x1b,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.down uncore interconnect AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.down_even uncore interconnect AD Ring In Use; Down and Event event=0x1b,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ad_used.down_odd uncore interconnect AD Ring In Use; Down and Odd event=0x1b,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ad_used.up uncore interconnect AD Ring In Use; Up event=0x1b,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.up_even uncore interconnect AD Ring In Use; Up and Even event=0x1b,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ad_used.up_odd uncore interconnect AD Ring In Use; Up and Odd event=0x1b,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_ak_used.all uncore interconnect AK Ring In Use; All event=0x1c,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.down uncore interconnect AK Ring In Use; Down event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.down_even uncore interconnect AK Ring In Use; Down and Event event=0x1c,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ak_used.down_odd uncore interconnect AK Ring In Use; Down and Odd event=0x1c,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ak_used.up uncore interconnect AK Ring In Use; Up event=0x1c,umask=0x3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.up_even uncore interconnect AK Ring In Use; Up and Even event=0x1c,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ak_used.up_odd uncore interconnect AK Ring In Use; Up and Odd event=0x1c,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bl_used.all uncore interconnect BL Ring in Use; All event=0x1d,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.down uncore interconnect BL Ring in Use; Down event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.down_even uncore interconnect BL Ring in Use; Down and Event event=0x1d,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_bl_used.down_odd uncore interconnect BL Ring in Use; Down and Odd event=0x1d,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_bl_used.up uncore interconnect BL Ring in Use; Up event=0x1d,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.up_even uncore interconnect BL Ring in Use; Up and Even event=0x1d,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_bl_used.up_odd uncore interconnect BL Ring in Use; Up and Odd event=0x1d,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bounces.ad_cache uncore interconnect Number of LLC responses that bounced on the Ring event=0x5,umask=0x1 01 unc_s_ring_bounces.ak_core uncore interconnect Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=0x5,umask=0x2 01 unc_s_ring_bounces.bl_core uncore interconnect Number of LLC responses that bounced on the Ring.; Data Responses to core event=0x5,umask=0x4 01 unc_s_ring_bounces.iv_core uncore interconnect Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=0x5,umask=0x8 01 unc_s_ring_iv_used.dn uncore interconnect BL Ring in Use; Any event=0x1e,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_s_ring_iv_used.up uncore interconnect BL Ring in Use; Any event=0x1e,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_s_ring_sink_starved.ad_cache uncore interconnect UNC_S_RING_SINK_STARVED.AD_CACHE event=0x6,umask=0x1 01 unc_s_ring_sink_starved.ak_core uncore interconnect UNC_S_RING_SINK_STARVED.AK_CORE event=0x6,umask=0x2 01 unc_s_ring_sink_starved.bl_core uncore interconnect UNC_S_RING_SINK_STARVED.BL_CORE event=0x6,umask=0x4 01 unc_s_ring_sink_starved.iv_core uncore interconnect UNC_S_RING_SINK_STARVED.IV_CORE event=0x6,umask=0x8 01 unc_s_rxr_busy_starved.ad_bnc uncore interconnect Injection Starvation; AD - Bounces event=0x15,umask=0x2 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_busy_starved.ad_crd uncore interconnect Injection Starvation; AD - Credits event=0x15,umask=0x1 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_busy_starved.bl_bnc uncore interconnect Injection Starvation; BL - Bounces event=0x15,umask=0x8 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_busy_starved.bl_crd uncore interconnect Injection Starvation; BL - Credits event=0x15,umask=0x4 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent unc_s_rxr_bypass.ad_bnc uncore interconnect Bypass; AD - Bounces event=0x12,umask=0x2 01 Bypass the Sbo Ingress unc_s_rxr_bypass.ad_crd uncore interconnect Bypass; AD - Credits event=0x12,umask=0x1 01 Bypass the Sbo Ingress unc_s_rxr_bypass.ak uncore interconnect Bypass; AK event=0x12,umask=0x10 01 Bypass the Sbo Ingress unc_s_rxr_bypass.bl_bnc uncore interconnect Bypass; BL - Bounces event=0x12,umask=0x8 01 Bypass the Sbo Ingress unc_s_rxr_bypass.bl_crd uncore interconnect Bypass; BL - Credits event=0x12,umask=0x4 01 Bypass the Sbo Ingress unc_s_rxr_bypass.iv uncore interconnect Bypass; IV event=0x12,umask=0x20 01 Bypass the Sbo Ingress unc_s_rxr_crd_starved.ad_bnc uncore interconnect Injection Starvation; AD - Bounces event=0x14,umask=0x2 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ad_crd uncore interconnect Injection Starvation; AD - Credits event=0x14,umask=0x1 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ak uncore interconnect Injection Starvation; AK event=0x14,umask=0x10 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.bl_bnc uncore interconnect Injection Starvation; BL - Bounces event=0x14,umask=0x8 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.bl_crd uncore interconnect Injection Starvation; BL - Credits event=0x14,umask=0x4 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ifv uncore interconnect Injection Starvation; IVF Credit event=0x14,umask=0x40 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.iv uncore interconnect Injection Starvation; IV event=0x14,umask=0x20 01 Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_inserts.ad_bnc uncore interconnect Ingress Allocations; AD - Bounces event=0x13,umask=0x2 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.ad_crd uncore interconnect Ingress Allocations; AD - Credits event=0x13,umask=0x1 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.ak uncore interconnect Ingress Allocations; AK event=0x13,umask=0x10 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.bl_bnc uncore interconnect Ingress Allocations; BL - Bounces event=0x13,umask=0x8 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.bl_crd uncore interconnect Ingress Allocations; BL - Credits event=0x13,umask=0x4 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.iv uncore interconnect Ingress Allocations; IV event=0x13,umask=0x20 01 Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ad_bnc uncore interconnect Ingress Occupancy; AD - Bounces event=0x11,umask=0x2 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ad_crd uncore interconnect Ingress Occupancy; AD - Credits event=0x11,umask=0x1 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ak uncore interconnect Ingress Occupancy; AK event=0x11,umask=0x10 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.bl_bnc uncore interconnect Ingress Occupancy; BL - Bounces event=0x11,umask=0x8 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.bl_crd uncore interconnect Ingress Occupancy; BL - Credits event=0x11,umask=0x4 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.iv uncore interconnect Ingress Occupancy; IV event=0x11,umask=0x20 01 Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring unc_s_txr_ads_used.ad uncore interconnect UNC_S_TxR_ADS_USED.AD event=0x4,umask=0x1 01 unc_s_txr_ads_used.ak uncore interconnect UNC_S_TxR_ADS_USED.AK event=0x4,umask=0x2 01 unc_s_txr_ads_used.bl uncore interconnect UNC_S_TxR_ADS_USED.BL event=0x4,umask=0x4 01 unc_s_txr_inserts.ad_bnc uncore interconnect Egress Allocations; AD - Bounces event=0x2,umask=0x2 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.ad_crd uncore interconnect Egress Allocations; AD - Credits event=0x2,umask=0x1 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.ak uncore interconnect Egress Allocations; AK event=0x2,umask=0x10 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.bl_bnc uncore interconnect Egress Allocations; BL - Bounces event=0x2,umask=0x8 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.bl_crd uncore interconnect Egress Allocations; BL - Credits event=0x2,umask=0x4 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.iv uncore interconnect Egress Allocations; IV event=0x2,umask=0x20 01 Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ad_bnc uncore interconnect Egress Occupancy; AD - Bounces event=0x1,umask=0x2 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ad_crd uncore interconnect Egress Occupancy; AD - Credits event=0x1,umask=0x1 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ak uncore interconnect Egress Occupancy; AK event=0x1,umask=0x10 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.bl_bnc uncore interconnect Egress Occupancy; BL - Bounces event=0x1,umask=0x8 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.bl_crd uncore interconnect Egress Occupancy; BL - Credits event=0x1,umask=0x4 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.iv uncore interconnect Egress Occupancy; IV event=0x1,umask=0x20 01 Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring unc_s_txr_starved.ad uncore interconnect Injection Starvation; Onto AD Ring event=0x3,umask=0x1 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.ak uncore interconnect Injection Starvation; Onto AK Ring event=0x3,umask=0x2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.bl uncore interconnect Injection Starvation; Onto BL Ring event=0x3,umask=0x4 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.iv uncore interconnect Injection Starvation; Onto IV Ring event=0x3,umask=0x8 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_u_clockticks uncore interconnect Clockticks in the UBOX using a dedicated 48-bit Fixed Counter event=0xff 01 llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=0x4,umask=0x3 0164Bytes DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills) llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=0x4,umask=0xc 0164Bytes DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel unc_m_clockticks uncore memory Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter event=0xff 01 unc_m_clockticks_p uncore memory Clockticks in the Memory Controller using one of the programmable counters event=0 01 unc_m_dclockticks uncore memory This event is deprecated. Refer to new event UNC_M_CLOCKTICKS_P event=0 01 l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=0x1 00 Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch event=0x48,period=2000003,umask=0x2 00 Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions l1d_pend_miss.pending cache L1D miss outstandings duration in cycles event=0x48,period=2000003,umask=0x1 00 Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=0x1 00 Counts duration of L1D miss outstanding in cycles l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=0x1f 00 Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.non_silent cache Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped event=0xf2,period=200003,umask=0x2 00 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped l2_lines_out.silent cache Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event event=0xf2,period=200003,umask=0x1 00 l2_lines_out.useless_hwpf cache Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache event=0xf2,period=200003,umask=0x4 00 l2_lines_out.useless_pref cache This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF event=0xf2,period=200003,umask=0x4 10 l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0xe1 00 Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27 00 Demand requests that miss L2 cache l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7 00 Demand requests to L2 cache l2_rqsts.all_pf cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches event=0x24,period=200003,umask=0xf8 00 Counts the total number of requests from the L2 hardware prefetchers l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects event=0x24,period=200003,umask=0x21 00 Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f 00 All requests that miss L2 cache l2_rqsts.pf_hit cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache event=0x24,period=200003,umask=0xd8 00 Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache l2_rqsts.pf_miss cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache event=0x24,period=200003,umask=0x38 00 Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff 00 All L2 requests l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 Counts L2 writebacks that access L2 cache longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 Spec update: SKL057 event=0x2e,period=100003,umask=0x41 00 Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3 Spec update: SKL057 longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 Spec update: SKL057 event=0x2e,period=100003,umask=0x4f 00 Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3 Spec update: SKL057 mem_inst_retired.all_loads cache Retired load instructions Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x81 00 Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise (Precise event) mem_inst_retired.all_stores cache Retired store instructions Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x82 00 Counts all retired store instructions Supports address when precise (Precise event) mem_inst_retired.any cache All retired memory instructions Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x83 00 Counts all retired memory instructions - loads and stores Supports address when precise (Precise event) mem_inst_retired.lock_loads cache Retired load instructions with locked access Supports address when precise (Precise event) event=0xd0,period=100007,umask=0x21 00 mem_load_l3_hit_retired.xsnp_hit cache Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x2 00 Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions which data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x4 00 Retired load instructions which data sources were HitM responses from shared L3 Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x1 00 mem_load_l3_hit_retired.xsnp_none cache Retired load instructions which data sources were hits in L3 without snoops required Supports address when precise (Precise event) event=0xd2,period=100003,umask=0x8 00 Retired load instructions which data sources were hits in L3 without snoops required Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_dram cache Retired load instructions which data sources missed L3 but serviced from remote dram Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x2 00 mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise event=0xd3,period=100007,umask=0x8 00 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise mem_load_l3_miss_retired.remote_hitm cache Retired load instructions whose data sources was remote HITM Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x4 00 Retired load instructions whose data sources was remote HITM Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_pmm cache Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x10 00 Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode) Supports address when precise (Precise event) mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=0x4 00 mem_load_retired.fb_hit cache Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x40 00 Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=2000003,umask=0x1 00 Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source Supports address when precise (Precise event) mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x8 00 Counts retired load instructions with at least one uop that missed in the L1 cache Supports address when precise (Precise event) mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x2 00 Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x10 00 Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x4 00 Counts retired load instructions with at least one uop that hit in the L3 cache Supports address when precise (Precise event) mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x20 00 Counts retired load instructions with at least one uop that missed in the L3 cache Supports address when precise (Precise event) mem_load_retired.local_pmm cache Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x80 00 Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode) Supports address when precise (Precise event) ocr.all_data_rd.l3_hit.any_snoop cache OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0491 00 ocr.all_data_rd.l3_hit.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0491 00 ocr.all_data_rd.l3_hit.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0491 00 ocr.all_data_rd.l3_hit.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0491 00 ocr.all_data_rd.l3_hit.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0491 00 ocr.all_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0491 00 ocr.all_data_rd.l3_hit.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0491 00 ocr.all_data_rd.l3_hit.snoop_none cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0491 00 ocr.all_data_rd.l3_hit_e.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080491 00 ocr.all_data_rd.l3_hit_e.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080491 00 ocr.all_data_rd.l3_hit_e.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080491 00 ocr.all_data_rd.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080491 00 ocr.all_data_rd.l3_hit_e.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080491 00 ocr.all_data_rd.l3_hit_e.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080491 00 ocr.all_data_rd.l3_hit_e.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080491 00 ocr.all_data_rd.l3_hit_f.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200491 00 ocr.all_data_rd.l3_hit_f.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200491 00 ocr.all_data_rd.l3_hit_f.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200491 00 ocr.all_data_rd.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200491 00 ocr.all_data_rd.l3_hit_f.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200491 00 ocr.all_data_rd.l3_hit_f.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200491 00 ocr.all_data_rd.l3_hit_f.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200491 00 ocr.all_data_rd.l3_hit_m.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040491 00 ocr.all_data_rd.l3_hit_m.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040491 00 ocr.all_data_rd.l3_hit_m.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040491 00 ocr.all_data_rd.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040491 00 ocr.all_data_rd.l3_hit_m.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040491 00 ocr.all_data_rd.l3_hit_m.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040491 00 ocr.all_data_rd.l3_hit_m.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040491 00 ocr.all_data_rd.l3_hit_s.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100491 00 ocr.all_data_rd.l3_hit_s.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100491 00 ocr.all_data_rd.l3_hit_s.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100491 00 ocr.all_data_rd.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100491 00 ocr.all_data_rd.l3_hit_s.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100491 00 ocr.all_data_rd.l3_hit_s.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100491 00 ocr.all_data_rd.l3_hit_s.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100491 00 ocr.all_pf_data_rd.l3_hit.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0490 00 ocr.all_pf_data_rd.l3_hit.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0490 00 ocr.all_pf_data_rd.l3_hit.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0490 00 ocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0490 00 ocr.all_pf_data_rd.l3_hit.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0490 00 ocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0490 00 ocr.all_pf_data_rd.l3_hit.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0490 00 ocr.all_pf_data_rd.l3_hit.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0490 00 ocr.all_pf_data_rd.l3_hit_e.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080490 00 ocr.all_pf_data_rd.l3_hit_e.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080490 00 ocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080490 00 ocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080490 00 ocr.all_pf_data_rd.l3_hit_e.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080490 00 ocr.all_pf_data_rd.l3_hit_e.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080490 00 ocr.all_pf_data_rd.l3_hit_e.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080490 00 ocr.all_pf_data_rd.l3_hit_f.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200490 00 ocr.all_pf_data_rd.l3_hit_f.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200490 00 ocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200490 00 ocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200490 00 ocr.all_pf_data_rd.l3_hit_f.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200490 00 ocr.all_pf_data_rd.l3_hit_f.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200490 00 ocr.all_pf_data_rd.l3_hit_f.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200490 00 ocr.all_pf_data_rd.l3_hit_m.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040490 00 ocr.all_pf_data_rd.l3_hit_m.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040490 00 ocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040490 00 ocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040490 00 ocr.all_pf_data_rd.l3_hit_m.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040490 00 ocr.all_pf_data_rd.l3_hit_m.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040490 00 ocr.all_pf_data_rd.l3_hit_m.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040490 00 ocr.all_pf_data_rd.l3_hit_s.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100490 00 ocr.all_pf_data_rd.l3_hit_s.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100490 00 ocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100490 00 ocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100490 00 ocr.all_pf_data_rd.l3_hit_s.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100490 00 ocr.all_pf_data_rd.l3_hit_s.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100490 00 ocr.all_pf_data_rd.l3_hit_s.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100490 00 ocr.all_pf_rfo.l3_hit.any_snoop cache OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0120 00 ocr.all_pf_rfo.l3_hit.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0120 00 ocr.all_pf_rfo.l3_hit.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0120 00 ocr.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0120 00 ocr.all_pf_rfo.l3_hit.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0120 00 ocr.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0120 00 ocr.all_pf_rfo.l3_hit.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0120 00 ocr.all_pf_rfo.l3_hit.snoop_none cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0120 00 ocr.all_pf_rfo.l3_hit_e.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080120 00 ocr.all_pf_rfo.l3_hit_e.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080120 00 ocr.all_pf_rfo.l3_hit_e.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080120 00 ocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080120 00 ocr.all_pf_rfo.l3_hit_e.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080120 00 ocr.all_pf_rfo.l3_hit_e.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080120 00 ocr.all_pf_rfo.l3_hit_e.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080120 00 ocr.all_pf_rfo.l3_hit_f.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200120 00 ocr.all_pf_rfo.l3_hit_f.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200120 00 ocr.all_pf_rfo.l3_hit_f.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200120 00 ocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200120 00 ocr.all_pf_rfo.l3_hit_f.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200120 00 ocr.all_pf_rfo.l3_hit_f.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200120 00 ocr.all_pf_rfo.l3_hit_f.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200120 00 ocr.all_pf_rfo.l3_hit_m.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040120 00 ocr.all_pf_rfo.l3_hit_m.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040120 00 ocr.all_pf_rfo.l3_hit_m.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040120 00 ocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040120 00 ocr.all_pf_rfo.l3_hit_m.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040120 00 ocr.all_pf_rfo.l3_hit_m.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040120 00 ocr.all_pf_rfo.l3_hit_m.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040120 00 ocr.all_pf_rfo.l3_hit_s.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100120 00 ocr.all_pf_rfo.l3_hit_s.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100120 00 ocr.all_pf_rfo.l3_hit_s.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100120 00 ocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100120 00 ocr.all_pf_rfo.l3_hit_s.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100120 00 ocr.all_pf_rfo.l3_hit_s.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100120 00 ocr.all_pf_rfo.l3_hit_s.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100120 00 ocr.all_reads.l3_hit.any_snoop cache OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C07F7 00 ocr.all_reads.l3_hit.hitm_other_core cache OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C07F7 00 ocr.all_reads.l3_hit.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C07F7 00 ocr.all_reads.l3_hit.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C07F7 00 ocr.all_reads.l3_hit.no_snoop_needed cache OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C07F7 00 ocr.all_reads.l3_hit.snoop_hit_with_fwd cache OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C07F7 00 ocr.all_reads.l3_hit.snoop_miss cache OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C07F7 00 ocr.all_reads.l3_hit.snoop_none cache OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C07F7 00 ocr.all_reads.l3_hit_e.any_snoop cache OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800807F7 00 ocr.all_reads.l3_hit_e.hitm_other_core cache OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000807F7 00 ocr.all_reads.l3_hit_e.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000807F7 00 ocr.all_reads.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000807F7 00 ocr.all_reads.l3_hit_e.no_snoop_needed cache OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000807F7 00 ocr.all_reads.l3_hit_e.snoop_miss cache OCR.ALL_READS.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000807F7 00 ocr.all_reads.l3_hit_e.snoop_none cache OCR.ALL_READS.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800807F7 00 ocr.all_reads.l3_hit_f.any_snoop cache OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F802007F7 00 ocr.all_reads.l3_hit_f.hitm_other_core cache OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002007F7 00 ocr.all_reads.l3_hit_f.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8002007F7 00 ocr.all_reads.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4002007F7 00 ocr.all_reads.l3_hit_f.no_snoop_needed cache OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002007F7 00 ocr.all_reads.l3_hit_f.snoop_miss cache OCR.ALL_READS.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002007F7 00 ocr.all_reads.l3_hit_f.snoop_none cache OCR.ALL_READS.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x802007F7 00 ocr.all_reads.l3_hit_m.any_snoop cache OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800407F7 00 ocr.all_reads.l3_hit_m.hitm_other_core cache OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000407F7 00 ocr.all_reads.l3_hit_m.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000407F7 00 ocr.all_reads.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000407F7 00 ocr.all_reads.l3_hit_m.no_snoop_needed cache OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000407F7 00 ocr.all_reads.l3_hit_m.snoop_miss cache OCR.ALL_READS.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000407F7 00 ocr.all_reads.l3_hit_m.snoop_none cache OCR.ALL_READS.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800407F7 00 ocr.all_reads.l3_hit_s.any_snoop cache OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F801007F7 00 ocr.all_reads.l3_hit_s.hitm_other_core cache OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001007F7 00 ocr.all_reads.l3_hit_s.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8001007F7 00 ocr.all_reads.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001007F7 00 ocr.all_reads.l3_hit_s.no_snoop_needed cache OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001007F7 00 ocr.all_reads.l3_hit_s.snoop_miss cache OCR.ALL_READS.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001007F7 00 ocr.all_reads.l3_hit_s.snoop_none cache OCR.ALL_READS.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801007F7 00 ocr.all_rfo.l3_hit.any_snoop cache OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0122 00 ocr.all_rfo.l3_hit.hitm_other_core cache OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122 00 ocr.all_rfo.l3_hit.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0122 00 ocr.all_rfo.l3_hit.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122 00 ocr.all_rfo.l3_hit.no_snoop_needed cache OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0122 00 ocr.all_rfo.l3_hit.snoop_hit_with_fwd cache OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0122 00 ocr.all_rfo.l3_hit.snoop_miss cache OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0122 00 ocr.all_rfo.l3_hit.snoop_none cache OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0122 00 ocr.all_rfo.l3_hit_e.any_snoop cache OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080122 00 ocr.all_rfo.l3_hit_e.hitm_other_core cache OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080122 00 ocr.all_rfo.l3_hit_e.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080122 00 ocr.all_rfo.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080122 00 ocr.all_rfo.l3_hit_e.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080122 00 ocr.all_rfo.l3_hit_e.snoop_miss cache OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080122 00 ocr.all_rfo.l3_hit_e.snoop_none cache OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080122 00 ocr.all_rfo.l3_hit_f.any_snoop cache OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200122 00 ocr.all_rfo.l3_hit_f.hitm_other_core cache OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200122 00 ocr.all_rfo.l3_hit_f.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200122 00 ocr.all_rfo.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200122 00 ocr.all_rfo.l3_hit_f.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200122 00 ocr.all_rfo.l3_hit_f.snoop_miss cache OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200122 00 ocr.all_rfo.l3_hit_f.snoop_none cache OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200122 00 ocr.all_rfo.l3_hit_m.any_snoop cache OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040122 00 ocr.all_rfo.l3_hit_m.hitm_other_core cache OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040122 00 ocr.all_rfo.l3_hit_m.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040122 00 ocr.all_rfo.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040122 00 ocr.all_rfo.l3_hit_m.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040122 00 ocr.all_rfo.l3_hit_m.snoop_miss cache OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040122 00 ocr.all_rfo.l3_hit_m.snoop_none cache OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040122 00 ocr.all_rfo.l3_hit_s.any_snoop cache OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100122 00 ocr.all_rfo.l3_hit_s.hitm_other_core cache OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100122 00 ocr.all_rfo.l3_hit_s.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100122 00 ocr.all_rfo.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100122 00 ocr.all_rfo.l3_hit_s.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100122 00 ocr.all_rfo.l3_hit_s.snoop_miss cache OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100122 00 ocr.all_rfo.l3_hit_s.snoop_none cache OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100122 00 ocr.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 00 ocr.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.l3_hit.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0004 00 ocr.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 00 ocr.demand_code_rd.l3_hit.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0004 00 ocr.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0004 00 ocr.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0004 00 ocr.demand_code_rd.l3_hit_e.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080004 00 ocr.demand_code_rd.l3_hit_e.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080004 00 ocr.demand_code_rd.l3_hit_e.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080004 00 ocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080004 00 ocr.demand_code_rd.l3_hit_e.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080004 00 ocr.demand_code_rd.l3_hit_e.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080004 00 ocr.demand_code_rd.l3_hit_e.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080004 00 ocr.demand_code_rd.l3_hit_f.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200004 00 ocr.demand_code_rd.l3_hit_f.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200004 00 ocr.demand_code_rd.l3_hit_f.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200004 00 ocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200004 00 ocr.demand_code_rd.l3_hit_f.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200004 00 ocr.demand_code_rd.l3_hit_f.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200004 00 ocr.demand_code_rd.l3_hit_f.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200004 00 ocr.demand_code_rd.l3_hit_m.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040004 00 ocr.demand_code_rd.l3_hit_m.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040004 00 ocr.demand_code_rd.l3_hit_m.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040004 00 ocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040004 00 ocr.demand_code_rd.l3_hit_m.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040004 00 ocr.demand_code_rd.l3_hit_m.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040004 00 ocr.demand_code_rd.l3_hit_m.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040004 00 ocr.demand_code_rd.l3_hit_s.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100004 00 ocr.demand_code_rd.l3_hit_s.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100004 00 ocr.demand_code_rd.l3_hit_s.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100004 00 ocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100004 00 ocr.demand_code_rd.l3_hit_s.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100004 00 ocr.demand_code_rd.l3_hit_s.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100004 00 ocr.demand_code_rd.l3_hit_s.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100004 00 ocr.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0001 00 ocr.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001 00 ocr.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0001 00 ocr.demand_data_rd.l3_hit_e.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080001 00 ocr.demand_data_rd.l3_hit_e.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080001 00 ocr.demand_data_rd.l3_hit_e.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080001 00 ocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080001 00 ocr.demand_data_rd.l3_hit_e.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080001 00 ocr.demand_data_rd.l3_hit_e.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080001 00 ocr.demand_data_rd.l3_hit_e.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080001 00 ocr.demand_data_rd.l3_hit_f.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200001 00 ocr.demand_data_rd.l3_hit_f.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200001 00 ocr.demand_data_rd.l3_hit_f.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200001 00 ocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200001 00 ocr.demand_data_rd.l3_hit_f.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200001 00 ocr.demand_data_rd.l3_hit_f.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200001 00 ocr.demand_data_rd.l3_hit_f.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200001 00 ocr.demand_data_rd.l3_hit_m.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040001 00 ocr.demand_data_rd.l3_hit_m.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040001 00 ocr.demand_data_rd.l3_hit_m.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040001 00 ocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040001 00 ocr.demand_data_rd.l3_hit_m.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040001 00 ocr.demand_data_rd.l3_hit_m.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040001 00 ocr.demand_data_rd.l3_hit_m.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040001 00 ocr.demand_data_rd.l3_hit_s.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100001 00 ocr.demand_data_rd.l3_hit_s.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100001 00 ocr.demand_data_rd.l3_hit_s.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100001 00 ocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100001 00 ocr.demand_data_rd.l3_hit_s.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100001 00 ocr.demand_data_rd.l3_hit_s.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100001 00 ocr.demand_data_rd.l3_hit_s.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100001 00 ocr.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.l3_hit.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0002 00 ocr.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 00 ocr.demand_rfo.l3_hit.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_with_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0002 00 ocr.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0002 00 ocr.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0002 00 ocr.demand_rfo.l3_hit_e.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080002 00 ocr.demand_rfo.l3_hit_e.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080002 00 ocr.demand_rfo.l3_hit_e.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080002 00 ocr.demand_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080002 00 ocr.demand_rfo.l3_hit_e.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080002 00 ocr.demand_rfo.l3_hit_e.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080002 00 ocr.demand_rfo.l3_hit_e.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080002 00 ocr.demand_rfo.l3_hit_f.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200002 00 ocr.demand_rfo.l3_hit_f.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200002 00 ocr.demand_rfo.l3_hit_f.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200002 00 ocr.demand_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200002 00 ocr.demand_rfo.l3_hit_f.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200002 00 ocr.demand_rfo.l3_hit_f.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200002 00 ocr.demand_rfo.l3_hit_f.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200002 00 ocr.demand_rfo.l3_hit_m.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040002 00 ocr.demand_rfo.l3_hit_m.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040002 00 ocr.demand_rfo.l3_hit_m.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040002 00 ocr.demand_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040002 00 ocr.demand_rfo.l3_hit_m.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040002 00 ocr.demand_rfo.l3_hit_m.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040002 00 ocr.demand_rfo.l3_hit_m.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040002 00 ocr.demand_rfo.l3_hit_s.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100002 00 ocr.demand_rfo.l3_hit_s.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100002 00 ocr.demand_rfo.l3_hit_s.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100002 00 ocr.demand_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100002 00 ocr.demand_rfo.l3_hit_s.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100002 00 ocr.demand_rfo.l3_hit_s.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100002 00 ocr.demand_rfo.l3_hit_s.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100002 00 ocr.other.l3_hit.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8000 00 ocr.other.l3_hit.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C8000 00 ocr.other.l3_hit.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C8000 00 ocr.other.l3_hit.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C8000 00 ocr.other.l3_hit.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C8000 00 ocr.other.l3_hit.snoop_hit_with_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C8000 00 ocr.other.l3_hit.snoop_miss cache Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C8000 00 ocr.other.l3_hit.snoop_none cache Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C8000 00 ocr.other.l3_hit_e.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80088000 00 ocr.other.l3_hit_e.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000088000 00 ocr.other.l3_hit_e.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800088000 00 ocr.other.l3_hit_e.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400088000 00 ocr.other.l3_hit_e.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100088000 00 ocr.other.l3_hit_e.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200088000 00 ocr.other.l3_hit_e.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80088000 00 ocr.other.l3_hit_f.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80208000 00 ocr.other.l3_hit_f.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000208000 00 ocr.other.l3_hit_f.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800208000 00 ocr.other.l3_hit_f.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400208000 00 ocr.other.l3_hit_f.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100208000 00 ocr.other.l3_hit_f.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200208000 00 ocr.other.l3_hit_f.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80208000 00 ocr.other.l3_hit_m.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80048000 00 ocr.other.l3_hit_m.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000048000 00 ocr.other.l3_hit_m.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800048000 00 ocr.other.l3_hit_m.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400048000 00 ocr.other.l3_hit_m.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100048000 00 ocr.other.l3_hit_m.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200048000 00 ocr.other.l3_hit_m.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80048000 00 ocr.other.l3_hit_s.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80108000 00 ocr.other.l3_hit_s.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000108000 00 ocr.other.l3_hit_s.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800108000 00 ocr.other.l3_hit_s.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400108000 00 ocr.other.l3_hit_s.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100108000 00 ocr.other.l3_hit_s.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200108000 00 ocr.other.l3_hit_s.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80108000 00 ocr.pf_l1d_and_sw.l3_hit.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0400 00 ocr.pf_l1d_and_sw.l3_hit.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0400 00 ocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0400 00 ocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0400 00 ocr.pf_l1d_and_sw.l3_hit.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0400 00 ocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0400 00 ocr.pf_l1d_and_sw.l3_hit.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0400 00 ocr.pf_l1d_and_sw.l3_hit.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0400 00 ocr.pf_l1d_and_sw.l3_hit_e.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080400 00 ocr.pf_l1d_and_sw.l3_hit_e.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080400 00 ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080400 00 ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080400 00 ocr.pf_l1d_and_sw.l3_hit_e.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080400 00 ocr.pf_l1d_and_sw.l3_hit_e.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080400 00 ocr.pf_l1d_and_sw.l3_hit_e.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080400 00 ocr.pf_l1d_and_sw.l3_hit_f.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200400 00 ocr.pf_l1d_and_sw.l3_hit_f.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200400 00 ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200400 00 ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200400 00 ocr.pf_l1d_and_sw.l3_hit_f.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200400 00 ocr.pf_l1d_and_sw.l3_hit_f.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200400 00 ocr.pf_l1d_and_sw.l3_hit_f.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200400 00 ocr.pf_l1d_and_sw.l3_hit_m.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040400 00 ocr.pf_l1d_and_sw.l3_hit_m.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040400 00 ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040400 00 ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040400 00 ocr.pf_l1d_and_sw.l3_hit_m.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040400 00 ocr.pf_l1d_and_sw.l3_hit_m.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040400 00 ocr.pf_l1d_and_sw.l3_hit_m.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040400 00 ocr.pf_l1d_and_sw.l3_hit_s.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100400 00 ocr.pf_l1d_and_sw.l3_hit_s.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100400 00 ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100400 00 ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100400 00 ocr.pf_l1d_and_sw.l3_hit_s.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100400 00 ocr.pf_l1d_and_sw.l3_hit_s.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100400 00 ocr.pf_l1d_and_sw.l3_hit_s.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100400 00 ocr.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010 00 ocr.pf_l2_data_rd.l3_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010 00 ocr.pf_l2_data_rd.l3_hit.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0010 00 ocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010 00 ocr.pf_l2_data_rd.l3_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010 00 ocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0010 00 ocr.pf_l2_data_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0010 00 ocr.pf_l2_data_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0010 00 ocr.pf_l2_data_rd.l3_hit_e.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080010 00 ocr.pf_l2_data_rd.l3_hit_e.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080010 00 ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080010 00 ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080010 00 ocr.pf_l2_data_rd.l3_hit_e.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080010 00 ocr.pf_l2_data_rd.l3_hit_e.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080010 00 ocr.pf_l2_data_rd.l3_hit_e.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080010 00 ocr.pf_l2_data_rd.l3_hit_f.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200010 00 ocr.pf_l2_data_rd.l3_hit_f.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200010 00 ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200010 00 ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200010 00 ocr.pf_l2_data_rd.l3_hit_f.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200010 00 ocr.pf_l2_data_rd.l3_hit_f.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200010 00 ocr.pf_l2_data_rd.l3_hit_f.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200010 00 ocr.pf_l2_data_rd.l3_hit_m.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040010 00 ocr.pf_l2_data_rd.l3_hit_m.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040010 00 ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040010 00 ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040010 00 ocr.pf_l2_data_rd.l3_hit_m.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040010 00 ocr.pf_l2_data_rd.l3_hit_m.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040010 00 ocr.pf_l2_data_rd.l3_hit_m.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040010 00 ocr.pf_l2_data_rd.l3_hit_s.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100010 00 ocr.pf_l2_data_rd.l3_hit_s.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100010 00 ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100010 00 ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100010 00 ocr.pf_l2_data_rd.l3_hit_s.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100010 00 ocr.pf_l2_data_rd.l3_hit_s.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100010 00 ocr.pf_l2_data_rd.l3_hit_s.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100010 00 ocr.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020 00 ocr.pf_l2_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020 00 ocr.pf_l2_rfo.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0020 00 ocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020 00 ocr.pf_l2_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020 00 ocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0020 00 ocr.pf_l2_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0020 00 ocr.pf_l2_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0020 00 ocr.pf_l2_rfo.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080020 00 ocr.pf_l2_rfo.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080020 00 ocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080020 00 ocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080020 00 ocr.pf_l2_rfo.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080020 00 ocr.pf_l2_rfo.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080020 00 ocr.pf_l2_rfo.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080020 00 ocr.pf_l2_rfo.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200020 00 ocr.pf_l2_rfo.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200020 00 ocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200020 00 ocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200020 00 ocr.pf_l2_rfo.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200020 00 ocr.pf_l2_rfo.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200020 00 ocr.pf_l2_rfo.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200020 00 ocr.pf_l2_rfo.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040020 00 ocr.pf_l2_rfo.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040020 00 ocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040020 00 ocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040020 00 ocr.pf_l2_rfo.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040020 00 ocr.pf_l2_rfo.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040020 00 ocr.pf_l2_rfo.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040020 00 ocr.pf_l2_rfo.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100020 00 ocr.pf_l2_rfo.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100020 00 ocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100020 00 ocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100020 00 ocr.pf_l2_rfo.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100020 00 ocr.pf_l2_rfo.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100020 00 ocr.pf_l2_rfo.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100020 00 ocr.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080 00 ocr.pf_l3_data_rd.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0080 00 ocr.pf_l3_data_rd.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0080 00 ocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0080 00 ocr.pf_l3_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0080 00 ocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0080 00 ocr.pf_l3_data_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0080 00 ocr.pf_l3_data_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0080 00 ocr.pf_l3_data_rd.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080080 00 ocr.pf_l3_data_rd.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080080 00 ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080080 00 ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080080 00 ocr.pf_l3_data_rd.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080080 00 ocr.pf_l3_data_rd.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080080 00 ocr.pf_l3_data_rd.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080080 00 ocr.pf_l3_data_rd.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200080 00 ocr.pf_l3_data_rd.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200080 00 ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200080 00 ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200080 00 ocr.pf_l3_data_rd.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200080 00 ocr.pf_l3_data_rd.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200080 00 ocr.pf_l3_data_rd.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200080 00 ocr.pf_l3_data_rd.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040080 00 ocr.pf_l3_data_rd.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040080 00 ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040080 00 ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040080 00 ocr.pf_l3_data_rd.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040080 00 ocr.pf_l3_data_rd.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040080 00 ocr.pf_l3_data_rd.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040080 00 ocr.pf_l3_data_rd.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100080 00 ocr.pf_l3_data_rd.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100080 00 ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100080 00 ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100080 00 ocr.pf_l3_data_rd.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100080 00 ocr.pf_l3_data_rd.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100080 00 ocr.pf_l3_data_rd.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100080 00 ocr.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100 00 ocr.pf_l3_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0100 00 ocr.pf_l3_rfo.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0100 00 ocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0100 00 ocr.pf_l3_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0100 00 ocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0100 00 ocr.pf_l3_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0100 00 ocr.pf_l3_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0100 00 ocr.pf_l3_rfo.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080100 00 ocr.pf_l3_rfo.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080100 00 ocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080100 00 ocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080100 00 ocr.pf_l3_rfo.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080100 00 ocr.pf_l3_rfo.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080100 00 ocr.pf_l3_rfo.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080100 00 ocr.pf_l3_rfo.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200100 00 ocr.pf_l3_rfo.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200100 00 ocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200100 00 ocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200100 00 ocr.pf_l3_rfo.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200100 00 ocr.pf_l3_rfo.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200100 00 ocr.pf_l3_rfo.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200100 00 ocr.pf_l3_rfo.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040100 00 ocr.pf_l3_rfo.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040100 00 ocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040100 00 ocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040100 00 ocr.pf_l3_rfo.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040100 00 ocr.pf_l3_rfo.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040100 00 ocr.pf_l3_rfo.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040100 00 ocr.pf_l3_rfo.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100100 00 ocr.pf_l3_rfo.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100100 00 ocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100100 00 ocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100100 00 ocr.pf_l3_rfo.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100100 00 ocr.pf_l3_rfo.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100100 00 ocr.pf_l3_rfo.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100100 00 offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=0x8 00 Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0xb0,period=100003,umask=0x80 00 Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=0x2 00 Counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=0x1 00 Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=0x4 00 Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=0x1 00 Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=0x8 00 Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x8 00 Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x1 00 Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x4 00 Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_code_rd cache Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=0x2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=0x1 00 Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=0x1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=0x4 00 Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_response.all_data_rd.any_response cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10491 10 offcore_response.all_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0491 10 offcore_response.all_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0491 10 offcore_response.all_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0491 10 offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0491 10 offcore_response.all_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0491 10 offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0491 10 offcore_response.all_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0491 10 offcore_response.all_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0491 10 offcore_response.all_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080491 10 offcore_response.all_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080491 10 offcore_response.all_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080491 10 offcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080491 10 offcore_response.all_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080491 10 offcore_response.all_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080491 10 offcore_response.all_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080491 10 offcore_response.all_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200491 10 offcore_response.all_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200491 10 offcore_response.all_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200491 10 offcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200491 10 offcore_response.all_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200491 10 offcore_response.all_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200491 10 offcore_response.all_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200491 10 offcore_response.all_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040491 10 offcore_response.all_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040491 10 offcore_response.all_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040491 10 offcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040491 10 offcore_response.all_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040491 10 offcore_response.all_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040491 10 offcore_response.all_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040491 10 offcore_response.all_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100491 10 offcore_response.all_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100491 10 offcore_response.all_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100491 10 offcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100491 10 offcore_response.all_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100491 10 offcore_response.all_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100491 10 offcore_response.all_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100491 10 offcore_response.all_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400491 10 offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400491 10 offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400491 10 offcore_response.all_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020491 10 offcore_response.all_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020491 10 offcore_response.all_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020491 10 offcore_response.all_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020491 10 offcore_response.all_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020491 10 offcore_response.all_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020491 10 offcore_response.all_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020491 10 offcore_response.all_pf_data_rd.any_response cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10490 10 offcore_response.all_pf_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0490 10 offcore_response.all_pf_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0490 10 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0490 10 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0490 10 offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0490 10 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0490 10 offcore_response.all_pf_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0490 10 offcore_response.all_pf_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0490 10 offcore_response.all_pf_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080490 10 offcore_response.all_pf_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080490 10 offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080490 10 offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080490 10 offcore_response.all_pf_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080490 10 offcore_response.all_pf_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080490 10 offcore_response.all_pf_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080490 10 offcore_response.all_pf_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200490 10 offcore_response.all_pf_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200490 10 offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200490 10 offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200490 10 offcore_response.all_pf_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200490 10 offcore_response.all_pf_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200490 10 offcore_response.all_pf_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200490 10 offcore_response.all_pf_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040490 10 offcore_response.all_pf_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040490 10 offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040490 10 offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040490 10 offcore_response.all_pf_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040490 10 offcore_response.all_pf_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040490 10 offcore_response.all_pf_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040490 10 offcore_response.all_pf_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100490 10 offcore_response.all_pf_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100490 10 offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100490 10 offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100490 10 offcore_response.all_pf_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100490 10 offcore_response.all_pf_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100490 10 offcore_response.all_pf_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100490 10 offcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400490 10 offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400490 10 offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400490 10 offcore_response.all_pf_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020490 10 offcore_response.all_pf_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020490 10 offcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020490 10 offcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020490 10 offcore_response.all_pf_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020490 10 offcore_response.all_pf_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020490 10 offcore_response.all_pf_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020490 10 offcore_response.all_pf_rfo.any_response cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10120 10 offcore_response.all_pf_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0120 10 offcore_response.all_pf_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0120 10 offcore_response.all_pf_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0120 10 offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0120 10 offcore_response.all_pf_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0120 10 offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0120 10 offcore_response.all_pf_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0120 10 offcore_response.all_pf_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0120 10 offcore_response.all_pf_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080120 10 offcore_response.all_pf_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080120 10 offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080120 10 offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080120 10 offcore_response.all_pf_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080120 10 offcore_response.all_pf_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080120 10 offcore_response.all_pf_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080120 10 offcore_response.all_pf_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200120 10 offcore_response.all_pf_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200120 10 offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200120 10 offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200120 10 offcore_response.all_pf_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200120 10 offcore_response.all_pf_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200120 10 offcore_response.all_pf_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200120 10 offcore_response.all_pf_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040120 10 offcore_response.all_pf_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040120 10 offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040120 10 offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040120 10 offcore_response.all_pf_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040120 10 offcore_response.all_pf_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040120 10 offcore_response.all_pf_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040120 10 offcore_response.all_pf_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100120 10 offcore_response.all_pf_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100120 10 offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100120 10 offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100120 10 offcore_response.all_pf_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100120 10 offcore_response.all_pf_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100120 10 offcore_response.all_pf_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100120 10 offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400120 10 offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400120 10 offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400120 10 offcore_response.all_pf_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020120 10 offcore_response.all_pf_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020120 10 offcore_response.all_pf_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020120 10 offcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020120 10 offcore_response.all_pf_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020120 10 offcore_response.all_pf_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020120 10 offcore_response.all_pf_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020120 10 offcore_response.all_reads.any_response cache This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107F7 10 offcore_response.all_reads.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C07F7 10 offcore_response.all_reads.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C07F7 10 offcore_response.all_reads.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C07F7 10 offcore_response.all_reads.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C07F7 10 offcore_response.all_reads.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C07F7 10 offcore_response.all_reads.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C07F7 10 offcore_response.all_reads.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C07F7 10 offcore_response.all_reads.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C07F7 10 offcore_response.all_reads.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800807F7 10 offcore_response.all_reads.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000807F7 10 offcore_response.all_reads.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000807F7 10 offcore_response.all_reads.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000807F7 10 offcore_response.all_reads.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000807F7 10 offcore_response.all_reads.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000807F7 10 offcore_response.all_reads.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800807F7 10 offcore_response.all_reads.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F802007F7 10 offcore_response.all_reads.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002007F7 10 offcore_response.all_reads.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8002007F7 10 offcore_response.all_reads.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4002007F7 10 offcore_response.all_reads.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002007F7 10 offcore_response.all_reads.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002007F7 10 offcore_response.all_reads.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x802007F7 10 offcore_response.all_reads.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800407F7 10 offcore_response.all_reads.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000407F7 10 offcore_response.all_reads.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000407F7 10 offcore_response.all_reads.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000407F7 10 offcore_response.all_reads.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000407F7 10 offcore_response.all_reads.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000407F7 10 offcore_response.all_reads.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800407F7 10 offcore_response.all_reads.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F801007F7 10 offcore_response.all_reads.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001007F7 10 offcore_response.all_reads.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8001007F7 10 offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001007F7 10 offcore_response.all_reads.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001007F7 10 offcore_response.all_reads.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001007F7 10 offcore_response.all_reads.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801007F7 10 offcore_response.all_reads.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F804007F7 10 offcore_response.all_reads.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804007F7 10 offcore_response.all_reads.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004007F7 10 offcore_response.all_reads.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800207F7 10 offcore_response.all_reads.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000207F7 10 offcore_response.all_reads.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000207F7 10 offcore_response.all_reads.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000207F7 10 offcore_response.all_reads.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000207F7 10 offcore_response.all_reads.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000207F7 10 offcore_response.all_reads.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800207F7 10 offcore_response.all_rfo.any_response cache This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10122 10 offcore_response.all_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0122 10 offcore_response.all_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122 10 offcore_response.all_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0122 10 offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122 10 offcore_response.all_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0122 10 offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0122 10 offcore_response.all_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0122 10 offcore_response.all_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0122 10 offcore_response.all_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080122 10 offcore_response.all_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080122 10 offcore_response.all_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080122 10 offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080122 10 offcore_response.all_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080122 10 offcore_response.all_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080122 10 offcore_response.all_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080122 10 offcore_response.all_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200122 10 offcore_response.all_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200122 10 offcore_response.all_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200122 10 offcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200122 10 offcore_response.all_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200122 10 offcore_response.all_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200122 10 offcore_response.all_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200122 10 offcore_response.all_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040122 10 offcore_response.all_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040122 10 offcore_response.all_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040122 10 offcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040122 10 offcore_response.all_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040122 10 offcore_response.all_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040122 10 offcore_response.all_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040122 10 offcore_response.all_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100122 10 offcore_response.all_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100122 10 offcore_response.all_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100122 10 offcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100122 10 offcore_response.all_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100122 10 offcore_response.all_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100122 10 offcore_response.all_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100122 10 offcore_response.all_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400122 10 offcore_response.all_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400122 10 offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400122 10 offcore_response.all_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020122 10 offcore_response.all_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020122 10 offcore_response.all_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020122 10 offcore_response.all_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020122 10 offcore_response.all_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020122 10 offcore_response.all_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020122 10 offcore_response.all_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020122 10 offcore_response.demand_code_rd.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10004 10 offcore_response.demand_code_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 10 offcore_response.demand_code_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 10 offcore_response.demand_code_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0004 10 offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 10 offcore_response.demand_code_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004 10 offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0004 10 offcore_response.demand_code_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0004 10 offcore_response.demand_code_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0004 10 offcore_response.demand_code_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080004 10 offcore_response.demand_code_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080004 10 offcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080004 10 offcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080004 10 offcore_response.demand_code_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080004 10 offcore_response.demand_code_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080004 10 offcore_response.demand_code_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080004 10 offcore_response.demand_code_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200004 10 offcore_response.demand_code_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200004 10 offcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200004 10 offcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200004 10 offcore_response.demand_code_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200004 10 offcore_response.demand_code_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200004 10 offcore_response.demand_code_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200004 10 offcore_response.demand_code_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040004 10 offcore_response.demand_code_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040004 10 offcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040004 10 offcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040004 10 offcore_response.demand_code_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040004 10 offcore_response.demand_code_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040004 10 offcore_response.demand_code_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040004 10 offcore_response.demand_code_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100004 10 offcore_response.demand_code_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100004 10 offcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100004 10 offcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100004 10 offcore_response.demand_code_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100004 10 offcore_response.demand_code_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100004 10 offcore_response.demand_code_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100004 10 offcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400004 10 offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400004 10 offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400004 10 offcore_response.demand_code_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020004 10 offcore_response.demand_code_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020004 10 offcore_response.demand_code_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020004 10 offcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020004 10 offcore_response.demand_code_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020004 10 offcore_response.demand_code_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020004 10 offcore_response.demand_code_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020004 10 offcore_response.demand_data_rd.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 10 offcore_response.demand_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 10 offcore_response.demand_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 10 offcore_response.demand_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 10 offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 10 offcore_response.demand_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 10 offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0001 10 offcore_response.demand_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001 10 offcore_response.demand_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0001 10 offcore_response.demand_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080001 10 offcore_response.demand_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080001 10 offcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080001 10 offcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080001 10 offcore_response.demand_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080001 10 offcore_response.demand_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080001 10 offcore_response.demand_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080001 10 offcore_response.demand_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200001 10 offcore_response.demand_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200001 10 offcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200001 10 offcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200001 10 offcore_response.demand_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200001 10 offcore_response.demand_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200001 10 offcore_response.demand_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200001 10 offcore_response.demand_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040001 10 offcore_response.demand_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040001 10 offcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040001 10 offcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040001 10 offcore_response.demand_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040001 10 offcore_response.demand_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040001 10 offcore_response.demand_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040001 10 offcore_response.demand_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100001 10 offcore_response.demand_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100001 10 offcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100001 10 offcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100001 10 offcore_response.demand_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100001 10 offcore_response.demand_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100001 10 offcore_response.demand_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100001 10 offcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400001 10 offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400001 10 offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400001 10 offcore_response.demand_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020001 10 offcore_response.demand_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020001 10 offcore_response.demand_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020001 10 offcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020001 10 offcore_response.demand_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020001 10 offcore_response.demand_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020001 10 offcore_response.demand_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020001 10 offcore_response.demand_rfo.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 10 offcore_response.demand_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 10 offcore_response.demand_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 10 offcore_response.demand_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0002 10 offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 10 offcore_response.demand_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002 10 offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0002 10 offcore_response.demand_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0002 10 offcore_response.demand_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0002 10 offcore_response.demand_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080002 10 offcore_response.demand_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080002 10 offcore_response.demand_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080002 10 offcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080002 10 offcore_response.demand_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080002 10 offcore_response.demand_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080002 10 offcore_response.demand_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080002 10 offcore_response.demand_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200002 10 offcore_response.demand_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200002 10 offcore_response.demand_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200002 10 offcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200002 10 offcore_response.demand_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200002 10 offcore_response.demand_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200002 10 offcore_response.demand_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200002 10 offcore_response.demand_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040002 10 offcore_response.demand_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040002 10 offcore_response.demand_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040002 10 offcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040002 10 offcore_response.demand_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040002 10 offcore_response.demand_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040002 10 offcore_response.demand_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040002 10 offcore_response.demand_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100002 10 offcore_response.demand_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100002 10 offcore_response.demand_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100002 10 offcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100002 10 offcore_response.demand_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100002 10 offcore_response.demand_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100002 10 offcore_response.demand_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100002 10 offcore_response.demand_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400002 10 offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400002 10 offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400002 10 offcore_response.demand_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020002 10 offcore_response.demand_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020002 10 offcore_response.demand_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020002 10 offcore_response.demand_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020002 10 offcore_response.demand_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020002 10 offcore_response.demand_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020002 10 offcore_response.demand_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020002 10 offcore_response.other.any_response cache This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000 10 offcore_response.other.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8000 10 offcore_response.other.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C8000 10 offcore_response.other.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C8000 10 offcore_response.other.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C8000 10 offcore_response.other.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C8000 10 offcore_response.other.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C8000 10 offcore_response.other.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C8000 10 offcore_response.other.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C8000 10 offcore_response.other.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80088000 10 offcore_response.other.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000088000 10 offcore_response.other.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800088000 10 offcore_response.other.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400088000 10 offcore_response.other.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100088000 10 offcore_response.other.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200088000 10 offcore_response.other.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80088000 10 offcore_response.other.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80208000 10 offcore_response.other.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000208000 10 offcore_response.other.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800208000 10 offcore_response.other.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400208000 10 offcore_response.other.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100208000 10 offcore_response.other.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200208000 10 offcore_response.other.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80208000 10 offcore_response.other.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80048000 10 offcore_response.other.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000048000 10 offcore_response.other.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800048000 10 offcore_response.other.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400048000 10 offcore_response.other.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100048000 10 offcore_response.other.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200048000 10 offcore_response.other.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80048000 10 offcore_response.other.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80108000 10 offcore_response.other.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000108000 10 offcore_response.other.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800108000 10 offcore_response.other.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400108000 10 offcore_response.other.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100108000 10 offcore_response.other.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200108000 10 offcore_response.other.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80108000 10 offcore_response.other.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80408000 10 offcore_response.other.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80408000 10 offcore_response.other.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100408000 10 offcore_response.other.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80028000 10 offcore_response.other.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000028000 10 offcore_response.other.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800028000 10 offcore_response.other.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400028000 10 offcore_response.other.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100028000 10 offcore_response.other.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200028000 10 offcore_response.other.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80028000 10 offcore_response.pf_l1d_and_sw.any_response cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400 10 offcore_response.pf_l1d_and_sw.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0400 10 offcore_response.pf_l1d_and_sw.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080400 10 offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200400 10 offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040400 10 offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100400 10 offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100400 10 offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400400 10 offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400400 10 offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400400 10 offcore_response.pf_l1d_and_sw.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020400 10 offcore_response.pf_l1d_and_sw.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020400 10 offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020400 10 offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020400 10 offcore_response.pf_l1d_and_sw.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020400 10 offcore_response.pf_l1d_and_sw.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020400 10 offcore_response.pf_l1d_and_sw.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020400 10 offcore_response.pf_l2_data_rd.any_response cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010 10 offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010 10 offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0010 10 offcore_response.pf_l2_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0010 10 offcore_response.pf_l2_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0010 10 offcore_response.pf_l2_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080010 10 offcore_response.pf_l2_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080010 10 offcore_response.pf_l2_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200010 10 offcore_response.pf_l2_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200010 10 offcore_response.pf_l2_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040010 10 offcore_response.pf_l2_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040010 10 offcore_response.pf_l2_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100010 10 offcore_response.pf_l2_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100010 10 offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400010 10 offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400010 10 offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400010 10 offcore_response.pf_l2_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020010 10 offcore_response.pf_l2_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020010 10 offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020010 10 offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020010 10 offcore_response.pf_l2_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020010 10 offcore_response.pf_l2_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020010 10 offcore_response.pf_l2_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020010 10 offcore_response.pf_l2_rfo.any_response cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020 10 offcore_response.pf_l2_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020 10 offcore_response.pf_l2_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020 10 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0020 10 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020 10 offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020 10 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0020 10 offcore_response.pf_l2_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0020 10 offcore_response.pf_l2_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0020 10 offcore_response.pf_l2_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080020 10 offcore_response.pf_l2_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080020 10 offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080020 10 offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080020 10 offcore_response.pf_l2_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080020 10 offcore_response.pf_l2_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080020 10 offcore_response.pf_l2_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080020 10 offcore_response.pf_l2_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200020 10 offcore_response.pf_l2_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200020 10 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200020 10 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200020 10 offcore_response.pf_l2_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200020 10 offcore_response.pf_l2_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200020 10 offcore_response.pf_l2_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200020 10 offcore_response.pf_l2_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040020 10 offcore_response.pf_l2_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040020 10 offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040020 10 offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040020 10 offcore_response.pf_l2_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040020 10 offcore_response.pf_l2_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040020 10 offcore_response.pf_l2_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040020 10 offcore_response.pf_l2_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100020 10 offcore_response.pf_l2_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100020 10 offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100020 10 offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100020 10 offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100020 10 offcore_response.pf_l2_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100020 10 offcore_response.pf_l2_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100020 10 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400020 10 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400020 10 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400020 10 offcore_response.pf_l2_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020020 10 offcore_response.pf_l2_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020020 10 offcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020020 10 offcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020020 10 offcore_response.pf_l2_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020020 10 offcore_response.pf_l2_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020020 10 offcore_response.pf_l2_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020020 10 offcore_response.pf_l3_data_rd.any_response cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10080 10 offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080 10 offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0080 10 offcore_response.pf_l3_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0080 10 offcore_response.pf_l3_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0080 10 offcore_response.pf_l3_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080080 10 offcore_response.pf_l3_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080080 10 offcore_response.pf_l3_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200080 10 offcore_response.pf_l3_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200080 10 offcore_response.pf_l3_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040080 10 offcore_response.pf_l3_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040080 10 offcore_response.pf_l3_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100080 10 offcore_response.pf_l3_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100080 10 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400080 10 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400080 10 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400080 10 offcore_response.pf_l3_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020080 10 offcore_response.pf_l3_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020080 10 offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020080 10 offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020080 10 offcore_response.pf_l3_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020080 10 offcore_response.pf_l3_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020080 10 offcore_response.pf_l3_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020080 10 offcore_response.pf_l3_rfo.any_response cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100 10 offcore_response.pf_l3_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100 10 offcore_response.pf_l3_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0100 10 offcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0100 10 offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0100 10 offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0100 10 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0100 10 offcore_response.pf_l3_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0100 10 offcore_response.pf_l3_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0100 10 offcore_response.pf_l3_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080100 10 offcore_response.pf_l3_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080100 10 offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080100 10 offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080100 10 offcore_response.pf_l3_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080100 10 offcore_response.pf_l3_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080100 10 offcore_response.pf_l3_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080100 10 offcore_response.pf_l3_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200100 10 offcore_response.pf_l3_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200100 10 offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200100 10 offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200100 10 offcore_response.pf_l3_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200100 10 offcore_response.pf_l3_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200100 10 offcore_response.pf_l3_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200100 10 offcore_response.pf_l3_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040100 10 offcore_response.pf_l3_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040100 10 offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040100 10 offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040100 10 offcore_response.pf_l3_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040100 10 offcore_response.pf_l3_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040100 10 offcore_response.pf_l3_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040100 10 offcore_response.pf_l3_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100100 10 offcore_response.pf_l3_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100100 10 offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100100 10 offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100100 10 offcore_response.pf_l3_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100100 10 offcore_response.pf_l3_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100100 10 offcore_response.pf_l3_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100100 10 offcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400100 10 offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400100 10 offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400100 10 offcore_response.pf_l3_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020100 10 offcore_response.pf_l3_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020100 10 offcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020100 10 offcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020100 10 offcore_response.pf_l3_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020100 10 offcore_response.pf_l3_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020100 10 offcore_response.pf_l3_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020100 10 sq_misc.split_lock cache Number of cache line split locks sent to uncore event=0xf4,period=100003,umask=0x10 00 Counts the number of cache line split locks sent to the uncore sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x32,period=2000003,umask=0x1 00 sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x32,period=2000003,umask=0x8 00 sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x32,period=2000003,umask=0x2 00 sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=2000003,umask=0x4 00 fp_arith_inst_retired.128b_packed_double floating point Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x4 00 Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x8 00 Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x10 00 Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x20 00 Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=1000003,umask=0x18 00 Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_double floating point Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x40 00 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x80 00 Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.8_flops floating point Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=1000003,umask=0x18 00 Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar floating point Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x3 00 Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x1 00 Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x2 00 Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired2.128bit_packed_bf16 floating point Intel AVX-512 computational 512-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x20 00 Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction. Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_arith_inst_retired2.256bit_packed_bf16 floating point Intel AVX-512 computational 128-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x40 00 Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_arith_inst_retired2.512bit_packed_bf16 floating point Intel AVX-512 computational 256-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x80 00 Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction. Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=0x1 00 Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore decode.lcp frontend Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP] event=0x87,period=2000003,umask=0x1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP] dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=0x1 00 This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=0x2 00 Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x12 00 frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x13 00 frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Must be precise) event=0xc6,period=100007,umask=0x1,frontend=0x400106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Must be precise) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x408006 00 frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x401006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x400206 00 frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x410006 00 frontend_retired.latency_ge_2_bubbles_ge_2 frontend Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x200206 00 frontend_retired.latency_ge_2_bubbles_ge_3 frontend Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x300206 00 frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x402006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x400406 00 frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x420006 00 frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x404006 00 frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x400806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) icache_16b.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache miss event=0x80,period=2000003,umask=0x4 00 Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity icache_64b.iftag_hit frontend Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=0x1 00 icache_64b.iftag_miss frontend Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=0x2 00 icache_64b.iftag_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] event=0x83,period=200003,umask=0x4 00 icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] event=0x83,period=200003,umask=0x4 00 idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK] event=0x79,cmask=4,period=2000003,umask=0x18 00 Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK] idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY] event=0x79,cmask=1,period=2000003,umask=0x18 00 Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_ANY] idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=0x8 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ idq.dsb_cycles_any frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS] event=0x79,cmask=1,period=2000003,umask=0x18 00 Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS] idq.dsb_cycles_ok frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS] event=0x79,cmask=4,period=2000003,umask=0x18 00 Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS] idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=0x8 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=0x4 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x4 00 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq.ms_switches frontend Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer event=0x79,cmask=1,edge=1,period=2000003,umask=0x30 00 Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=0x1 00 Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=0x1 00 Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=0x1 00 Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end event=0x9c,cmask=2,period=2000003,umask=0x1 00 Cycles with less than 2 uops delivered by the front-end idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end event=0x9c,cmask=1,period=2000003,umask=0x1 00 Cycles with less than 3 uops delivered by the front-end cycle_activity.cycles_l3_miss memory Cycles while L3 cache miss demand load is outstanding event=0xa3,cmask=2,period=2000003,umask=0x2 00 cycle_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand load is outstanding event=0xa3,cmask=6,period=2000003,umask=0x6 00 hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc8,period=2000003,umask=0x4 00 Number of times HLE abort was triggered (Precise event) hle_retired.aborted_events memory Number of times an HLE execution aborted due to unfriendly events (such as interrupts) event=0xc8,period=2000003,umask=0x80 00 hle_retired.aborted_mem memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=0x8 00 hle_retired.aborted_memtype memory Number of times an HLE execution aborted due to incompatible memory type event=0xc8,period=2000003,umask=0x40 00 Number of times an HLE execution aborted due to incompatible memory type hle_retired.aborted_timer memory Number of times an HLE execution aborted due to hardware timer expiration event=0xc8,period=2000003,umask=0x10 00 hle_retired.aborted_unfriendly memory Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) event=0xc8,period=2000003,umask=0x20 00 hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=2000003,umask=0x2 00 Number of times HLE commit succeeded hle_retired.start memory Number of times an HLE execution started event=0xc8,period=2000003,umask=0x1 00 Number of times we entered an HLE region. Does not count nested transactions machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts Spec update: SKL089 event=0xc3,period=100003,umask=0x2 00 Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer Spec update: SKL089 ocr.all_data_rd.l3_miss.any_snoop memory OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000491 00 ocr.all_data_rd.l3_miss.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000491 00 ocr.all_data_rd.l3_miss.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000491 00 ocr.all_data_rd.l3_miss.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000491 00 ocr.all_data_rd.l3_miss.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000491 00 ocr.all_data_rd.l3_miss.remote_hitm memory OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00491 00 ocr.all_data_rd.l3_miss.remote_hit_forward memory OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00491 00 ocr.all_data_rd.l3_miss.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000491 00 ocr.all_data_rd.l3_miss.snoop_none memory OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000491 00 ocr.all_data_rd.l3_miss_local_dram.any_snoop memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000491 00 ocr.all_data_rd.l3_miss_local_dram.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000491 00 ocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000491 00 ocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000491 00 ocr.all_data_rd.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000491 00 ocr.all_data_rd.l3_miss_local_dram.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000491 00 ocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000491 00 ocr.all_data_rd.l3_miss_local_dram.snoop_none memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000491 00 ocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000491 00 ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000491 00 ocr.all_pf_data_rd.l3_miss.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000490 00 ocr.all_pf_data_rd.l3_miss.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000490 00 ocr.all_pf_data_rd.l3_miss.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000490 00 ocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000490 00 ocr.all_pf_data_rd.l3_miss.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000490 00 ocr.all_pf_data_rd.l3_miss.remote_hitm memory OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00490 00 ocr.all_pf_data_rd.l3_miss.remote_hit_forward memory OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00490 00 ocr.all_pf_data_rd.l3_miss.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000490 00 ocr.all_pf_data_rd.l3_miss.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000490 00 ocr.all_pf_data_rd.l3_miss_local_dram.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000490 00 ocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000490 00 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000490 00 ocr.all_pf_rfo.l3_miss.any_snoop memory OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000120 00 ocr.all_pf_rfo.l3_miss.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000120 00 ocr.all_pf_rfo.l3_miss.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000120 00 ocr.all_pf_rfo.l3_miss.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000120 00 ocr.all_pf_rfo.l3_miss.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000120 00 ocr.all_pf_rfo.l3_miss.remote_hitm memory OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00120 00 ocr.all_pf_rfo.l3_miss.remote_hit_forward memory OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00120 00 ocr.all_pf_rfo.l3_miss.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000120 00 ocr.all_pf_rfo.l3_miss.snoop_none memory OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000120 00 ocr.all_pf_rfo.l3_miss_local_dram.any_snoop memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000120 00 ocr.all_pf_rfo.l3_miss_local_dram.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000120 00 ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000120 00 ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000120 00 ocr.all_pf_rfo.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000120 00 ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000120 00 ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000120 00 ocr.all_pf_rfo.l3_miss_local_dram.snoop_none memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000120 00 ocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000120 00 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000120 00 ocr.all_reads.l3_miss.any_snoop memory OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC0007F7 00 ocr.all_reads.l3_miss.hitm_other_core memory OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C0007F7 00 ocr.all_reads.l3_miss.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C0007F7 00 ocr.all_reads.l3_miss.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C0007F7 00 ocr.all_reads.l3_miss.no_snoop_needed memory OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C0007F7 00 ocr.all_reads.l3_miss.remote_hitm memory OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC007F7 00 ocr.all_reads.l3_miss.remote_hit_forward memory OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC007F7 00 ocr.all_reads.l3_miss.snoop_miss memory OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C0007F7 00 ocr.all_reads.l3_miss.snoop_none memory OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC0007F7 00 ocr.all_reads.l3_miss_local_dram.any_snoop memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F840007F7 00 ocr.all_reads.l3_miss_local_dram.hitm_other_core memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040007F7 00 ocr.all_reads.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8040007F7 00 ocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4040007F7 00 ocr.all_reads.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1040007F7 00 ocr.all_reads.l3_miss_local_dram.snoop_miss memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2040007F7 00 ocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6040007F7 00 ocr.all_reads.l3_miss_local_dram.snoop_none memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x840007F7 00 ocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B8007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F900007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2100007F7 00 ocr.all_reads.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x900007F7 00 ocr.all_rfo.l3_miss.any_snoop memory OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000122 00 ocr.all_rfo.l3_miss.hitm_other_core memory OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000122 00 ocr.all_rfo.l3_miss.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000122 00 ocr.all_rfo.l3_miss.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000122 00 ocr.all_rfo.l3_miss.no_snoop_needed memory OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000122 00 ocr.all_rfo.l3_miss.remote_hitm memory OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00122 00 ocr.all_rfo.l3_miss.remote_hit_forward memory OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00122 00 ocr.all_rfo.l3_miss.snoop_miss memory OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000122 00 ocr.all_rfo.l3_miss.snoop_none memory OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000122 00 ocr.all_rfo.l3_miss_local_dram.any_snoop memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000122 00 ocr.all_rfo.l3_miss_local_dram.hitm_other_core memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000122 00 ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000122 00 ocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000122 00 ocr.all_rfo.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000122 00 ocr.all_rfo.l3_miss_local_dram.snoop_miss memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000122 00 ocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000122 00 ocr.all_rfo.l3_miss_local_dram.snoop_none memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000122 00 ocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000122 00 ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000122 00 ocr.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000004 00 ocr.demand_code_rd.l3_miss.hitm_other_core memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000004 00 ocr.demand_code_rd.l3_miss.hit_other_core_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000004 00 ocr.demand_code_rd.l3_miss.hit_other_core_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000004 00 ocr.demand_code_rd.l3_miss.no_snoop_needed memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000004 00 ocr.demand_code_rd.l3_miss.remote_hitm memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00004 00 ocr.demand_code_rd.l3_miss.remote_hit_forward memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00004 00 ocr.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000004 00 ocr.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000004 00 ocr.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000004 00 ocr.demand_code_rd.l3_miss_local_dram.hitm_other_core memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000004 00 ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000004 00 ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000004 00 ocr.demand_code_rd.l3_miss_local_dram.no_snoop_needed memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000004 00 ocr.demand_code_rd.l3_miss_local_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000004 00 ocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000004 00 ocr.demand_code_rd.l3_miss_local_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000004 00 ocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000004 00 ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000004 00 ocr.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000001 00 ocr.demand_data_rd.l3_miss.hitm_other_core memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000001 00 ocr.demand_data_rd.l3_miss.hit_other_core_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000001 00 ocr.demand_data_rd.l3_miss.hit_other_core_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000001 00 ocr.demand_data_rd.l3_miss.no_snoop_needed memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000001 00 ocr.demand_data_rd.l3_miss.remote_hitm memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00001 00 ocr.demand_data_rd.l3_miss.remote_hit_forward memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00001 00 ocr.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000001 00 ocr.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000001 00 ocr.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000001 00 ocr.demand_data_rd.l3_miss_local_dram.hitm_other_core memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000001 00 ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000001 00 ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000001 00 ocr.demand_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000001 00 ocr.demand_data_rd.l3_miss_local_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000001 00 ocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000001 00 ocr.demand_data_rd.l3_miss_local_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000001 00 ocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000001 00 ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000001 00 ocr.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000002 00 ocr.demand_rfo.l3_miss.hitm_other_core memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000002 00 ocr.demand_rfo.l3_miss.hit_other_core_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000002 00 ocr.demand_rfo.l3_miss.hit_other_core_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000002 00 ocr.demand_rfo.l3_miss.no_snoop_needed memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000002 00 ocr.demand_rfo.l3_miss.remote_hitm memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00002 00 ocr.demand_rfo.l3_miss.remote_hit_forward memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00002 00 ocr.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000002 00 ocr.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000002 00 ocr.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000002 00 ocr.demand_rfo.l3_miss_local_dram.hitm_other_core memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000002 00 ocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000002 00 ocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000002 00 ocr.demand_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000002 00 ocr.demand_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000002 00 ocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000002 00 ocr.demand_rfo.l3_miss_local_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000002 00 ocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000002 00 ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000002 00 ocr.other.l3_miss.any_snoop memory Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC008000 00 ocr.other.l3_miss.hitm_other_core memory Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C008000 00 ocr.other.l3_miss.hit_other_core_fwd memory Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C008000 00 ocr.other.l3_miss.hit_other_core_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C008000 00 ocr.other.l3_miss.no_snoop_needed memory Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C008000 00 ocr.other.l3_miss.remote_hitm memory Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC08000 00 ocr.other.l3_miss.remote_hit_forward memory Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC08000 00 ocr.other.l3_miss.snoop_miss memory Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C008000 00 ocr.other.l3_miss.snoop_none memory Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC008000 00 ocr.other.l3_miss_local_dram.any_snoop memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84008000 00 ocr.other.l3_miss_local_dram.hitm_other_core memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004008000 00 ocr.other.l3_miss_local_dram.hit_other_core_fwd memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804008000 00 ocr.other.l3_miss_local_dram.hit_other_core_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404008000 00 ocr.other.l3_miss_local_dram.no_snoop_needed memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104008000 00 ocr.other.l3_miss_local_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204008000 00 ocr.other.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604008000 00 ocr.other.l3_miss_local_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84008000 00 ocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B808000 00 ocr.other.l3_miss_remote_hop1_dram.any_snoop memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90008000 00 ocr.other.l3_miss_remote_hop1_dram.hitm_other_core memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010008000 00 ocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810008000 00 ocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410008000 00 ocr.other.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110008000 00 ocr.other.l3_miss_remote_hop1_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210008000 00 ocr.other.l3_miss_remote_hop1_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90008000 00 ocr.pf_l1d_and_sw.l3_miss.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000400 00 ocr.pf_l1d_and_sw.l3_miss.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000400 00 ocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000400 00 ocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000400 00 ocr.pf_l1d_and_sw.l3_miss.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000400 00 ocr.pf_l1d_and_sw.l3_miss.remote_hitm memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00400 00 ocr.pf_l1d_and_sw.l3_miss.remote_hit_forward memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00400 00 ocr.pf_l1d_and_sw.l3_miss.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000400 00 ocr.pf_l1d_and_sw.l3_miss.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000400 00 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000400 00 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000400 00 ocr.pf_l2_data_rd.l3_miss.any_snoop memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000010 00 ocr.pf_l2_data_rd.l3_miss.hitm_other_core memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000010 00 ocr.pf_l2_data_rd.l3_miss.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000010 00 ocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000010 00 ocr.pf_l2_data_rd.l3_miss.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000010 00 ocr.pf_l2_data_rd.l3_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00010 00 ocr.pf_l2_data_rd.l3_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00010 00 ocr.pf_l2_data_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000010 00 ocr.pf_l2_data_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000010 00 ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000010 00 ocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000010 00 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000010 00 ocr.pf_l2_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000020 00 ocr.pf_l2_rfo.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000020 00 ocr.pf_l2_rfo.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000020 00 ocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000020 00 ocr.pf_l2_rfo.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000020 00 ocr.pf_l2_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00020 00 ocr.pf_l2_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00020 00 ocr.pf_l2_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000020 00 ocr.pf_l2_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000020 00 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000020 00 ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000020 00 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000020 00 ocr.pf_l3_data_rd.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000080 00 ocr.pf_l3_data_rd.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000080 00 ocr.pf_l3_data_rd.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000080 00 ocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000080 00 ocr.pf_l3_data_rd.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000080 00 ocr.pf_l3_data_rd.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00080 00 ocr.pf_l3_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00080 00 ocr.pf_l3_data_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000080 00 ocr.pf_l3_data_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000080 00 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000080 00 ocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000080 00 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000080 00 ocr.pf_l3_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000100 00 ocr.pf_l3_rfo.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000100 00 ocr.pf_l3_rfo.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000100 00 ocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000100 00 ocr.pf_l3_rfo.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000100 00 ocr.pf_l3_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00100 00 ocr.pf_l3_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00100 00 ocr.pf_l3_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000100 00 ocr.pf_l3_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000100 00 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000100 00 ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000100 00 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000100 00 offcore_requests.l3_miss_demand_data_rd memory Demand Data Read requests who miss L3 cache event=0xb0,period=100003,umask=0x10 00 Demand Data Read requests who miss L3 cache offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ event=0x60,cmask=1,period=2000003,umask=0x10 00 offcore_requests_outstanding.l3_miss_demand_data_rd memory Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle event=0x60,period=2000003,umask=0x10 00 offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 memory Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ event=0x60,cmask=6,period=2000003,umask=0x10 00 offcore_response.all_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000491 10 offcore_response.all_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000491 10 offcore_response.all_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000491 10 offcore_response.all_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000491 10 offcore_response.all_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000491 10 offcore_response.all_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00491 10 offcore_response.all_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00491 10 offcore_response.all_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000491 10 offcore_response.all_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000491 10 offcore_response.all_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000491 10 offcore_response.all_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000491 10 offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000491 10 offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000491 10 offcore_response.all_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000491 10 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000491 10 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000491 10 offcore_response.all_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000491 10 offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000491 10 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000491 10 offcore_response.all_pf_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000490 10 offcore_response.all_pf_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000490 10 offcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000490 10 offcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000490 10 offcore_response.all_pf_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000490 10 offcore_response.all_pf_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00490 10 offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00490 10 offcore_response.all_pf_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000490 10 offcore_response.all_pf_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000490 10 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000490 10 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000490 10 offcore_response.all_pf_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000120 10 offcore_response.all_pf_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000120 10 offcore_response.all_pf_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000120 10 offcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000120 10 offcore_response.all_pf_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000120 10 offcore_response.all_pf_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00120 10 offcore_response.all_pf_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00120 10 offcore_response.all_pf_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000120 10 offcore_response.all_pf_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000120 10 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000120 10 offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000120 10 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000120 10 offcore_response.all_reads.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC0007F7 10 offcore_response.all_reads.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C0007F7 10 offcore_response.all_reads.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C0007F7 10 offcore_response.all_reads.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C0007F7 10 offcore_response.all_reads.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C0007F7 10 offcore_response.all_reads.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC007F7 10 offcore_response.all_reads.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC007F7 10 offcore_response.all_reads.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C0007F7 10 offcore_response.all_reads.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC0007F7 10 offcore_response.all_reads.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F840007F7 10 offcore_response.all_reads.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040007F7 10 offcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8040007F7 10 offcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4040007F7 10 offcore_response.all_reads.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1040007F7 10 offcore_response.all_reads.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2040007F7 10 offcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6040007F7 10 offcore_response.all_reads.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x840007F7 10 offcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B8007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F900007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2100007F7 10 offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x900007F7 10 offcore_response.all_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000122 10 offcore_response.all_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000122 10 offcore_response.all_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000122 10 offcore_response.all_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000122 10 offcore_response.all_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000122 10 offcore_response.all_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00122 10 offcore_response.all_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00122 10 offcore_response.all_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000122 10 offcore_response.all_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000122 10 offcore_response.all_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000122 10 offcore_response.all_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000122 10 offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000122 10 offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000122 10 offcore_response.all_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000122 10 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000122 10 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000122 10 offcore_response.all_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000122 10 offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000122 10 offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000122 10 offcore_response.demand_code_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000004 10 offcore_response.demand_code_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000004 10 offcore_response.demand_code_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000004 10 offcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000004 10 offcore_response.demand_code_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000004 10 offcore_response.demand_code_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00004 10 offcore_response.demand_code_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00004 10 offcore_response.demand_code_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000004 10 offcore_response.demand_code_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000004 10 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000004 10 offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000004 10 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000004 10 offcore_response.demand_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000001 10 offcore_response.demand_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000001 10 offcore_response.demand_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000001 10 offcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000001 10 offcore_response.demand_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000001 10 offcore_response.demand_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00001 10 offcore_response.demand_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00001 10 offcore_response.demand_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000001 10 offcore_response.demand_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000001 10 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000001 10 offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000001 10 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000001 10 offcore_response.demand_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000002 10 offcore_response.demand_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000002 10 offcore_response.demand_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000002 10 offcore_response.demand_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000002 10 offcore_response.demand_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000002 10 offcore_response.demand_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00002 10 offcore_response.demand_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00002 10 offcore_response.demand_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000002 10 offcore_response.demand_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000002 10 offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000002 10 offcore_response.demand_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000002 10 offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000002 10 offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000002 10 offcore_response.demand_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000002 10 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000002 10 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000002 10 offcore_response.demand_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000002 10 offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000002 10 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000002 10 offcore_response.other.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC008000 10 offcore_response.other.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C008000 10 offcore_response.other.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C008000 10 offcore_response.other.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C008000 10 offcore_response.other.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C008000 10 offcore_response.other.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC08000 10 offcore_response.other.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC08000 10 offcore_response.other.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C008000 10 offcore_response.other.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC008000 10 offcore_response.other.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84008000 10 offcore_response.other.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004008000 10 offcore_response.other.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804008000 10 offcore_response.other.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404008000 10 offcore_response.other.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104008000 10 offcore_response.other.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204008000 10 offcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604008000 10 offcore_response.other.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84008000 10 offcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B808000 10 offcore_response.other.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90008000 10 offcore_response.other.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010008000 10 offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810008000 10 offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410008000 10 offcore_response.other.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110008000 10 offcore_response.other.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210008000 10 offcore_response.other.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90008000 10 offcore_response.pf_l1d_and_sw.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000400 10 offcore_response.pf_l1d_and_sw.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00400 10 offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00400 10 offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000400 10 offcore_response.pf_l1d_and_sw.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000400 10 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000400 10 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000400 10 offcore_response.pf_l2_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000010 10 offcore_response.pf_l2_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000010 10 offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000010 10 offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000010 10 offcore_response.pf_l2_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000010 10 offcore_response.pf_l2_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00010 10 offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00010 10 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000010 10 offcore_response.pf_l2_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000010 10 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000010 10 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000010 10 offcore_response.pf_l2_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000020 10 offcore_response.pf_l2_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000020 10 offcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000020 10 offcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000020 10 offcore_response.pf_l2_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000020 10 offcore_response.pf_l2_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00020 10 offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00020 10 offcore_response.pf_l2_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000020 10 offcore_response.pf_l2_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000020 10 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000020 10 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000020 10 offcore_response.pf_l3_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000080 10 offcore_response.pf_l3_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000080 10 offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000080 10 offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000080 10 offcore_response.pf_l3_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000080 10 offcore_response.pf_l3_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00080 10 offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00080 10 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000080 10 offcore_response.pf_l3_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000080 10 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000080 10 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000080 10 offcore_response.pf_l3_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000100 10 offcore_response.pf_l3_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000100 10 offcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000100 10 offcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000100 10 offcore_response.pf_l3_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000100 10 offcore_response.pf_l3_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00100 10 offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00100 10 offcore_response.pf_l3_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000100 10 offcore_response.pf_l3_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000100 10 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000100 10 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000100 10 rtm_retired.aborted memory Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc9,period=2000003,umask=0x4 00 Number of times RTM abort was triggered (Precise event) rtm_retired.aborted_events memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80 00 Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) rtm_retired.aborted_mem memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x8 00 Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) rtm_retired.aborted_memtype memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=2000003,umask=0x40 00 Number of times an RTM execution aborted due to incompatible memory type rtm_retired.aborted_timer memory Number of times an RTM execution aborted due to uncommon conditions event=0xc9,period=2000003,umask=0x10 00 rtm_retired.aborted_unfriendly memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20 00 Number of times an RTM execution aborted due to HLE-unfriendly instructions rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=2000003,umask=0x2 00 Number of times RTM commit succeeded rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=2000003,umask=0x1 00 Number of times we entered an RTM region. Does not count nested transactions tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=0x2 00 Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc5 memory Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region event=0x5d,period=2000003,umask=0x10 00 Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region tx_mem.abort_capacity memory Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes event=0x54,period=2000003,umask=0x2 00 tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=2000003,umask=0x1 00 Number of times a TSX line had a cache conflict tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=2000003,umask=0x10 00 Number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=2000003,umask=0x8 00 Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=2000003,umask=0x20 00 Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=2000003,umask=0x4 00 Number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=2000003,umask=0x40 00 Number of times we could not allocate Lock Buffer core_power.lvl0_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule event=0x28,period=200003,umask=0x7 00 Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes core_power.lvl1_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule event=0x28,period=200003,umask=0x18 00 Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions core_power.lvl2_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule event=0x28,period=200003,umask=0x20 00 Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions core_power.throttle other Core cycles the core was throttled due to a pending power level request event=0x28,period=200003,umask=0x40 00 Core cycles the out-of-order engine was throttled due to a pending power level request core_snoop_response.rsp_ifwdfe other CORE_SNOOP_RESPONSE.RSP_IFWDFE event=0xef,period=2000003,umask=0x20 00 core_snoop_response.rsp_ifwdm other CORE_SNOOP_RESPONSE.RSP_IFWDM event=0xef,period=2000003,umask=0x10 00 core_snoop_response.rsp_ihitfse other CORE_SNOOP_RESPONSE.RSP_IHITFSE event=0xef,period=2000003,umask=0x2 00 core_snoop_response.rsp_ihiti other CORE_SNOOP_RESPONSE.RSP_IHITI event=0xef,period=2000003,umask=0x1 00 core_snoop_response.rsp_sfwdfe other CORE_SNOOP_RESPONSE.RSP_SFWDFE event=0xef,period=2000003,umask=0x40 00 core_snoop_response.rsp_sfwdm other CORE_SNOOP_RESPONSE.RSP_SFWDM event=0xef,period=2000003,umask=0x8 00 core_snoop_response.rsp_shitfse other CORE_SNOOP_RESPONSE.RSP_SHITFSE event=0xef,period=2000003,umask=0x4 00 hw_interrupts.received other Number of hardware interrupts received by the processor event=0xcb,period=203,umask=0x1 00 Counts the number of hardware interruptions received by the processor idi_misc.wb_downgrade other Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly event=0xfe,period=100003,umask=0x4 00 Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly idi_misc.wb_upgrade other Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly event=0xfe,period=100003,umask=0x2 00 Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly ocr.all_data_rd.any_response other OCR.ALL_DATA_RD.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10491 00 ocr.all_data_rd.pmm_hit_local_pmm.any_snoop other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400491 00 ocr.all_data_rd.pmm_hit_local_pmm.snoop_none other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400491 00 ocr.all_data_rd.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400491 00 ocr.all_data_rd.supplier_none.any_snoop other OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020491 00 ocr.all_data_rd.supplier_none.hitm_other_core other OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020491 00 ocr.all_data_rd.supplier_none.hit_other_core_fwd other OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020491 00 ocr.all_data_rd.supplier_none.hit_other_core_no_fwd other OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020491 00 ocr.all_data_rd.supplier_none.no_snoop_needed other OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020491 00 ocr.all_data_rd.supplier_none.snoop_miss other OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020491 00 ocr.all_data_rd.supplier_none.snoop_none other OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020491 00 ocr.all_pf_data_rd.any_response other OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10490 00 ocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoop other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400490 00 ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_none other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400490 00 ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400490 00 ocr.all_pf_data_rd.supplier_none.any_snoop other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020490 00 ocr.all_pf_data_rd.supplier_none.hitm_other_core other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020490 00 ocr.all_pf_data_rd.supplier_none.hit_other_core_fwd other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020490 00 ocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwd other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020490 00 ocr.all_pf_data_rd.supplier_none.no_snoop_needed other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020490 00 ocr.all_pf_data_rd.supplier_none.snoop_miss other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020490 00 ocr.all_pf_data_rd.supplier_none.snoop_none other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020490 00 ocr.all_pf_rfo.any_response other OCR.ALL_PF_RFO.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10120 00 ocr.all_pf_rfo.pmm_hit_local_pmm.any_snoop other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400120 00 ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_none other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400120 00 ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400120 00 ocr.all_pf_rfo.supplier_none.any_snoop other OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020120 00 ocr.all_pf_rfo.supplier_none.hitm_other_core other OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020120 00 ocr.all_pf_rfo.supplier_none.hit_other_core_fwd other OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020120 00 ocr.all_pf_rfo.supplier_none.hit_other_core_no_fwd other OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020120 00 ocr.all_pf_rfo.supplier_none.no_snoop_needed other OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020120 00 ocr.all_pf_rfo.supplier_none.snoop_miss other OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020120 00 ocr.all_pf_rfo.supplier_none.snoop_none other OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020120 00 ocr.all_reads.any_response other OCR.ALL_READS.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107F7 00 ocr.all_reads.pmm_hit_local_pmm.any_snoop other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F804007F7 00 ocr.all_reads.pmm_hit_local_pmm.snoop_none other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804007F7 00 ocr.all_reads.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004007F7 00 ocr.all_reads.supplier_none.any_snoop other OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800207F7 00 ocr.all_reads.supplier_none.hitm_other_core other OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000207F7 00 ocr.all_reads.supplier_none.hit_other_core_fwd other OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000207F7 00 ocr.all_reads.supplier_none.hit_other_core_no_fwd other OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000207F7 00 ocr.all_reads.supplier_none.no_snoop_needed other OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000207F7 00 ocr.all_reads.supplier_none.snoop_miss other OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000207F7 00 ocr.all_reads.supplier_none.snoop_none other OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800207F7 00 ocr.all_rfo.any_response other OCR.ALL_RFO.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10122 00 ocr.all_rfo.pmm_hit_local_pmm.any_snoop other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400122 00 ocr.all_rfo.pmm_hit_local_pmm.snoop_none other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400122 00 ocr.all_rfo.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400122 00 ocr.all_rfo.supplier_none.any_snoop other OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020122 00 ocr.all_rfo.supplier_none.hitm_other_core other OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020122 00 ocr.all_rfo.supplier_none.hit_other_core_fwd other OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020122 00 ocr.all_rfo.supplier_none.hit_other_core_no_fwd other OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020122 00 ocr.all_rfo.supplier_none.no_snoop_needed other OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020122 00 ocr.all_rfo.supplier_none.snoop_miss other OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020122 00 ocr.all_rfo.supplier_none.snoop_none other OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020122 00 ocr.demand_code_rd.any_response other Counts all demand code reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10004 00 ocr.demand_code_rd.pmm_hit_local_pmm.any_snoop other Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400004 00 ocr.demand_code_rd.pmm_hit_local_pmm.snoop_none other Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400004 00 ocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed other Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400004 00 ocr.demand_code_rd.supplier_none.any_snoop other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020004 00 ocr.demand_code_rd.supplier_none.hitm_other_core other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020004 00 ocr.demand_code_rd.supplier_none.hit_other_core_fwd other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020004 00 ocr.demand_code_rd.supplier_none.hit_other_core_no_fwd other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020004 00 ocr.demand_code_rd.supplier_none.no_snoop_needed other Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020004 00 ocr.demand_code_rd.supplier_none.snoop_miss other Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020004 00 ocr.demand_code_rd.supplier_none.snoop_none other Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020004 00 ocr.demand_data_rd.any_response other Counts demand data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 00 ocr.demand_data_rd.pmm_hit_local_pmm.any_snoop other Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400001 00 ocr.demand_data_rd.pmm_hit_local_pmm.snoop_none other Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400001 00 ocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400001 00 ocr.demand_data_rd.supplier_none.any_snoop other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020001 00 ocr.demand_data_rd.supplier_none.hitm_other_core other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020001 00 ocr.demand_data_rd.supplier_none.hit_other_core_fwd other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020001 00 ocr.demand_data_rd.supplier_none.hit_other_core_no_fwd other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020001 00 ocr.demand_data_rd.supplier_none.no_snoop_needed other Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020001 00 ocr.demand_data_rd.supplier_none.snoop_miss other Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020001 00 ocr.demand_data_rd.supplier_none.snoop_none other Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020001 00 ocr.demand_rfo.any_response other Counts all demand data writes (RFOs) have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 00 ocr.demand_rfo.pmm_hit_local_pmm.any_snoop other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400002 00 ocr.demand_rfo.pmm_hit_local_pmm.snoop_none other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400002 00 ocr.demand_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400002 00 ocr.demand_rfo.supplier_none.any_snoop other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020002 00 ocr.demand_rfo.supplier_none.hitm_other_core other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020002 00 ocr.demand_rfo.supplier_none.hit_other_core_fwd other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020002 00 ocr.demand_rfo.supplier_none.hit_other_core_no_fwd other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020002 00 ocr.demand_rfo.supplier_none.no_snoop_needed other Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020002 00 ocr.demand_rfo.supplier_none.snoop_miss other Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020002 00 ocr.demand_rfo.supplier_none.snoop_none other Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020002 00 ocr.other.any_response other Counts any other requests have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000 00 ocr.other.pmm_hit_local_pmm.any_snoop other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80408000 00 ocr.other.pmm_hit_local_pmm.snoop_none other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80408000 00 ocr.other.pmm_hit_local_pmm.snoop_not_needed other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100408000 00 ocr.other.supplier_none.any_snoop other Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80028000 00 ocr.other.supplier_none.hitm_other_core other Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000028000 00 ocr.other.supplier_none.hit_other_core_fwd other Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800028000 00 ocr.other.supplier_none.hit_other_core_no_fwd other Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400028000 00 ocr.other.supplier_none.no_snoop_needed other Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100028000 00 ocr.other.supplier_none.snoop_miss other Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200028000 00 ocr.other.supplier_none.snoop_none other Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80028000 00 ocr.pf_l1d_and_sw.any_response other Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400 00 ocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400400 00 ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400400 00 ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400400 00 ocr.pf_l1d_and_sw.supplier_none.any_snoop other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020400 00 ocr.pf_l1d_and_sw.supplier_none.hitm_other_core other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020400 00 ocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwd other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020400 00 ocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020400 00 ocr.pf_l1d_and_sw.supplier_none.no_snoop_needed other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020400 00 ocr.pf_l1d_and_sw.supplier_none.snoop_miss other Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020400 00 ocr.pf_l1d_and_sw.supplier_none.snoop_none other Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020400 00 ocr.pf_l2_data_rd.any_response other Counts prefetch (that bring data to L2) data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010 00 ocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400010 00 ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400010 00 ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400010 00 ocr.pf_l2_data_rd.supplier_none.any_snoop other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020010 00 ocr.pf_l2_data_rd.supplier_none.hitm_other_core other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020010 00 ocr.pf_l2_data_rd.supplier_none.hit_other_core_fwd other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020010 00 ocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020010 00 ocr.pf_l2_data_rd.supplier_none.no_snoop_needed other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020010 00 ocr.pf_l2_data_rd.supplier_none.snoop_miss other Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020010 00 ocr.pf_l2_data_rd.supplier_none.snoop_none other Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020010 00 ocr.pf_l2_rfo.any_response other Counts all prefetch (that bring data to L2) RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020 00 ocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400020 00 ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400020 00 ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400020 00 ocr.pf_l2_rfo.supplier_none.any_snoop other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020020 00 ocr.pf_l2_rfo.supplier_none.hitm_other_core other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020020 00 ocr.pf_l2_rfo.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020020 00 ocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020020 00 ocr.pf_l2_rfo.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020020 00 ocr.pf_l2_rfo.supplier_none.snoop_miss other Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020020 00 ocr.pf_l2_rfo.supplier_none.snoop_none other Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020020 00 ocr.pf_l3_data_rd.any_response other Counts all prefetch (that bring data to LLC only) data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10080 00 ocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400080 00 ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400080 00 ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400080 00 ocr.pf_l3_data_rd.supplier_none.any_snoop other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020080 00 ocr.pf_l3_data_rd.supplier_none.hitm_other_core other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020080 00 ocr.pf_l3_data_rd.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020080 00 ocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020080 00 ocr.pf_l3_data_rd.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020080 00 ocr.pf_l3_data_rd.supplier_none.snoop_miss other Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020080 00 ocr.pf_l3_data_rd.supplier_none.snoop_none other Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020080 00 ocr.pf_l3_rfo.any_response other Counts all prefetch (that bring data to LLC only) RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100 00 ocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400100 00 ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400100 00 ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400100 00 ocr.pf_l3_rfo.supplier_none.any_snoop other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020100 00 ocr.pf_l3_rfo.supplier_none.hitm_other_core other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020100 00 ocr.pf_l3_rfo.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020100 00 ocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020100 00 ocr.pf_l3_rfo.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020100 00 ocr.pf_l3_rfo.supplier_none.snoop_miss other Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020100 00 ocr.pf_l3_rfo.supplier_none.snoop_none other Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020100 00 arith.divider_active pipeline Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations event=0x14,cmask=1,period=2000003,umask=0x1 00 br_inst_retired.all_branches pipeline All (macro) branch instructions retired Spec update: SKL091 event=0xc4,period=400009 00 Counts all (macro) branch instructions retired Spec update: SKL091 br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired Spec update: SKL091 (Must be precise) event=0xc4,period=400009,umask=0x4 00 This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: SKL091 (Must be precise) br_inst_retired.cond pipeline Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL] Spec update: SKL091 event=0xc4,period=400009,umask=0x1 00 This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL] Spec update: SKL091 br_inst_retired.conditional pipeline Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND] Spec update: SKL091 (Precise event) event=0xc4,period=400009,umask=0x1 00 This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND] Spec update: SKL091 (Precise event) br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired Spec update: SKL091 event=0xc4,period=400009,umask=0x10 00 This event counts not taken branch instructions retired Spec update: SKL091 br_inst_retired.far_branch pipeline Far branch instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=0x40 00 This event counts far branch instructions retired Spec update: SKL091 (Precise event) br_inst_retired.near_call pipeline Direct and indirect near call instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=0x2 00 This event counts both direct and indirect near call instructions retired Spec update: SKL091 (Precise event) br_inst_retired.near_return pipeline Return instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=0x8 00 This event counts return instructions retired Spec update: SKL091 (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired Spec update: SKL091 (Precise event) event=0xc4,period=400009,umask=0x20 00 This event counts taken branch instructions retired Spec update: SKL091 (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired Spec update: SKL091 event=0xc4,period=400009,umask=0x10 00 This event counts not taken branch instructions retired Spec update: SKL091 br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=0x4 00 This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) br_misp_retired.near_call pipeline Mispredicted direct and indirect near call instructions retired (Precise event) event=0xc5,period=400009,umask=0x2 00 Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 cpu_clk_thread_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=0x2 00 cpu_clk_thread_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=0x1 00 cpu_clk_thread_unhalted.ref_xclk_any pipeline Core crystal clock cycles when at least one thread on the physical core is unhalted event=0x3c,any=1,period=25003,umask=0x1 00 cpu_clk_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=0x2 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=0x1 00 cpu_clk_unhalted.ref_xclk_any pipeline Core crystal clock cycles when at least one thread on the physical core is unhalted event=0x3c,any=1,period=25003,umask=0x1 00 cpu_clk_unhalted.ring0_trans pipeline Counts when there is a transition from ring 1, 2 or 3 to ring 0 event=0x3c,cmask=1,edge=1,period=100007 00 Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel) cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=16,period=2000003,umask=0x10 00 cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=20,period=2000003,umask=0x14 00 exe_activity.bound_on_stores pipeline Cycles where the Store Buffer was full and no outstanding load event=0xa6,period=2000003,umask=0x40 00 exe_activity.exe_bound_0_ports pipeline Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load event=0xa6,period=2000003,umask=0x1 00 Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP] event=0x87,period=2000003,umask=0x1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP] inst_decoded.decoders pipeline Instruction decoders utilized in a cycle event=0x55,period=2000003,umask=0x1 00 Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event Spec update: SKL091, SKL044 event=0xc0,period=2000003 00 Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: SKL091, SKL044 inst_retired.nop pipeline Number of all retired NOP instructions Spec update: SKL091, SKL044 (Precise event) event=0xc0,period=2000003,umask=0x2 00 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: SKL091, SKL044 (Must be precise) event=0xc0,period=2000003,umask=0x1 00 A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled Spec update: SKL091, SKL044 (Must be precise) inst_retired.total_cycles_ps pipeline Number of cycles using always true condition applied to PEBS instructions retired event Spec update: SKL091, SKL044 (Must be precise) event=0xc0,cmask=10,inv=1,period=2000003,umask=0x1 00 Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16) Spec update: SKL091, SKL044 (Must be precise) int_misc.clears_count pipeline Clears speculative count event=0xd,cmask=1,edge=1,period=2000003,umask=0x1 00 Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events event=0xd,period=2000003,umask=0x80 00 int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,period=2000003,umask=0x1 00 Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,period=2000003,umask=0x1 00 ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=0x3,period=100003,umask=0x8 00 The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Loads blocked due to overlapping with a preceding store that cannot be forwarded event=0x3,period=100003,umask=0x2 00 Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=0x7,period=100003,umask=0x1 00 Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased load_hit_pre.sw_pf pipeline Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=0x1 00 Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK] event=0xa8,cmask=4,period=2000003,umask=0x1 00 Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_OK] lsd.cycles_ok pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS] event=0xa8,cmask=4,period=2000003,umask=0x1 00 Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_4_UOPS] lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=0x1 00 Number of uops delivered to the back-end by the LSD(Loop Stream Detector) other_assists.any pipeline Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists event=0xc1,period=100003,umask=0x3f 00 partial_rat_stalls.scoreboard pipeline Cycles where the pipeline is stalled due to serializing operations event=0x59,period=2000003,umask=0x1 00 This event counts cycles during which the microcode scoreboard stalls happen resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=0x1 00 Counts resource-related stall cycles resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=0x8 00 Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end rob_misc_events.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=2000003,umask=0x20 00 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT rob_misc_events.pause_inst pipeline Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products event=0xcc,period=2000003,umask=0x40 00 rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=0x1 00 Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=0x1 00 Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=0x1 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=0x2 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=0x4 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=0x8 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7 uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,cmask=1,inv=1,period=2000003,umask=0x2 00 uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=0x1 00 Cycles where at least 1 uop was executed per-thread uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=0x1 00 Cycles where at least 2 uops were executed per-thread uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=0x1 00 Cycles where at least 3 uops were executed per-thread uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=0x1 00 Cycles where at least 4 uops were executed per-thread uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=0x1 00 Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=0x1 00 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=0x1 00 Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=2000003,umask=0x2 00 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide uops_retired.macro_fused pipeline Number of macro-fused uops retired. (non precise) event=0xc2,period=2000003,umask=0x4 00 Counts the number of macro-fused uops retired. (non precise) uops_retired.retire_slots pipeline Retirement slots used event=0xc2,period=2000003,umask=0x2 00 Counts the retirement slots used uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=0x2 00 This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=0x2 00 Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event uncore_cha llc_misses.mmio_read uncore cache MMIO reads. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40040e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_misses.mmio_write uncore cache MMIO writes. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40041e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_misses.uncacheable uncore cache LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_references.streaming_full uncore cache Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x41833 0164Bytes TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_references.streaming_partial uncore cache Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x41a33 0164Bytes TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_ag0_ad_crd_acquired.tgr0 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=0x1 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr1 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=0x2 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr2 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=0x4 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr3 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=0x8 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr4 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr5 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr0 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=0x1 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr1 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=0x2 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr2 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=0x4 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr3 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=0x8 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr4 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr5 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr0 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=0x1 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr1 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=0x2 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr2 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=0x4 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr3 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=0x8 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr4 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr5 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr0 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=0x1 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr1 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=0x2 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr2 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=0x4 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr3 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=0x8 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr4 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr5 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr0 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=0x1 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr1 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=0x2 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr2 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=0x4 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr3 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=0x8 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr4 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr5 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr0 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=0x1 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr1 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=0x2 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr2 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=0x4 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr3 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=0x8 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr4 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr5 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr0 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=0x1 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr1 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=0x2 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr2 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=0x4 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr3 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=0x8 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr4 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr5 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr0 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=0x1 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr1 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=0x2 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr2 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=0x4 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr3 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=0x8 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr4 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr5 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_bypass_cha_imc.intermediate uncore cache CHA to iMC Bypass; Intermediate bypass Taken event=0x57,umask=0x2 01 Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass unc_cha_bypass_cha_imc.not_taken uncore cache CHA to iMC Bypass; Not Taken event=0x57,umask=0x4 01 Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted unc_cha_bypass_cha_imc.taken uncore cache CHA to iMC Bypass; Taken event=0x57,umask=0x1 01 Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass unc_cha_clockticks uncore cache Uncore cache clock ticks event=0 01 Counts clockticks of the clock controlling the uncore caching and home agent (CHA) unc_cha_cms_clockticks uncore cache CMS Clockticks event=0xc0 01 unc_cha_core_pma.c1_state uncore cache Core PMA Events; C1 State event=0x17,umask=0x1 01 unc_cha_core_pma.c1_transition uncore cache Core PMA Events; C1 Transition event=0x17,umask=0x2 01 unc_cha_core_pma.c6_state uncore cache Core PMA Events; C6 State event=0x17,umask=0x4 01 unc_cha_core_pma.c6_transition uncore cache Core PMA Events; C6 Transition event=0x17,umask=0x8 01 unc_cha_core_pma.gv uncore cache Core PMA Events; GV event=0x17,umask=0x10 01 unc_cha_core_snp.any_gtone uncore cache Core Cross Snoops Issued; Any Cycle with Multiple Snoops event=0x33,umask=0xe2 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_one uncore cache Core Cross Snoops Issued; Any Single Snoop event=0x33,umask=0xe1 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_remote uncore cache Core Cross Snoops Issued; Any Snoop to Remote Node event=0x33,umask=0xe4 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_gtone uncore cache Core Cross Snoops Issued; Multiple Core Requests event=0x33,umask=0x42 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_one uncore cache Core Cross Snoops Issued; Single Core Requests event=0x33,umask=0x41 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_remote uncore cache Core Cross Snoops Issued; Core Request to Remote Node event=0x33,umask=0x44 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_gtone uncore cache Core Cross Snoops Issued; Multiple Eviction event=0x33,umask=0x82 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_one uncore cache Core Cross Snoops Issued; Single Eviction event=0x33,umask=0x81 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_remote uncore cache Core Cross Snoops Issued; Eviction to Remote Node event=0x33,umask=0x84 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_gtone uncore cache Core Cross Snoops Issued; Multiple External Snoops event=0x33,umask=0x22 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_one uncore cache Core Cross Snoops Issued; Single External Snoops event=0x33,umask=0x21 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_remote uncore cache Core Cross Snoops Issued; External Snoop to Remote Node event=0x33,umask=0x24 01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f 01 Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_cha_dir_lookup.no_snp uncore cache Multi-socket cacheline Directory state lookups; Snoop Not Needed event=0x53,umask=0x2 01 Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed unc_cha_dir_lookup.snp uncore cache Multi-socket cacheline Directory state lookups; Snoop Needed event=0x53,umask=0x1 01 Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed unc_cha_dir_update.ha uncore cache Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe event=0x54,umask=0x1 01 Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_dir_update.tor uncore cache Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe event=0x54,umask=0x2 01 Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_egress_ordering.iv_snoopgo_dn uncore cache Egress Blocking due to Ordering requirements; Down event=0xae,umask=0x4 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_egress_ordering.iv_snoopgo_up uncore cache Egress Blocking due to Ordering requirements; Up event=0xae,umask=0x1 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_fast_asserted.horz uncore cache FaST wire asserted; Horizontal event=0xa5,umask=0x2 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_cha_fast_asserted.vert uncore cache FaST wire asserted; Vertical event=0xa5,umask=0x1 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_cha_hitme_hit.ex_rds uncore cache Read request from a remote socket which hit in the HitMe Cache to a line In the E state event=0x5f,umask=0x1 01 Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*) unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv* event=0x5f,umask=0x4 01 unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoE event=0x5f,umask=0x8 01 unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5f,umask=0x10 01 unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* event=0x5e,umask=0x1 01 unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5e,umask=0x2 01 unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x40 01 unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* event=0x60,umask=0x80 01 unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x20 01 unc_cha_hitme_update.deallocate uncore cache Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI* event=0x61,umask=0x10 01 unc_cha_hitme_update.deallocate_rspfwdi_loc uncore cache Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request event=0x61,umask=0x1 01 Received RspFwdI* for a local request, but converted HitME$ to SF entry unc_cha_hitme_update.rdinvown uncore cache Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI* event=0x61,umask=0x8 01 unc_cha_hitme_update.rspfwdi_rem uncore cache Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request event=0x61,umask=0x2 01 Updated HitME$ on RspFwdI* or local HitM/E received for a remote request unc_cha_hitme_update.shared uncore cache Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed event=0x61,umask=0x4 01 unc_cha_horz_ring_ad_in_use.left_even uncore cache Horizontal AD Ring In Use; Left and Even event=0xa7,umask=0x1 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.left_odd uncore cache Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=0x2 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_even uncore cache Horizontal AD Ring In Use; Right and Even event=0xa7,umask=0x4 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_odd uncore cache Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=0x8 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_even uncore cache Horizontal AK Ring In Use; Left and Even event=0xa9,umask=0x1 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_odd uncore cache Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=0x2 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_even uncore cache Horizontal AK Ring In Use; Right and Even event=0xa9,umask=0x4 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_odd uncore cache Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=0x8 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_even uncore cache Horizontal BL Ring in Use; Left and Even event=0xab,umask=0x1 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_odd uncore cache Horizontal BL Ring in Use; Left and Odd event=0xab,umask=0x2 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_even uncore cache Horizontal BL Ring in Use; Right and Even event=0xab,umask=0x4 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_odd uncore cache Horizontal BL Ring in Use; Right and Odd event=0xab,umask=0x8 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_iv_in_use.left uncore cache Horizontal IV Ring in Use; Left event=0xad,umask=0x1 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_horz_ring_iv_in_use.right uncore cache Horizontal IV Ring in Use; Right event=0xad,umask=0x4 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_imc_reads_count.normal uncore cache Normal priority reads issued to the memory controller from the CHA event=0x59,umask=0x1 01 Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA unc_cha_imc_reads_count.priority uncore cache HA to iMC Reads Issued; ISOCH event=0x59,umask=0x2 01 Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads unc_cha_imc_writes_count.full uncore cache CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH event=0x5b,umask=0x1 01 Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels unc_cha_imc_writes_count.full_mig uncore cache Writes Issued to the iMC by the HA; Full Line MIG event=0x5b,umask=0x10 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.full_priority uncore cache Writes Issued to the iMC by the HA; ISOCH Full Line event=0x5b,umask=0x4 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.partial uncore cache Writes Issued to the iMC by the HA; Partial Non-ISOCH event=0x5b,umask=0x2 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.partial_mig uncore cache Writes Issued to the iMC by the HA; Partial MIG event=0x5b,umask=0x20 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only unc_cha_imc_writes_count.partial_priority uncore cache Writes Issued to the iMC by the HA; ISOCH Partial event=0x5b,umask=0x8 01 Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_iodc_alloc.invitom uncore cache Counts Number of times IODC entry allocation is attempted; Number of IODC allocations event=0x62,umask=0x1 01 unc_cha_iodc_alloc.iodcfull uncore cache Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full event=0x62,umask=0x2 01 unc_cha_iodc_alloc.osbgated uncore cache Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate event=0x62,umask=0x4 01 unc_cha_iodc_dealloc.all uncore cache Counts number of IODC deallocations; IODC deallocated due to any reason event=0x63,umask=0x10 01 unc_cha_iodc_dealloc.snpout uncore cache Counts number of IODC deallocations; IODC deallocated due to conflicting transaction event=0x63,umask=0x8 01 unc_cha_iodc_dealloc.wbmtoe uncore cache Counts number of IODC deallocations; IODC deallocated due to WbMtoE event=0x63,umask=0x1 01 unc_cha_iodc_dealloc.wbmtoi uncore cache Counts number of IODC deallocations; IODC deallocated due to WbMtoI event=0x63,umask=0x2 01 unc_cha_iodc_dealloc.wbpushmtoi uncore cache Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI event=0x63,umask=0x4 01 Moved to Cbo section unc_cha_llc_lookup.any uncore cache Cache and Snoop Filter Lookups; Any Request event=0x34,umask=0x11 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_cha_llc_lookup.data_read uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=0x3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions unc_cha_llc_lookup.local uncore cache Cache and Snoop Filter Lookups; Local event=0x34,umask=0x31 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state unc_cha_llc_lookup.remote uncore cache Cache and Snoop Filter Lookups; Remote event=0x34,umask=0x91 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state unc_cha_llc_lookup.remote_snoop uncore cache Cache and Snoop Filter Lookups; External Snoop Request event=0x34,umask=0x9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_cha_llc_lookup.write uncore cache Cache and Snoop Filter Lookups; Write Requests event=0x34,umask=0x5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_victims.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E event=0x37,umask=0x2 11 unc_cha_llc_victims.f_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F event=0x37,umask=0x8 11 unc_cha_llc_victims.local uncore cache This event is deprecated event=0x37,umask=0x20 11 unc_cha_llc_victims.local_all uncore cache Lines Victimized; Local - All Lines event=0x37,umask=0x2f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized; Local - Lines in E State event=0x37,umask=0x22 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_f uncore cache Lines Victimized; Local - Lines in F State event=0x37,umask=0x28 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized; Local - Lines in M State event=0x37,umask=0x21 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized; Local - Lines in S State event=0x37,umask=0x24 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M event=0x37,umask=0x1 11 unc_cha_llc_victims.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL event=0x37,umask=0x80 11 unc_cha_llc_victims.remote_all uncore cache Lines Victimized; Remote - All Lines event=0x37,umask=0x8f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized; Remote - Lines in E State event=0x37,umask=0x82 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_f uncore cache Lines Victimized; Remote - Lines in F State event=0x37,umask=0x88 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized; Remote - Lines in M State event=0x37,umask=0x81 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized; Remote - Lines in S State event=0x37,umask=0x84 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S event=0x37,umask=0x4 11 unc_cha_llc_victims.total_e uncore cache Lines Victimized; Lines in E state event=0x37,umask=0x2 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_f uncore cache Lines Victimized; Lines in F State event=0x37,umask=0x8 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_m uncore cache Lines Victimized; Lines in M state event=0x37,umask=0x1 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_s uncore cache Lines Victimized; Lines in S State event=0x37,umask=0x4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_misc.cv0_pref_miss uncore cache Cbo Misc; CV0 Prefetch Miss event=0x39,umask=0x20 01 Miscellaneous events in the Cbo unc_cha_misc.cv0_pref_vic uncore cache Cbo Misc; CV0 Prefetch Victim event=0x39,umask=0x10 01 Miscellaneous events in the Cbo unc_cha_misc.rfo_hit_s uncore cache Number of times that an RFO hit in S state event=0x39,umask=0x8 01 Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state unc_cha_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=0x1 01 Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings unc_cha_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=0x2 01 Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing unc_cha_osb uncore cache OSB Snoop Broadcast event=0x55 01 Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_pmm_memmode_nm_setconflicts.iodc uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC event=0x64,umask=0x10 01 2LM related events; Counts the number of times CHA saw NM Set conflict in IODC unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=0x2 01 NM evictions due to another read to the same near memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=0x1 01 NM evictions due to another read to the same near memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR event=0x64,umask=0x4 01 No Reject in the CHA due to a pending read to the same near memory set in the TOR unc_cha_pmm_memmode_nm_setconflicts.tor_reject uncore cache Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected event=0x64,umask=0x8 01 Rejects in the CHA due to a pending read to the same near memory set in the TOR unc_cha_read_no_credits.edc0_smi2 uncore cache CHA iMC CHNx READ Credits Empty; EDC0_SMI2 event=0x58,umask=0x4 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only unc_cha_read_no_credits.edc1_smi3 uncore cache CHA iMC CHNx READ Credits Empty; EDC1_SMI3 event=0x58,umask=0x8 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only unc_cha_read_no_credits.edc2_smi4 uncore cache CHA iMC CHNx READ Credits Empty; EDC2_SMI4 event=0x58,umask=0x10 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only unc_cha_read_no_credits.edc3_smi5 uncore cache CHA iMC CHNx READ Credits Empty; EDC3_SMI5 event=0x58,umask=0x20 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only unc_cha_read_no_credits.mc0_smi0 uncore cache CHA iMC CHNx READ Credits Empty; MC0_SMI0 event=0x58,umask=0x1 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only unc_cha_read_no_credits.mc1_smi1 uncore cache CHA iMC CHNx READ Credits Empty; MC1_SMI1 event=0x58,umask=0x2 01 Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only unc_cha_requests.invitoe_local uncore cache Local requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x10 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Local requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x20 01 Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Read requests event=0x50,umask=0x3 01 Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_local uncore cache Read requests from a unit on this socket event=0x50,umask=0x1 01 Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_remote uncore cache Read requests from a remote socket event=0x50,umask=0x2 01 Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.writes uncore cache Write requests event=0x50,umask=0xc 01 Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_local uncore cache Write Requests from a unit on this socket event=0x50,umask=0x4 01 Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_remote uncore cache Read and Write Requests; Writes Remote event=0x50,umask=0x8 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_cha_ring_bounces_horz.ad uncore cache Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=0x1 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.ak uncore cache Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=0x2 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.bl uncore cache Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=0x4 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.iv uncore cache Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=0x8 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_vert.ad uncore cache Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=0x1 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.ak uncore cache Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=0x2 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.bl uncore cache Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=0x4 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.iv uncore cache Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=0x8 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_sink_starved_horz.ad uncore cache Sink Starvation on Horizontal Ring; AD event=0xa3,umask=0x1 01 unc_cha_ring_sink_starved_horz.ak uncore cache Sink Starvation on Horizontal Ring; AK event=0xa3,umask=0x2 01 unc_cha_ring_sink_starved_horz.ak_ag1 uncore cache Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20 01 unc_cha_ring_sink_starved_horz.bl uncore cache Sink Starvation on Horizontal Ring; BL event=0xa3,umask=0x4 01 unc_cha_ring_sink_starved_horz.iv uncore cache Sink Starvation on Horizontal Ring; IV event=0xa3,umask=0x8 01 unc_cha_ring_sink_starved_vert.ad uncore cache Sink Starvation on Vertical Ring; AD event=0xa2,umask=0x1 01 unc_cha_ring_sink_starved_vert.ak uncore cache Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=0x2 01 unc_cha_ring_sink_starved_vert.bl uncore cache Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=0x4 01 unc_cha_ring_sink_starved_vert.iv uncore cache Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=0x8 01 unc_cha_ring_src_thrtl uncore cache Source Throttle event=0xa4 01 unc_cha_rxc_inserts.ipq uncore cache Ingress (from CMS) Allocations; IPQ event=0x13,umask=0x4 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq uncore cache Ingress (from CMS) Allocations; IRQ event=0x13,umask=0x1 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq_rej uncore cache Ingress (from CMS) Allocations; IRQ Rejected event=0x13,umask=0x2 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq uncore cache Ingress (from CMS) Allocations; PRQ event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq_rej uncore cache Ingress (from CMS) Allocations; PRQ event=0x13,umask=0x20 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.rrq uncore cache Ingress (from CMS) Allocations; RRQ event=0x13,umask=0x40 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.wbq uncore cache Ingress (from CMS) Allocations; WBQ event=0x13,umask=0x80 01 Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_ipq0_reject.ad_req_vn0 uncore cache Ingress Probe Queue Rejects; AD REQ on VN0 event=0x22,umask=0x1 01 unc_cha_rxc_ipq0_reject.ad_rsp_vn0 uncore cache Ingress Probe Queue Rejects; AD RSP on VN0 event=0x22,umask=0x2 01 unc_cha_rxc_ipq0_reject.ak_non_upi uncore cache Ingress Probe Queue Rejects; Non UPI AK Request event=0x22,umask=0x40 01 unc_cha_rxc_ipq0_reject.bl_ncb_vn0 uncore cache Ingress Probe Queue Rejects; BL NCB on VN0 event=0x22,umask=0x10 01 unc_cha_rxc_ipq0_reject.bl_ncs_vn0 uncore cache Ingress Probe Queue Rejects; BL NCS on VN0 event=0x22,umask=0x20 01 unc_cha_rxc_ipq0_reject.bl_rsp_vn0 uncore cache Ingress Probe Queue Rejects; BL RSP on VN0 event=0x22,umask=0x4 01 unc_cha_rxc_ipq0_reject.bl_wb_vn0 uncore cache Ingress Probe Queue Rejects; BL WB on VN0 event=0x22,umask=0x8 01 unc_cha_rxc_ipq0_reject.iv_non_upi uncore cache Ingress Probe Queue Rejects; Non UPI IV Request event=0x22,umask=0x80 01 unc_cha_rxc_ipq1_reject.allow_snp uncore cache Ingress Probe Queue Rejects; Allow Snoop event=0x23,umask=0x40 01 unc_cha_rxc_ipq1_reject.any0 uncore cache Ingress Probe Queue Rejects; ANY0 event=0x23,umask=0x1 01 unc_cha_rxc_ipq1_reject.ha uncore cache Ingress Probe Queue Rejects; HA event=0x23,umask=0x2 01 unc_cha_rxc_ipq1_reject.llc_or_sf_way uncore cache Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x23,umask=0x20 01 unc_cha_rxc_ipq1_reject.llc_victim uncore cache Ingress Probe Queue Rejects; LLC Victim event=0x23,umask=0x4 01 unc_cha_rxc_ipq1_reject.pa_match uncore cache Ingress Probe Queue Rejects; PhyAddr Match event=0x23,umask=0x80 01 unc_cha_rxc_ipq1_reject.sf_victim uncore cache Ingress Probe Queue Rejects; SF Victim event=0x23,umask=0x8 01 unc_cha_rxc_ipq1_reject.victim uncore cache Ingress Probe Queue Rejects; Victim event=0x23,umask=0x10 01 unc_cha_rxc_irq0_reject.ad_req_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD REQ on VN0 event=0x18,umask=0x1 01 unc_cha_rxc_irq0_reject.ad_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD RSP on VN0 event=0x18,umask=0x2 01 unc_cha_rxc_irq0_reject.ak_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI AK Request event=0x18,umask=0x40 01 unc_cha_rxc_irq0_reject.bl_ncb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCB on VN0 event=0x18,umask=0x10 01 unc_cha_rxc_irq0_reject.bl_ncs_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCS on VN0 event=0x18,umask=0x20 01 unc_cha_rxc_irq0_reject.bl_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL RSP on VN0 event=0x18,umask=0x4 01 unc_cha_rxc_irq0_reject.bl_wb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL WB on VN0 event=0x18,umask=0x8 01 unc_cha_rxc_irq0_reject.iv_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI IV Request event=0x18,umask=0x80 01 unc_cha_rxc_irq1_reject.allow_snp uncore cache Ingress (from CMS) Request Queue Rejects; Allow Snoop event=0x19,umask=0x40 01 unc_cha_rxc_irq1_reject.any0 uncore cache Ingress (from CMS) Request Queue Rejects; ANY0 event=0x19,umask=0x1 01 unc_cha_rxc_irq1_reject.ha uncore cache Ingress (from CMS) Request Queue Rejects; HA event=0x19,umask=0x2 01 unc_cha_rxc_irq1_reject.llc_or_sf_way uncore cache Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x19,umask=0x20 01 unc_cha_rxc_irq1_reject.llc_victim uncore cache Ingress (from CMS) Request Queue Rejects; LLC Victim event=0x19,umask=0x4 01 unc_cha_rxc_irq1_reject.pa_match uncore cache Ingress (from CMS) Request Queue Rejects; PhyAddr Match event=0x19,umask=0x80 01 unc_cha_rxc_irq1_reject.sf_victim uncore cache Ingress (from CMS) Request Queue Rejects; SF Victim event=0x19,umask=0x8 01 unc_cha_rxc_irq1_reject.victim uncore cache Ingress (from CMS) Request Queue Rejects; Victim event=0x19,umask=0x10 01 unc_cha_rxc_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects; AD REQ on VN0 event=0x24,umask=0x1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects; AD RSP on VN0 event=0x24,umask=0x2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects; Non UPI AK Request event=0x24,umask=0x40 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects; BL NCB on VN0 event=0x24,umask=0x10 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects; BL NCS on VN0 event=0x24,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects; BL RSP on VN0 event=0x24,umask=0x4 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects; BL WB on VN0 event=0x24,umask=0x8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects; Non UPI IV Request event=0x24,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries; AD REQ on VN0 event=0x2c,umask=0x1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries; AD RSP on VN0 event=0x2c,umask=0x2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ak_non_upi uncore cache ISMQ Retries; Non UPI AK Request event=0x2c,umask=0x40 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries; BL NCB on VN0 event=0x2c,umask=0x10 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries; BL NCS on VN0 event=0x2c,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries; BL RSP on VN0 event=0x2c,umask=0x4 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries; BL WB on VN0 event=0x2c,umask=0x8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.iv_non_upi uncore cache ISMQ Retries; Non UPI IV Request event=0x2c,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_reject.any0 uncore cache ISMQ Rejects; ANY0 event=0x25,umask=0x1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_reject.ha uncore cache ISMQ Rejects; HA event=0x25,umask=0x2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.any0 uncore cache ISMQ Retries; ANY0 event=0x2d,umask=0x1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.ha uncore cache ISMQ Retries; HA event=0x2d,umask=0x2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_occupancy.ipq uncore cache Ingress (from CMS) Occupancy; IPQ event=0x11,umask=0x4 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.irq uncore cache Ingress (from CMS) Occupancy; IRQ event=0x11,umask=0x1 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.rrq uncore cache Ingress (from CMS) Occupancy; RRQ event=0x11,umask=0x40 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.wbq uncore cache Ingress (from CMS) Occupancy; WBQ event=0x11,umask=0x80 01 Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_other0_retry.ad_req_vn0 uncore cache Other Retries; AD REQ on VN0 event=0x2e,umask=0x1 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.ad_rsp_vn0 uncore cache Other Retries; AD RSP on VN0 event=0x2e,umask=0x2 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.ak_non_upi uncore cache Other Retries; Non UPI AK Request event=0x2e,umask=0x40 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_ncb_vn0 uncore cache Other Retries; BL NCB on VN0 event=0x2e,umask=0x10 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_ncs_vn0 uncore cache Other Retries; BL NCS on VN0 event=0x2e,umask=0x20 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_rsp_vn0 uncore cache Other Retries; BL RSP on VN0 event=0x2e,umask=0x4 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_wb_vn0 uncore cache Other Retries; BL WB on VN0 event=0x2e,umask=0x8 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.iv_non_upi uncore cache Other Retries; Non UPI IV Request event=0x2e,umask=0x80 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.allow_snp uncore cache Other Retries; Allow Snoop event=0x2f,umask=0x40 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.any0 uncore cache Other Retries; ANY0 event=0x2f,umask=0x1 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.ha uncore cache Other Retries; HA event=0x2f,umask=0x2 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_or_sf_way uncore cache Other Retries; Merging these two together to make room for ANY_REJECT_*0 event=0x2f,umask=0x20 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_victim uncore cache Other Retries; LLC Victim event=0x2f,umask=0x4 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.pa_match uncore cache Other Retries; PhyAddr Match event=0x2f,umask=0x80 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.sf_victim uncore cache Other Retries; SF Victim event=0x2f,umask=0x8 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.victim uncore cache Other Retries; Victim event=0x2f,umask=0x10 01 Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_prq0_reject.ad_req_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD REQ on VN0 event=0x20,umask=0x1 01 unc_cha_rxc_prq0_reject.ad_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD RSP on VN0 event=0x20,umask=0x2 01 unc_cha_rxc_prq0_reject.ak_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI AK Request event=0x20,umask=0x40 01 unc_cha_rxc_prq0_reject.bl_ncb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCB on VN0 event=0x20,umask=0x10 01 unc_cha_rxc_prq0_reject.bl_ncs_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCS on VN0 event=0x20,umask=0x20 01 unc_cha_rxc_prq0_reject.bl_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL RSP on VN0 event=0x20,umask=0x4 01 unc_cha_rxc_prq0_reject.bl_wb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL WB on VN0 event=0x20,umask=0x8 01 unc_cha_rxc_prq0_reject.iv_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI IV Request event=0x20,umask=0x80 01 unc_cha_rxc_prq1_reject.allow_snp uncore cache Ingress (from CMS) Request Queue Rejects; Allow Snoop event=0x21,umask=0x40 01 unc_cha_rxc_prq1_reject.any0 uncore cache Ingress (from CMS) Request Queue Rejects; ANY0 event=0x21,umask=0x1 01 unc_cha_rxc_prq1_reject.ha uncore cache Ingress (from CMS) Request Queue Rejects; HA event=0x21,umask=0x2 01 unc_cha_rxc_prq1_reject.llc_or_sf_way uncore cache Ingress (from CMS) Request Queue Rejects; LLC OR SF Way event=0x21,umask=0x20 01 unc_cha_rxc_prq1_reject.llc_victim uncore cache Ingress (from CMS) Request Queue Rejects; LLC Victim event=0x21,umask=0x4 01 unc_cha_rxc_prq1_reject.pa_match uncore cache Ingress (from CMS) Request Queue Rejects; PhyAddr Match event=0x21,umask=0x80 01 unc_cha_rxc_prq1_reject.sf_victim uncore cache Ingress (from CMS) Request Queue Rejects; SF Victim event=0x21,umask=0x8 01 unc_cha_rxc_prq1_reject.victim uncore cache Ingress (from CMS) Request Queue Rejects; Victim event=0x21,umask=0x10 01 unc_cha_rxc_req_q0_retry.ad_req_vn0 uncore cache Request Queue Retries; AD REQ on VN0 event=0x2a,umask=0x1 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.ad_rsp_vn0 uncore cache Request Queue Retries; AD RSP on VN0 event=0x2a,umask=0x2 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.ak_non_upi uncore cache Request Queue Retries; Non UPI AK Request event=0x2a,umask=0x40 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_ncb_vn0 uncore cache Request Queue Retries; BL NCB on VN0 event=0x2a,umask=0x10 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_ncs_vn0 uncore cache Request Queue Retries; BL NCS on VN0 event=0x2a,umask=0x20 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_rsp_vn0 uncore cache Request Queue Retries; BL RSP on VN0 event=0x2a,umask=0x4 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_wb_vn0 uncore cache Request Queue Retries; BL WB on VN0 event=0x2a,umask=0x8 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.iv_non_upi uncore cache Request Queue Retries; Non UPI IV Request event=0x2a,umask=0x80 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.allow_snp uncore cache Request Queue Retries; Allow Snoop event=0x2b,umask=0x40 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.any0 uncore cache Request Queue Retries; ANY0 event=0x2b,umask=0x1 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.ha uncore cache Request Queue Retries; HA event=0x2b,umask=0x2 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_or_sf_way uncore cache Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0 event=0x2b,umask=0x20 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_victim uncore cache Request Queue Retries; LLC Victim event=0x2b,umask=0x4 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.pa_match uncore cache Request Queue Retries; PhyAddr Match event=0x2b,umask=0x80 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.sf_victim uncore cache Request Queue Retries; SF Victim event=0x2b,umask=0x8 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.victim uncore cache Request Queue Retries; Victim event=0x2b,umask=0x10 01 REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_rrq0_reject.ad_req_vn0 uncore cache RRQ Rejects; AD REQ on VN0 event=0x26,umask=0x1 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.ad_rsp_vn0 uncore cache RRQ Rejects; AD RSP on VN0 event=0x26,umask=0x2 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.ak_non_upi uncore cache RRQ Rejects; Non UPI AK Request event=0x26,umask=0x40 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_ncb_vn0 uncore cache RRQ Rejects; BL NCB on VN0 event=0x26,umask=0x10 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_ncs_vn0 uncore cache RRQ Rejects; BL NCS on VN0 event=0x26,umask=0x20 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_rsp_vn0 uncore cache RRQ Rejects; BL RSP on VN0 event=0x26,umask=0x4 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_wb_vn0 uncore cache RRQ Rejects; BL WB on VN0 event=0x26,umask=0x8 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.iv_non_upi uncore cache RRQ Rejects; Non UPI IV Request event=0x26,umask=0x80 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.allow_snp uncore cache RRQ Rejects; Allow Snoop event=0x27,umask=0x40 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.any0 uncore cache RRQ Rejects; ANY0 event=0x27,umask=0x1 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.ha uncore cache RRQ Rejects; HA event=0x27,umask=0x2 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_or_sf_way uncore cache RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x27,umask=0x20 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_victim uncore cache RRQ Rejects; LLC Victim event=0x27,umask=0x4 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.pa_match uncore cache RRQ Rejects; PhyAddr Match event=0x27,umask=0x80 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.sf_victim uncore cache RRQ Rejects; SF Victim event=0x27,umask=0x8 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.victim uncore cache RRQ Rejects; Victim event=0x27,umask=0x10 01 Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_wbq0_reject.ad_req_vn0 uncore cache WBQ Rejects; AD REQ on VN0 event=0x28,umask=0x1 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.ad_rsp_vn0 uncore cache WBQ Rejects; AD RSP on VN0 event=0x28,umask=0x2 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.ak_non_upi uncore cache WBQ Rejects; Non UPI AK Request event=0x28,umask=0x40 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_ncb_vn0 uncore cache WBQ Rejects; BL NCB on VN0 event=0x28,umask=0x10 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_ncs_vn0 uncore cache WBQ Rejects; BL NCS on VN0 event=0x28,umask=0x20 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_rsp_vn0 uncore cache WBQ Rejects; BL RSP on VN0 event=0x28,umask=0x4 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_wb_vn0 uncore cache WBQ Rejects; BL WB on VN0 event=0x28,umask=0x8 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.iv_non_upi uncore cache WBQ Rejects; Non UPI IV Request event=0x28,umask=0x80 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.allow_snp uncore cache WBQ Rejects; Allow Snoop event=0x29,umask=0x40 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.any0 uncore cache WBQ Rejects; ANY0 event=0x29,umask=0x1 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.ha uncore cache WBQ Rejects; HA event=0x29,umask=0x2 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_or_sf_way uncore cache WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x29,umask=0x20 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_victim uncore cache WBQ Rejects; LLC Victim event=0x29,umask=0x4 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.pa_match uncore cache WBQ Rejects; PhyAddr Match event=0x29,umask=0x80 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.sf_victim uncore cache WBQ Rejects; SF Victim event=0x29,umask=0x8 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.victim uncore cache WBQ Rejects; Victim event=0x29,umask=0x10 01 Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxr_busy_starved.ad_bnc uncore cache Transgress Injection Starvation; AD - Bounce event=0xb4,umask=0x1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.ad_crd uncore cache Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_bnc uncore cache Transgress Injection Starvation; BL - Bounce event=0xb4,umask=0x4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_crd uncore cache Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_bypass.ad_bnc uncore cache Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=0x1 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ad_crd uncore cache Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ak_bnc uncore cache Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=0x2 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_bnc uncore cache Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=0x4 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_crd uncore cache Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.iv_bnc uncore cache Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=0x8 01 Number of packets bypassing the CMS Ingress unc_cha_rxr_crd_starved.ad_bnc uncore cache Transgress Injection Starvation; AD - Bounce event=0xb3,umask=0x1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ad_crd uncore cache Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ak_bnc uncore cache Transgress Injection Starvation; AK - Bounce event=0xb3,umask=0x2 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_bnc uncore cache Transgress Injection Starvation; BL - Bounce event=0xb3,umask=0x4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_crd uncore cache Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ifv uncore cache Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.iv_bnc uncore cache Transgress Injection Starvation; IV - Bounce event=0xb3,umask=0x8 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_inserts.ad_bnc uncore cache Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=0x1 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ad_crd uncore cache Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ak_bnc uncore cache Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=0x2 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_bnc uncore cache Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=0x4 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_crd uncore cache Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.iv_bnc uncore cache Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=0x8 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_bnc uncore cache Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=0x1 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_crd uncore cache Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ak_bnc uncore cache Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=0x2 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_bnc uncore cache Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=0x4 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_crd uncore cache Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.iv_bnc uncore cache Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=0x8 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_sf_eviction.e_state uncore cache Snoop filter capacity evictions for E-state entries event=0x3d,umask=0x2 01 Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.m_state uncore cache Snoop filter capacity evictions for M-state entries event=0x3d,umask=0x1 01 Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.s_state uncore cache Snoop filter capacity evictions for S-state entries event=0x3d,umask=0x4 01 Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_snoops_sent.all uncore cache Snoops Sent; All event=0x51,umask=0x1 01 Counts the number of snoops issued by the HA unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent; Broadcast snoop for Local Requests event=0x51,umask=0x10 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent; Broadcast snoops for Remote Requests event=0x51,umask=0x20 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets unc_cha_snoops_sent.direct_local uncore cache Snoops Sent; Directed snoops for Local Requests event=0x51,umask=0x40 01 Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent; Directed snoops for Remote Requests event=0x51,umask=0x80 01 Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets unc_cha_snoops_sent.local uncore cache Snoops Sent; Broadcast or directed Snoops sent for Local Requests event=0x51,umask=0x4 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket unc_cha_snoops_sent.remote uncore cache Snoops Sent; Broadcast or directed Snoops sent for Remote Requests event=0x51,umask=0x8 01 Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket unc_cha_snoop_resp.rspcnflcts uncore cache RspCnflct* Snoop Responses Received event=0x5c,umask=0x40 01 Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI unc_cha_snoop_resp.rspfwd uncore cache Snoop Responses Received; RspFwd event=0x5c,umask=0x80 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp.rspi uncore cache RspI Snoop Responses Received event=0x5c,umask=0x1 01 Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) unc_cha_snoop_resp.rspifwd uncore cache RspIFwd Snoop Responses Received event=0x5c,umask=0x4 01 Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states unc_cha_snoop_resp.rsps uncore cache Snoop Responses Received : RspS event=0x5c,umask=0x2 01 Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp.rspsfwd uncore cache RspSFwd Snoop Responses Received event=0x5c,umask=0x8 01 Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state unc_cha_snoop_resp.rsp_fwd_wb uncore cache Rsp*Fwd*WB Snoop Responses Received event=0x5c,umask=0x20 01 Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory unc_cha_snoop_resp.rsp_wbwb uncore cache Rsp*WB Snoop Responses Received event=0x5c,umask=0x10 01 Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership unc_cha_snoop_resp_local.rspcnflct uncore cache Snoop Responses Received Local; RspCnflct event=0x5d,umask=0x40 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp_local.rspfwd uncore cache Snoop Responses Received Local; RspFwd event=0x5d,umask=0x80 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp_local.rspi uncore cache Snoop Responses Received Local; RspI event=0x5d,umask=0x1 01 Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_cha_snoop_resp_local.rspifwd uncore cache Snoop Responses Received Local; RspIFwd event=0x5d,umask=0x4 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_cha_snoop_resp_local.rsps uncore cache Snoop Responses Received Local; RspS event=0x5d,umask=0x2 01 Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x5d,umask=0x8 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_cha_snoop_resp_local.rsp_fwd_wb uncore cache Snoop Responses Received Local; Rsp*FWD*WB event=0x5d,umask=0x20 01 Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp_local.rsp_wb uncore cache Snoop Responses Received Local; Rsp*WB event=0x5d,umask=0x10 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=0x1 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=0x2 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=0x4 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=0x8 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=0x1 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=0x2 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=0x4 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=0x8 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=0x1 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=0x2 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=0x4 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=0x8 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=0x1 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=0x2 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=0x4 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=0x8 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_tor_inserts.all uncore cache TOR Inserts; All event=0x35,umask=0xff 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.all_hit uncore cache TOR Inserts; Hits from Local event=0x35,umask=0x15 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.all_io_ia uncore cache TOR Inserts; All from Local iA and IO event=0x35,umask=0x35 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests unc_cha_tor_inserts.all_miss uncore cache TOR Inserts; Misses from Local event=0x35,umask=0x25 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.evict uncore cache TOR Inserts; SF/LLC Evictions event=0x35,umask=0x2 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts; Hit (Not a Miss) event=0x35,umask=0x10 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true) unc_cha_tor_inserts.ia uncore cache TOR Inserts; All from Local iA event=0x35,umask=0x31 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts; Hits from Local iA event=0x35,umask=0x11 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts : CRds issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x40233 01 TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts : DRds issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x40433 01 TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcrd uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD event=0x35,umask=0x11,config1=0x4b233 01 unc_cha_tor_inserts.ia_hit_llcprefdrd uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD event=0x35,umask=0x11,config1=0x4b433 01 unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC event=0x35,umask=0x11,config1=0x4b033 01 TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x40033 01 TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts : All requests from iA Cores that Missed the LLC event=0x35,umask=0x21 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts : CRds issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x40233 01 TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x40433 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcrd uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD event=0x35,umask=0x21,config1=0x4b233 01 unc_cha_tor_inserts.ia_miss_llcprefdrd uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD event=0x35,umask=0x21,config1=0x4b433 01 unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC event=0x35,umask=0x21,config1=0x4b033 01 TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x40033 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts; All from Local IO event=0x35,umask=0x34 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic unc_cha_tor_inserts.io_hit uncore cache TOR Inserts; Hits from Local IO event=0x35,umask=0x14 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.io_miss uncore cache TOR Inserts; Misses from Local IO event=0x35,umask=0x24 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts; ItoM misses from Local IO event=0x35,umask=0x24,config1=0x49033 01 Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership unc_cha_tor_inserts.io_miss_rdcur uncore cache TOR Inserts; RdCur misses from Local IO event=0x35,umask=0x24,config1=0x43C33 01 Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts; RFO misses from Local IO event=0x35,umask=0x24,config1=0x40033 01 Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify unc_cha_tor_inserts.ipq uncore cache TOR Inserts; IPQ event=0x35,umask=0x8 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ipq_hit uncore cache This event is deprecated event=0x35,umask=0x18 11 unc_cha_tor_inserts.ipq_miss uncore cache This event is deprecated event=0x35,umask=0x28 11 unc_cha_tor_inserts.irq uncore cache TOR Inserts; IRQ event=0x35,umask=0x1 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.loc_all uncore cache This event is deprecated event=0x35,umask=0x37 11 unc_cha_tor_inserts.miss uncore cache TOR Inserts; Miss event=0x35,umask=0x20 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com unc_cha_tor_inserts.prq uncore cache TOR Inserts; PRQ event=0x35,umask=0x4 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rem_all uncore cache This event is deprecated event=0x35,umask=0x30 11 unc_cha_tor_inserts.rrq_hit uncore cache This event is deprecated event=0x35,umask=0x50 11 unc_cha_tor_inserts.rrq_miss uncore cache This event is deprecated event=0x35,umask=0x60 11 unc_cha_tor_inserts.wbq_hit uncore cache This event is deprecated event=0x35,umask=0x90 11 unc_cha_tor_inserts.wbq_miss uncore cache This event is deprecated event=0x35,umask=0xa0 11 unc_cha_tor_occupancy.all uncore cache TOR Occupancy : All event=0x36,umask=0xff 01 TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.all_from_loc uncore cache TOR Occupancy; All from Local event=0x36,umask=0x37 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests unc_cha_tor_occupancy.all_hit uncore cache TOR Occupancy; Hits from Local event=0x36,umask=0x17 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.all_miss uncore cache TOR Occupancy; Misses from Local event=0x36,umask=0x27 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.evict uncore cache TOR Occupancy; SF/LLC Evictions event=0x36,umask=0x2 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy; Hit (Not a Miss) event=0x36,umask=0x10 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true) unc_cha_tor_occupancy.ia uncore cache TOR Occupancy; All from Local iA event=0x36,umask=0x31 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy; Hits from Local iA event=0x36,umask=0x11 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x40233 01 TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x40433 01 TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD event=0x36,umask=0x11,config1=0x4b233 01 unc_cha_tor_occupancy.ia_hit_llcprefdrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD event=0x36,umask=0x11,config1=0x4b433 01 unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC event=0x36,umask=0x11,config1=0x4b033 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x40033 01 TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy; Misses from Local iA event=0x36,umask=0x21 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x40233 01 TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x40433 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefcrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD event=0x36,umask=0x21,config1=0x4b233 01 unc_cha_tor_occupancy.ia_miss_llcprefdrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD event=0x36,umask=0x21,config1=0x4b433 01 unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC event=0x36,umask=0x21,config1=0x4b033 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x40033 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy; All from Local IO event=0x36,umask=0x34 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy; Hits from Local IO event=0x36,umask=0x14 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy; Misses from Local IO event=0x36,umask=0x24 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy; ITOM Misses from Local IO event=0x36,umask=0x24,config1=0x49033 01 For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership unc_cha_tor_occupancy.io_miss_rdcur uncore cache TOR Occupancy; RDCUR misses from Local IO event=0x36,umask=0x24,config1=0x43C33 01 For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy; RFO misses from Local IO event=0x36,umask=0x24,config1=0x40033 01 For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy; IPQ event=0x36,umask=0x8 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ipq_hit uncore cache This event is deprecated event=0x36,umask=0x18 11 unc_cha_tor_occupancy.ipq_miss uncore cache This event is deprecated event=0x36,umask=0x28 11 unc_cha_tor_occupancy.irq uncore cache TOR Occupancy; IRQ event=0x36,umask=0x1 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.loc_all uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC event=0x36,umask=0x37 11 unc_cha_tor_occupancy.miss uncore cache TOR Occupancy; Miss event=0x36,umask=0x20 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com unc_cha_tor_occupancy.prq uncore cache TOR Occupancy; PRQ event=0x36,umask=0x4 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_txr_horz_ads_used.ad_bnc uncore cache CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=0x1 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ad_crd uncore cache CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ak_bnc uncore cache CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=0x2 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_bnc uncore cache CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=0x4 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_crd uncore cache CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_bnc uncore cache CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=0x1 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_crd uncore cache CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ak_bnc uncore cache CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=0x2 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_bnc uncore cache CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=0x4 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_crd uncore cache CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.iv_bnc uncore cache CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=0x8 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_cycles_full.ad_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=0x1 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ak_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=0x2 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=0x4 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.iv_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=0x8 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=0x1 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ak_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=0x2 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=0x4 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.iv_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=0x8 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_bnc uncore cache CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=0x1 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_crd uncore cache CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ak_bnc uncore cache CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=0x2 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_bnc uncore cache CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=0x4 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_crd uncore cache CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.iv_bnc uncore cache CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=0x8 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_nack.ad_bnc uncore cache CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=0x1 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ad_crd uncore cache CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ak_bnc uncore cache CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=0x2 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_bnc uncore cache CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=0x4 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_crd uncore cache CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.iv_bnc uncore cache CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=0x8 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_occupancy.ad_bnc uncore cache CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=0x1 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ad_crd uncore cache CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ak_bnc uncore cache CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=0x2 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_bnc uncore cache CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=0x4 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_crd uncore cache CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.iv_bnc uncore cache CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=0x8 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_starved.ad_bnc uncore cache CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=0x1 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.ak_bnc uncore cache CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=0x2 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.bl_bnc uncore cache CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=0x4 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.iv_bnc uncore cache CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=0x8 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=0x1 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ak_ag0 uncore cache CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=0x2 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ak_ag1 uncore cache CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=0x4 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag0 uncore cache CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=0x1 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag1 uncore cache CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag0 uncore cache CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=0x2 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag1 uncore cache CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag0 uncore cache CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=0x4 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag1 uncore cache CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.iv uncore cache CMS Vertical ADS Used; IV event=0x9e,umask=0x8 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_cycles_full.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=0x1 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_full.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=0x2 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_full.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_full.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=0x4 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_full.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_full.iv uncore cache Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=0x8 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_ne.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=0x1 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_ne.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=0x2 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_ne.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=0x4 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_ne.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_ne.iv uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=0x8 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_inserts.ad_ag0 uncore cache CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=0x1 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts.ad_ag1 uncore cache CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_inserts.ak_ag0 uncore cache CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=0x2 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts.ak_ag1 uncore cache CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_inserts.bl_ag0 uncore cache CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=0x4 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_inserts.bl_ag1 uncore cache CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_inserts.iv uncore cache CMS Vert Egress Allocations; IV event=0x91,umask=0x8 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_nack.ad_ag0 uncore cache CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=0x1 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ad_ag1 uncore cache CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ak_ag0 uncore cache CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=0x2 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ak_ag1 uncore cache CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.bl_ag0 uncore cache CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=0x4 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.bl_ag1 uncore cache CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.iv uncore cache CMS Vertical Egress NACKs; IV event=0x98,umask=0x8 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_occupancy.ad_ag0 uncore cache CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=0x1 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy.ad_ag1 uncore cache CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_occupancy.ak_ag0 uncore cache CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=0x2 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_occupancy.ak_ag1 uncore cache CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_occupancy.bl_ag0 uncore cache CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=0x4 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_occupancy.bl_ag1 uncore cache CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_occupancy.iv uncore cache CMS Vert Egress Occupancy; IV event=0x90,umask=0x8 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_starved.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=0x1 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=0x2 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=0x4 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.iv uncore cache CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=0x8 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_upi_credits_acquired.ad_req uncore cache UPI Ingress Credit Allocations; AD REQ Credits event=0x38,umask=0x4 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.ad_rsp uncore cache UPI Ingress Credit Allocations; AD RSP VN0 Credits event=0x38,umask=0x8 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_ncb uncore cache UPI Ingress Credit Allocations; BL NCB Credits event=0x38,umask=0x40 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_ncs uncore cache UPI Ingress Credit Allocations; BL NCS Credits event=0x38,umask=0x80 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_rsp uncore cache UPI Ingress Credit Allocations; BL RSP Credits event=0x38,umask=0x10 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_wb uncore cache UPI Ingress Credit Allocations; BL DRS Credits event=0x38,umask=0x20 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.vn0 uncore cache UPI Ingress Credit Allocations; VN0 Credits event=0x38,umask=0x2 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.vna uncore cache UPI Ingress Credit Allocations; VNA Credits event=0x38,umask=0x1 01 Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_ad_req uncore cache UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits event=0x3b,umask=0x4 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_ad_rsp uncore cache UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits event=0x3b,umask=0x8 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_ncb uncore cache UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits event=0x3b,umask=0x40 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_ncs uncore cache UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits event=0x3b,umask=0x80 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_rsp uncore cache UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits event=0x3b,umask=0x10 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_wb uncore cache UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits event=0x3b,umask=0x20 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vna_ad uncore cache UPI Ingress Credits In Use Cycles; AD VNA Credits event=0x3b,umask=0x1 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vna_bl uncore cache UPI Ingress Credits In Use Cycles; BL VNA Credits event=0x3b,umask=0x2 01 Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_vert_ring_ad_in_use.dn_even uncore cache Vertical AD Ring In Use; Down and Even event=0xa6,umask=0x4 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.dn_odd uncore cache Vertical AD Ring In Use; Down and Odd event=0xa6,umask=0x8 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_even uncore cache Vertical AD Ring In Use; Up and Even event=0xa6,umask=0x1 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_odd uncore cache Vertical AD Ring In Use; Up and Odd event=0xa6,umask=0x2 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_even uncore cache Vertical AK Ring In Use; Down and Even event=0xa8,umask=0x4 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_odd uncore cache Vertical AK Ring In Use; Down and Odd event=0xa8,umask=0x8 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_even uncore cache Vertical AK Ring In Use; Up and Even event=0xa8,umask=0x1 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_odd uncore cache Vertical AK Ring In Use; Up and Odd event=0xa8,umask=0x2 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_even uncore cache Vertical BL Ring in Use; Down and Even event=0xaa,umask=0x4 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_odd uncore cache Vertical BL Ring in Use; Down and Odd event=0xaa,umask=0x8 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_even uncore cache Vertical BL Ring in Use; Up and Even event=0xaa,umask=0x1 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_odd uncore cache Vertical BL Ring in Use; Up and Odd event=0xaa,umask=0x2 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_iv_in_use.dn uncore cache Vertical IV Ring in Use; Down event=0xac,umask=0x4 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_iv_in_use.up uncore cache Vertical IV Ring in Use; Up event=0xac,umask=0x1 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_wb_push_mtoi.llc uncore cache WbPushMtoI; Pushed to LLC event=0x56,umask=0x1 01 Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC unc_cha_wb_push_mtoi.mem uncore cache WbPushMtoI; Pushed to Memory event=0x56,umask=0x2 01 Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM) unc_cha_write_no_credits.edc0_smi2 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2 event=0x5a,umask=0x4 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only unc_cha_write_no_credits.edc1_smi3 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3 event=0x5a,umask=0x8 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only unc_cha_write_no_credits.edc2_smi4 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4 event=0x5a,umask=0x10 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only unc_cha_write_no_credits.edc3_smi5 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5 event=0x5a,umask=0x20 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only unc_cha_write_no_credits.mc0_smi0 uncore cache CHA iMC CHNx WRITE Credits Empty; MC0_SMI0 event=0x5a,umask=0x1 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only unc_cha_write_no_credits.mc1_smi1 uncore cache CHA iMC CHNx WRITE Credits Empty; MC1_SMI1 event=0x5a,umask=0x2 01 Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only unc_cha_xsnp_resp.any_rspi_fwdfe uncore cache Core Cross Snoop Responses; Any RspIFwdFE event=0x32,umask=0xe4 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E unc_cha_xsnp_resp.any_rspi_fwdm uncore cache Core Cross Snoop Responses event=0x32,umask=0xf0 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M unc_cha_xsnp_resp.any_rsps_fwdfe uncore cache Core Cross Snoop Responses; Any RspSFwdFE event=0x32,umask=0xe2 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E unc_cha_xsnp_resp.any_rsps_fwdm uncore cache Core Cross Snoop Responses; Any RspSFwdM event=0x32,umask=0xe8 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M unc_cha_xsnp_resp.any_rsp_hitfse uncore cache Core Cross Snoop Responses; Any RspHitFSE event=0x32,umask=0xe1 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E unc_cha_xsnp_resp.core_rspi_fwdfe uncore cache Core Cross Snoop Responses; Core RspIFwdFE event=0x32,umask=0x44 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E unc_cha_xsnp_resp.core_rspi_fwdm uncore cache Core Cross Snoop Responses; Core RspIFwdM event=0x32,umask=0x50 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M unc_cha_xsnp_resp.core_rsps_fwdfe uncore cache Core Cross Snoop Responses; Core RspSFwdFE event=0x32,umask=0x42 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E unc_cha_xsnp_resp.core_rsps_fwdm uncore cache Core Cross Snoop Responses; Core RspSFwdM event=0x32,umask=0x48 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M unc_cha_xsnp_resp.core_rsp_hitfse uncore cache Core Cross Snoop Responses; Core RspHitFSE event=0x32,umask=0x41 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E unc_cha_xsnp_resp.evict_rspi_fwdfe uncore cache Core Cross Snoop Responses; Evict RspIFwdFE event=0x32,umask=0x84 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E unc_cha_xsnp_resp.evict_rspi_fwdm uncore cache Core Cross Snoop Responses; Evict RspIFwdM event=0x32,umask=0x90 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M unc_cha_xsnp_resp.evict_rsps_fwdfe uncore cache Core Cross Snoop Responses; Evict RspSFwdFE event=0x32,umask=0x82 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E unc_cha_xsnp_resp.evict_rsps_fwdm uncore cache Core Cross Snoop Responses; Evict RspSFwdM event=0x32,umask=0x88 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M unc_cha_xsnp_resp.evict_rsp_hitfse uncore cache Core Cross Snoop Responses; Evict RspHitFSE event=0x32,umask=0x81 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E unc_cha_xsnp_resp.ext_rspi_fwdfe uncore cache Core Cross Snoop Responses; External RspIFwdFE event=0x32,umask=0x24 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E unc_cha_xsnp_resp.ext_rspi_fwdm uncore cache Core Cross Snoop Responses; External RspIFwdM event=0x32,umask=0x30 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M unc_cha_xsnp_resp.ext_rsps_fwdfe uncore cache Core Cross Snoop Responses; External RspSFwdFE event=0x32,umask=0x22 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E unc_cha_xsnp_resp.ext_rsps_fwdm uncore cache Core Cross Snoop Responses; External RspSFwdM event=0x32,umask=0x28 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M unc_cha_xsnp_resp.ext_rsp_hitfse uncore cache Core Cross Snoop Responses; External RspHitFSE event=0x32,umask=0x21 01 Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E unc_c_clockticks uncore cache This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS event=0 11 unc_c_fast_asserted uncore cache This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ event=0xa5,umask=0x2 11 unc_c_llc_lookup.any uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY event=0x34,umask=0x11 11 unc_c_llc_lookup.data_read uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ event=0x34,umask=0x3 11 unc_c_llc_lookup.local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL event=0x34,umask=0x31 11 unc_c_llc_lookup.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE event=0x34,umask=0x91 11 unc_c_llc_lookup.remote_snoop uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP event=0x34,umask=0x9 11 unc_c_llc_lookup.write uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE event=0x34,umask=0x5 11 unc_c_llc_victims.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E event=0x37,umask=0x2 11 unc_c_llc_victims.f_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F event=0x37,umask=0x8 11 unc_c_llc_victims.local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL event=0x37,umask=0x2f 11 unc_c_llc_victims.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M event=0x37,umask=0x1 11 unc_c_llc_victims.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL event=0x37,umask=0x80 11 unc_c_llc_victims.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S event=0x37,umask=0x4 11 unc_c_ring_src_thrtl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL event=0xa4 11 unc_c_tor_inserts.evict uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT event=0x35,umask=0x2 11 unc_c_tor_inserts.hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT event=0x35,umask=0x10 11 unc_c_tor_inserts.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ event=0x35,umask=0x8 11 unc_c_tor_inserts.ipq_hit uncore cache This event is deprecated event=0x35,umask=0x18 11 unc_c_tor_inserts.ipq_miss uncore cache This event is deprecated event=0x35,umask=0x28 11 unc_c_tor_inserts.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA event=0x35,umask=0x31 11 unc_c_tor_inserts.irq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT event=0x35,umask=0x11 11 unc_c_tor_inserts.irq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS event=0x35,umask=0x21 11 unc_c_tor_inserts.loc_all uncore cache This event is deprecated event=0x35,umask=0x37 11 unc_c_tor_inserts.loc_ia uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA event=0x35,umask=0x31 11 unc_c_tor_inserts.loc_io uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO event=0x35,umask=0x34 11 unc_c_tor_inserts.miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS event=0x35,umask=0x20 11 unc_c_tor_inserts.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ event=0x35,umask=0x4 11 unc_c_tor_inserts.prq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT event=0x35,umask=0x14 11 unc_c_tor_inserts.prq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS event=0x35,umask=0x24 11 unc_c_tor_inserts.rem_all uncore cache This event is deprecated event=0x35,umask=0x30 11 unc_c_tor_inserts.rrq_hit uncore cache This event is deprecated event=0x35,umask=0x50 11 unc_c_tor_inserts.rrq_miss uncore cache This event is deprecated event=0x35,umask=0x60 11 unc_c_tor_inserts.wbq_hit uncore cache This event is deprecated event=0x35,umask=0x90 11 unc_c_tor_inserts.wbq_miss uncore cache This event is deprecated event=0x35,umask=0xa0 11 unc_c_tor_occupancy.evict uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT event=0x36,umask=0x2 11 unc_c_tor_occupancy.hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT event=0x36,umask=0x10 11 unc_c_tor_occupancy.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ event=0x36,umask=0x8 11 unc_c_tor_occupancy.ipq_hit uncore cache This event is deprecated event=0x36,umask=0x18 11 unc_c_tor_occupancy.ipq_miss uncore cache This event is deprecated event=0x36,umask=0x28 11 unc_c_tor_occupancy.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA event=0x36,umask=0x31 11 unc_c_tor_occupancy.irq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT event=0x36,umask=0x11 11 unc_c_tor_occupancy.irq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS event=0x36,umask=0x21 11 unc_c_tor_occupancy.loc_all uncore cache This event is deprecated event=0x36,umask=0x37 11 unc_c_tor_occupancy.loc_ia uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA event=0x36,umask=0x31 11 unc_c_tor_occupancy.loc_io uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO event=0x36,umask=0x34 11 unc_c_tor_occupancy.miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS event=0x36,umask=0x20 11 unc_c_tor_occupancy.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ event=0x36,umask=0x4 11 unc_c_tor_occupancy.prq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT event=0x36,umask=0x14 11 unc_c_tor_occupancy.prq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS event=0x36,umask=0x24 11 unc_h_ag0_ad_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0 event=0x80,umask=0x1 11 unc_h_ag0_ad_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1 event=0x80,umask=0x2 11 unc_h_ag0_ad_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2 event=0x80,umask=0x4 11 unc_h_ag0_ad_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3 event=0x80,umask=0x8 11 unc_h_ag0_ad_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4 event=0x80,umask=0x10 11 unc_h_ag0_ad_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5 event=0x80,umask=0x20 11 unc_h_ag0_ad_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0 event=0x82,umask=0x1 11 unc_h_ag0_ad_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1 event=0x82,umask=0x2 11 unc_h_ag0_ad_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2 event=0x82,umask=0x4 11 unc_h_ag0_ad_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3 event=0x82,umask=0x8 11 unc_h_ag0_ad_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4 event=0x82,umask=0x10 11 unc_h_ag0_ad_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5 event=0x82,umask=0x20 11 unc_h_ag0_bl_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0 event=0x88,umask=0x1 11 unc_h_ag0_bl_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1 event=0x88,umask=0x2 11 unc_h_ag0_bl_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2 event=0x88,umask=0x4 11 unc_h_ag0_bl_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3 event=0x88,umask=0x8 11 unc_h_ag0_bl_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4 event=0x88,umask=0x10 11 unc_h_ag0_bl_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5 event=0x88,umask=0x20 11 unc_h_ag0_bl_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0 event=0x8a,umask=0x1 11 unc_h_ag0_bl_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1 event=0x8a,umask=0x2 11 unc_h_ag0_bl_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2 event=0x8a,umask=0x4 11 unc_h_ag0_bl_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3 event=0x8a,umask=0x8 11 unc_h_ag0_bl_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4 event=0x8a,umask=0x10 11 unc_h_ag0_bl_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5 event=0x8a,umask=0x20 11 unc_h_ag1_ad_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0 event=0x84,umask=0x1 11 unc_h_ag1_ad_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1 event=0x84,umask=0x2 11 unc_h_ag1_ad_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2 event=0x84,umask=0x4 11 unc_h_ag1_ad_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3 event=0x84,umask=0x8 11 unc_h_ag1_ad_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4 event=0x84,umask=0x10 11 unc_h_ag1_ad_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5 event=0x84,umask=0x20 11 unc_h_ag1_ad_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0 event=0x86,umask=0x1 11 unc_h_ag1_ad_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1 event=0x86,umask=0x2 11 unc_h_ag1_ad_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2 event=0x86,umask=0x4 11 unc_h_ag1_ad_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3 event=0x86,umask=0x8 11 unc_h_ag1_ad_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4 event=0x86,umask=0x10 11 unc_h_ag1_ad_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5 event=0x86,umask=0x20 11 unc_h_ag1_bl_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0 event=0x8e,umask=0x1 11 unc_h_ag1_bl_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1 event=0x8e,umask=0x2 11 unc_h_ag1_bl_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2 event=0x8e,umask=0x4 11 unc_h_ag1_bl_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3 event=0x8e,umask=0x8 11 unc_h_ag1_bl_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4 event=0x8e,umask=0x10 11 unc_h_ag1_bl_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5 event=0x8e,umask=0x20 11 unc_h_ag1_bl_credits_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0 event=0x8c,umask=0x1 11 unc_h_ag1_bl_credits_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1 event=0x8c,umask=0x2 11 unc_h_ag1_bl_credits_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2 event=0x8c,umask=0x4 11 unc_h_ag1_bl_credits_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3 event=0x8c,umask=0x8 11 unc_h_ag1_bl_credits_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4 event=0x8c,umask=0x10 11 unc_h_ag1_bl_credits_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5 event=0x8c,umask=0x20 11 unc_h_bypass_cha_imc.intermediate uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE event=0x57,umask=0x2 11 unc_h_bypass_cha_imc.not_taken uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN event=0x57,umask=0x4 11 unc_h_bypass_cha_imc.taken uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN event=0x57,umask=0x1 11 unc_h_clock uncore cache This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS event=0xc0 11 unc_h_core_pma.c1_state uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE event=0x17,umask=0x1 11 unc_h_core_pma.c1_transition uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION event=0x17,umask=0x2 11 unc_h_core_pma.c6_state uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE event=0x17,umask=0x4 11 unc_h_core_pma.c6_transition uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION event=0x17,umask=0x8 11 unc_h_core_pma.gv uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV event=0x17,umask=0x10 11 unc_h_core_snp.any_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE event=0x33,umask=0xe2 11 unc_h_core_snp.any_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE event=0x33,umask=0xe1 11 unc_h_core_snp.any_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE event=0x33,umask=0xe4 11 unc_h_core_snp.core_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE event=0x33,umask=0x42 11 unc_h_core_snp.core_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE event=0x33,umask=0x41 11 unc_h_core_snp.core_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE event=0x33,umask=0x44 11 unc_h_core_snp.evict_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE event=0x33,umask=0x82 11 unc_h_core_snp.evict_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE event=0x33,umask=0x81 11 unc_h_core_snp.evict_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE event=0x33,umask=0x84 11 unc_h_core_snp.ext_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE event=0x33,umask=0x22 11 unc_h_core_snp.ext_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE event=0x33,umask=0x21 11 unc_h_core_snp.ext_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE event=0x33,umask=0x24 11 unc_h_counter0_occupancy uncore cache This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY event=0x1f 11 unc_h_dir_lookup.no_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP event=0x53,umask=0x2 11 unc_h_dir_lookup.snp uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP event=0x53,umask=0x1 11 unc_h_dir_update.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA event=0x54,umask=0x1 11 unc_h_dir_update.tor uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR event=0x54,umask=0x2 11 unc_h_egress_ordering.iv_snoopgo_dn uncore cache This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN event=0xae,umask=0x4 11 unc_h_egress_ordering.iv_snoopgo_up uncore cache This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP event=0xae,umask=0x1 11 unc_h_hitme_hit.ex_rds uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS event=0x5f,umask=0x1 11 unc_h_hitme_hit.shared_ownreq uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ event=0x5f,umask=0x4 11 unc_h_hitme_hit.wbmtoe uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE event=0x5f,umask=0x8 11 unc_h_hitme_hit.wbmtoi_or_s uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S event=0x5f,umask=0x10 11 unc_h_hitme_lookup.read uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ event=0x5e,umask=0x1 11 unc_h_hitme_lookup.write uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE event=0x5e,umask=0x2 11 unc_h_hitme_miss.notshared_rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN event=0x60,umask=0x40 11 unc_h_hitme_miss.read_or_inv uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV event=0x60,umask=0x80 11 unc_h_hitme_miss.shared_rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN event=0x60,umask=0x20 11 unc_h_hitme_update.deallocate uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE event=0x61,umask=0x10 11 unc_h_hitme_update.deallocate_rspfwdi_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC event=0x61,umask=0x1 11 unc_h_hitme_update.rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN event=0x61,umask=0x8 11 unc_h_hitme_update.rspfwdi_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM event=0x61,umask=0x2 11 unc_h_hitme_update.shared uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED event=0x61,umask=0x4 11 unc_h_horz_ring_ad_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN event=0xa7,umask=0x1 11 unc_h_horz_ring_ad_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD event=0xa7,umask=0x2 11 unc_h_horz_ring_ad_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN event=0xa7,umask=0x4 11 unc_h_horz_ring_ad_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD event=0xa7,umask=0x8 11 unc_h_horz_ring_ak_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN event=0xa9,umask=0x1 11 unc_h_horz_ring_ak_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD event=0xa9,umask=0x2 11 unc_h_horz_ring_ak_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN event=0xa9,umask=0x4 11 unc_h_horz_ring_ak_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD event=0xa9,umask=0x8 11 unc_h_horz_ring_bl_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN event=0xab,umask=0x1 11 unc_h_horz_ring_bl_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD event=0xab,umask=0x2 11 unc_h_horz_ring_bl_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN event=0xab,umask=0x4 11 unc_h_horz_ring_bl_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD event=0xab,umask=0x8 11 unc_h_horz_ring_iv_in_use.left uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT event=0xad,umask=0x1 11 unc_h_horz_ring_iv_in_use.right uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT event=0xad,umask=0x4 11 unc_h_imc_reads_count.normal uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL event=0x59,umask=0x1 11 unc_h_imc_reads_count.priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY event=0x59,umask=0x2 11 unc_h_imc_writes_count.full uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL event=0x5b,umask=0x1 11 unc_h_imc_writes_count.full_mig uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG event=0x5b,umask=0x10 11 unc_h_imc_writes_count.full_priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY event=0x5b,umask=0x4 11 unc_h_imc_writes_count.partial uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL event=0x5b,umask=0x2 11 unc_h_imc_writes_count.partial_mig uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG event=0x5b,umask=0x20 11 unc_h_imc_writes_count.partial_priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY event=0x5b,umask=0x8 11 unc_h_iodc_alloc.invitom uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM event=0x62,umask=0x1 11 unc_h_iodc_alloc.iodcfull uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL event=0x62,umask=0x2 11 unc_h_iodc_alloc.osbgated uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED event=0x62,umask=0x4 11 unc_h_iodc_dealloc.all uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL event=0x63,umask=0x10 11 unc_h_iodc_dealloc.snpout uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT event=0x63,umask=0x8 11 unc_h_iodc_dealloc.wbmtoe uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE event=0x63,umask=0x1 11 unc_h_iodc_dealloc.wbmtoi uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI event=0x63,umask=0x2 11 unc_h_iodc_dealloc.wbpushmtoi uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI event=0x63,umask=0x4 11 unc_h_misc.cv0_pref_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS event=0x39,umask=0x20 11 unc_h_misc.cv0_pref_vic uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC event=0x39,umask=0x10 11 unc_h_misc.rfo_hit_s uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S event=0x39,umask=0x8 11 unc_h_misc.rspi_was_fse uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE event=0x39,umask=0x1 11 unc_h_misc.wc_aliasing uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING event=0x39,umask=0x2 11 unc_h_osb uncore cache This event is deprecated. Refer to new event UNC_CHA_OSB event=0x55 11 unc_h_read_no_credits.edc0_smi2 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2 event=0x58,umask=0x4 11 unc_h_read_no_credits.edc1_smi3 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3 event=0x58,umask=0x8 11 unc_h_read_no_credits.edc2_smi4 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4 event=0x58,umask=0x10 11 unc_h_read_no_credits.edc3_smi5 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5 event=0x58,umask=0x20 11 unc_h_read_no_credits.mc0_smi0 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0 event=0x58,umask=0x1 11 unc_h_read_no_credits.mc1_smi1 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1 event=0x58,umask=0x2 11 unc_h_requests.invitoe_local uncore cache This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL event=0x50,umask=0x10 11 unc_h_requests.invitoe_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE event=0x50,umask=0x20 11 unc_h_requests.reads uncore cache read requests from home agent event=0x50,umask=0x3 11 unc_h_requests.reads_local uncore cache read requests from local home agent event=0x50,umask=0x1 11 unc_h_requests.reads_remote uncore cache read requests from remote home agent event=0x50,umask=0x2 11 unc_h_requests.writes uncore cache write requests from home agent event=0x50,umask=0xc 11 unc_h_requests.writes_local uncore cache write requests from local home agent event=0x50,umask=0x4 11 unc_h_requests.writes_remote uncore cache write requests from remote home agent event=0x50,umask=0x8 11 unc_h_ring_bounces_horz.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD event=0xa1,umask=0x1 11 unc_h_ring_bounces_horz.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK event=0xa1,umask=0x2 11 unc_h_ring_bounces_horz.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL event=0xa1,umask=0x4 11 unc_h_ring_bounces_horz.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV event=0xa1,umask=0x8 11 unc_h_ring_bounces_vert.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD event=0xa0,umask=0x1 11 unc_h_ring_bounces_vert.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK event=0xa0,umask=0x2 11 unc_h_ring_bounces_vert.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL event=0xa0,umask=0x4 11 unc_h_ring_bounces_vert.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV event=0xa0,umask=0x8 11 unc_h_ring_sink_starved_horz.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD event=0xa3,umask=0x1 11 unc_h_ring_sink_starved_horz.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK event=0xa3,umask=0x2 11 unc_h_ring_sink_starved_horz.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1 event=0xa3,umask=0x20 11 unc_h_ring_sink_starved_horz.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL event=0xa3,umask=0x4 11 unc_h_ring_sink_starved_horz.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV event=0xa3,umask=0x8 11 unc_h_ring_sink_starved_vert.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD event=0xa2,umask=0x1 11 unc_h_ring_sink_starved_vert.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK event=0xa2,umask=0x2 11 unc_h_ring_sink_starved_vert.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL event=0xa2,umask=0x4 11 unc_h_ring_sink_starved_vert.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV event=0xa2,umask=0x8 11 unc_h_rxc_inserts.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ event=0x13,umask=0x4 11 unc_h_rxc_inserts.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ event=0x13,umask=0x1 11 unc_h_rxc_inserts.irq_rej uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ event=0x13,umask=0x2 11 unc_h_rxc_inserts.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ event=0x13,umask=0x10 11 unc_h_rxc_inserts.prq_rej uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ event=0x13,umask=0x20 11 unc_h_rxc_inserts.rrq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ event=0x13,umask=0x40 11 unc_h_rxc_inserts.wbq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ event=0x13,umask=0x80 11 unc_h_rxc_ipq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0 event=0x22,umask=0x1 11 unc_h_rxc_ipq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0 event=0x22,umask=0x2 11 unc_h_rxc_ipq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0 event=0x22,umask=0x10 11 unc_h_rxc_ipq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0 event=0x22,umask=0x20 11 unc_h_rxc_ipq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0 event=0x22,umask=0x4 11 unc_h_rxc_ipq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0 event=0x22,umask=0x8 11 unc_h_rxc_ipq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP event=0x23,umask=0x40 11 unc_h_rxc_ipq1_reject.any_ipq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0 event=0x23,umask=0x1 11 unc_h_rxc_ipq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA event=0x23,umask=0x2 11 unc_h_rxc_ipq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY event=0x23,umask=0x20 11 unc_h_rxc_ipq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM event=0x23,umask=0x4 11 unc_h_rxc_ipq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH event=0x23,umask=0x80 11 unc_h_rxc_ipq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM event=0x23,umask=0x8 11 unc_h_rxc_ipq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM event=0x23,umask=0x10 11 unc_h_rxc_irq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0 event=0x18,umask=0x1 11 unc_h_rxc_irq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0 event=0x18,umask=0x2 11 unc_h_rxc_irq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0 event=0x18,umask=0x10 11 unc_h_rxc_irq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0 event=0x18,umask=0x20 11 unc_h_rxc_irq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0 event=0x18,umask=0x4 11 unc_h_rxc_irq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0 event=0x18,umask=0x8 11 unc_h_rxc_irq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP event=0x19,umask=0x40 11 unc_h_rxc_irq1_reject.any_reject_irq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0 event=0x19,umask=0x1 11 unc_h_rxc_irq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA event=0x19,umask=0x2 11 unc_h_rxc_irq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY event=0x19,umask=0x20 11 unc_h_rxc_irq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM event=0x19,umask=0x4 11 unc_h_rxc_irq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH event=0x19,umask=0x80 11 unc_h_rxc_irq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM event=0x19,umask=0x8 11 unc_h_rxc_irq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM event=0x19,umask=0x10 11 unc_h_rxc_ismq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0 event=0x24,umask=0x1 11 unc_h_rxc_ismq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0 event=0x24,umask=0x2 11 unc_h_rxc_ismq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0 event=0x24,umask=0x10 11 unc_h_rxc_ismq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0 event=0x24,umask=0x20 11 unc_h_rxc_ismq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0 event=0x24,umask=0x4 11 unc_h_rxc_ismq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0 event=0x24,umask=0x8 11 unc_h_rxc_ismq0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0 event=0x2c,umask=0x1 11 unc_h_rxc_ismq0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0 event=0x2c,umask=0x2 11 unc_h_rxc_ismq0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0 event=0x2c,umask=0x10 11 unc_h_rxc_ismq0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0 event=0x2c,umask=0x20 11 unc_h_rxc_ismq0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0 event=0x2c,umask=0x4 11 unc_h_rxc_ismq0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0 event=0x2c,umask=0x8 11 unc_h_rxc_ismq1_reject.any_ismq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0 event=0x25,umask=0x1 11 unc_h_rxc_ismq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA event=0x25,umask=0x2 11 unc_h_rxc_ismq1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0 event=0x2d,umask=0x1 11 unc_h_rxc_ismq1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA event=0x2d,umask=0x2 11 unc_h_rxc_occupancy.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ event=0x11,umask=0x4 11 unc_h_rxc_occupancy.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ event=0x11,umask=0x1 11 unc_h_rxc_occupancy.rrq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ event=0x11,umask=0x40 11 unc_h_rxc_occupancy.wbq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ event=0x11,umask=0x80 11 unc_h_rxc_other0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0 event=0x2e,umask=0x1 11 unc_h_rxc_other0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0 event=0x2e,umask=0x2 11 unc_h_rxc_other0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0 event=0x2e,umask=0x10 11 unc_h_rxc_other0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0 event=0x2e,umask=0x20 11 unc_h_rxc_other0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0 event=0x2e,umask=0x4 11 unc_h_rxc_other0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0 event=0x2e,umask=0x8 11 unc_h_rxc_other1_retry.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP event=0x2f,umask=0x40 11 unc_h_rxc_other1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0 event=0x2f,umask=0x1 11 unc_h_rxc_other1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA event=0x2f,umask=0x2 11 unc_h_rxc_other1_retry.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY event=0x2f,umask=0x20 11 unc_h_rxc_other1_retry.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM event=0x2f,umask=0x4 11 unc_h_rxc_other1_retry.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH event=0x2f,umask=0x80 11 unc_h_rxc_other1_retry.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM event=0x2f,umask=0x8 11 unc_h_rxc_other1_retry.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM event=0x2f,umask=0x10 11 unc_h_rxc_prq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0 event=0x20,umask=0x1 11 unc_h_rxc_prq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0 event=0x20,umask=0x2 11 unc_h_rxc_prq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0 event=0x20,umask=0x10 11 unc_h_rxc_prq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0 event=0x20,umask=0x20 11 unc_h_rxc_prq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0 event=0x20,umask=0x4 11 unc_h_rxc_prq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0 event=0x20,umask=0x8 11 unc_h_rxc_prq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP event=0x21,umask=0x40 11 unc_h_rxc_prq1_reject.any_prq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0 event=0x21,umask=0x1 11 unc_h_rxc_prq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA event=0x21,umask=0x2 11 unc_h_rxc_prq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY event=0x21,umask=0x20 11 unc_h_rxc_prq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM event=0x21,umask=0x4 11 unc_h_rxc_prq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH event=0x21,umask=0x80 11 unc_h_rxc_prq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM event=0x21,umask=0x8 11 unc_h_rxc_prq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM event=0x21,umask=0x10 11 unc_h_rxc_req_q0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0 event=0x2a,umask=0x1 11 unc_h_rxc_req_q0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0 event=0x2a,umask=0x2 11 unc_h_rxc_req_q0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0 event=0x2a,umask=0x10 11 unc_h_rxc_req_q0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0 event=0x2a,umask=0x20 11 unc_h_rxc_req_q0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0 event=0x2a,umask=0x4 11 unc_h_rxc_req_q0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0 event=0x2a,umask=0x8 11 unc_h_rxc_req_q1_retry.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP event=0x2b,umask=0x40 11 unc_h_rxc_req_q1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0 event=0x2b,umask=0x1 11 unc_h_rxc_req_q1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA event=0x2b,umask=0x2 11 unc_h_rxc_req_q1_retry.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY event=0x2b,umask=0x20 11 unc_h_rxc_req_q1_retry.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM event=0x2b,umask=0x4 11 unc_h_rxc_req_q1_retry.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH event=0x2b,umask=0x80 11 unc_h_rxc_req_q1_retry.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM event=0x2b,umask=0x8 11 unc_h_rxc_req_q1_retry.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM event=0x2b,umask=0x10 11 unc_h_rxc_rrq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0 event=0x26,umask=0x1 11 unc_h_rxc_rrq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0 event=0x26,umask=0x2 11 unc_h_rxc_rrq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0 event=0x26,umask=0x10 11 unc_h_rxc_rrq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0 event=0x26,umask=0x20 11 unc_h_rxc_rrq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0 event=0x26,umask=0x4 11 unc_h_rxc_rrq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0 event=0x26,umask=0x8 11 unc_h_rxc_rrq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP event=0x27,umask=0x40 11 unc_h_rxc_rrq1_reject.any_rrq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0 event=0x27,umask=0x1 11 unc_h_rxc_rrq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA event=0x27,umask=0x2 11 unc_h_rxc_rrq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY event=0x27,umask=0x20 11 unc_h_rxc_rrq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM event=0x27,umask=0x4 11 unc_h_rxc_rrq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH event=0x27,umask=0x80 11 unc_h_rxc_rrq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM event=0x27,umask=0x8 11 unc_h_rxc_rrq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM event=0x27,umask=0x10 11 unc_h_rxc_wbq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0 event=0x28,umask=0x1 11 unc_h_rxc_wbq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0 event=0x28,umask=0x2 11 unc_h_rxc_wbq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0 event=0x28,umask=0x10 11 unc_h_rxc_wbq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0 event=0x28,umask=0x20 11 unc_h_rxc_wbq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0 event=0x28,umask=0x4 11 unc_h_rxc_wbq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0 event=0x28,umask=0x8 11 unc_h_rxc_wbq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP event=0x29,umask=0x40 11 unc_h_rxc_wbq1_reject.any_wbq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0 event=0x29,umask=0x1 11 unc_h_rxc_wbq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA event=0x29,umask=0x2 11 unc_h_rxc_wbq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY event=0x29,umask=0x20 11 unc_h_rxc_wbq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM event=0x29,umask=0x4 11 unc_h_rxc_wbq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH event=0x29,umask=0x80 11 unc_h_rxc_wbq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM event=0x29,umask=0x8 11 unc_h_rxc_wbq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM event=0x29,umask=0x10 11 unc_h_rxr_busy_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC event=0xb4,umask=0x1 11 unc_h_rxr_busy_starved.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD event=0xb4,umask=0x10 11 unc_h_rxr_busy_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC event=0xb4,umask=0x4 11 unc_h_rxr_busy_starved.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD event=0xb4,umask=0x40 11 unc_h_rxr_bypass.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC event=0xb2,umask=0x1 11 unc_h_rxr_bypass.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD event=0xb2,umask=0x10 11 unc_h_rxr_bypass.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC event=0xb2,umask=0x2 11 unc_h_rxr_bypass.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC event=0xb2,umask=0x4 11 unc_h_rxr_bypass.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD event=0xb2,umask=0x40 11 unc_h_rxr_bypass.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC event=0xb2,umask=0x8 11 unc_h_rxr_crd_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC event=0xb3,umask=0x1 11 unc_h_rxr_crd_starved.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD event=0xb3,umask=0x10 11 unc_h_rxr_crd_starved.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC event=0xb3,umask=0x2 11 unc_h_rxr_crd_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC event=0xb3,umask=0x4 11 unc_h_rxr_crd_starved.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD event=0xb3,umask=0x40 11 unc_h_rxr_crd_starved.ifv uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV event=0xb3,umask=0x80 11 unc_h_rxr_crd_starved.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC event=0xb3,umask=0x8 11 unc_h_rxr_inserts.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC event=0xb1,umask=0x1 11 unc_h_rxr_inserts.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD event=0xb1,umask=0x10 11 unc_h_rxr_inserts.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC event=0xb1,umask=0x2 11 unc_h_rxr_inserts.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC event=0xb1,umask=0x4 11 unc_h_rxr_inserts.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD event=0xb1,umask=0x40 11 unc_h_rxr_inserts.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC event=0xb1,umask=0x8 11 unc_h_rxr_occupancy.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC event=0xb0,umask=0x1 11 unc_h_rxr_occupancy.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD event=0xb0,umask=0x10 11 unc_h_rxr_occupancy.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC event=0xb0,umask=0x2 11 unc_h_rxr_occupancy.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC event=0xb0,umask=0x4 11 unc_h_rxr_occupancy.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD event=0xb0,umask=0x40 11 unc_h_rxr_occupancy.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC event=0xb0,umask=0x8 11 unc_h_sf_eviction.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE event=0x3d,umask=0x2 11 unc_h_sf_eviction.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE event=0x3d,umask=0x1 11 unc_h_sf_eviction.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE event=0x3d,umask=0x4 11 unc_h_snoops_sent. uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL event=0x51,umask=0x1 11 unc_h_snoops_sent.bcst_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL event=0x51,umask=0x10 11 unc_h_snoops_sent.bcst_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE event=0x51,umask=0x20 11 unc_h_snoops_sent.direct_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL event=0x51,umask=0x40 11 unc_h_snoops_sent.direct_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE event=0x51,umask=0x80 11 unc_h_snoops_sent.local uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL event=0x51,umask=0x4 11 unc_h_snoops_sent.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE event=0x51,umask=0x8 11 unc_h_snoop_resp.rspcnflct uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS event=0x5c,umask=0x40 11 unc_h_snoop_resp.rspfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD event=0x5c,umask=0x80 11 unc_h_snoop_resp.rspi uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI event=0x5c,umask=0x1 11 unc_h_snoop_resp.rspifwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD event=0x5c,umask=0x4 11 unc_h_snoop_resp.rsps uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS event=0x5c,umask=0x2 11 unc_h_snoop_resp.rspsfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD event=0x5c,umask=0x8 11 unc_h_snoop_resp.rsp_fwd_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB event=0x5c,umask=0x20 11 unc_h_snoop_resp.rsp_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB event=0x5c,umask=0x10 11 unc_h_snp_rsp_rcv_local.rspcnflct uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT event=0x5d,umask=0x40 11 unc_h_snp_rsp_rcv_local.rspfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD event=0x5d,umask=0x80 11 unc_h_snp_rsp_rcv_local.rspi uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI event=0x5d,umask=0x1 11 unc_h_snp_rsp_rcv_local.rspifwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD event=0x5d,umask=0x4 11 unc_h_snp_rsp_rcv_local.rsps uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS event=0x5d,umask=0x2 11 unc_h_snp_rsp_rcv_local.rspsfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD event=0x5d,umask=0x8 11 unc_h_snp_rsp_rcv_local.rsp_fwd_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB event=0x5d,umask=0x20 11 unc_h_snp_rsp_rcv_local.rsp_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB event=0x5d,umask=0x10 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0 event=0xd0,umask=0x1 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1 event=0xd0,umask=0x2 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2 event=0xd0,umask=0x4 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3 event=0xd0,umask=0x8 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4 event=0xd0,umask=0x10 11 unc_h_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5 event=0xd0,umask=0x20 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0 event=0xd2,umask=0x1 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1 event=0xd2,umask=0x2 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2 event=0xd2,umask=0x4 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3 event=0xd2,umask=0x8 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4 event=0xd2,umask=0x10 11 unc_h_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5 event=0xd2,umask=0x20 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0 event=0xd4,umask=0x1 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1 event=0xd4,umask=0x2 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2 event=0xd4,umask=0x4 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3 event=0xd4,umask=0x8 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4 event=0xd4,umask=0x10 11 unc_h_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5 event=0xd4,umask=0x20 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0 event=0xd6,umask=0x1 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1 event=0xd6,umask=0x2 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2 event=0xd6,umask=0x4 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3 event=0xd6,umask=0x8 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4 event=0xd6,umask=0x10 11 unc_h_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5 event=0xd6,umask=0x20 11 unc_h_txr_horz_ads_used.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC event=0x9d,umask=0x1 11 unc_h_txr_horz_ads_used.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD event=0x9d,umask=0x10 11 unc_h_txr_horz_ads_used.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC event=0x9d,umask=0x2 11 unc_h_txr_horz_ads_used.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC event=0x9d,umask=0x4 11 unc_h_txr_horz_ads_used.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD event=0x9d,umask=0x40 11 unc_h_txr_horz_bypass.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC event=0x9f,umask=0x1 11 unc_h_txr_horz_bypass.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD event=0x9f,umask=0x10 11 unc_h_txr_horz_bypass.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC event=0x9f,umask=0x2 11 unc_h_txr_horz_bypass.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC event=0x9f,umask=0x4 11 unc_h_txr_horz_bypass.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD event=0x9f,umask=0x40 11 unc_h_txr_horz_bypass.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC event=0x9f,umask=0x8 11 unc_h_txr_horz_cycles_full.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC event=0x96,umask=0x1 11 unc_h_txr_horz_cycles_full.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD event=0x96,umask=0x10 11 unc_h_txr_horz_cycles_full.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC event=0x96,umask=0x2 11 unc_h_txr_horz_cycles_full.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC event=0x96,umask=0x4 11 unc_h_txr_horz_cycles_full.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD event=0x96,umask=0x40 11 unc_h_txr_horz_cycles_full.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC event=0x96,umask=0x8 11 unc_h_txr_horz_cycles_ne.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC event=0x97,umask=0x1 11 unc_h_txr_horz_cycles_ne.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD event=0x97,umask=0x10 11 unc_h_txr_horz_cycles_ne.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC event=0x97,umask=0x2 11 unc_h_txr_horz_cycles_ne.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC event=0x97,umask=0x4 11 unc_h_txr_horz_cycles_ne.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD event=0x97,umask=0x40 11 unc_h_txr_horz_cycles_ne.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC event=0x97,umask=0x8 11 unc_h_txr_horz_inserts.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC event=0x95,umask=0x1 11 unc_h_txr_horz_inserts.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD event=0x95,umask=0x10 11 unc_h_txr_horz_inserts.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC event=0x95,umask=0x2 11 unc_h_txr_horz_inserts.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC event=0x95,umask=0x4 11 unc_h_txr_horz_inserts.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD event=0x95,umask=0x40 11 unc_h_txr_horz_inserts.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC event=0x95,umask=0x8 11 unc_h_txr_horz_nack.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC event=0x99,umask=0x1 11 unc_h_txr_horz_nack.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD event=0x99,umask=0x20 11 unc_h_txr_horz_nack.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC event=0x99,umask=0x2 11 unc_h_txr_horz_nack.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC event=0x99,umask=0x4 11 unc_h_txr_horz_nack.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD event=0x99,umask=0x40 11 unc_h_txr_horz_nack.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC event=0x99,umask=0x8 11 unc_h_txr_horz_occupancy.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC event=0x94,umask=0x1 11 unc_h_txr_horz_occupancy.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD event=0x94,umask=0x10 11 unc_h_txr_horz_occupancy.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC event=0x94,umask=0x2 11 unc_h_txr_horz_occupancy.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC event=0x94,umask=0x4 11 unc_h_txr_horz_occupancy.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD event=0x94,umask=0x40 11 unc_h_txr_horz_occupancy.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC event=0x94,umask=0x8 11 unc_h_txr_horz_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC event=0x9b,umask=0x1 11 unc_h_txr_horz_starved.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC event=0x9b,umask=0x2 11 unc_h_txr_horz_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC event=0x9b,umask=0x4 11 unc_h_txr_horz_starved.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC event=0x9b,umask=0x8 11 unc_h_txr_vert_ads_used.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0 event=0x9c,umask=0x1 11 unc_h_txr_vert_ads_used.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1 event=0x9c,umask=0x10 11 unc_h_txr_vert_ads_used.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0 event=0x9c,umask=0x2 11 unc_h_txr_vert_ads_used.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1 event=0x9c,umask=0x20 11 unc_h_txr_vert_ads_used.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0 event=0x9c,umask=0x4 11 unc_h_txr_vert_ads_used.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1 event=0x9c,umask=0x40 11 unc_h_txr_vert_bypass.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0 event=0x9e,umask=0x1 11 unc_h_txr_vert_bypass.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1 event=0x9e,umask=0x10 11 unc_h_txr_vert_bypass.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0 event=0x9e,umask=0x2 11 unc_h_txr_vert_bypass.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1 event=0x9e,umask=0x20 11 unc_h_txr_vert_bypass.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0 event=0x9e,umask=0x4 11 unc_h_txr_vert_bypass.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1 event=0x9e,umask=0x40 11 unc_h_txr_vert_bypass.iv_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV event=0x9e,umask=0x8 11 unc_h_txr_vert_cycles_full.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0 event=0x92,umask=0x1 11 unc_h_txr_vert_cycles_full.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1 event=0x92,umask=0x10 11 unc_h_txr_vert_cycles_full.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0 event=0x92,umask=0x2 11 unc_h_txr_vert_cycles_full.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1 event=0x92,umask=0x20 11 unc_h_txr_vert_cycles_full.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0 event=0x92,umask=0x4 11 unc_h_txr_vert_cycles_full.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1 event=0x92,umask=0x40 11 unc_h_txr_vert_cycles_full.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV event=0x92,umask=0x8 11 unc_h_txr_vert_cycles_ne.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0 event=0x93,umask=0x1 11 unc_h_txr_vert_cycles_ne.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1 event=0x93,umask=0x10 11 unc_h_txr_vert_cycles_ne.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0 event=0x93,umask=0x2 11 unc_h_txr_vert_cycles_ne.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1 event=0x93,umask=0x20 11 unc_h_txr_vert_cycles_ne.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0 event=0x93,umask=0x4 11 unc_h_txr_vert_cycles_ne.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1 event=0x93,umask=0x40 11 unc_h_txr_vert_cycles_ne.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV event=0x93,umask=0x8 11 unc_h_txr_vert_inserts.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0 event=0x91,umask=0x1 11 unc_h_txr_vert_inserts.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1 event=0x91,umask=0x10 11 unc_h_txr_vert_inserts.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0 event=0x91,umask=0x2 11 unc_h_txr_vert_inserts.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1 event=0x91,umask=0x20 11 unc_h_txr_vert_inserts.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0 event=0x91,umask=0x4 11 unc_h_txr_vert_inserts.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1 event=0x91,umask=0x40 11 unc_h_txr_vert_inserts.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV event=0x91,umask=0x8 11 unc_h_txr_vert_nack.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0 event=0x98,umask=0x1 11 unc_h_txr_vert_nack.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1 event=0x98,umask=0x10 11 unc_h_txr_vert_nack.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0 event=0x98,umask=0x2 11 unc_h_txr_vert_nack.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1 event=0x98,umask=0x20 11 unc_h_txr_vert_nack.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0 event=0x98,umask=0x4 11 unc_h_txr_vert_nack.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1 event=0x98,umask=0x40 11 unc_h_txr_vert_nack.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV event=0x98,umask=0x8 11 unc_h_txr_vert_occupancy.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0 event=0x90,umask=0x1 11 unc_h_txr_vert_occupancy.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1 event=0x90,umask=0x10 11 unc_h_txr_vert_occupancy.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0 event=0x90,umask=0x2 11 unc_h_txr_vert_occupancy.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1 event=0x90,umask=0x20 11 unc_h_txr_vert_occupancy.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0 event=0x90,umask=0x4 11 unc_h_txr_vert_occupancy.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1 event=0x90,umask=0x40 11 unc_h_txr_vert_occupancy.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV event=0x90,umask=0x8 11 unc_h_txr_vert_starved.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0 event=0x9a,umask=0x1 11 unc_h_txr_vert_starved.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1 event=0x9a,umask=0x10 11 unc_h_txr_vert_starved.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0 event=0x9a,umask=0x2 11 unc_h_txr_vert_starved.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1 event=0x9a,umask=0x20 11 unc_h_txr_vert_starved.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0 event=0x9a,umask=0x4 11 unc_h_txr_vert_starved.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1 event=0x9a,umask=0x40 11 unc_h_txr_vert_starved.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV event=0x9a,umask=0x8 11 unc_h_vert_ring_ad_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN event=0xa6,umask=0x4 11 unc_h_vert_ring_ad_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD event=0xa6,umask=0x8 11 unc_h_vert_ring_ad_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN event=0xa6,umask=0x1 11 unc_h_vert_ring_ad_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD event=0xa6,umask=0x2 11 unc_h_vert_ring_ak_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN event=0xa8,umask=0x4 11 unc_h_vert_ring_ak_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD event=0xa8,umask=0x8 11 unc_h_vert_ring_ak_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN event=0xa8,umask=0x1 11 unc_h_vert_ring_ak_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD event=0xa8,umask=0x2 11 unc_h_vert_ring_bl_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN event=0xaa,umask=0x4 11 unc_h_vert_ring_bl_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD event=0xaa,umask=0x8 11 unc_h_vert_ring_bl_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN event=0xaa,umask=0x1 11 unc_h_vert_ring_bl_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD event=0xaa,umask=0x2 11 unc_h_vert_ring_iv_in_use.dn uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN event=0xac,umask=0x4 11 unc_h_vert_ring_iv_in_use.up uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP event=0xac,umask=0x1 11 unc_h_wb_push_mtoi.llc uncore cache This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC event=0x56,umask=0x1 11 unc_h_wb_push_mtoi.mem uncore cache This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM event=0x56,umask=0x2 11 unc_h_write_no_credits.edc0_smi2 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2 event=0x5a,umask=0x4 11 unc_h_write_no_credits.edc1_smi3 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3 event=0x5a,umask=0x8 11 unc_h_write_no_credits.edc2_smi4 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4 event=0x5a,umask=0x10 11 unc_h_write_no_credits.edc3_smi5 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5 event=0x5a,umask=0x20 11 unc_h_write_no_credits.mc0_smi0 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0 event=0x5a,umask=0x1 11 unc_h_write_no_credits.mc1_smi1 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1 event=0x5a,umask=0x2 11 unc_h_xsnp_resp.any_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE event=0x32,umask=0xe4 11 unc_h_xsnp_resp.any_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM event=0x32,umask=0xf0 11 unc_h_xsnp_resp.any_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE event=0x32,umask=0xe2 11 unc_h_xsnp_resp.any_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM event=0x32,umask=0xe8 11 unc_h_xsnp_resp.any_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE event=0x32,umask=0xe1 11 unc_h_xsnp_resp.core_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE event=0x32,umask=0x44 11 unc_h_xsnp_resp.core_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM event=0x32,umask=0x50 11 unc_h_xsnp_resp.core_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE event=0x32,umask=0x42 11 unc_h_xsnp_resp.core_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM event=0x32,umask=0x48 11 unc_h_xsnp_resp.core_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE event=0x32,umask=0x41 11 unc_h_xsnp_resp.evict_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE event=0x32,umask=0x84 11 unc_h_xsnp_resp.evict_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM event=0x32,umask=0x90 11 unc_h_xsnp_resp.evict_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE event=0x32,umask=0x82 11 unc_h_xsnp_resp.evict_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM event=0x32,umask=0x88 11 unc_h_xsnp_resp.evict_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE event=0x32,umask=0x81 11 unc_h_xsnp_resp.ext_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE event=0x32,umask=0x24 11 unc_h_xsnp_resp.ext_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM event=0x32,umask=0x30 11 unc_h_xsnp_resp.ext_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE event=0x32,umask=0x22 11 unc_h_xsnp_resp.ext_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM event=0x32,umask=0x28 11 unc_h_xsnp_resp.ext_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE event=0x32,umask=0x21 11 unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0xf,umask=0x1 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port unc_i_cache_total_occupancy.iv_q uncore interconnect Total Write Cache Occupancy; Snoops event=0xf,umask=0x2 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_total_occupancy.mem uncore interconnect Total IRP occupancy of inbound read and write requests event=0xf,umask=0x4 01 Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy unc_i_clockticks uncore interconnect IRP Clocks event=0x1 01 unc_i_coherent_ops.clflush uncore interconnect Coherent Ops; CLFlush event=0x10,umask=0x80 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.crd uncore interconnect Coherent Ops; CRd event=0x10,umask=0x2 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.drd uncore interconnect Coherent Ops; DRd event=0x10,umask=0x4 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcidcahint uncore interconnect Coherent Ops; PCIDCAHin5t event=0x10,umask=0x20 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcirdcur uncore interconnect Coherent Ops; PCIRdCur event=0x10,umask=0x1 01 Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.pcitom uncore interconnect PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline event=0x10,umask=0x10 01 PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache unc_i_coherent_ops.rfo uncore interconnect RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline event=0x10,umask=0x8 01 RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops; WbMtoI event=0x10,umask=0x40 01 Counts the number of coherency related operations servied by the IRP unc_i_faf_full uncore interconnect FAF RF full event=0x17 01 unc_i_faf_inserts uncore interconnect Inbound read requests received by the IRP and inserted into the FAF queue event=0x18 01 Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP unc_i_faf_occupancy uncore interconnect Occupancy of the IRP FAF queue event=0x19 01 Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP unc_i_faf_transactions uncore interconnect FAF allocation -- sent to ADQ event=0x16 01 unc_i_irp_all.inbound_inserts uncore interconnect All Inserts Inbound (p2p + faf + cset) event=0x1e,umask=0x1 01 unc_i_irp_all.outbound_inserts uncore interconnect All Inserts Outbound (BL, AK, Snoops) event=0x1e,umask=0x2 01 unc_i_misc0.2nd_atomic_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary event=0x1c,umask=0x10 01 unc_i_misc0.2nd_rd_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary event=0x1c,umask=0x4 01 unc_i_misc0.2nd_wr_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary event=0x1c,umask=0x8 01 unc_i_misc0.fast_rej uncore interconnect Misc Events - Set 0; Fastpath Rejects event=0x1c,umask=0x2 01 unc_i_misc0.fast_req uncore interconnect Misc Events - Set 0; Fastpath Requests event=0x1c,umask=0x1 01 unc_i_misc0.fast_xfer uncore interconnect Misc Events - Set 0; Fastpath Transfers From Primary to Secondary event=0x1c,umask=0x20 01 unc_i_misc0.pf_ack_hint uncore interconnect Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary event=0x1c,umask=0x40 01 unc_i_misc0.unknown uncore interconnect Misc Events - Set 0 event=0x1c,umask=0x80 01 unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1; Lost Forward event=0x1d,umask=0x10 01 Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1; Received Invalid event=0x1d,umask=0x20 01 Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1; Received Valid event=0x1d,umask=0x40 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1; Slow Transfer of E Line event=0x1d,umask=0x4 01 Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1; Slow Transfer of I Line event=0x1d,umask=0x1 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1; Slow Transfer of M Line event=0x1d,umask=0x8 01 Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1; Slow Transfer of S Line event=0x1d,umask=0x2 01 Secondary received a transfer that did not have sufficient MESI state unc_i_p2p_inserts uncore interconnect P2P Requests event=0x14 01 P2P requests from the ITC unc_i_p2p_occupancy uncore interconnect P2P Occupancy event=0x15 01 P2P B & S Queue Occupancy unc_i_p2p_transactions.cmpl uncore interconnect P2P Transactions; P2P completions event=0x13,umask=0x8 01 unc_i_p2p_transactions.loc uncore interconnect P2P Transactions; match if local only event=0x13,umask=0x40 01 unc_i_p2p_transactions.loc_and_tgt_match uncore interconnect P2P Transactions; match if local and target matches event=0x13,umask=0x80 01 unc_i_p2p_transactions.msg uncore interconnect P2P Transactions; P2P Message event=0x13,umask=0x4 01 unc_i_p2p_transactions.rd uncore interconnect P2P Transactions; P2P reads event=0x13,umask=0x1 01 unc_i_p2p_transactions.rem uncore interconnect P2P Transactions; Match if remote only event=0x13,umask=0x10 01 unc_i_p2p_transactions.rem_and_tgt_match uncore interconnect P2P Transactions; match if remote and target matches event=0x13,umask=0x20 01 unc_i_p2p_transactions.wr uncore interconnect P2P Transactions; P2P Writes event=0x13,umask=0x2 01 unc_i_snoop_resp.all_hit uncore interconnect Responses to snoops of any type that hit M, E, S or I line in the IIO event=0x12,umask=0x7e 01 Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO unc_i_snoop_resp.all_hit_es uncore interconnect Responses to snoops of any type that hit E or S line in the IIO cache event=0x12,umask=0x74 01 Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache unc_i_snoop_resp.all_hit_i uncore interconnect Responses to snoops of any type that hit I line in the IIO cache event=0x12,umask=0x72 01 Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache unc_i_snoop_resp.all_hit_m uncore interconnect Responses to snoops of any type that hit M line in the IIO cache event=0x12,umask=0x78 01 Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache unc_i_snoop_resp.all_miss uncore interconnect Responses to snoops of any type that miss the IIO cache event=0x12,umask=0x71 01 Responses to snoops of any type (code, data, invalidate) that miss the IIO cache unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses; Hit E or S event=0x12,umask=0x4 01 unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses; Hit I event=0x12,umask=0x2 01 unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses; Hit M event=0x12,umask=0x8 01 unc_i_snoop_resp.miss uncore interconnect Snoop Responses; Miss event=0x12,umask=0x1 01 unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses; SnpCode event=0x12,umask=0x10 01 unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses; SnpData event=0x12,umask=0x20 01 unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses; SnpInv event=0x12,umask=0x40 01 unc_i_transactions.atomic uncore interconnect Inbound Transaction Count; Atomic event=0x11,umask=0x10 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count; Other event=0x11,umask=0x20 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions unc_i_transactions.rd_pref uncore interconnect Inbound Transaction Count; Read Prefetches event=0x11,umask=0x4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x11,umask=0x1 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x11,umask=0x2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_transactions.wr_pref uncore interconnect Inbound write (fast path) requests received by the IRP event=0x11,umask=0x8 01 Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh unc_i_txc_ak_inserts uncore interconnect AK Egress Allocations event=0xb 01 unc_i_txc_bl_drs_cycles_full uncore interconnect BL DRS Egress Cycles Full event=0x5 01 unc_i_txc_bl_drs_inserts uncore interconnect BL DRS Egress Inserts event=0x2 01 unc_i_txc_bl_drs_occupancy uncore interconnect BL DRS Egress Occupancy event=0x8 01 unc_i_txc_bl_ncb_cycles_full uncore interconnect BL NCB Egress Cycles Full event=0x6 01 unc_i_txc_bl_ncb_inserts uncore interconnect BL NCB Egress Inserts event=0x3 01 unc_i_txc_bl_ncb_occupancy uncore interconnect BL NCB Egress Occupancy event=0x9 01 unc_i_txc_bl_ncs_cycles_full uncore interconnect BL NCS Egress Cycles Full event=0x7 01 unc_i_txc_bl_ncs_inserts uncore interconnect BL NCS Egress Inserts event=0x4 01 unc_i_txc_bl_ncs_occupancy uncore interconnect BL NCS Egress Occupancy event=0xa 01 unc_i_txr2_ad_stall_credit_cycles uncore interconnect No AD Egress Credit Stalls event=0x1a 01 Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available unc_i_txr2_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x1b 01 Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txs_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xd 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txs_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xe 01 Counts the number of requests issued to the switch (towards the devices) unc_i_txs_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xc 01 Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests uncore_m2m unc_m2m_ag0_ad_crd_acquired.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=0x1 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=0x2 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=0x4 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=0x8 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=0x1 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=0x2 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=0x4 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=0x8 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=0x1 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=0x2 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=0x4 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=0x8 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=0x1 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=0x2 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=0x4 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=0x8 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=0x1 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=0x2 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=0x4 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=0x8 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=0x1 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=0x2 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=0x4 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=0x8 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=0x1 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=0x2 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=0x4 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=0x8 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=0x1 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=0x2 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=0x4 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=0x8 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_bypass_m2m_egress.not_taken uncore interconnect Traffic in which the M2M to iMC Bypass was not taken event=0x22,umask=0x2 01 Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken unc_m2m_bypass_m2m_egress.taken uncore interconnect M2M to iMC Bypass; Taken event=0x22,umask=0x1 01 unc_m2m_bypass_m2m_ingress.not_taken uncore interconnect M2M to iMC Bypass; Not Taken event=0x21,umask=0x2 01 unc_m2m_bypass_m2m_ingress.taken uncore interconnect M2M to iMC Bypass; Taken event=0x21,umask=0x1 01 unc_m2m_clockticks uncore interconnect Cycles - at UCLK event=0 01 unc_m2m_cms_clockticks uncore interconnect CMS Clockticks event=0xc0 01 unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x24 01 Counts cycles when direct to core mode (which bypasses the CHA) was disabled unc_m2m_direct2core_taken uncore interconnect Messages sent direct to core (bypassing the CHA) event=0x23 01 Counts when messages were sent direct to core (bypassing the CHA) unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction were overridden event=0x25 01 Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel(R) UPI transactions were overridden event=0x28 01 Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when direct to Intel(R) UPI was disabled event=0x27 01 Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled unc_m2m_direct2upi_taken uncore interconnect Messages sent direct to the Intel(R) UPI event=0x26 01 Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel(R) UPI was overridden event=0x29 01 Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit; On NonDirty Line in A State event=0x2a,umask=0x80 01 unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit; On NonDirty Line in I State event=0x2a,umask=0x10 01 unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit; On NonDirty Line in L State event=0x2a,umask=0x40 01 unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit; On NonDirty Line in S State event=0x2a,umask=0x20 01 unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit; On Dirty Line in A State event=0x2a,umask=0x8 01 unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit; On Dirty Line in I State event=0x2a,umask=0x1 01 unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit; On Dirty Line in L State event=0x2a,umask=0x4 01 unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit; On Dirty Line in S State event=0x2a,umask=0x2 01 unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory lookups (any state found) event=0x2d,umask=0x1 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused) unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x2d,umask=0x8 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x2d,umask=0x2 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x2d,umask=0x4 01 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss; On NonDirty Line in A State event=0x2b,umask=0x80 01 unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss; On NonDirty Line in I State event=0x2b,umask=0x10 01 unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss; On NonDirty Line in L State event=0x2b,umask=0x40 01 unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss; On NonDirty Line in S State event=0x2b,umask=0x20 01 unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss; On Dirty Line in A State event=0x2b,umask=0x8 01 unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss; On Dirty Line in I State event=0x2b,umask=0x1 01 unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss; On Dirty Line in L State event=0x2b,umask=0x4 01 unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss; On Dirty Line in S State event=0x2b,umask=0x2 01 unc_m2m_directory_update.a2i uncore interconnect Multi-socket cacheline Directory update from A to I event=0x2e,umask=0x20 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid) unc_m2m_directory_update.a2s uncore interconnect Multi-socket cacheline Directory update from A to S event=0x2e,umask=0x40 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared) unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory update from/to Any state event=0x2e,umask=0x1 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state unc_m2m_directory_update.i2a uncore interconnect Multi-socket cacheline Directory update from I to A event=0x2e,umask=0x4 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll) unc_m2m_directory_update.i2s uncore interconnect Multi-socket cacheline Directory update from I to S event=0x2e,umask=0x2 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared) unc_m2m_directory_update.s2a uncore interconnect Multi-socket cacheline Directory update from S to A event=0x2e,umask=0x10 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll) unc_m2m_directory_update.s2i uncore interconnect Multi-socket cacheline Directory update from S to I event=0x2e,umask=0x8 01 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid) unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements; Down event=0xae,umask=0x4 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements; Up event=0xae,umask=0x1 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_fast_asserted.horz uncore interconnect FaST wire asserted; Horizontal event=0xa5,umask=0x2 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m2m_fast_asserted.vert uncore interconnect FaST wire asserted; Vertical event=0xa5,umask=0x1 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m2m_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use; Left and Even event=0xa7,umask=0x1 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=0x2 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use; Right and Even event=0xa7,umask=0x4 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=0x8 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use; Left and Even event=0xa9,umask=0x1 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=0x2 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use; Right and Even event=0xa9,umask=0x4 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=0x8 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use; Left and Even event=0xab,umask=0x1 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use; Left and Odd event=0xab,umask=0x2 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use; Right and Even event=0xab,umask=0x4 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use; Right and Odd event=0xab,umask=0x8 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use; Left event=0xad,umask=0x1 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use; Right event=0xad,umask=0x4 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_imc_reads.all uncore interconnect Reads to iMC issued event=0x37,umask=0x4 01 Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller) unc_m2m_imc_reads.from_transgress uncore interconnect M2M Reads Issued to iMC; All, regardless of priority event=0x37,umask=0x10 01 unc_m2m_imc_reads.isoch uncore interconnect M2M Reads Issued to iMC; Critical Priority event=0x37,umask=0x2 01 unc_m2m_imc_reads.normal uncore interconnect Reads to iMC issued at Normal Priority (Non-Isochronous) event=0x37,umask=0x1 01 Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads unc_m2m_imc_reads.to_pmm uncore interconnect Read requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M event=0x37,umask=0x8 01 M2M Reads Issued to iMC; All, regardless of priority unc_m2m_imc_writes.all uncore interconnect Writes to iMC issued event=0x38,umask=0x10 01 Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller) unc_m2m_imc_writes.from_transgress uncore interconnect M2M Writes Issued to iMC; All, regardless of priority event=0x38,umask=0x40 01 unc_m2m_imc_writes.full uncore interconnect M2M Writes Issued to iMC; Full Line Non-ISOCH event=0x38,umask=0x1 01 unc_m2m_imc_writes.full_isoch uncore interconnect M2M Writes Issued to iMC; ISOCH Full Line event=0x38,umask=0x4 01 unc_m2m_imc_writes.ni uncore interconnect M2M Writes Issued to iMC; All, regardless of priority event=0x38,umask=0x80 01 unc_m2m_imc_writes.partial uncore interconnect Partial Non-Isochronous writes to the iMC event=0x38,umask=0x2 01 Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes unc_m2m_imc_writes.partial_isoch uncore interconnect M2M Writes Issued to iMC; ISOCH Partial event=0x38,umask=0x8 01 unc_m2m_imc_writes.to_pmm uncore interconnect Write requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M event=0x38,umask=0x20 01 M2M Writes Issued to iMC; All, regardless of priority unc_m2m_pkt_match.mc uncore interconnect Number Packet Header Matches; MC Match event=0x4c,umask=0x2 01 unc_m2m_pkt_match.mesh uncore interconnect Number Packet Header Matches; Mesh Match event=0x4c,umask=0x1 01 unc_m2m_pmm_rpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0 event=0x4f,umask=0x1 01 unc_m2m_pmm_rpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1 event=0x4f,umask=0x2 01 unc_m2m_pmm_rpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2 event=0x4f,umask=0x4 01 unc_m2m_pmm_wpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0 event=0x51,umask=0x1 01 unc_m2m_pmm_wpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1 event=0x51,umask=0x2 01 unc_m2m_pmm_wpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2 event=0x51,umask=0x4 01 unc_m2m_prefcam_cycles_full uncore interconnect Prefetch CAM Cycles Full event=0x53 01 unc_m2m_prefcam_cycles_ne uncore interconnect Prefetch CAM Cycles Not Empty event=0x54 01 unc_m2m_prefcam_demand_promotions uncore interconnect Prefetch requests that got turn into a demand request event=0x56 01 Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory) unc_m2m_prefcam_inserts uncore interconnect Inserts into the Memory Controller Prefetch Queue event=0x57 01 Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory unc_m2m_prefcam_occupancy uncore interconnect Prefetch CAM Occupancy event=0x55 01 unc_m2m_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=0x1 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=0x2 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=0x4 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=0x8 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=0x1 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=0x2 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=0x4 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=0x8 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring; AD event=0xa3,umask=0x1 01 unc_m2m_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring; AK event=0xa3,umask=0x2 01 unc_m2m_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20 01 unc_m2m_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring; BL event=0xa3,umask=0x4 01 unc_m2m_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring; IV event=0xa3,umask=0x8 01 unc_m2m_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring; AD event=0xa2,umask=0x1 01 unc_m2m_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=0x2 01 unc_m2m_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=0x4 01 unc_m2m_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=0x8 01 unc_m2m_ring_src_thrtl uncore interconnect Source Throttle event=0xa4 01 unc_m2m_rpq_cycles_no_spec_credits.chn0 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0 event=0x44,umask=0x1 11 unc_m2m_rpq_cycles_no_spec_credits.chn1 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1 event=0x44,umask=0x2 11 unc_m2m_rpq_cycles_no_spec_credits.chn2 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2 event=0x44,umask=0x4 11 unc_m2m_rpq_cycles_reg_credits.chn0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0 event=0x43,umask=0x1 01 unc_m2m_rpq_cycles_reg_credits.chn1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1 event=0x43,umask=0x2 01 unc_m2m_rpq_cycles_reg_credits.chn2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2 event=0x43,umask=0x4 01 unc_m2m_rpq_cycles_spec_credits.chn0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 0 event=0x44,umask=0x1 01 unc_m2m_rpq_cycles_spec_credits.chn1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 1 event=0x44,umask=0x2 01 unc_m2m_rpq_cycles_spec_credits.chn2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 2 event=0x44,umask=0x4 01 unc_m2m_rxc_ad_cycles_full uncore interconnect AD Ingress (from CMS) Full event=0x4 01 unc_m2m_rxc_ad_cycles_ne uncore interconnect AD Ingress (from CMS) Not Empty event=0x3 01 unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) Queue Inserts event=0x1 01 Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and unc_m2m_rxc_ad_occupancy uncore interconnect AD Ingress (from CMS) Occupancy event=0x2 01 unc_m2m_rxc_bl_cycles_full uncore interconnect BL Ingress (from CMS) Full event=0x8 01 unc_m2m_rxc_bl_cycles_ne uncore interconnect BL Ingress (from CMS) Not Empty event=0x7 01 unc_m2m_rxc_bl_inserts uncore interconnect BL Ingress (from CMS) Allocations event=0x5 01 unc_m2m_rxc_bl_occupancy uncore interconnect BL Ingress (from CMS) Occupancy event=0x6 01 unc_m2m_rxr_busy_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb4,umask=0x1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb4,umask=0x4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_bypass.ad_bnc uncore interconnect Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=0x1 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ak_bnc uncore interconnect Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=0x2 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_bnc uncore interconnect Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=0x4 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.iv_bnc uncore interconnect Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=0x8 01 Number of packets bypassing the CMS Ingress unc_m2m_rxr_crd_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb3,umask=0x1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ak_bnc uncore interconnect Transgress Injection Starvation; AK - Bounce event=0xb3,umask=0x2 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb3,umask=0x4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.iv_bnc uncore interconnect Transgress Injection Starvation; IV - Bounce event=0xb3,umask=0x8 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_inserts.ad_bnc uncore interconnect Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=0x1 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ak_bnc uncore interconnect Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=0x2 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_bnc uncore interconnect Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=0x4 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.iv_bnc uncore interconnect Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=0x8 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_bnc uncore interconnect Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=0x1 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ak_bnc uncore interconnect Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=0x2 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_bnc uncore interconnect Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=0x4 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.iv_bnc uncore interconnect Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=0x8 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=0x1 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=0x2 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=0x4 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=0x8 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=0x1 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=0x2 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=0x4 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=0x8 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=0x1 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=0x2 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=0x4 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=0x8 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=0x1 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=0x2 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=0x4 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=0x8 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM event=0x2c,umask=0x1 01 Tag Hit; Read Hit from NearMem, Clean Line unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=0x2 01 Tag Hit; Read Hit from NearMem, Dirty Line unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=0x4 01 Tag Hit; Underfill Rd Hit from NearMem, Clean Line unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=0x8 01 Tag Hit; Underfill Rd Hit from NearMem, Dirty Line unc_m2m_tgr_ad_credits uncore interconnect Number AD Ingress Credits event=0x41 01 unc_m2m_tgr_bl_credits uncore interconnect Number BL Ingress Credits event=0x42 01 unc_m2m_tracker_cycles_full.ch0 uncore interconnect Tracker Cycles Full; Channel 0 event=0x45,umask=0x1 01 unc_m2m_tracker_cycles_full.ch1 uncore interconnect Tracker Cycles Full; Channel 1 event=0x45,umask=0x2 01 unc_m2m_tracker_cycles_full.ch2 uncore interconnect Tracker Cycles Full; Channel 2 event=0x45,umask=0x4 01 unc_m2m_tracker_cycles_ne.ch0 uncore interconnect Tracker Cycles Not Empty; Channel 0 event=0x46,umask=0x1 01 unc_m2m_tracker_cycles_ne.ch1 uncore interconnect Tracker Cycles Not Empty; Channel 1 event=0x46,umask=0x2 01 unc_m2m_tracker_cycles_ne.ch2 uncore interconnect Tracker Cycles Not Empty; Channel 2 event=0x46,umask=0x4 01 unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts; Channel 0 event=0x49,umask=0x1 01 unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts; Channel 1 event=0x49,umask=0x2 01 unc_m2m_tracker_inserts.ch2 uncore interconnect Tracker Inserts; Channel 2 event=0x49,umask=0x4 01 unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy; Channel 0 event=0x47,umask=0x1 01 unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy; Channel 1 event=0x47,umask=0x2 01 unc_m2m_tracker_occupancy.ch2 uncore interconnect Tracker Occupancy; Channel 2 event=0x47,umask=0x4 01 unc_m2m_tracker_pending_occupancy uncore interconnect Data Pending Occupancy event=0x48 01 unc_m2m_txc_ad_credits_acquired uncore interconnect AD Egress (to CMS) Credit Acquired event=0xd 01 unc_m2m_txc_ad_credit_occupancy uncore interconnect AD Egress (to CMS) Credits Occupancy event=0xe 01 unc_m2m_txc_ad_cycles_full uncore interconnect AD Egress (to CMS) Full event=0xc 01 unc_m2m_txc_ad_cycles_ne uncore interconnect AD Egress (to CMS) Not Empty event=0xb 01 unc_m2m_txc_ad_inserts uncore interconnect AD Egress (to CMS) Allocations event=0x9 01 unc_m2m_txc_ad_no_credit_cycles uncore interconnect Cycles with No AD Egress (to CMS) Credits event=0xf 01 unc_m2m_txc_ad_no_credit_stalled uncore interconnect Cycles Stalled with No AD Egress (to CMS) Credits event=0x10 01 unc_m2m_txc_ad_occupancy uncore interconnect AD Egress (to CMS) Occupancy event=0xa 01 unc_m2m_txc_ak.crd_cbo uncore interconnect Outbound Ring Transactions on AK; CRD Transactions to Cbo event=0x39,umask=0x2 01 unc_m2m_txc_ak.ndr uncore interconnect Outbound Ring Transactions on AK; NDR Transactions event=0x39,umask=0x1 01 unc_m2m_txc_ak_credits_acquired.cms0 uncore interconnect AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side event=0x1d,umask=0x1 01 unc_m2m_txc_ak_credits_acquired.cms1 uncore interconnect AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side event=0x1d,umask=0x2 01 unc_m2m_txc_ak_credit_occupancy.cms0 uncore interconnect AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side event=0x1e,umask=0x1 01 unc_m2m_txc_ak_credit_occupancy.cms1 uncore interconnect AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side event=0x1e,umask=0x2 01 unc_m2m_txc_ak_cycles_full.all uncore interconnect AK Egress (to CMS) Full; All event=0x14,umask=0x3 01 unc_m2m_txc_ak_cycles_full.cms0 uncore interconnect AK Egress (to CMS) Full; Common Mesh Stop - Near Side event=0x14,umask=0x1 01 unc_m2m_txc_ak_cycles_full.cms1 uncore interconnect AK Egress (to CMS) Full; Common Mesh Stop - Far Side event=0x14,umask=0x2 01 unc_m2m_txc_ak_cycles_full.rdcrd0 uncore interconnect AK Egress (to CMS) Full; Read Credit Request event=0x14,umask=0x8 01 unc_m2m_txc_ak_cycles_full.rdcrd1 uncore interconnect AK Egress (to CMS) Full; Read Credit Request event=0x14,umask=0x88 01 unc_m2m_txc_ak_cycles_full.wrcmp0 uncore interconnect AK Egress (to CMS) Full; Write Compare Request event=0x14,umask=0x20 01 unc_m2m_txc_ak_cycles_full.wrcmp1 uncore interconnect AK Egress (to CMS) Full; Write Compare Request event=0x14,umask=0xa0 01 unc_m2m_txc_ak_cycles_full.wrcrd0 uncore interconnect AK Egress (to CMS) Full; Write Credit Request event=0x14,umask=0x10 01 unc_m2m_txc_ak_cycles_full.wrcrd1 uncore interconnect AK Egress (to CMS) Full; Write Credit Request event=0x14,umask=0x90 01 unc_m2m_txc_ak_cycles_ne.all uncore interconnect AK Egress (to CMS) Not Empty; All event=0x13,umask=0x3 01 unc_m2m_txc_ak_cycles_ne.cms0 uncore interconnect AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side event=0x13,umask=0x1 01 unc_m2m_txc_ak_cycles_ne.cms1 uncore interconnect AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side event=0x13,umask=0x2 01 unc_m2m_txc_ak_cycles_ne.rdcrd uncore interconnect AK Egress (to CMS) Not Empty; Read Credit Request event=0x13,umask=0x8 01 unc_m2m_txc_ak_cycles_ne.wrcmp uncore interconnect AK Egress (to CMS) Not Empty; Write Compare Request event=0x13,umask=0x20 01 unc_m2m_txc_ak_cycles_ne.wrcrd uncore interconnect AK Egress (to CMS) Not Empty; Write Credit Request event=0x13,umask=0x10 01 unc_m2m_txc_ak_inserts.all uncore interconnect AK Egress (to CMS) Allocations; All event=0x11,umask=0x3 01 unc_m2m_txc_ak_inserts.cms0 uncore interconnect AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side event=0x11,umask=0x1 01 unc_m2m_txc_ak_inserts.cms1 uncore interconnect AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side event=0x11,umask=0x2 01 unc_m2m_txc_ak_inserts.pref_rd_cam_hit uncore interconnect AK Egress (to CMS) Allocations; Prefetch Read Cam Hit event=0x11,umask=0x40 01 unc_m2m_txc_ak_inserts.rdcrd uncore interconnect AK Egress (to CMS) Allocations; Read Credit Request event=0x11,umask=0x8 01 unc_m2m_txc_ak_inserts.wrcmp uncore interconnect AK Egress (to CMS) Allocations; Write Compare Request event=0x11,umask=0x20 01 unc_m2m_txc_ak_inserts.wrcrd uncore interconnect AK Egress (to CMS) Allocations; Write Credit Request event=0x11,umask=0x10 01 unc_m2m_txc_ak_no_credit_cycles.cms0 uncore interconnect Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1f,umask=0x1 01 unc_m2m_txc_ak_no_credit_cycles.cms1 uncore interconnect Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1f,umask=0x2 01 unc_m2m_txc_ak_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x20,umask=0x1 01 unc_m2m_txc_ak_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x20,umask=0x2 01 unc_m2m_txc_ak_occupancy.all uncore interconnect AK Egress (to CMS) Occupancy; All event=0x12,umask=0x3 01 unc_m2m_txc_ak_occupancy.cms0 uncore interconnect AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side event=0x12,umask=0x1 01 unc_m2m_txc_ak_occupancy.cms1 uncore interconnect AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side event=0x12,umask=0x2 01 unc_m2m_txc_ak_occupancy.rdcrd uncore interconnect AK Egress (to CMS) Occupancy; Read Credit Request event=0x12,umask=0x8 01 unc_m2m_txc_ak_occupancy.wrcmp uncore interconnect AK Egress (to CMS) Occupancy; Write Compare Request event=0x12,umask=0x20 01 unc_m2m_txc_ak_occupancy.wrcrd uncore interconnect AK Egress (to CMS) Occupancy; Write Credit Request event=0x12,umask=0x10 01 unc_m2m_txc_ak_sideband.rd uncore interconnect AK Egress (to CMS) Sideband event=0x6b,umask=0x1 01 unc_m2m_txc_ak_sideband.wr uncore interconnect AK Egress (to CMS) Sideband event=0x6b,umask=0x2 01 unc_m2m_txc_bl.drs_cache uncore interconnect Outbound DRS Ring Transactions to Cache; Data to Cache event=0x40,umask=0x1 01 unc_m2m_txc_bl.drs_core uncore interconnect Outbound DRS Ring Transactions to Cache; Data to Core event=0x40,umask=0x2 01 unc_m2m_txc_bl.drs_upi uncore interconnect Outbound DRS Ring Transactions to Cache; Data to QPI event=0x40,umask=0x4 01 unc_m2m_txc_bl_credits_acquired.cms0 uncore interconnect BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side event=0x19,umask=0x1 01 unc_m2m_txc_bl_credits_acquired.cms1 uncore interconnect BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side event=0x19,umask=0x2 01 unc_m2m_txc_bl_credit_occupancy.cms0 uncore interconnect BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side event=0x1a,umask=0x1 01 unc_m2m_txc_bl_credit_occupancy.cms1 uncore interconnect BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side event=0x1a,umask=0x2 01 unc_m2m_txc_bl_cycles_full.all uncore interconnect BL Egress (to CMS) Full; All event=0x18,umask=0x3 01 unc_m2m_txc_bl_cycles_full.cms0 uncore interconnect BL Egress (to CMS) Full; Common Mesh Stop - Near Side event=0x18,umask=0x1 01 unc_m2m_txc_bl_cycles_full.cms1 uncore interconnect BL Egress (to CMS) Full; Common Mesh Stop - Far Side event=0x18,umask=0x2 01 unc_m2m_txc_bl_cycles_ne.all uncore interconnect BL Egress (to CMS) Not Empty; All event=0x17,umask=0x3 01 unc_m2m_txc_bl_cycles_ne.cms0 uncore interconnect BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side event=0x17,umask=0x1 01 unc_m2m_txc_bl_cycles_ne.cms1 uncore interconnect BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side event=0x17,umask=0x2 01 unc_m2m_txc_bl_inserts.all uncore interconnect BL Egress (to CMS) Allocations; All event=0x15,umask=0x3 01 unc_m2m_txc_bl_inserts.cms0 uncore interconnect BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side event=0x15,umask=0x1 01 unc_m2m_txc_bl_inserts.cms1 uncore interconnect BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side event=0x15,umask=0x2 01 unc_m2m_txc_bl_no_credit_cycles.cms0 uncore interconnect Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1b,umask=0x1 01 unc_m2m_txc_bl_no_credit_cycles.cms1 uncore interconnect Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1b,umask=0x2 01 unc_m2m_txc_bl_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1c,umask=0x1 01 unc_m2m_txc_bl_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1c,umask=0x2 01 unc_m2m_txc_bl_occupancy.all uncore interconnect BL Egress (to CMS) Occupancy; All event=0x16,umask=0x3 01 unc_m2m_txc_bl_occupancy.cms0 uncore interconnect BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side event=0x16,umask=0x1 01 unc_m2m_txc_bl_occupancy.cms1 uncore interconnect BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side event=0x16,umask=0x2 01 unc_m2m_txr_horz_ads_used.ad_bnc uncore interconnect CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=0x1 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ak_bnc uncore interconnect CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=0x2 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_bnc uncore interconnect CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=0x4 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_bnc uncore interconnect CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=0x1 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ak_bnc uncore interconnect CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=0x2 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_bnc uncore interconnect CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=0x4 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.iv_bnc uncore interconnect CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=0x8 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_cycles_full.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=0x1 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=0x2 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=0x4 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=0x8 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=0x1 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=0x2 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=0x4 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=0x8 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_bnc uncore interconnect CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=0x1 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ak_bnc uncore interconnect CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=0x2 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_bnc uncore interconnect CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=0x4 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.iv_bnc uncore interconnect CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=0x8 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_nack.ad_bnc uncore interconnect CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=0x1 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ak_bnc uncore interconnect CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=0x2 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_bnc uncore interconnect CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=0x4 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.iv_bnc uncore interconnect CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=0x8 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_occupancy.ad_bnc uncore interconnect CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=0x1 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ak_bnc uncore interconnect CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=0x2 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_bnc uncore interconnect CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=0x4 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.iv_bnc uncore interconnect CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=0x8 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_starved.ad_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=0x1 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.ak_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=0x2 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.bl_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=0x4 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.iv_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=0x8 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=0x1 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=0x2 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=0x4 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=0x1 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=0x2 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=0x4 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.iv uncore interconnect CMS Vertical ADS Used; IV event=0x9e,umask=0x8 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_cycles_full.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=0x1 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_full.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=0x2 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_full.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_full.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=0x4 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_full.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_full.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=0x8 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_ne.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=0x1 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_ne.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=0x2 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_ne.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=0x4 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_ne.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_ne.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=0x8 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_inserts.ad_ag0 uncore interconnect CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=0x1 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts.ad_ag1 uncore interconnect CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_inserts.ak_ag0 uncore interconnect CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=0x2 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts.ak_ag1 uncore interconnect CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_inserts.bl_ag0 uncore interconnect CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=0x4 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_inserts.bl_ag1 uncore interconnect CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_inserts.iv uncore interconnect CMS Vert Egress Allocations; IV event=0x91,umask=0x8 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_nack.ad_ag0 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=0x1 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ad_ag1 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ak_ag0 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=0x2 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ak_ag1 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.bl_ag0 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=0x4 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.bl_ag1 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.iv uncore interconnect CMS Vertical Egress NACKs; IV event=0x98,umask=0x8 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_occupancy.ad_ag0 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=0x1 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy.ad_ag1 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_occupancy.ak_ag0 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=0x2 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_occupancy.ak_ag1 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_occupancy.bl_ag0 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=0x4 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_occupancy.bl_ag1 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_occupancy.iv uncore interconnect CMS Vert Egress Occupancy; IV event=0x90,umask=0x8 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_starved.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=0x1 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=0x2 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=0x4 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.iv uncore interconnect CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=0x8 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use; Down and Even event=0xa6,umask=0x4 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use; Down and Odd event=0xa6,umask=0x8 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use; Up and Even event=0xa6,umask=0x1 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use; Up and Odd event=0xa6,umask=0x2 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use; Down and Even event=0xa8,umask=0x4 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use; Down and Odd event=0xa8,umask=0x8 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use; Up and Even event=0xa8,umask=0x1 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use; Up and Odd event=0xa8,umask=0x2 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use; Down and Even event=0xaa,umask=0x4 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use; Down and Odd event=0xaa,umask=0x8 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use; Up and Even event=0xaa,umask=0x1 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use; Up and Odd event=0xaa,umask=0x2 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use; Down event=0xac,umask=0x4 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use; Up event=0xac,umask=0x1 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_wpq_cycles_no_reg_credits.chn0 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0 event=0x4d,umask=0x1 11 unc_m2m_wpq_cycles_no_reg_credits.chn1 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1 event=0x4d,umask=0x2 11 unc_m2m_wpq_cycles_no_reg_credits.chn2 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2 event=0x4d,umask=0x4 11 unc_m2m_wpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0 event=0x4d,umask=0x1 01 unc_m2m_wpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1 event=0x4d,umask=0x2 01 unc_m2m_wpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2 event=0x4d,umask=0x4 01 unc_m2m_wpq_cycles_spec_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 0 event=0x4e,umask=0x1 01 unc_m2m_wpq_cycles_spec_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 1 event=0x4e,umask=0x2 01 unc_m2m_wpq_cycles_spec_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 2 event=0x4e,umask=0x4 01 unc_m2m_write_tracker_cycles_full.ch0 uncore interconnect Write Tracker Cycles Full; Channel 0 event=0x4a,umask=0x1 01 unc_m2m_write_tracker_cycles_full.ch1 uncore interconnect Write Tracker Cycles Full; Channel 1 event=0x4a,umask=0x2 01 unc_m2m_write_tracker_cycles_full.ch2 uncore interconnect Write Tracker Cycles Full; Channel 2 event=0x4a,umask=0x4 01 unc_m2m_write_tracker_cycles_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty; Channel 0 event=0x4b,umask=0x1 01 unc_m2m_write_tracker_cycles_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty; Channel 1 event=0x4b,umask=0x2 01 unc_m2m_write_tracker_cycles_ne.ch2 uncore interconnect Write Tracker Cycles Not Empty; Channel 2 event=0x4b,umask=0x4 01 unc_m2m_write_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts; Channel 0 event=0x61,umask=0x1 01 unc_m2m_write_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts; Channel 1 event=0x61,umask=0x2 01 unc_m2m_write_tracker_inserts.ch2 uncore interconnect Write Tracker Inserts; Channel 2 event=0x61,umask=0x4 01 unc_m2m_write_tracker_occupancy.ch0 uncore interconnect Write Tracker Occupancy; Channel 0 event=0x60,umask=0x1 01 unc_m2m_write_tracker_occupancy.ch1 uncore interconnect Write Tracker Occupancy; Channel 1 event=0x60,umask=0x2 01 unc_m2m_write_tracker_occupancy.ch2 uncore interconnect Write Tracker Occupancy; Channel 2 event=0x60,umask=0x4 01 uncore_m3upi unc_m3upi_ag0_ad_crd_acquired.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=0x1 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=0x2 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=0x4 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=0x8 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20 01 Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=0x1 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=0x2 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=0x4 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=0x8 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20 01 Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=0x1 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=0x2 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=0x4 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=0x8 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20 01 Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=0x1 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=0x2 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=0x4 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=0x8 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20 01 Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=0x1 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=0x2 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=0x4 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=0x8 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20 01 Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=0x1 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=0x2 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=0x4 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=0x8 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20 01 Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=0x1 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=0x2 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=0x4 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=0x8 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20 01 Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=0x1 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=0x2 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=0x4 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=0x8 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20 01 Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_cha_ad_credits_empty.req uncore interconnect CBox AD Credits Empty; Requests event=0x22,umask=0x4 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.snp uncore interconnect CBox AD Credits Empty; Snoops event=0x22,umask=0x8 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.vna uncore interconnect CBox AD Credits Empty; VNA Messages event=0x22,umask=0x1 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.wb uncore interconnect CBox AD Credits Empty; Writebacks event=0x22,umask=0x2 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_clockticks uncore interconnect Number of uclks in domain event=0x1 01 Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m3upi_cms_clockticks uncore interconnect CMS Clockticks event=0xc0 01 unc_m3upi_d2c_sent uncore interconnect D2C Sent event=0x2b 01 Count cases BL sends direct to core unc_m3upi_d2u_sent uncore interconnect D2U Sent event=0x2a 01 Cases where SMI3 sends D2U command unc_m3upi_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements; Down event=0xae,umask=0x4 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements; Up event=0xae,umask=0x1 01 Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_fast_asserted.horz uncore interconnect FaST wire asserted; Horizontal event=0xa5,umask=0x2 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m3upi_fast_asserted.vert uncore interconnect FaST wire asserted; Vertical event=0xa5,umask=0x1 01 Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_m3upi_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use; Left and Even event=0xa7,umask=0x1 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=0x2 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use; Right and Even event=0xa7,umask=0x4 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=0x8 01 Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use; Left and Even event=0xa9,umask=0x1 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=0x2 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use; Right and Even event=0xa9,umask=0x4 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=0x8 01 Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use; Left and Even event=0xab,umask=0x1 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use; Left and Odd event=0xab,umask=0x2 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use; Right and Even event=0xab,umask=0x4 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use; Right and Odd event=0xab,umask=0x8 01 Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use; Left event=0xad,umask=0x1 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use; Right event=0xad,umask=0x4 01 Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_m2_bl_credits_empty.iio0_iio1_ncb uncore interconnect M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) event=0x23,umask=0x1 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio2_ncb uncore interconnect M2 BL Credits Empty; IIO2 event=0x23,umask=0x2 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio3_ncb uncore interconnect M2 BL Credits Empty; IIO3 event=0x23,umask=0x4 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio4_ncb uncore interconnect M2 BL Credits Empty; IIO4 event=0x23,umask=0x8 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio5_ncb uncore interconnect M2 BL Credits Empty; IIO5 event=0x23,umask=0x10 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs uncore interconnect M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together event=0x23,umask=0x20 01 No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs_sel uncore interconnect M2 BL Credits Empty; Selected M2p BL NCS credits event=0x23,umask=0x40 01 No vn0 and vna credits available to send to M2 unc_m3upi_multi_slot_rcvd.ad_slot0 uncore interconnect Multi Slot Flit Received; AD - Slot 0 event=0x3e,umask=0x1 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot1 uncore interconnect Multi Slot Flit Received; AD - Slot 1 event=0x3e,umask=0x2 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot2 uncore interconnect Multi Slot Flit Received; AD - Slot 2 event=0x3e,umask=0x4 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot0 uncore interconnect Multi Slot Flit Received; AK - Slot 0 event=0x3e,umask=0x10 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot2 uncore interconnect Multi Slot Flit Received; AK - Slot 2 event=0x3e,umask=0x20 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.bl_slot0 uncore interconnect Multi Slot Flit Received; BL - Slot 0 event=0x3e,umask=0x8 01 Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=0x1 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=0x2 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=0x4 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=0x8 01 Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=0x1 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=0x2 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=0x4 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=0x8 01 Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring; AD event=0xa3,umask=0x1 01 unc_m3upi_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring; AK event=0xa3,umask=0x2 01 unc_m3upi_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20 01 unc_m3upi_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring; BL event=0xa3,umask=0x4 01 unc_m3upi_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring; IV event=0xa3,umask=0x8 01 unc_m3upi_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring; AD event=0xa2,umask=0x1 01 unc_m3upi_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=0x2 01 unc_m3upi_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=0x4 01 unc_m3upi_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=0x8 01 unc_m3upi_ring_src_thrtl uncore interconnect Source Throttle event=0xa4 01 unc_m3upi_rxc_arb_lost_vn0.ad_req uncore interconnect Lost Arb for VN0; REQ on AD event=0x4b,umask=0x1 01 VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn0.ad_rsp uncore interconnect Lost Arb for VN0; RSP on AD event=0x4b,umask=0x4 01 VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.ad_snp uncore interconnect Lost Arb for VN0; SNP on AD event=0x4b,umask=0x2 01 VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn0.bl_ncb uncore interconnect Lost Arb for VN0; NCB on BL event=0x4b,umask=0x20 01 VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn0.bl_ncs uncore interconnect Lost Arb for VN0; NCS on BL event=0x4b,umask=0x40 01 VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn0.bl_rsp uncore interconnect Lost Arb for VN0; RSP on BL event=0x4b,umask=0x8 01 VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.bl_wb uncore interconnect Lost Arb for VN0; WB on BL event=0x4b,umask=0x10 01 VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_lost_vn1.ad_req uncore interconnect Lost Arb for VN1; REQ on AD event=0x4c,umask=0x1 01 VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn1.ad_rsp uncore interconnect Lost Arb for VN1; RSP on AD event=0x4c,umask=0x4 01 VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.ad_snp uncore interconnect Lost Arb for VN1; SNP on AD event=0x4c,umask=0x2 01 VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn1.bl_ncb uncore interconnect Lost Arb for VN1; NCB on BL event=0x4c,umask=0x20 01 VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn1.bl_ncs uncore interconnect Lost Arb for VN1; NCS on BL event=0x4c,umask=0x40 01 VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn1.bl_rsp uncore interconnect Lost Arb for VN1; RSP on BL event=0x4c,umask=0x8 01 VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.bl_wb uncore interconnect Lost Arb for VN1; WB on BL event=0x4c,umask=0x10 01 VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_misc.adbl_parallel_win uncore interconnect Arb Miscellaneous; AD, BL Parallel Win event=0x4d,umask=0x40 01 AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.no_prog_ad_vn0 uncore interconnect Arb Miscellaneous; No Progress on Pending AD VN0 event=0x4d,umask=0x4 01 Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_ad_vn1 uncore interconnect Arb Miscellaneous; No Progress on Pending AD VN1 event=0x4d,umask=0x8 01 Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn0 uncore interconnect Arb Miscellaneous; No Progress on Pending BL VN0 event=0x4d,umask=0x10 01 Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn1 uncore interconnect Arb Miscellaneous; No Progress on Pending BL VN1 event=0x4d,umask=0x20 01 Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.par_bias_vn0 uncore interconnect Arb Miscellaneous; Parallel Bias to VN0 event=0x4d,umask=0x1 01 VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl unc_m3upi_rxc_arb_misc.par_bias_vn1 uncore interconnect Arb Miscellaneous; Parallel Bias to VN1 event=0x4d,umask=0x2 01 VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl unc_m3upi_rxc_arb_noad_req_vn0.ad_req uncore interconnect Can't Arb for VN0; REQ on AD event=0x49,umask=0x1 01 VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noad_req_vn0.ad_rsp uncore interconnect Can't Arb for VN0; RSP on AD event=0x49,umask=0x4 01 VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn0.ad_snp uncore interconnect Can't Arb for VN0; SNP on AD event=0x49,umask=0x2 01 VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noad_req_vn0.bl_ncb uncore interconnect Can't Arb for VN0; NCB on BL event=0x49,umask=0x20 01 VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noad_req_vn0.bl_ncs uncore interconnect Can't Arb for VN0; NCS on BL event=0x49,umask=0x40 01 VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noad_req_vn0.bl_rsp uncore interconnect Can't Arb for VN0; RSP on BL event=0x49,umask=0x8 01 VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn0.bl_wb uncore interconnect Can't Arb for VN0; WB on BL event=0x49,umask=0x10 01 VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noad_req_vn1.ad_req uncore interconnect Can't Arb for VN1; REQ on AD event=0x4a,umask=0x1 01 VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noad_req_vn1.ad_rsp uncore interconnect Can't Arb for VN1; RSP on AD event=0x4a,umask=0x4 01 VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn1.ad_snp uncore interconnect Can't Arb for VN1; SNP on AD event=0x4a,umask=0x2 01 VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noad_req_vn1.bl_ncb uncore interconnect Can't Arb for VN1; NCB on BL event=0x4a,umask=0x20 01 VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noad_req_vn1.bl_ncs uncore interconnect Can't Arb for VN1; NCS on BL event=0x4a,umask=0x40 01 VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noad_req_vn1.bl_rsp uncore interconnect Can't Arb for VN1; RSP on BL event=0x4a,umask=0x8 01 VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn1.bl_wb uncore interconnect Can't Arb for VN1; WB on BL event=0x4a,umask=0x10 01 VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocred_vn0.ad_req uncore interconnect No Credits to Arb for VN0; REQ on AD event=0x47,umask=0x1 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocred_vn0.ad_rsp uncore interconnect No Credits to Arb for VN0; RSP on AD event=0x47,umask=0x4 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn0.ad_snp uncore interconnect No Credits to Arb for VN0; SNP on AD event=0x47,umask=0x2 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocred_vn0.bl_ncb uncore interconnect No Credits to Arb for VN0; NCB on BL event=0x47,umask=0x20 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocred_vn0.bl_ncs uncore interconnect No Credits to Arb for VN0; NCS on BL event=0x47,umask=0x40 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocred_vn0.bl_rsp uncore interconnect No Credits to Arb for VN0; RSP on BL event=0x47,umask=0x8 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn0.bl_wb uncore interconnect No Credits to Arb for VN0; WB on BL event=0x47,umask=0x10 01 VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocred_vn1.ad_req uncore interconnect No Credits to Arb for VN1; REQ on AD event=0x48,umask=0x1 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocred_vn1.ad_rsp uncore interconnect No Credits to Arb for VN1; RSP on AD event=0x48,umask=0x4 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn1.ad_snp uncore interconnect No Credits to Arb for VN1; SNP on AD event=0x48,umask=0x2 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocred_vn1.bl_ncb uncore interconnect No Credits to Arb for VN1; NCB on BL event=0x48,umask=0x20 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocred_vn1.bl_ncs uncore interconnect No Credits to Arb for VN1; NCS on BL event=0x48,umask=0x40 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocred_vn1.bl_rsp uncore interconnect No Credits to Arb for VN1; RSP on BL event=0x48,umask=0x8 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn1.bl_wb uncore interconnect No Credits to Arb for VN1; WB on BL event=0x48,umask=0x10 01 VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_bypassed.ad_s0_bl_arb uncore interconnect Ingress Queue Bypasses; AD to Slot 0 on BL Arb event=0x40,umask=0x2 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration unc_m3upi_rxc_bypassed.ad_s0_idle uncore interconnect Ingress Queue Bypasses; AD to Slot 0 on Idle event=0x40,umask=0x1 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle unc_m3upi_rxc_bypassed.ad_s1_bl_slot uncore interconnect Ingress Queue Bypasses; AD + BL to Slot 1 event=0x40,umask=0x4 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit unc_m3upi_rxc_bypassed.ad_s2_bl_slot uncore interconnect Ingress Queue Bypasses; AD + BL to Slot 2 event=0x40,umask=0x8 01 Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit unc_m3upi_rxc_collision_vn0.ad_req uncore interconnect VN0 message lost contest for flit; REQ on AD event=0x50,umask=0x1 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_collision_vn0.ad_rsp uncore interconnect VN0 message lost contest for flit; RSP on AD event=0x50,umask=0x4 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn0.ad_snp uncore interconnect VN0 message lost contest for flit; SNP on AD event=0x50,umask=0x2 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_collision_vn0.bl_ncb uncore interconnect VN0 message lost contest for flit; NCB on BL event=0x50,umask=0x20 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_collision_vn0.bl_ncs uncore interconnect VN0 message lost contest for flit; NCS on BL event=0x50,umask=0x40 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_collision_vn0.bl_rsp uncore interconnect VN0 message lost contest for flit; RSP on BL event=0x50,umask=0x8 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn0.bl_wb uncore interconnect VN0 message lost contest for flit; WB on BL event=0x50,umask=0x10 01 Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_collision_vn1.ad_req uncore interconnect VN1 message lost contest for flit; REQ on AD event=0x51,umask=0x1 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_collision_vn1.ad_rsp uncore interconnect VN1 message lost contest for flit; RSP on AD event=0x51,umask=0x4 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn1.ad_snp uncore interconnect VN1 message lost contest for flit; SNP on AD event=0x51,umask=0x2 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_collision_vn1.bl_ncb uncore interconnect VN1 message lost contest for flit; NCB on BL event=0x51,umask=0x20 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_collision_vn1.bl_ncs uncore interconnect VN1 message lost contest for flit; NCS on BL event=0x51,umask=0x40 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_collision_vn1.bl_rsp uncore interconnect VN1 message lost contest for flit; RSP on BL event=0x51,umask=0x8 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn1.bl_wb uncore interconnect VN1 message lost contest for flit; WB on BL event=0x51,umask=0x10 01 Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_crd_misc.any_bgf_fifo uncore interconnect Miscellaneous Credit Events; Any In BGF FIFO event=0x60,umask=0x1 01 Indication that at least one packet (flit) is in the bgf (fifo only) unc_m3upi_rxc_crd_misc.any_bgf_path uncore interconnect Miscellaneous Credit Events; Any in BGF Path event=0x60,umask=0x2 01 Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo) unc_m3upi_rxc_crd_misc.no_d2k_for_arb uncore interconnect Miscellaneous Credit Events; No D2K For Arb event=0x60,umask=0x4 01 VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits unc_m3upi_rxc_crd_occ.d2k_crd uncore interconnect Credit Occupancy; D2K Credits event=0x61,umask=0x10 01 D2K completion fifo credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.flits_in_fifo uncore interconnect Credit Occupancy; Packets in BGF FIFO event=0x61,umask=0x2 01 Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo unc_m3upi_rxc_crd_occ.flits_in_path uncore interconnect Credit Occupancy; Packets in BGF Path event=0x61,umask=0x4 01 Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo) unc_m3upi_rxc_crd_occ.p1p_fifo uncore interconnect Credit Occupancy event=0x61,umask=0x40 01 count of bl messages in pump-1-pending state, in completion fifo only unc_m3upi_rxc_crd_occ.p1p_total uncore interconnect Credit Occupancy event=0x61,umask=0x20 01 count of bl messages in pump-1-pending state, in marker table and in fifo unc_m3upi_rxc_crd_occ.txq_crd uncore interconnect Credit Occupancy; Transmit Credits event=0x61,umask=0x8 01 Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.vna_in_use uncore interconnect Credit Occupancy; VNA In Use event=0x61,umask=0x1 01 Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles unc_m3upi_rxc_cycles_ne_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD event=0x43,umask=0x1 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD event=0x43,umask=0x4 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD event=0x43,umask=0x2 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL event=0x43,umask=0x20 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL event=0x43,umask=0x40 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL event=0x43,umask=0x8 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL event=0x43,umask=0x10 01 Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_cycles_ne_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD event=0x44,umask=0x1 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD event=0x44,umask=0x4 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD event=0x44,umask=0x2 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL event=0x44,umask=0x20 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL event=0x44,umask=0x40 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL event=0x44,umask=0x8 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL event=0x44,umask=0x10 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_flits_data_not_sent.all uncore interconnect Data Flit Not Sent; All event=0x57,umask=0x1 01 Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_data_not_sent.no_bgf uncore interconnect Data Flit Not Sent; No BGF Credits event=0x57,umask=0x2 01 Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_data_not_sent.no_txq uncore interconnect Data Flit Not Sent; No TxQ Credits event=0x57,umask=0x4 01 Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_gen_bl.p0_wait uncore interconnect Generating BL Data Flit Sequence; Wait on Pump 0 event=0x59,umask=0x1 01 generating bl data flit sequence; waiting for data pump 0 unc_m3upi_rxc_flits_gen_bl.p1p_at_limit uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x10 01 pump-1-pending logic is at capacity (pending table plus completion fifo at limit) unc_m3upi_rxc_flits_gen_bl.p1p_busy uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x8 01 pump-1-pending logic is tracking at least one message unc_m3upi_rxc_flits_gen_bl.p1p_fifo_full uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x40 01 pump-1-pending completion fifo is full unc_m3upi_rxc_flits_gen_bl.p1p_hold_p0 uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x20 01 pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage unc_m3upi_rxc_flits_gen_bl.p1p_to_limbo uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x4 01 a bl message finished but is in limbo and moved to pump-1-pending logic unc_m3upi_rxc_flits_gen_bl.p1_wait uncore interconnect Generating BL Data Flit Sequence; Wait on Pump 1 event=0x59,umask=0x2 01 generating bl data flit sequence; waiting for data pump 1 unc_m3upi_rxc_flits_misc uncore interconnect UNC_M3UPI_RxC_FLITS_MISC event=0x5a 01 unc_m3upi_rxc_flits_sent.1_msg uncore interconnect Sent Header Flit; One Message event=0x56,umask=0x1 01 One message in flit; VNA or non-VNA flit unc_m3upi_rxc_flits_sent.1_msg_vnx uncore interconnect Sent Header Flit; One Message in non-VNA event=0x56,umask=0x8 01 One message in flit; non-VNA flit unc_m3upi_rxc_flits_sent.2_msgs uncore interconnect Sent Header Flit; Two Messages event=0x56,umask=0x2 01 Two messages in flit; VNA flit unc_m3upi_rxc_flits_sent.3_msgs uncore interconnect Sent Header Flit; Three Messages event=0x56,umask=0x4 01 Three messages in flit; VNA flit unc_m3upi_rxc_flits_sent.slots_1 uncore interconnect Sent Header Flit event=0x56,umask=0x10 01 unc_m3upi_rxc_flits_sent.slots_2 uncore interconnect Sent Header Flit event=0x56,umask=0x20 01 unc_m3upi_rxc_flits_sent.slots_3 uncore interconnect Sent Header Flit event=0x56,umask=0x40 01 unc_m3upi_rxc_flits_slot_bl.all uncore interconnect Slotting BL Message Into Header Flit; All event=0x58,umask=0x1 01 unc_m3upi_rxc_flits_slot_bl.need_data uncore interconnect Slotting BL Message Into Header Flit; Needs Data Flit event=0x58,umask=0x2 01 BL message requires data flit sequence unc_m3upi_rxc_flits_slot_bl.p0_wait uncore interconnect Slotting BL Message Into Header Flit; Wait on Pump 0 event=0x58,umask=0x4 01 Waiting for header pump 0 unc_m3upi_rxc_flits_slot_bl.p1_not_req uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 event=0x58,umask=0x10 01 Header pump 1 is not required for flit unc_m3upi_rxc_flits_slot_bl.p1_not_req_but_bubble uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble event=0x58,umask=0x20 01 Header pump 1 is not required for flit but flit transmission delayed unc_m3upi_rxc_flits_slot_bl.p1_not_req_not_avail uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail event=0x58,umask=0x40 01 Header pump 1 is not required for flit and not available unc_m3upi_rxc_flits_slot_bl.p1_wait uncore interconnect Slotting BL Message Into Header Flit; Wait on Pump 1 event=0x58,umask=0x8 01 Waiting for header pump 1 unc_m3upi_rxc_flit_gen_hdr1.accum uncore interconnect Flit Gen - Header 1; Accumulate event=0x53,umask=0x1 01 Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles unc_m3upi_rxc_flit_gen_hdr1.accum_read uncore interconnect Flit Gen - Header 1; Accumulate Ready event=0x53,umask=0x2 01 Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit unc_m3upi_rxc_flit_gen_hdr1.accum_wasted uncore interconnect Flit Gen - Header 1; Accumulate Wasted event=0x53,umask=0x4 01 Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_blocked uncore interconnect Flit Gen - Header 1; Run-Ahead - Blocked event=0x53,umask=0x8 01 Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked unc_m3upi_rxc_flit_gen_hdr1.ahead_msg uncore interconnect Flit Gen - Header 1; Run-Ahead - Message event=0x53,umask=0x10 01 Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit unc_m3upi_rxc_flit_gen_hdr1.par uncore interconnect Flit Gen - Header 1; Parallel Ok event=0x53,umask=0x20 01 Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr1.par_flit uncore interconnect Flit Gen - Header 1; Parallel Flit Finished event=0x53,umask=0x80 01 Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr1.par_msg uncore interconnect Flit Gen - Header 1; Parallel Message event=0x53,umask=0x40 01 Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.rmstall uncore interconnect Flit Gen - Header 2; Rate-matching Stall event=0x54,umask=0x1 01 Events related to Header Flit Generation - Set 2; Rate-matching stall injected unc_m3upi_rxc_flit_gen_hdr2.rmstall_nomsg uncore interconnect Flit Gen - Header 2; Rate-matching Stall - No Message event=0x54,umask=0x2 01 Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle unc_m3upi_rxc_flit_not_sent.all uncore interconnect Header Not Sent; All event=0x55,umask=0x1 01 header flit is ready for transmission but could not be sent unc_m3upi_rxc_flit_not_sent.no_bgf_crd uncore interconnect Header Not Sent; No BGF Credits event=0x55,umask=0x2 01 header flit is ready for transmission but could not be sent; No BGF credits available unc_m3upi_rxc_flit_not_sent.no_bgf_no_msg uncore interconnect Header Not Sent; No BGF Credits + No Extra Message Slotted event=0x55,umask=0x8 01 header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit unc_m3upi_rxc_flit_not_sent.no_txq_crd uncore interconnect Header Not Sent; No TxQ Credits event=0x55,umask=0x4 01 header flit is ready for transmission but could not be sent; No TxQ credits available unc_m3upi_rxc_flit_not_sent.no_txq_no_msg uncore interconnect Header Not Sent; No TxQ Credits + No Extra Message Slotted event=0x55,umask=0x10 01 header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit unc_m3upi_rxc_flit_not_sent.one_taken uncore interconnect Header Not Sent; Sent - One Slot Taken event=0x55,umask=0x20 01 header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free) unc_m3upi_rxc_flit_not_sent.three_taken uncore interconnect Header Not Sent; Sent - Three Slots Taken event=0x55,umask=0x80 01 header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free) unc_m3upi_rxc_flit_not_sent.two_taken uncore interconnect Header Not Sent; Sent - Two Slots Taken event=0x55,umask=0x40 01 header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free) unc_m3upi_rxc_held.cant_slot_ad uncore interconnect Message Held; Can't Slot AD event=0x52,umask=0x40 01 some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.cant_slot_bl uncore interconnect Message Held; Can't Slot BL event=0x52,umask=0x80 01 some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_ad_lost uncore interconnect Message Held; Parallel AD Lost event=0x52,umask=0x10 01 some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_attempt uncore interconnect Message Held; Parallel Attempt event=0x52,umask=0x4 01 ad and bl messages attempted to slot into the same flit in parallel unc_m3upi_rxc_held.parallel_bl_lost uncore interconnect Message Held; Parallel BL Lost event=0x52,umask=0x20 01 some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_success uncore interconnect Message Held; Parallel Success event=0x52,umask=0x8 01 ad and bl messages were actually slotted into the same flit in parallel unc_m3upi_rxc_held.vn0 uncore interconnect Message Held; VN0 event=0x52,umask=0x1 01 vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit unc_m3upi_rxc_held.vn1 uncore interconnect Message Held; VN1 event=0x52,umask=0x2 01 vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit unc_m3upi_rxc_inserts_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; REQ on AD event=0x41,umask=0x1 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; RSP on AD event=0x41,umask=0x4 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; SNP on AD event=0x41,umask=0x2 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; NCB on BL event=0x41,umask=0x20 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; NCS on BL event=0x41,umask=0x40 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; RSP on BL event=0x41,umask=0x8 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; WB on BL event=0x41,umask=0x10 01 Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; REQ on AD event=0x42,umask=0x1 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; RSP on AD event=0x42,umask=0x4 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; SNP on AD event=0x42,umask=0x2 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; NCB on BL event=0x42,umask=0x20 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; NCS on BL event=0x42,umask=0x40 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; RSP on BL event=0x42,umask=0x8 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; WB on BL event=0x42,umask=0x10 01 Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD event=0x45,umask=0x1 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD event=0x45,umask=0x4 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD event=0x45,umask=0x2 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL event=0x45,umask=0x20 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL event=0x45,umask=0x40 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL event=0x45,umask=0x8 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; WB on BL event=0x45,umask=0x10 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD event=0x46,umask=0x1 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD event=0x46,umask=0x4 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD event=0x46,umask=0x2 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL event=0x46,umask=0x20 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL event=0x46,umask=0x40 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL event=0x46,umask=0x8 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; WB on BL event=0x46,umask=0x10 01 Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn0.ad_req uncore interconnect VN0 message can't slot into flit; REQ on AD event=0x4e,umask=0x1 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn0.ad_rsp uncore interconnect VN0 message can't slot into flit; RSP on AD event=0x4e,umask=0x4 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.ad_snp uncore interconnect VN0 message can't slot into flit; SNP on AD event=0x4e,umask=0x2 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn0.bl_ncb uncore interconnect VN0 message can't slot into flit; NCB on BL event=0x4e,umask=0x20 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn0.bl_ncs uncore interconnect VN0 message can't slot into flit; NCS on BL event=0x4e,umask=0x40 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn0.bl_rsp uncore interconnect VN0 message can't slot into flit; RSP on BL event=0x4e,umask=0x8 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.bl_wb uncore interconnect VN0 message can't slot into flit; WB on BL event=0x4e,umask=0x10 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn1.ad_req uncore interconnect VN1 message can't slot into flit; REQ on AD event=0x4f,umask=0x1 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn1.ad_rsp uncore interconnect VN1 message can't slot into flit; RSP on AD event=0x4f,umask=0x4 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.ad_snp uncore interconnect VN1 message can't slot into flit; SNP on AD event=0x4f,umask=0x2 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn1.bl_ncb uncore interconnect VN1 message can't slot into flit; NCB on BL event=0x4f,umask=0x20 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn1.bl_ncs uncore interconnect VN1 message can't slot into flit; NCS on BL event=0x4f,umask=0x40 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn1.bl_rsp uncore interconnect VN1 message can't slot into flit; RSP on BL event=0x4f,umask=0x8 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.bl_wb uncore interconnect VN1 message can't slot into flit; WB on BL event=0x4f,umask=0x10 01 Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_smi3_pftch.arb_lost uncore interconnect SMI3 Prefetch Messages; Lost Arbitration event=0x62,umask=0x2 01 unc_m3upi_rxc_smi3_pftch.arrived uncore interconnect SMI3 Prefetch Messages; Arrived event=0x62,umask=0x1 01 unc_m3upi_rxc_smi3_pftch.drop_old uncore interconnect SMI3 Prefetch Messages; Dropped - Old event=0x62,umask=0x8 01 unc_m3upi_rxc_smi3_pftch.drop_wrap uncore interconnect SMI3 Prefetch Messages; Dropped - Wrap event=0x62,umask=0x10 01 Dropped because it was overwritten by new message while prefetch queue was full unc_m3upi_rxc_smi3_pftch.slotted uncore interconnect SMI3 Prefetch Messages; Slotted event=0x62,umask=0x4 01 unc_m3upi_rxc_vna_crd.any_in_use uncore interconnect Remote VNA Credits; Any In Use event=0x5b,umask=0x20 01 At least one remote vna credit is in use unc_m3upi_rxc_vna_crd.corrected uncore interconnect Remote VNA Credits; Corrected event=0x5b,umask=0x2 01 Number of remote vna credits corrected (local return) per cycle unc_m3upi_rxc_vna_crd.lt1 uncore interconnect Remote VNA Credits; Level < 1 event=0x5b,umask=0x4 01 Remote vna credit level is less than 1 (i.e. no vna credits available) unc_m3upi_rxc_vna_crd.lt4 uncore interconnect Remote VNA Credits; Level < 4 event=0x5b,umask=0x8 01 Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna unc_m3upi_rxc_vna_crd.lt5 uncore interconnect Remote VNA Credits; Level < 5 event=0x5b,umask=0x10 01 Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible unc_m3upi_rxc_vna_crd.used uncore interconnect Remote VNA Credits; Used event=0x5b,umask=0x1 01 Number of remote vna credits consumed per cycle unc_m3upi_rxr_busy_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb4,umask=0x1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb4,umask=0x4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_bypass.ad_bnc uncore interconnect Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=0x1 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ak_bnc uncore interconnect Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=0x2 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_bnc uncore interconnect Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=0x4 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.iv_bnc uncore interconnect Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=0x8 01 Number of packets bypassing the CMS Ingress unc_m3upi_rxr_crd_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb3,umask=0x1 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ak_bnc uncore interconnect Transgress Injection Starvation; AK - Bounce event=0xb3,umask=0x2 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb3,umask=0x4 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.iv_bnc uncore interconnect Transgress Injection Starvation; IV - Bounce event=0xb3,umask=0x8 01 Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_inserts.ad_bnc uncore interconnect Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=0x1 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ak_bnc uncore interconnect Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=0x2 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_bnc uncore interconnect Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=0x4 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.iv_bnc uncore interconnect Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=0x8 01 Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_bnc uncore interconnect Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=0x1 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ak_bnc uncore interconnect Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=0x2 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_bnc uncore interconnect Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=0x4 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.iv_bnc uncore interconnect Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=0x8 01 Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=0x1 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=0x2 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=0x4 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=0x8 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20 01 Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=0x1 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=0x2 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=0x4 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=0x8 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20 01 Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=0x1 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=0x2 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=0x4 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=0x8 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20 01 Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=0x1 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=0x2 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=0x4 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=0x8 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20 01 Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_txc_ad_arb_fail.vn0_req uncore interconnect Failed ARB for AD; VN0 REQ Messages event=0x30,umask=0x1 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_rsp uncore interconnect Failed ARB for AD; VN0 RSP Messages event=0x30,umask=0x4 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_snp uncore interconnect Failed ARB for AD; VN0 SNP Messages event=0x30,umask=0x2 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_wb uncore interconnect Failed ARB for AD; VN0 WB Messages event=0x30,umask=0x8 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_req uncore interconnect Failed ARB for AD; VN1 REQ Messages event=0x30,umask=0x10 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_rsp uncore interconnect Failed ARB for AD; VN1 RSP Messages event=0x30,umask=0x40 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_snp uncore interconnect Failed ARB for AD; VN1 SNP Messages event=0x30,umask=0x20 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_wb uncore interconnect Failed ARB for AD; VN1 WB Messages event=0x30,umask=0x80 01 AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_flq_bypass.ad_slot0 uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x1 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot1 uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x2 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot2 uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x4 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.bl_early_rsp uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x8 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_cycles_ne.vn0_req uncore interconnect AD Flow Q Not Empty; VN0 REQ Messages event=0x27,umask=0x1 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_rsp uncore interconnect AD Flow Q Not Empty; VN0 RSP Messages event=0x27,umask=0x4 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_snp uncore interconnect AD Flow Q Not Empty; VN0 SNP Messages event=0x27,umask=0x2 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_wb uncore interconnect AD Flow Q Not Empty; VN0 WB Messages event=0x27,umask=0x8 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_req uncore interconnect AD Flow Q Not Empty; VN1 REQ Messages event=0x27,umask=0x10 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_rsp uncore interconnect AD Flow Q Not Empty; VN1 RSP Messages event=0x27,umask=0x40 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_snp uncore interconnect AD Flow Q Not Empty; VN1 SNP Messages event=0x27,umask=0x20 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_wb uncore interconnect AD Flow Q Not Empty; VN1 WB Messages event=0x27,umask=0x80 01 Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_inserts.vn0_req uncore interconnect AD Flow Q Inserts; VN0 REQ Messages event=0x2d,umask=0x1 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_rsp uncore interconnect AD Flow Q Inserts; VN0 RSP Messages event=0x2d,umask=0x4 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_snp uncore interconnect AD Flow Q Inserts; VN0 SNP Messages event=0x2d,umask=0x2 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_wb uncore interconnect AD Flow Q Inserts; VN0 WB Messages event=0x2d,umask=0x8 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_req uncore interconnect AD Flow Q Inserts; VN1 REQ Messages event=0x2d,umask=0x10 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_rsp uncore interconnect AD Flow Q Inserts; VN1 RSP Messages event=0x2d,umask=0x40 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_snp uncore interconnect AD Flow Q Inserts; VN1 SNP Messages event=0x2d,umask=0x20 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_occupancy.vn0_req uncore interconnect AD Flow Q Occupancy; VN0 REQ Messages event=0x1c,umask=0x1 01 unc_m3upi_txc_ad_flq_occupancy.vn0_rsp uncore interconnect AD Flow Q Occupancy; VN0 RSP Messages event=0x1c,umask=0x4 01 unc_m3upi_txc_ad_flq_occupancy.vn0_snp uncore interconnect AD Flow Q Occupancy; VN0 SNP Messages event=0x1c,umask=0x2 01 unc_m3upi_txc_ad_flq_occupancy.vn0_wb uncore interconnect AD Flow Q Occupancy; VN0 WB Messages event=0x1c,umask=0x8 01 unc_m3upi_txc_ad_flq_occupancy.vn1_req uncore interconnect AD Flow Q Occupancy; VN1 REQ Messages event=0x1c,umask=0x10 01 unc_m3upi_txc_ad_flq_occupancy.vn1_rsp uncore interconnect AD Flow Q Occupancy; VN1 RSP Messages event=0x1c,umask=0x40 01 unc_m3upi_txc_ad_flq_occupancy.vn1_snp uncore interconnect AD Flow Q Occupancy; VN1 SNP Messages event=0x1c,umask=0x20 01 unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_cha uncore interconnect Number of Snoop Targets; CHA on VN0 event=0x3c,umask=0x4 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_non_idle uncore interconnect Number of Snoop Targets; Non Idle cycles on VN0 event=0x3c,umask=0x40 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_peer_upi0 uncore interconnect Number of Snoop Targets; Peer UPI0 on VN0 event=0x3c,umask=0x1 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0 unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_peer_upi1 uncore interconnect Number of Snoop Targets; Peer UPI1 on VN0 event=0x3c,umask=0x2 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1 unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_cha uncore interconnect Number of Snoop Targets; CHA on VN1 event=0x3c,umask=0x20 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_non_idle uncore interconnect Number of Snoop Targets; Non Idle cycles on VN1 event=0x3c,umask=0x80 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_peer_upi0 uncore interconnect Number of Snoop Targets; Peer UPI0 on VN1 event=0x3c,umask=0x8 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0 unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_peer_upi1 uncore interconnect Number of Snoop Targets; Peer UPI1 on VN1 event=0x3c,umask=0x10 01 Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn0_snpfp_nonsnp uncore interconnect Snoop Arbitration; FlowQ Won event=0x3d,umask=0x1 01 Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0 unc_m3upi_txc_ad_snpf_grp2_vn1.vn0_snpfp_vn2snp uncore interconnect Snoop Arbitration; FlowQ SnpF Won event=0x3d,umask=0x4 01 Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn1_snpfp_nonsnp uncore interconnect Snoop Arbitration; FlowQ Won event=0x3d,umask=0x2 01 Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn1_snpfp_vn0snp uncore interconnect Snoop Arbitration; FlowQ SnpF Won event=0x3d,umask=0x8 01 Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0 unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_req uncore interconnect Speculative ARB for AD - Credit Available; VN0 REQ Messages event=0x34,umask=0x1 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_snp uncore interconnect Speculative ARB for AD - Credit Available; VN0 SNP Messages event=0x34,umask=0x2 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_wb uncore interconnect Speculative ARB for AD - Credit Available; VN0 WB Messages event=0x34,umask=0x8 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_req uncore interconnect Speculative ARB for AD - Credit Available; VN1 REQ Messages event=0x34,umask=0x10 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_snp uncore interconnect Speculative ARB for AD - Credit Available; VN1 SNP Messages event=0x34,umask=0x20 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_wb uncore interconnect Speculative ARB for AD - Credit Available; VN1 WB Messages event=0x34,umask=0x80 01 AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_new_msg.vn0_req uncore interconnect Speculative ARB for AD - New Message; VN0 REQ Messages event=0x33,umask=0x1 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn0_snp uncore interconnect Speculative ARB for AD - New Message; VN0 SNP Messages event=0x33,umask=0x2 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn0_wb uncore interconnect Speculative ARB for AD - New Message; VN0 WB Messages event=0x33,umask=0x8 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_req uncore interconnect Speculative ARB for AD - New Message; VN1 REQ Messages event=0x33,umask=0x10 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_snp uncore interconnect Speculative ARB for AD - New Message; VN1 SNP Messages event=0x33,umask=0x20 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_wb uncore interconnect Speculative ARB for AD - New Message; VN1 WB Messages event=0x33,umask=0x80 01 AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_req uncore interconnect Speculative ARB for AD - No Credit; VN0 REQ Messages event=0x32,umask=0x1 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_rsp uncore interconnect Speculative ARB for AD - No Credit; VN0 RSP Messages event=0x32,umask=0x4 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_snp uncore interconnect Speculative ARB for AD - No Credit; VN0 SNP Messages event=0x32,umask=0x2 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_wb uncore interconnect Speculative ARB for AD - No Credit; VN0 WB Messages event=0x32,umask=0x8 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_req uncore interconnect Speculative ARB for AD - No Credit; VN1 REQ Messages event=0x32,umask=0x10 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_rsp uncore interconnect Speculative ARB for AD - No Credit; VN1 RSP Messages event=0x32,umask=0x40 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_snp uncore interconnect Speculative ARB for AD - No Credit; VN1 SNP Messages event=0x32,umask=0x20 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_wb uncore interconnect Speculative ARB for AD - No Credit; VN1 WB Messages event=0x32,umask=0x80 01 AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ak_flq_inserts uncore interconnect AK Flow Q Inserts event=0x2f 01 unc_m3upi_txc_ak_flq_occupancy uncore interconnect AK Flow Q Occupancy event=0x1e 01 unc_m3upi_txc_bl_arb_fail.vn0_ncb uncore interconnect Failed ARB for BL; VN0 NCB Messages event=0x35,umask=0x4 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_ncs uncore interconnect Failed ARB for BL; VN0 NCS Messages event=0x35,umask=0x8 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_rsp uncore interconnect Failed ARB for BL; VN0 RSP Messages event=0x35,umask=0x1 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_wb uncore interconnect Failed ARB for BL; VN0 WB Messages event=0x35,umask=0x2 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncb uncore interconnect Failed ARB for BL; VN1 NCS Messages event=0x35,umask=0x40 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncs uncore interconnect Failed ARB for BL; VN1 NCB Messages event=0x35,umask=0x80 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_rsp uncore interconnect Failed ARB for BL; VN1 RSP Messages event=0x35,umask=0x10 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_wb uncore interconnect Failed ARB for BL; VN1 WB Messages event=0x35,umask=0x20 01 BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_flq_cycles_ne.vn0_req uncore interconnect BL Flow Q Not Empty; VN0 REQ Messages event=0x28,umask=0x1 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_rsp uncore interconnect BL Flow Q Not Empty; VN0 RSP Messages event=0x28,umask=0x4 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_snp uncore interconnect BL Flow Q Not Empty; VN0 SNP Messages event=0x28,umask=0x2 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_wb uncore interconnect BL Flow Q Not Empty; VN0 WB Messages event=0x28,umask=0x8 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_req uncore interconnect BL Flow Q Not Empty; VN1 REQ Messages event=0x28,umask=0x10 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_rsp uncore interconnect BL Flow Q Not Empty; VN1 RSP Messages event=0x28,umask=0x40 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_snp uncore interconnect BL Flow Q Not Empty; VN1 SNP Messages event=0x28,umask=0x20 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_wb uncore interconnect BL Flow Q Not Empty; VN1 WB Messages event=0x28,umask=0x80 01 Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_inserts.vn0_ncb uncore interconnect BL Flow Q Inserts; VN0 RSP Messages event=0x2e,umask=0x1 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_ncs uncore interconnect BL Flow Q Inserts; VN0 WB Messages event=0x2e,umask=0x2 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_rsp uncore interconnect BL Flow Q Inserts; VN0 NCS Messages event=0x2e,umask=0x8 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_wb uncore interconnect BL Flow Q Inserts; VN0 NCB Messages event=0x2e,umask=0x4 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncb uncore interconnect BL Flow Q Inserts; VN1 RSP Messages event=0x2e,umask=0x10 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncs uncore interconnect BL Flow Q Inserts; VN1 WB Messages event=0x2e,umask=0x20 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_rsp uncore interconnect BL Flow Q Inserts; VN1_NCB Messages event=0x2e,umask=0x80 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_wb uncore interconnect BL Flow Q Inserts; VN1_NCS Messages event=0x2e,umask=0x40 01 Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_occupancy.vn0_ncb uncore interconnect BL Flow Q Occupancy; VN0 NCB Messages event=0x1d,umask=0x4 01 unc_m3upi_txc_bl_flq_occupancy.vn0_ncs uncore interconnect BL Flow Q Occupancy; VN0 NCS Messages event=0x1d,umask=0x8 01 unc_m3upi_txc_bl_flq_occupancy.vn0_rsp uncore interconnect BL Flow Q Occupancy; VN0 RSP Messages event=0x1d,umask=0x1 01 unc_m3upi_txc_bl_flq_occupancy.vn0_wb uncore interconnect BL Flow Q Occupancy; VN0 WB Messages event=0x1d,umask=0x2 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncb uncore interconnect BL Flow Q Occupancy; VN1_NCS Messages event=0x1d,umask=0x40 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncs uncore interconnect BL Flow Q Occupancy; VN1_NCB Messages event=0x1d,umask=0x80 01 unc_m3upi_txc_bl_flq_occupancy.vn1_rsp uncore interconnect BL Flow Q Occupancy; VN1 RSP Messages event=0x1d,umask=0x10 01 unc_m3upi_txc_bl_flq_occupancy.vn1_wb uncore interconnect BL Flow Q Occupancy; VN1 WB Messages event=0x1d,umask=0x20 01 unc_m3upi_txc_bl_spec_arb_new_msg.vn0_ncb uncore interconnect Speculative ARB for BL - New Message; VN0 WB Messages event=0x38,umask=0x2 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn0_ncs uncore interconnect Speculative ARB for BL - New Message; VN0 NCS Messages event=0x38,umask=0x8 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn0_wb uncore interconnect Speculative ARB for BL - New Message; VN0 WB Messages event=0x38,umask=0x1 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_ncb uncore interconnect Speculative ARB for BL - New Message; VN1 WB Messages event=0x38,umask=0x20 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_ncs uncore interconnect Speculative ARB for BL - New Message; VN1 NCB Messages event=0x38,umask=0x80 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_wb uncore interconnect Speculative ARB for BL - New Message; VN1 RSP Messages event=0x38,umask=0x10 01 BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_ncb uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 NCB Messages event=0x37,umask=0x4 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_ncs uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 NCS Messages event=0x37,umask=0x8 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_rsp uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 RSP Messages event=0x37,umask=0x1 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_wb uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 WB Messages event=0x37,umask=0x2 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_ncb uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 NCS Messages event=0x37,umask=0x40 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_ncs uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 NCB Messages event=0x37,umask=0x80 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_rsp uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 RSP Messages event=0x37,umask=0x10 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_wb uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 WB Messages event=0x37,umask=0x20 01 BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txr_horz_ads_used.ad_bnc uncore interconnect CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=0x1 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ak_bnc uncore interconnect CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=0x2 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_bnc uncore interconnect CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=0x4 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40 01 Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_bnc uncore interconnect CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=0x1 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ak_bnc uncore interconnect CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=0x2 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_bnc uncore interconnect CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=0x4 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.iv_bnc uncore interconnect CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=0x8 01 Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_cycles_full.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=0x1 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=0x2 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=0x4 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=0x8 01 Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=0x1 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=0x2 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=0x4 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=0x8 01 Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_bnc uncore interconnect CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=0x1 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ak_bnc uncore interconnect CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=0x2 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_bnc uncore interconnect CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=0x4 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.iv_bnc uncore interconnect CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=0x8 01 Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_nack.ad_bnc uncore interconnect CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=0x1 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ak_bnc uncore interconnect CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=0x2 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_bnc uncore interconnect CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=0x4 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.iv_bnc uncore interconnect CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=0x8 01 Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_occupancy.ad_bnc uncore interconnect CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=0x1 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ak_bnc uncore interconnect CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=0x2 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_bnc uncore interconnect CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=0x4 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.iv_bnc uncore interconnect CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=0x8 01 Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_starved.ad_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=0x1 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.ak_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=0x2 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.bl_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=0x4 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.iv_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=0x8 01 Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=0x1 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=0x2 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=0x4 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40 01 Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=0x1 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=0x2 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=0x4 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.iv uncore interconnect CMS Vertical ADS Used; IV event=0x9e,umask=0x8 01 Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_cycles_full.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=0x1 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_full.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=0x2 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_full.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_full.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=0x4 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_full.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_full.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=0x8 01 Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_ne.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=0x1 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_ne.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=0x2 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_ne.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=0x4 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_ne.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_ne.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=0x8 01 Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_inserts.ad_ag0 uncore interconnect CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=0x1 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts.ad_ag1 uncore interconnect CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_inserts.ak_ag0 uncore interconnect CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=0x2 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts.ak_ag1 uncore interconnect CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_inserts.bl_ag0 uncore interconnect CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=0x4 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_inserts.bl_ag1 uncore interconnect CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_inserts.iv uncore interconnect CMS Vert Egress Allocations; IV event=0x91,umask=0x8 01 Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_nack.ad_ag0 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=0x1 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ad_ag1 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ak_ag0 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=0x2 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ak_ag1 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.bl_ag0 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=0x4 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.bl_ag1 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.iv uncore interconnect CMS Vertical Egress NACKs; IV event=0x98,umask=0x8 01 Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_occupancy.ad_ag0 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=0x1 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy.ad_ag1 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_occupancy.ak_ag0 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=0x2 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_occupancy.ak_ag1 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_occupancy.bl_ag0 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=0x4 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_occupancy.bl_ag1 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_occupancy.iv uncore interconnect CMS Vert Egress Occupancy; IV event=0x90,umask=0x8 01 Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_starved.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=0x1 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=0x2 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=0x4 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.iv uncore interconnect CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=0x8 01 Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_upi_peer_ad_credits_empty.vn0_req uncore interconnect UPI0 AD Credits Empty; VN0 REQ Messages event=0x20,umask=0x2 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_rsp uncore interconnect UPI0 AD Credits Empty; VN0 RSP Messages event=0x20,umask=0x8 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_snp uncore interconnect UPI0 AD Credits Empty; VN0 SNP Messages event=0x20,umask=0x4 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_req uncore interconnect UPI0 AD Credits Empty; VN1 REQ Messages event=0x20,umask=0x10 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_rsp uncore interconnect UPI0 AD Credits Empty; VN1 RSP Messages event=0x20,umask=0x40 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_snp uncore interconnect UPI0 AD Credits Empty; VN1 SNP Messages event=0x20,umask=0x20 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vna uncore interconnect UPI0 AD Credits Empty; VNA event=0x20,umask=0x1 01 No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_bl_credits_empty.vn0_ncs_ncb uncore interconnect UPI0 BL Credits Empty; VN0 RSP Messages event=0x21,umask=0x4 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_rsp uncore interconnect UPI0 BL Credits Empty; VN0 REQ Messages event=0x21,umask=0x2 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_wb uncore interconnect UPI0 BL Credits Empty; VN0 SNP Messages event=0x21,umask=0x8 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_ncs_ncb uncore interconnect UPI0 BL Credits Empty; VN1 RSP Messages event=0x21,umask=0x20 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_rsp uncore interconnect UPI0 BL Credits Empty; VN1 REQ Messages event=0x21,umask=0x10 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_wb uncore interconnect UPI0 BL Credits Empty; VN1 SNP Messages event=0x21,umask=0x40 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vna uncore interconnect UPI0 BL Credits Empty; VNA event=0x21,umask=0x1 01 No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_prefetch_spawn uncore interconnect Prefetches generated by the flow control queue of the M3UPI unit event=0x29 01 Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller) unc_m3upi_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use; Down and Even event=0xa6,umask=0x4 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use; Down and Odd event=0xa6,umask=0x8 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use; Up and Even event=0xa6,umask=0x1 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use; Up and Odd event=0xa6,umask=0x2 01 Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use; Down and Even event=0xa8,umask=0x4 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use; Down and Odd event=0xa8,umask=0x8 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use; Up and Even event=0xa8,umask=0x1 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use; Up and Odd event=0xa8,umask=0x2 01 Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use; Down and Even event=0xaa,umask=0x4 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use; Down and Odd event=0xaa,umask=0x8 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use; Up and Even event=0xaa,umask=0x1 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use; Up and Odd event=0xaa,umask=0x2 01 Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use; Down event=0xac,umask=0x4 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use; Up event=0xac,umask=0x1 01 Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; WB on BL event=0x5c,umask=0x10 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCB on BL event=0x5c,umask=0x20 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_credits_used.req uncore interconnect VN0 Credit Used; REQ on AD event=0x5c,umask=0x1 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_credits_used.rsp uncore interconnect VN0 Credit Used; RSP on AD event=0x5c,umask=0x4 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP on AD event=0x5c,umask=0x2 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_credits_used.wb uncore interconnect VN0 Credit Used; RSP on BL event=0x5c,umask=0x8 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.ncb uncore interconnect VN0 No Credits; WB on BL event=0x5e,umask=0x10 01 Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_no_credits.ncs uncore interconnect VN0 No Credits; NCB on BL event=0x5e,umask=0x20 01 Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_no_credits.req uncore interconnect VN0 No Credits; REQ on AD event=0x5e,umask=0x1 01 Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_no_credits.rsp uncore interconnect VN0 No Credits; RSP on AD event=0x5e,umask=0x4 01 Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.snp uncore interconnect VN0 No Credits; SNP on AD event=0x5e,umask=0x2 01 Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_no_credits.wb uncore interconnect VN0 No Credits; RSP on BL event=0x5e,umask=0x8 01 Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.ncb uncore interconnect VN1 Credit Used; WB on BL event=0x5d,umask=0x10 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_credits_used.ncs uncore interconnect VN1 Credit Used; NCB on BL event=0x5d,umask=0x20 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_credits_used.req uncore interconnect VN1 Credit Used; REQ on AD event=0x5d,umask=0x1 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_credits_used.rsp uncore interconnect VN1 Credit Used; RSP on AD event=0x5d,umask=0x4 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.snp uncore interconnect VN1 Credit Used; SNP on AD event=0x5d,umask=0x2 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_credits_used.wb uncore interconnect VN1 Credit Used; RSP on BL event=0x5d,umask=0x8 01 Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.ncb uncore interconnect VN1 No Credits; WB on BL event=0x5f,umask=0x10 01 Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_no_credits.ncs uncore interconnect VN1 No Credits; NCB on BL event=0x5f,umask=0x20 01 Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_no_credits.req uncore interconnect VN1 No Credits; REQ on AD event=0x5f,umask=0x1 01 Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_no_credits.rsp uncore interconnect VN1 No Credits; RSP on AD event=0x5f,umask=0x4 01 Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.snp uncore interconnect VN1 No Credits; SNP on AD event=0x5f,umask=0x2 01 Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_no_credits.wb uncore interconnect VN1 No Credits; RSP on BL event=0x5f,umask=0x8 01 Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_nounit_txc_bl.drs_upi uncore interconnect This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI event=0x40,umask=0x4 11 uncore_upi unc_upi_clockticks uncore interconnect Clocks of the Intel(R) Ultra Path Interconnect (UPI) event=0x1 01 Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz unc_upi_direct_attempts.d2c uncore interconnect Data Response packets that go direct to core event=0x12,umask=0x1 01 Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA unc_upi_direct_attempts.d2k uncore interconnect This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U event=0x12,umask=0x2 11 unc_upi_direct_attempts.d2u uncore interconnect Data Response packets that go direct to Intel(R) UPI event=0x12,umask=0x2 01 Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA unc_upi_flowq_no_vna_crd.ad_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0 event=0x18,umask=0x1 01 unc_upi_flowq_no_vna_crd.ad_vna_eq1 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1 event=0x18,umask=0x2 01 unc_upi_flowq_no_vna_crd.ad_vna_eq2 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2 event=0x18,umask=0x4 01 unc_upi_flowq_no_vna_crd.ak_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0 event=0x18,umask=0x10 01 unc_upi_flowq_no_vna_crd.ak_vna_eq1 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1 event=0x18,umask=0x20 01 unc_upi_flowq_no_vna_crd.ak_vna_eq2 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2 event=0x18,umask=0x40 01 unc_upi_flowq_no_vna_crd.ak_vna_eq3 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3 event=0x18,umask=0x80 01 unc_upi_flowq_no_vna_crd.bl_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0 event=0x18,umask=0x8 01 unc_upi_l1_power_cycles uncore interconnect Cycles Intel(R) UPI is in L1 power mode (shutdown) event=0x21 01 Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown unc_upi_m3_byp_blocked.bgf_crd uncore interconnect UNC_UPI_M3_BYP_BLOCKED.BGF_CRD event=0x14,umask=0x8 01 unc_upi_m3_byp_blocked.flowq_ad_vna_le2 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2 event=0x14,umask=0x1 01 unc_upi_m3_byp_blocked.flowq_ak_vna_le3 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3 event=0x14,umask=0x4 01 unc_upi_m3_byp_blocked.flowq_bl_vna_eq0 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0 event=0x14,umask=0x2 01 unc_upi_m3_byp_blocked.gv_block uncore interconnect UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK event=0x14,umask=0x10 01 unc_upi_m3_crd_return_blocked uncore interconnect UNC_UPI_M3_CRD_RETURN_BLOCKED event=0x16 01 unc_upi_m3_rxq_blocked.bgf_crd uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD event=0x15,umask=0x20 01 unc_upi_m3_rxq_blocked.flowq_ad_vna_btw_2_thresh uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH event=0x15,umask=0x2 01 unc_upi_m3_rxq_blocked.flowq_ad_vna_le2 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2 event=0x15,umask=0x1 01 unc_upi_m3_rxq_blocked.flowq_ak_vna_le3 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3 event=0x15,umask=0x10 01 unc_upi_m3_rxq_blocked.flowq_bl_vna_btw_0_thresh uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH event=0x15,umask=0x8 01 unc_upi_m3_rxq_blocked.flowq_bl_vna_eq0 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0 event=0x15,umask=0x4 01 unc_upi_m3_rxq_blocked.gv_block uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK event=0x15,umask=0x40 01 unc_upi_phy_init_cycles uncore interconnect Cycles where phy is not in L0, L0c, L0p, L1 event=0x20 01 unc_upi_power_l1_nack uncore interconnect L1 Req Nack event=0x23 01 Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_power_l1_req uncore interconnect L1 Req (same as L1 Ack) event=0x22 01 Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_req_slot2_from_m3.ack uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.ACK event=0x46,umask=0x8 01 unc_upi_req_slot2_from_m3.vn0 uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VN0 event=0x46,umask=0x2 01 unc_upi_req_slot2_from_m3.vn1 uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VN1 event=0x46,umask=0x4 01 unc_upi_req_slot2_from_m3.vna uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VNA event=0x46,umask=0x1 01 unc_upi_rxl0p_power_cycles uncore interconnect Cycles the Rx of the Intel(R) UPI is in L0p power mode event=0x25 01 Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_rxl0_power_cycles uncore interconnect Cycles in L0. Receive side event=0x24 01 Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Bypass event=0x5,umask=0xe 01 Match Message Class - NCB unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Bypass event=0x5,umask=0x10e 01 Match Message Class - NCB unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Standard event=0x5,umask=0xf 01 Match Message Class - NCS unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Standard event=0x5,umask=0x10f 01 Match Message Class - NCS unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port; Request event=0x5,umask=0x8 01 REQ Message Class unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port; Request Opcode event=0x5,umask=0x108 01 Match REQ Opcodes - Specified in Umask[7:4] unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port; Response - Conflict event=0x5,umask=0x1aa 01 unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port; Response - Invalid event=0x5,umask=0x12a 01 unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port; Response - Data event=0x5,umask=0xc 01 Match Message Class -WB unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port; Response - Data event=0x5,umask=0x10c 01 Match Message Class -WB unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port; Response - No Data event=0x5,umask=0xa 01 Match Message Class - RSP unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port; Response - No Data event=0x5,umask=0x10a 01 Match Message Class - RSP unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port; Snoop event=0x5,umask=0x9 01 SNP Message Class unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port; Snoop Opcode event=0x5,umask=0x109 01 Match SNP Opcodes - Specified in Umask[7:4] unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port; Writeback event=0x5,umask=0xd 01 Match Message Class -WB unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port; Writeback event=0x5,umask=0x10d 01 Match Message Class -WB unc_upi_rxl_bypassed.slot0 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=0x1 01 Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot1 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=0x2 01 Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot2 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=0x4 01 Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_credits_consumed_vn0 uncore interconnect VN0 Credit Consumed event=0x39 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vn1 uncore interconnect VN1 Credit Consumed event=0x3a 01 Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x38 01 Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_data uncore interconnect Valid data FLITs received from any slot event=0x3,umask=0xf 01 Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=0x3,umask=0x27 01 Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.data uncore interconnect Valid Flits Received; Data event=0x3,umask=0x8 01 Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received; Idle event=0x3,umask=0x47 01 Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received; LLCRD Not Empty event=0x3,umask=0x10 01 Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received; LLCTRL event=0x3,umask=0x40 01 Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_rxl_flits.non_data uncore interconnect Protocol header and credit FLITs received from any slot event=0x3,umask=0x97 01 Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit unc_upi_rxl_flits.null uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL event=0x3,umask=0x20 11 unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received; Protocol Header event=0x3,umask=0x80 01 Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_rxl_flits.prot_hdr uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR event=0x3,umask=0x80 11 unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received; Slot 0 event=0x3,umask=0x1 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received; Slot 1 event=0x3,umask=0x2 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received; Slot 2 event=0x3,umask=0x4 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count unc_upi_rxl_hdr_match.ncb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB event=0x5,umask=0xc 11 unc_upi_rxl_hdr_match.ncs uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS event=0x5,umask=0xd 11 unc_upi_rxl_hdr_match.req uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ event=0x5,umask=0x8 11 unc_upi_rxl_hdr_match.rsp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA event=0x5,umask=0xa 11 unc_upi_rxl_hdr_match.snp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP event=0x5,umask=0x9 11 unc_upi_rxl_hdr_match.wb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB event=0x5,umask=0xb 11 unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations; Slot 0 event=0x30,umask=0x1 01 Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations; Slot 1 event=0x30,umask=0x2 01 Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations; Slot 2 event=0x30,umask=0x4 01 Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets; Slot 0 event=0x32,umask=0x1 01 Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets; Slot 1 event=0x32,umask=0x2 01 Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets; Slot 2 event=0x32,umask=0x4 01 Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_slot_bypass.s0_rxq1 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1 event=0x33,umask=0x1 01 unc_upi_rxl_slot_bypass.s0_rxq2 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2 event=0x33,umask=0x2 01 unc_upi_rxl_slot_bypass.s1_rxq0 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0 event=0x33,umask=0x4 01 unc_upi_rxl_slot_bypass.s1_rxq2 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2 event=0x33,umask=0x8 01 unc_upi_rxl_slot_bypass.s2_rxq0 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0 event=0x33,umask=0x10 01 unc_upi_rxl_slot_bypass.s2_rxq1 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1 event=0x33,umask=0x20 01 unc_upi_txl0p_clk_active.cfg_ctl uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL event=0x2a,umask=0x1 01 unc_upi_txl0p_clk_active.dfx uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.DFX event=0x2a,umask=0x40 01 unc_upi_txl0p_clk_active.retry uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RETRY event=0x2a,umask=0x20 01 unc_upi_txl0p_clk_active.rxq uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ event=0x2a,umask=0x2 01 unc_upi_txl0p_clk_active.rxq_bypass uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS event=0x2a,umask=0x4 01 unc_upi_txl0p_clk_active.rxq_cred uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED event=0x2a,umask=0x8 01 unc_upi_txl0p_clk_active.spare uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.SPARE event=0x2a,umask=0x80 01 unc_upi_txl0p_clk_active.txq uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.TXQ event=0x2a,umask=0x10 01 unc_upi_txl0p_power_cycles uncore interconnect Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode event=0x27 01 Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_txl0p_power_cycles_ll_enter uncore interconnect UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER event=0x28 01 unc_upi_txl0p_power_cycles_m3_exit uncore interconnect UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT event=0x29 01 unc_upi_txl0_power_cycles uncore interconnect Cycles in L0. Transmit side event=0x26 01 Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Bypass event=0x4,umask=0xe 01 Match Message Class - NCB unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Bypass event=0x4,umask=0x10e 01 Match Message Class - NCB unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Standard event=0x4,umask=0xf 01 Match Message Class - NCS unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Standard event=0x4,umask=0x10f 01 Match Message Class - NCS unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port; Request event=0x4,umask=0x8 01 REQ Message Class unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port; Request Opcode event=0x4,umask=0x108 01 Match REQ Opcodes - Specified in Umask[7:4] unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port; Response - Conflict event=0x4,umask=0x1aa 01 unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port; Response - Invalid event=0x4,umask=0x12a 01 unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port; Response - Data event=0x4,umask=0xc 01 Match Message Class -WB unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port; Response - Data event=0x4,umask=0x10c 01 Match Message Class -WB unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port; Response - No Data event=0x4,umask=0xa 01 Match Message Class - RSP unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port; Response - No Data event=0x4,umask=0x10a 01 Match Message Class - RSP unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port; Snoop event=0x4,umask=0x9 01 SNP Message Class unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port; Snoop Opcode event=0x4,umask=0x109 01 Match SNP Opcodes - Specified in Umask[7:4] unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port; Writeback event=0x4,umask=0xd 01 Match Message Class -WB unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port; Writeback event=0x4,umask=0x10d 01 Match Message Class -WB unc_upi_txl_bypassed uncore interconnect FLITs that bypassed the TxL Buffer event=0x41 01 Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link unc_upi_txl_flits.all_data uncore interconnect Valid data FLITs transmitted via any slot event=0x2,umask=0xf 01 Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit unc_upi_txl_flits.all_null uncore interconnect Null FLITs transmitted from any slot event=0x2,umask=0x27 01 Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit unc_upi_txl_flits.data uncore interconnect Valid Flits Sent; Data event=0x2,umask=0x8 01 Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_txl_flits.idle uncore interconnect Idle FLITs transmitted event=0x2,umask=0x47 01 Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent; LLCRD Not Empty event=0x2,umask=0x10 01 Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent; LLCTRL event=0x2,umask=0x40 01 Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_txl_flits.non_data uncore interconnect Protocol header and credit FLITs transmitted across any slot event=0x2,umask=0x97 01 Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit unc_upi_txl_flits.null uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL event=0x2,umask=0x20 11 unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent; Protocol Header event=0x2,umask=0x80 01 Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_txl_flits.prot_hdr uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR event=0x2,umask=0x80 11 unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent; Slot 0 event=0x2,umask=0x1 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent; Slot 1 event=0x2,umask=0x2 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent; Slot 2 event=0x2,umask=0x4 01 Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count unc_upi_txl_hdr_match.data_hdr uncore interconnect This event is deprecated event=0x4 11 unc_upi_txl_hdr_match.dual_slot_hdr uncore interconnect This event is deprecated event=0x4 11 unc_upi_txl_hdr_match.loc uncore interconnect This event is deprecated event=0x4 11 unc_upi_txl_hdr_match.ncb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB event=0x4,umask=0xe 11 unc_upi_txl_hdr_match.ncs uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS event=0x4,umask=0xf 11 unc_upi_txl_hdr_match.non_data_hdr uncore interconnect This event is deprecated event=0x4 11 unc_upi_txl_hdr_match.rem uncore interconnect This event is deprecated event=0x4 11 unc_upi_txl_hdr_match.req uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ event=0x4,umask=0x8 11 unc_upi_txl_hdr_match.rsp_data uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA event=0x4,umask=0xc 11 unc_upi_txl_hdr_match.rsp_nodata uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA event=0x4,umask=0xa 11 unc_upi_txl_hdr_match.sgl_slot_hdr uncore interconnect This event is deprecated event=0x4 11 unc_upi_txl_hdr_match.snp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP event=0x4,umask=0x9 11 unc_upi_txl_hdr_match.wb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB event=0x4,umask=0xc 11 unc_upi_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=0x40 01 Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=0x42 01 Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_upi_vna_credit_return_blocked_vn01 uncore interconnect UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01 event=0x45 01 unc_upi_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x44 01 Number of VNA credits in the Rx side that are waitng to be returned back across the link unc_u_event_msg.doorbell_rcvd uncore interconnect Message Received event=0x42,umask=0x8 01 Virtual Logical Wire (legacy) message were received from Uncore unc_u_event_msg.int_prio uncore interconnect Message Received event=0x42,umask=0x10 01 Virtual Logical Wire (legacy) message were received from Uncore unc_u_event_msg.ipi_rcvd uncore interconnect Message Received; IPI event=0x42,umask=0x4 01 Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts unc_u_event_msg.msi_rcvd uncore interconnect Message Received; MSI event=0x42,umask=0x2 01 Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only) unc_u_event_msg.vlw_rcvd uncore interconnect Message Received; VLW event=0x42,umask=0x1 01 Virtual Logical Wire (legacy) message were received from Uncore unc_u_lock_cycles uncore interconnect IDI Lock/SplitLock Cycles event=0x44 01 Number of times an IDI Lock/SplitLock sequence was started unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack; Assert to ACK event=0x45,umask=0x1 01 PHOLD cycles unc_u_racu_drng.pftch_buf_empty uncore interconnect UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY event=0x4c,umask=0x4 01 unc_u_racu_drng.rdrand uncore interconnect UNC_U_RACU_DRNG.RDRAND event=0x4c,umask=0x1 01 unc_u_racu_drng.rdseed uncore interconnect UNC_U_RACU_DRNG.RDSEED event=0x4c,umask=0x2 01 upi_data_bandwidth_tx uncore interconnect UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data event=0x2,umask=0xf 017.11E-06Bytes Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit uncore_iio llc_misses.pcie_read uncore io PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x4,ch_mask=0x1f 014Bytes Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus llc_misses.pcie_write uncore io PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x1,ch_mask=0x1f 014Bytes Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_clockticks uncore io Clockticks of the IIO Traffic Controller event=0x1 01 Counts clockticks of the 1GHz traffic controller clock in the IIO unit unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-3 event=0xc2,ch_mask=0x0f,fc_mask=0x4,umask=0x3 01 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=0x01,fc_mask=0x4,umask=0x3 01 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=0x02,fc_mask=0x4,umask=0x3 01 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=0x04,fc_mask=0x4,umask=0x3 01 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=0x08,fc_mask=0x4,umask=0x3 01 unc_iio_comp_buf_inserts.port0 uncore io PCIe Completion Buffer Inserts; Port 0 event=0xc2,ch_mask=0x01,fc_mask=0x7,umask=0x4 01 unc_iio_comp_buf_inserts.port1 uncore io PCIe Completion Buffer Inserts; Port 1 event=0xc2,ch_mask=0x02,fc_mask=0x7,umask=0x4 01 unc_iio_comp_buf_inserts.port2 uncore io PCIe Completion Buffer Inserts; Port 2 event=0xc2,ch_mask=0x04,fc_mask=0x7,umask=0x4 01 unc_iio_comp_buf_inserts.port3 uncore io PCIe Completion Buffer Inserts; Port 3 event=0xc2,ch_mask=0x08,fc_mask=0x7,umask=0x4 01 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io PCIe Completion Buffer occupancy of completions with data: Part 0-3 event=0xd5,fc_mask=0x04,umask=0xf 01 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer occupancy of completions with data: Part 0 event=0xd5,fc_mask=0x04,umask=0x1 01 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer occupancy of completions with data: Part 1 event=0xd5,fc_mask=0x04,umask=0x2 01 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer occupancy of completions with data: Part 2 event=0xd5,fc_mask=0x04,umask=0x4 01 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer occupancy of completions with data: Part 3 event=0xd5,fc_mask=0x04,umask=0x8 01 unc_iio_data_req_by_cpu.cfg_read.part0 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_read.part1 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_read.part2 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_read.part3 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.cfg_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.cfg_write.part0 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_write.part1 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_write.part2 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_write.part3 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.cfg_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.io_read.part0 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_read.part1 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_read.part2 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_read.part3 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.io_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x80 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.io_write.part0 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_write.part1 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_write.part2 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_write.part3 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.io_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Read request for 4 bytes made by the CPU to IIO Part0 event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part1 uncore io Read request for 4 bytes made by the CPU to IIO Part1 event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part2 uncore io Read request for 4 bytes made by the CPU to IIO Part2 event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part3 uncore io Read request for 4 bytes made by the CPU to IIO Part3 event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.mem_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Write request of 4 bytes made to IIO Part0 by the CPU event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part1 uncore io Write request of 4 bytes made to IIO Part1 by the CPU event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part2 uncore io Write request of 4 bytes made to IIO Part2 by the CPU event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part3 uncore io Write request of 4 bytes made to IIO Part3 by the CPU event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.mem_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1 event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2 event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3 event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.vtd0 uncore io Data requested by the CPU; Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.peer_read.vtd1 uncore io Data requested by the CPU; Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.vtd0 uncore io Data requested by the CPU; Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.peer_write.vtd1 uncore io Data requested by the CPU; Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_of_cpu.atomic.part0 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomic.part1 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomic.part2 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomic.part3 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.atomic.vtd0 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.atomic.vtd1 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.atomiccmp.part0 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomiccmp.part1 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomiccmp.part2 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomiccmp.part3 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x20 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part0 uncore io PCI Express bandwidth reading at IIO, part 0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part1 uncore io PCI Express bandwidth reading at IIO, part 1 event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part2 uncore io PCI Express bandwidth reading at IIO, part 2 event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part3 uncore io PCI Express bandwidth reading at IIO, part 3 event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.vtd0 uncore io Data requested of the CPU; Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.mem_read.vtd1 uncore io Data requested of the CPU; Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.mem_write.part0 uncore io PCI Express bandwidth writing at IIO, part 0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part1 uncore io PCI Express bandwidth writing at IIO, part 1 event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part2 uncore io PCI Express bandwidth writing at IIO, part 2 event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part3 uncore io PCI Express bandwidth writing at IIO, part 3 event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.vtd0 uncore io Data requested of the CPU; Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.mem_write.vtd1 uncore io Data requested of the CPU; Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.msg.part0 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.msg.part1 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.msg.part2 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.msg.part3 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.msg.vtd0 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.msg.vtd1 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.vtd0 uncore io Data requested of the CPU; Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.peer_read.vtd1 uncore io Data requested of the CPU; Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.vtd0 uncore io Data requested of the CPU; Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.peer_write.vtd1 uncore io Data requested of the CPU; Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_link_num_corr_err uncore io Num Link Correctable Errors event=0xf 01 unc_iio_link_num_retries uncore io Num Link Retries event=0xe 01 unc_iio_mask_match uncore io Number packets that passed the Mask/Match Filter event=0x21 01 unc_iio_mask_match_and.bus0 uncore io AND Mask/match for debug bus; Non-PCIE bus event=0x2,umask=0x1 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_bus1 uncore io AND Mask/match for debug bus; Non-PCIE bus and PCIE bus event=0x2,umask=0x8 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_not_bus1 uncore io AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus) event=0x2,umask=0x4 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.bus1 uncore io AND Mask/match for debug bus; PCIE bus event=0x2,umask=0x2 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_bus1 uncore io AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus event=0x2,umask=0x10 01 Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_not_bus1 uncore io AND Mask/match for debug bus event=0x2,umask=0x20 01 Asserted if all bits specified by mask match unc_iio_mask_match_or.bus0 uncore io OR Mask/match for debug bus; Non-PCIE bus event=0x3,umask=0x1 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_bus1 uncore io OR Mask/match for debug bus; Non-PCIE bus and PCIE bus event=0x3,umask=0x8 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_not_bus1 uncore io OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus) event=0x3,umask=0x4 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.bus1 uncore io OR Mask/match for debug bus; PCIE bus event=0x3,umask=0x2 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_bus1 uncore io OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus event=0x3,umask=0x10 01 Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_not_bus1 uncore io OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus) event=0x3,umask=0x20 01 Asserted if any bits specified by mask match unc_iio_nothing uncore io Counting disabled event=0 01 unc_iio_payload_bytes_in.atomic.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0 event=0x83,ch_mask=0x1,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1 event=0x83,ch_mask=0x2,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2 event=0x83,ch_mask=0x4,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3 event=0x83,ch_mask=0x8,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0 event=0x83,ch_mask=0x10,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_in.atomic.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1 event=0x83,ch_mask=0x20,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_in.atomiccmp.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0 event=0x83,ch_mask=0x1,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_in.atomiccmp.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1 event=0x83,ch_mask=0x2,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_in.atomiccmp.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2 event=0x83,ch_mask=0x4,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_in.atomiccmp.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3 event=0x83,ch_mask=0x8,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_in.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 event=0x83,ch_mask=0x1,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_in.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 event=0x83,ch_mask=0x2,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_in.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 event=0x83,ch_mask=0x4,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_in.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 event=0x83,ch_mask=0x8,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_in.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0 event=0x83,ch_mask=0x10,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_in.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1 event=0x83,ch_mask=0x20,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_in.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 event=0x83,ch_mask=0x1,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_in.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 event=0x83,ch_mask=0x2,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_in.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 event=0x83,ch_mask=0x4,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_in.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 event=0x83,ch_mask=0x8,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_in.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0 event=0x83,ch_mask=0x10,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_in.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1 event=0x83,ch_mask=0x20,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_in.msg.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0 event=0x83,ch_mask=0x1,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_in.msg.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1 event=0x83,ch_mask=0x2,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_in.msg.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2 event=0x83,ch_mask=0x4,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_in.msg.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3 event=0x83,ch_mask=0x8,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_in.msg.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0 event=0x83,ch_mask=0x10,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_in.msg.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1 event=0x83,ch_mask=0x20,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_in.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0 event=0x83,ch_mask=0x1,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_in.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1 event=0x83,ch_mask=0x2,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_in.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2 event=0x83,ch_mask=0x4,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_in.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3 event=0x83,ch_mask=0x8,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_in.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0 event=0x83,ch_mask=0x10,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_in.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1 event=0x83,ch_mask=0x20,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_in.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0 event=0x83,ch_mask=0x1,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_in.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1 event=0x83,ch_mask=0x2,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_in.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2 event=0x83,ch_mask=0x4,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_in.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3 event=0x83,ch_mask=0x8,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_in.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0 event=0x83,ch_mask=0x10,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_in.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1 event=0x83,ch_mask=0x20,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_out.cfg_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x40 11 unc_iio_payload_bytes_out.cfg_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_out.cfg_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x10 11 unc_iio_payload_bytes_out.io_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x80 11 unc_iio_payload_bytes_out.io_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x80 11 unc_iio_payload_bytes_out.io_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_out.io_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x20 11 unc_iio_payload_bytes_out.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_out.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_out.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_out.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_out.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_out.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x4 11 unc_iio_payload_bytes_out.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_out.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_out.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_out.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_out.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_out.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x1 11 unc_iio_payload_bytes_out.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_out.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_out.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_out.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_out.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_out.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x8 11 unc_iio_payload_bytes_out.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0 event=0xc0,ch_mask=0x1,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_out.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1 event=0xc0,ch_mask=0x2,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_out.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2 event=0xc0,ch_mask=0x4,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_out.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3 event=0xc0,ch_mask=0x8,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_out.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=0x7,umask=0x2 11 unc_iio_payload_bytes_out.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=0x7,umask=0x2 11 unc_iio_symbol_times uncore io Symbol Times on Link event=0x82 01 Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS unc_iio_txn_in.atomic.part0 uncore io This event is deprecated event=0x84,ch_mask=0x1,fc_mask=0x7,umask=0x10 11 unc_iio_txn_in.atomic.part1 uncore io This event is deprecated event=0x84,ch_mask=0x2,fc_mask=0x7,umask=0x10 11 unc_iio_txn_in.atomic.part2 uncore io This event is deprecated event=0x84,ch_mask=0x4,fc_mask=0x7,umask=0x10 11 unc_iio_txn_in.atomic.part3 uncore io This event is deprecated event=0x84,ch_mask=0x8,fc_mask=0x7,umask=0x10 11 unc_iio_txn_in.atomic.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=0x7,umask=0x10 11 unc_iio_txn_in.atomic.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=0x7,umask=0x10 11 unc_iio_txn_in.atomiccmp.part0 uncore io This event is deprecated event=0x84,ch_mask=0x1,fc_mask=0x7,umask=0x20 11 unc_iio_txn_in.atomiccmp.part1 uncore io This event is deprecated event=0x84,ch_mask=0x2,fc_mask=0x7,umask=0x20 11 unc_iio_txn_in.atomiccmp.part2 uncore io This event is deprecated event=0x84,ch_mask=0x4,fc_mask=0x7,umask=0x20 11 unc_iio_txn_in.atomiccmp.part3 uncore io This event is deprecated event=0x84,ch_mask=0x8,fc_mask=0x7,umask=0x20 11 unc_iio_txn_in.mem_read.part0 uncore io This event is deprecated event=0x84,ch_mask=0x1,fc_mask=0x7,umask=0x4 11 unc_iio_txn_in.mem_read.part1 uncore io This event is deprecated event=0x84,ch_mask=0x2,fc_mask=0x7,umask=0x4 11 unc_iio_txn_in.mem_read.part2 uncore io This event is deprecated event=0x84,ch_mask=0x4,fc_mask=0x7,umask=0x4 11 unc_iio_txn_in.mem_read.part3 uncore io This event is deprecated event=0x84,ch_mask=0x8,fc_mask=0x7,umask=0x4 11 unc_iio_txn_in.mem_read.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=0x7,umask=0x4 11 unc_iio_txn_in.mem_read.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=0x7,umask=0x4 11 unc_iio_txn_in.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 event=0x84,ch_mask=0x1,fc_mask=0x7,umask=0x1 11 unc_iio_txn_in.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 event=0x84,ch_mask=0x2,fc_mask=0x7,umask=0x1 11 unc_iio_txn_in.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 event=0x84,ch_mask=0x4,fc_mask=0x7,umask=0x1 11 unc_iio_txn_in.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 event=0x84,ch_mask=0x8,fc_mask=0x7,umask=0x1 11 unc_iio_txn_in.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0 event=0x84,ch_mask=0x10,fc_mask=0x7,umask=0x1 11 unc_iio_txn_in.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1 event=0x84,ch_mask=0x20,fc_mask=0x7,umask=0x1 11 unc_iio_txn_in.msg.part0 uncore io This event is deprecated event=0x84,ch_mask=0x1,fc_mask=0x7,umask=0x40 11 unc_iio_txn_in.msg.part1 uncore io This event is deprecated event=0x84,ch_mask=0x2,fc_mask=0x7,umask=0x40 11 unc_iio_txn_in.msg.part2 uncore io This event is deprecated event=0x84,ch_mask=0x4,fc_mask=0x7,umask=0x40 11 unc_iio_txn_in.msg.part3 uncore io This event is deprecated event=0x84,ch_mask=0x8,fc_mask=0x7,umask=0x40 11 unc_iio_txn_in.msg.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=0x7,umask=0x40 11 unc_iio_txn_in.msg.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=0x7,umask=0x40 11 unc_iio_txn_in.peer_read.part0 uncore io This event is deprecated event=0x84,ch_mask=0x1,fc_mask=0x7,umask=0x8 11 unc_iio_txn_in.peer_read.part1 uncore io This event is deprecated event=0x84,ch_mask=0x2,fc_mask=0x7,umask=0x8 11 unc_iio_txn_in.peer_read.part2 uncore io This event is deprecated event=0x84,ch_mask=0x4,fc_mask=0x7,umask=0x8 11 unc_iio_txn_in.peer_read.part3 uncore io This event is deprecated event=0x84,ch_mask=0x8,fc_mask=0x7,umask=0x8 11 unc_iio_txn_in.peer_read.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=0x7,umask=0x8 11 unc_iio_txn_in.peer_read.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=0x7,umask=0x8 11 unc_iio_txn_in.peer_write.part0 uncore io This event is deprecated event=0x84,ch_mask=0x1,fc_mask=0x7,umask=0x2 11 unc_iio_txn_in.peer_write.part1 uncore io This event is deprecated event=0x84,ch_mask=0x2,fc_mask=0x7,umask=0x2 11 unc_iio_txn_in.peer_write.part2 uncore io This event is deprecated event=0x84,ch_mask=0x4,fc_mask=0x7,umask=0x2 11 unc_iio_txn_in.peer_write.part3 uncore io This event is deprecated event=0x84,ch_mask=0x8,fc_mask=0x7,umask=0x2 11 unc_iio_txn_in.peer_write.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=0x7,umask=0x2 11 unc_iio_txn_in.peer_write.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=0x7,umask=0x2 11 unc_iio_txn_out.cfg_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x40 11 unc_iio_txn_out.cfg_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x40 11 unc_iio_txn_out.cfg_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x40 11 unc_iio_txn_out.cfg_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x40 11 unc_iio_txn_out.cfg_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x40 11 unc_iio_txn_out.cfg_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=0x7,umask=0x40 11 unc_iio_txn_out.cfg_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x10 11 unc_iio_txn_out.cfg_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x10 11 unc_iio_txn_out.cfg_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x10 11 unc_iio_txn_out.cfg_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x10 11 unc_iio_txn_out.cfg_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x10 11 unc_iio_txn_out.io_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x80 11 unc_iio_txn_out.io_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x80 11 unc_iio_txn_out.io_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x80 11 unc_iio_txn_out.io_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x80 11 unc_iio_txn_out.io_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x80 11 unc_iio_txn_out.io_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=0x7,umask=0x80 11 unc_iio_txn_out.io_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x20 11 unc_iio_txn_out.io_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x20 11 unc_iio_txn_out.io_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x20 11 unc_iio_txn_out.io_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x20 11 unc_iio_txn_out.io_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x20 11 unc_iio_txn_out.io_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=0x7,umask=0x20 11 unc_iio_txn_out.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x4 11 unc_iio_txn_out.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x4 11 unc_iio_txn_out.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x4 11 unc_iio_txn_out.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x4 11 unc_iio_txn_out.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x4 11 unc_iio_txn_out.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=0x7,umask=0x4 11 unc_iio_txn_out.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x1 11 unc_iio_txn_out.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x1 11 unc_iio_txn_out.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x1 11 unc_iio_txn_out.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x1 11 unc_iio_txn_out.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x1 11 unc_iio_txn_out.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=0x7,umask=0x1 11 unc_iio_txn_out.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x8 11 unc_iio_txn_out.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x8 11 unc_iio_txn_out.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x8 11 unc_iio_txn_out.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x8 11 unc_iio_txn_out.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x8 11 unc_iio_txn_out.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=0x7,umask=0x8 11 unc_iio_txn_out.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0 event=0xc1,ch_mask=0x1,fc_mask=0x7,umask=0x2 11 unc_iio_txn_out.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1 event=0xc1,ch_mask=0x2,fc_mask=0x7,umask=0x2 11 unc_iio_txn_out.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2 event=0xc1,ch_mask=0x4,fc_mask=0x7,umask=0x2 11 unc_iio_txn_out.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3 event=0xc1,ch_mask=0x8,fc_mask=0x7,umask=0x2 11 unc_iio_txn_out.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=0x7,umask=0x2 11 unc_iio_txn_out.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=0x7,umask=0x2 11 unc_iio_txn_req_by_cpu.cfg_read.part0 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_read.part1 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_read.part2 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_read.part3 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.cfg_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.cfg_write.part0 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_write.part1 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_write.part2 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_write.part3 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.cfg_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.io_read.part0 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_read.part1 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_read.part2 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_read.part3 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.io_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x80 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.io_write.part0 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_write.part1 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_write.part2 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_write.part3 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.io_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x20 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part0 event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part1 event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part2 event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part3 event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.mem_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.mem_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0 event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1 event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2 event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3 event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.vtd0 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.peer_read.vtd1 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.vtd0 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.peer_write.vtd1 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_of_cpu.atomic.part0 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomic.part1 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomic.part2 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomic.part3 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.atomic.vtd0 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.atomic.vtd1 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.atomiccmp.part0 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomiccmp.part1 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomiccmp.part2 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomiccmp.part3 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x20 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.vtd0 uncore io Number Transactions requested of the CPU; Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.mem_read.vtd1 uncore io Number Transactions requested of the CPU; Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.vtd0 uncore io Number Transactions requested of the CPU; Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.mem_write.vtd1 uncore io Number Transactions requested of the CPU; Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.msg.part0 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.msg.part1 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.msg.part2 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.msg.part3 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.msg.vtd0 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.msg.vtd1 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.vtd0 uncore io Number Transactions requested of the CPU; Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.peer_read.vtd1 uncore io Number Transactions requested of the CPU; Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.vtd0 uncore io Number Transactions requested of the CPU; Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.peer_write.vtd1 uncore io Number Transactions requested of the CPU; Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_vtd_access.ctxt_miss uncore io VTd Access; context cache miss event=0x41,umask=0x2 01 unc_iio_vtd_access.l1_miss uncore io VTd Access; L1 miss event=0x41,umask=0x4 01 unc_iio_vtd_access.l2_miss uncore io VTd Access; L2 miss event=0x41,umask=0x8 01 unc_iio_vtd_access.l3_miss uncore io VTd Access; L3 miss event=0x41,umask=0x10 01 unc_iio_vtd_access.l4_page_hit uncore io VTd Access; Vtd hit event=0x41,umask=0x1 01 unc_iio_vtd_access.tlb1_miss uncore io VTd Access; TLB miss event=0x41,umask=0x80 01 unc_iio_vtd_access.tlb_full uncore io VTd Access; TLB is full event=0x41,umask=0x40 01 unc_iio_vtd_access.tlb_miss uncore io VTd Access; TLB miss event=0x41,umask=0x20 01 unc_iio_vtd_occupancy uncore io VTd Occupancy event=0x40 01 llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=0x4,umask=0x3 0164Bytes Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=0x4,umask=0xc 0164Bytes Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_act_count.byp uncore memory DRAM Activate Count; Activate due to Bypass event=0x1,umask=0x8 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.wr uncore memory DRAM Page Activate commands sent due to a write request event=0x1,umask=0x2 01 Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command unc_m_cas_count.all uncore memory All DRAM CAS Commands issued event=0x4,umask=0xf 01 Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd uncore memory All DRAM Read CAS Commands issued (including underfills) event=0x4,umask=0x3 01 Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd_isoch uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode event=0x4,umask=0x40 01 unc_m_cas_count.rd_reg uncore memory All DRAM Read CAS Commands issued (does not include underfills) event=0x4,umask=0x1 01 Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd_rmm uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM event=0x4,umask=0x20 01 unc_m_cas_count.rd_underfill uncore memory DRAM Underfill Read CAS Commands issued event=0x4,umask=0x2 01 Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request) unc_m_cas_count.rd_wmm uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM event=0x4,umask=0x10 01 unc_m_cas_count.wr uncore memory All DRAM Write CAS commands issued event=0x4,umask=0xc 01 Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.wr_isoch uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode event=0x4,umask=0x80 01 unc_m_cas_count.wr_rmm uncore memory DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=0x4,umask=0x8 01 Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode unc_m_cas_count.wr_wmm uncore memory DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=0x4,umask=0x4 01 Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode unc_m_clockticks uncore memory Memory controller clock ticks event=0 01 Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters unc_m_clockticks_f uncore memory Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter event=0xff 01 unc_m_majmode2.dram_cyc uncore memory UNC_M_MAJMODE2.DRAM_CYC event=0xed,umask=0x2 01 unc_m_majmode2.dram_enter uncore memory UNC_M_MAJMODE2.DRAM_ENTER event=0xed,umask=0x8 01 unc_m_majmode2.pmm_cyc uncore memory Major Mode 2 : Cycles in PMM major mode event=0xed,umask=0x1 01 unc_m_majmode2.pmm_enter uncore memory Major Mode 2 : Entered PMM major mode event=0xed,umask=0x4 01 unc_m_pmm_bandwidth.read uncore memory Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts event=0xe3 016.103515625E-5MB/sec unc_m_pmm_bandwidth.total uncore memory Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts event=0xe3 016.103515625E-5MB/sec unc_m_pmm_bandwidth.write uncore memory Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts event=0xe7 016.103515625E-5MB/sec unc_m_pmm_cmd1.all uncore memory All commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=0x1 01 unc_m_pmm_cmd1.misc uncore memory Misc Commands (error, flow ACKs) event=0xea,umask=0x80 01 unc_m_pmm_cmd1.misc_gnt uncore memory Misc GNTs event=0xea,umask=0x40 01 unc_m_pmm_cmd1.rd uncore memory Regular reads(RPQ) commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=0x2 01 All Reads - RPQ or Ufill unc_m_pmm_cmd1.rpq_gnts uncore memory RPQ GNTs event=0xea,umask=0x10 01 unc_m_pmm_cmd1.ufill_rd uncore memory Underfill read commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=0x8 01 Underfill reads unc_m_pmm_cmd1.wpq_gnts uncore memory Underfill GNTs event=0xea,umask=0x20 01 unc_m_pmm_cmd1.wr uncore memory Write commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=0x4 01 Writes unc_m_pmm_cmd2.nodata_exp uncore memory Expected No data packet (ERID matched NDP encoding) event=0xeb,umask=0x2 01 unc_m_pmm_cmd2.nodata_unexp uncore memory Unexpected No data packet (ERID matched a Read, but data was a NDP) event=0xeb,umask=0x4 01 unc_m_pmm_cmd2.opp_rd uncore memory Opportunistic Reads event=0xeb,umask=0x1 01 unc_m_pmm_cmd2.pmm_ecc_error uncore memory PMM ECC Errors event=0xeb,umask=0x20 01 unc_m_pmm_cmd2.pmm_erid_error uncore memory PMM ERID detectable parity error event=0xeb,umask=0x40 01 unc_m_pmm_cmd2.reqs_slot0 uncore memory Read Requests - Slot 0 event=0xeb,umask=0x8 01 unc_m_pmm_cmd2.reqs_slot1 uncore memory Read Requests - Slot 1 event=0xeb,umask=0x10 01 unc_m_pmm_majmode1.partial_wr_cyc uncore memory PMM Major Mode; Cycles PMM is in Partial Write Major Mode event=0xec,umask=0x4 01 unc_m_pmm_majmode1.partial_wr_enter uncore memory PMM Major Mode event=0xec,umask=0x20 01 unc_m_pmm_majmode1.partial_wr_exit uncore memory PMM Major Mode event=0xec,umask=0x40 01 unc_m_pmm_majmode1.rd_cyc uncore memory PMM Major Mode; Cycles PMM is in Read Major Mode event=0xec,umask=0x1 01 unc_m_pmm_majmode1.wr_cyc uncore memory PMM Major Mode; Cycles PMM is in Write Major Mode event=0xec,umask=0x2 01 unc_m_pmm_read_latency uncore memory Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all event=0xe0,umask=0x1 016000000000ns unc_m_pmm_rpq_cycles_full uncore memory PMM Read Queue Cycles Full event=0xe2 01 unc_m_pmm_rpq_cycles_ne uncore memory PMM Read Queue Cycles Not Empty event=0xe1 01 unc_m_pmm_rpq_inserts uncore memory Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory event=0xe3 01 unc_m_pmm_rpq_occupancy.all uncore memory Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory event=0xe0,umask=0x1 01 unc_m_pmm_rpq_occupancy.gnt_wait uncore memory PMM Occupancy event=0xe0,umask=0x4 01 unc_m_pmm_wpq_cycles_full uncore memory PMM Write Queue Cycles Full event=0xe6 01 unc_m_pmm_wpq_cycles_ne uncore memory PMM Write Queue Cycles Not Empty event=0xe5 01 unc_m_pmm_wpq_inserts uncore memory Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory event=0xe7 01 unc_m_pmm_wpq_occupancy.all uncore memory Write Pending Queue Occupancy of all write requests for Intel(R) Optane(TM) DC persistent memory event=0xe4,umask=0x1 01 unc_m_pmm_wpq_occupancy.cas uncore memory PMM Occupancy event=0xe4,umask=0x2 01 unc_m_pmm_wpq_occupancy.pwr uncore memory PMM Occupancy event=0xe4,umask=0x4 01 unc_m_pmm_wpq_pcommit uncore memory UNC_M_PMM_WPQ_PCOMMIT event=0xe8 01 unc_m_pmm_wpq_pcommit_cyc uncore memory UNC_M_PMM_WPQ_PCOMMIT_CYC event=0xe9 01 unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode+C37 event=0x85 01 Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of unc_m_power_self_refresh uncore memory Cycles Memory is in self refresh power mode event=0x43 01 Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.page_miss uncore memory Pre-charges due to page misses event=0x2,umask=0x1 01 Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration unc_m_pre_count.rd uncore memory Pre-charge for reads event=0x2,umask=0x4 01 Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page unc_m_pre_count.wr uncore memory Pre-charge for writes event=0x2,umask=0x8 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_rd_cas_rank0.allbanks uncore memory RD_CAS Access to Rank 0; All Banks event=0xb0,umask=0x10 01 unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0 01 unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=0x1 01 unc_m_rd_cas_rank0.bank10 uncore memory RD_CAS Access to Rank 0; Bank 10 event=0xb0,umask=0xa 01 unc_m_rd_cas_rank0.bank11 uncore memory RD_CAS Access to Rank 0; Bank 11 event=0xb0,umask=0xb 01 unc_m_rd_cas_rank0.bank12 uncore memory RD_CAS Access to Rank 0; Bank 12 event=0xb0,umask=0xc 01 unc_m_rd_cas_rank0.bank13 uncore memory RD_CAS Access to Rank 0; Bank 13 event=0xb0,umask=0xd 01 unc_m_rd_cas_rank0.bank14 uncore memory RD_CAS Access to Rank 0; Bank 14 event=0xb0,umask=0xe 01 unc_m_rd_cas_rank0.bank15 uncore memory RD_CAS Access to Rank 0; Bank 15 event=0xb0,umask=0xf 01 unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=0x2 01 unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=0x3 01 unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=0x4 01 unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=0x5 01 unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=0x6 01 unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=0x7 01 unc_m_rd_cas_rank0.bank8 uncore memory RD_CAS Access to Rank 0; Bank 8 event=0xb0,umask=0x8 01 unc_m_rd_cas_rank0.bank9 uncore memory RD_CAS Access to Rank 0; Bank 9 event=0xb0,umask=0x9 01 unc_m_rd_cas_rank0.bankg0 uncore memory RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb0,umask=0x11 01 unc_m_rd_cas_rank0.bankg1 uncore memory RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb0,umask=0x12 01 unc_m_rd_cas_rank0.bankg2 uncore memory RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb0,umask=0x13 01 unc_m_rd_cas_rank0.bankg3 uncore memory RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb0,umask=0x14 01 unc_m_rd_cas_rank1.allbanks uncore memory RD_CAS Access to Rank 1; All Banks event=0xb1,umask=0x10 01 unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1 01 unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=0x1 01 unc_m_rd_cas_rank1.bank10 uncore memory RD_CAS Access to Rank 1; Bank 10 event=0xb1,umask=0xa 01 unc_m_rd_cas_rank1.bank11 uncore memory RD_CAS Access to Rank 1; Bank 11 event=0xb1,umask=0xb 01 unc_m_rd_cas_rank1.bank12 uncore memory RD_CAS Access to Rank 1; Bank 12 event=0xb1,umask=0xc 01 unc_m_rd_cas_rank1.bank13 uncore memory RD_CAS Access to Rank 1; Bank 13 event=0xb1,umask=0xd 01 unc_m_rd_cas_rank1.bank14 uncore memory RD_CAS Access to Rank 1; Bank 14 event=0xb1,umask=0xe 01 unc_m_rd_cas_rank1.bank15 uncore memory RD_CAS Access to Rank 1; Bank 15 event=0xb1,umask=0xf 01 unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=0x2 01 unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=0x3 01 unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=0x4 01 unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=0x5 01 unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=0x6 01 unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=0x7 01 unc_m_rd_cas_rank1.bank8 uncore memory RD_CAS Access to Rank 1; Bank 8 event=0xb1,umask=0x8 01 unc_m_rd_cas_rank1.bank9 uncore memory RD_CAS Access to Rank 1; Bank 9 event=0xb1,umask=0x9 01 unc_m_rd_cas_rank1.bankg0 uncore memory RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb1,umask=0x11 01 unc_m_rd_cas_rank1.bankg1 uncore memory RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb1,umask=0x12 01 unc_m_rd_cas_rank1.bankg2 uncore memory RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb1,umask=0x13 01 unc_m_rd_cas_rank1.bankg3 uncore memory RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb1,umask=0x14 01 unc_m_rd_cas_rank2.allbanks uncore memory RD_CAS Access to Rank 2; All Banks event=0xb2,umask=0x10 01 unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2 01 unc_m_rd_cas_rank2.bank1 uncore memory RD_CAS Access to Rank 2; Bank 1 event=0xb2,umask=0x1 01 unc_m_rd_cas_rank2.bank10 uncore memory RD_CAS Access to Rank 2; Bank 10 event=0xb2,umask=0xa 01 unc_m_rd_cas_rank2.bank11 uncore memory RD_CAS Access to Rank 2; Bank 11 event=0xb2,umask=0xb 01 unc_m_rd_cas_rank2.bank12 uncore memory RD_CAS Access to Rank 2; Bank 12 event=0xb2,umask=0xc 01 unc_m_rd_cas_rank2.bank13 uncore memory RD_CAS Access to Rank 2; Bank 13 event=0xb2,umask=0xd 01 unc_m_rd_cas_rank2.bank14 uncore memory RD_CAS Access to Rank 2; Bank 14 event=0xb2,umask=0xe 01 unc_m_rd_cas_rank2.bank15 uncore memory RD_CAS Access to Rank 2; Bank 15 event=0xb2,umask=0xf 01 unc_m_rd_cas_rank2.bank2 uncore memory RD_CAS Access to Rank 2; Bank 2 event=0xb2,umask=0x2 01 unc_m_rd_cas_rank2.bank3 uncore memory RD_CAS Access to Rank 2; Bank 3 event=0xb2,umask=0x3 01 unc_m_rd_cas_rank2.bank4 uncore memory RD_CAS Access to Rank 2; Bank 4 event=0xb2,umask=0x4 01 unc_m_rd_cas_rank2.bank5 uncore memory RD_CAS Access to Rank 2; Bank 5 event=0xb2,umask=0x5 01 unc_m_rd_cas_rank2.bank6 uncore memory RD_CAS Access to Rank 2; Bank 6 event=0xb2,umask=0x6 01 unc_m_rd_cas_rank2.bank7 uncore memory RD_CAS Access to Rank 2; Bank 7 event=0xb2,umask=0x7 01 unc_m_rd_cas_rank2.bank8 uncore memory RD_CAS Access to Rank 2; Bank 8 event=0xb2,umask=0x8 01 unc_m_rd_cas_rank2.bank9 uncore memory RD_CAS Access to Rank 2; Bank 9 event=0xb2,umask=0x9 01 unc_m_rd_cas_rank2.bankg0 uncore memory RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3) event=0xb2,umask=0x11 01 unc_m_rd_cas_rank2.bankg1 uncore memory RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7) event=0xb2,umask=0x12 01 unc_m_rd_cas_rank2.bankg2 uncore memory RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11) event=0xb2,umask=0x13 01 unc_m_rd_cas_rank2.bankg3 uncore memory RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15) event=0xb2,umask=0x14 01 unc_m_rd_cas_rank3.allbanks uncore memory RD_CAS Access to Rank 3; All Banks event=0xb3,umask=0x10 01 unc_m_rd_cas_rank3.bank0 uncore memory RD_CAS Access to Rank 3; Bank 0 event=0xb3 01 unc_m_rd_cas_rank3.bank1 uncore memory RD_CAS Access to Rank 3; Bank 1 event=0xb3,umask=0x1 01 unc_m_rd_cas_rank3.bank10 uncore memory RD_CAS Access to Rank 3; Bank 10 event=0xb3,umask=0xa 01 unc_m_rd_cas_rank3.bank11 uncore memory RD_CAS Access to Rank 3; Bank 11 event=0xb3,umask=0xb 01 unc_m_rd_cas_rank3.bank12 uncore memory RD_CAS Access to Rank 3; Bank 12 event=0xb3,umask=0xc 01 unc_m_rd_cas_rank3.bank13 uncore memory RD_CAS Access to Rank 3; Bank 13 event=0xb3,umask=0xd 01 unc_m_rd_cas_rank3.bank14 uncore memory RD_CAS Access to Rank 3; Bank 14 event=0xb3,umask=0xe 01 unc_m_rd_cas_rank3.bank15 uncore memory RD_CAS Access to Rank 3; Bank 15 event=0xb3,umask=0xf 01 unc_m_rd_cas_rank3.bank2 uncore memory RD_CAS Access to Rank 3; Bank 2 event=0xb3,umask=0x2 01 unc_m_rd_cas_rank3.bank3 uncore memory RD_CAS Access to Rank 3; Bank 3 event=0xb3,umask=0x3 01 unc_m_rd_cas_rank3.bank4 uncore memory RD_CAS Access to Rank 3; Bank 4 event=0xb3,umask=0x4 01 unc_m_rd_cas_rank3.bank5 uncore memory RD_CAS Access to Rank 3; Bank 5 event=0xb3,umask=0x5 01 unc_m_rd_cas_rank3.bank6 uncore memory RD_CAS Access to Rank 3; Bank 6 event=0xb3,umask=0x6 01 unc_m_rd_cas_rank3.bank7 uncore memory RD_CAS Access to Rank 3; Bank 7 event=0xb3,umask=0x7 01 unc_m_rd_cas_rank3.bank8 uncore memory RD_CAS Access to Rank 3; Bank 8 event=0xb3,umask=0x8 01 unc_m_rd_cas_rank3.bank9 uncore memory RD_CAS Access to Rank 3; Bank 9 event=0xb3,umask=0x9 01 unc_m_rd_cas_rank3.bankg0 uncore memory RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3) event=0xb3,umask=0x11 01 unc_m_rd_cas_rank3.bankg1 uncore memory RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7) event=0xb3,umask=0x12 01 unc_m_rd_cas_rank3.bankg2 uncore memory RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11) event=0xb3,umask=0x13 01 unc_m_rd_cas_rank3.bankg3 uncore memory RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15) event=0xb3,umask=0x14 01 unc_m_rd_cas_rank4.allbanks uncore memory RD_CAS Access to Rank 4; All Banks event=0xb4,umask=0x10 01 unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4 01 unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=0x1 01 unc_m_rd_cas_rank4.bank10 uncore memory RD_CAS Access to Rank 4; Bank 10 event=0xb4,umask=0xa 01 unc_m_rd_cas_rank4.bank11 uncore memory RD_CAS Access to Rank 4; Bank 11 event=0xb4,umask=0xb 01 unc_m_rd_cas_rank4.bank12 uncore memory RD_CAS Access to Rank 4; Bank 12 event=0xb4,umask=0xc 01 unc_m_rd_cas_rank4.bank13 uncore memory RD_CAS Access to Rank 4; Bank 13 event=0xb4,umask=0xd 01 unc_m_rd_cas_rank4.bank14 uncore memory RD_CAS Access to Rank 4; Bank 14 event=0xb4,umask=0xe 01 unc_m_rd_cas_rank4.bank15 uncore memory RD_CAS Access to Rank 4; Bank 15 event=0xb4,umask=0xf 01 unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=0x2 01 unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=0x3 01 unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=0x4 01 unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=0x5 01 unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=0x6 01 unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=0x7 01 unc_m_rd_cas_rank4.bank8 uncore memory RD_CAS Access to Rank 4; Bank 8 event=0xb4,umask=0x8 01 unc_m_rd_cas_rank4.bank9 uncore memory RD_CAS Access to Rank 4; Bank 9 event=0xb4,umask=0x9 01 unc_m_rd_cas_rank4.bankg0 uncore memory RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xb4,umask=0x11 01 unc_m_rd_cas_rank4.bankg1 uncore memory RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xb4,umask=0x12 01 unc_m_rd_cas_rank4.bankg2 uncore memory RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xb4,umask=0x13 01 unc_m_rd_cas_rank4.bankg3 uncore memory RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xb4,umask=0x14 01 unc_m_rd_cas_rank5.allbanks uncore memory RD_CAS Access to Rank 5; All Banks event=0xb5,umask=0x10 01 unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5 01 unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=0x1 01 unc_m_rd_cas_rank5.bank10 uncore memory RD_CAS Access to Rank 5; Bank 10 event=0xb5,umask=0xa 01 unc_m_rd_cas_rank5.bank11 uncore memory RD_CAS Access to Rank 5; Bank 11 event=0xb5,umask=0xb 01 unc_m_rd_cas_rank5.bank12 uncore memory RD_CAS Access to Rank 5; Bank 12 event=0xb5,umask=0xc 01 unc_m_rd_cas_rank5.bank13 uncore memory RD_CAS Access to Rank 5; Bank 13 event=0xb5,umask=0xd 01 unc_m_rd_cas_rank5.bank14 uncore memory RD_CAS Access to Rank 5; Bank 14 event=0xb5,umask=0xe 01 unc_m_rd_cas_rank5.bank15 uncore memory RD_CAS Access to Rank 5; Bank 15 event=0xb5,umask=0xf 01 unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=0x2 01 unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=0x3 01 unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=0x4 01 unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=0x5 01 unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=0x6 01 unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=0x7 01 unc_m_rd_cas_rank5.bank8 uncore memory RD_CAS Access to Rank 5; Bank 8 event=0xb5,umask=0x8 01 unc_m_rd_cas_rank5.bank9 uncore memory RD_CAS Access to Rank 5; Bank 9 event=0xb5,umask=0x9 01 unc_m_rd_cas_rank5.bankg0 uncore memory RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xb5,umask=0x11 01 unc_m_rd_cas_rank5.bankg1 uncore memory RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xb5,umask=0x12 01 unc_m_rd_cas_rank5.bankg2 uncore memory RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xb5,umask=0x13 01 unc_m_rd_cas_rank5.bankg3 uncore memory RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xb5,umask=0x14 01 unc_m_rd_cas_rank6.allbanks uncore memory RD_CAS Access to Rank 6; All Banks event=0xb6,umask=0x10 01 unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6 01 unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=0x1 01 unc_m_rd_cas_rank6.bank10 uncore memory RD_CAS Access to Rank 6; Bank 10 event=0xb6,umask=0xa 01 unc_m_rd_cas_rank6.bank11 uncore memory RD_CAS Access to Rank 6; Bank 11 event=0xb6,umask=0xb 01 unc_m_rd_cas_rank6.bank12 uncore memory RD_CAS Access to Rank 6; Bank 12 event=0xb6,umask=0xc 01 unc_m_rd_cas_rank6.bank13 uncore memory RD_CAS Access to Rank 6; Bank 13 event=0xb6,umask=0xd 01 unc_m_rd_cas_rank6.bank14 uncore memory RD_CAS Access to Rank 6; Bank 14 event=0xb6,umask=0xe 01 unc_m_rd_cas_rank6.bank15 uncore memory RD_CAS Access to Rank 6; Bank 15 event=0xb6,umask=0xf 01 unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=0x2 01 unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=0x3 01 unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=0x4 01 unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=0x5 01 unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=0x6 01 unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=0x7 01 unc_m_rd_cas_rank6.bank8 uncore memory RD_CAS Access to Rank 6; Bank 8 event=0xb6,umask=0x8 01 unc_m_rd_cas_rank6.bank9 uncore memory RD_CAS Access to Rank 6; Bank 9 event=0xb6,umask=0x9 01 unc_m_rd_cas_rank6.bankg0 uncore memory RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xb6,umask=0x11 01 unc_m_rd_cas_rank6.bankg1 uncore memory RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xb6,umask=0x12 01 unc_m_rd_cas_rank6.bankg2 uncore memory RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xb6,umask=0x13 01 unc_m_rd_cas_rank6.bankg3 uncore memory RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xb6,umask=0x14 01 unc_m_rd_cas_rank7.allbanks uncore memory RD_CAS Access to Rank 7; All Banks event=0xb7,umask=0x10 01 unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7 01 unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=0x1 01 unc_m_rd_cas_rank7.bank10 uncore memory RD_CAS Access to Rank 7; Bank 10 event=0xb7,umask=0xa 01 unc_m_rd_cas_rank7.bank11 uncore memory RD_CAS Access to Rank 7; Bank 11 event=0xb7,umask=0xb 01 unc_m_rd_cas_rank7.bank12 uncore memory RD_CAS Access to Rank 7; Bank 12 event=0xb7,umask=0xc 01 unc_m_rd_cas_rank7.bank13 uncore memory RD_CAS Access to Rank 7; Bank 13 event=0xb7,umask=0xd 01 unc_m_rd_cas_rank7.bank14 uncore memory RD_CAS Access to Rank 7; Bank 14 event=0xb7,umask=0xe 01 unc_m_rd_cas_rank7.bank15 uncore memory RD_CAS Access to Rank 7; Bank 15 event=0xb7,umask=0xf 01 unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=0x2 01 unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=0x3 01 unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=0x4 01 unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=0x5 01 unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=0x6 01 unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=0x7 01 unc_m_rd_cas_rank7.bank8 uncore memory RD_CAS Access to Rank 7; Bank 8 event=0xb7,umask=0x8 01 unc_m_rd_cas_rank7.bank9 uncore memory RD_CAS Access to Rank 7; Bank 9 event=0xb7,umask=0x9 01 unc_m_rd_cas_rank7.bankg0 uncore memory RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xb7,umask=0x11 01 unc_m_rd_cas_rank7.bankg1 uncore memory RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xb7,umask=0x12 01 unc_m_rd_cas_rank7.bankg2 uncore memory RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xb7,umask=0x13 01 unc_m_rd_cas_rank7.bankg3 uncore memory RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xb7,umask=0x14 01 unc_m_rpq_cycles_full uncore memory Read Pending Queue Full Cycles event=0x12 01 Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries unc_m_rpq_inserts uncore memory Read Pending Queue Allocations event=0x10 01 Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ unc_m_rpq_occupancy uncore memory Read Pending Queue Occupancy event=0x80 01 Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory unc_m_sb_accesses.fm_rd_cmps uncore memory Scoreboard Accesses; Write Accepts event=0xd2,umask=0x40 01 unc_m_sb_accesses.fm_wr_cmps uncore memory Scoreboard Accesses; Write Rejects event=0xd2,umask=0x80 01 unc_m_sb_accesses.nm_rd_cmps uncore memory Scoreboard Accesses; FM read completions event=0xd2,umask=0x10 01 unc_m_sb_accesses.nm_wr_cmps uncore memory Scoreboard Accesses; FM write completions event=0xd2,umask=0x20 01 unc_m_sb_accesses.rd_accepts uncore memory Scoreboard Accesses; Read Accepts event=0xd2,umask=0x1 01 unc_m_sb_accesses.rd_rejects uncore memory Scoreboard Accesses; Read Rejects event=0xd2,umask=0x2 01 unc_m_sb_accesses.wr_accepts uncore memory Scoreboard Accesses; NM read completions event=0xd2,umask=0x4 01 unc_m_sb_accesses.wr_rejects uncore memory Scoreboard Accesses; NM write completions event=0xd2,umask=0x8 01 unc_m_sb_canary.alloc uncore memory Alloc event=0xd9,umask=0x1 01 unc_m_sb_canary.dealloc uncore memory Dealloc event=0xd9,umask=0x2 01 unc_m_sb_canary.fmrd_starved uncore memory Far Mem Read Starved event=0xd9,umask=0x40 01 unc_m_sb_canary.fmwr_starved uncore memory Far Mem Write Starved event=0xd9,umask=0x80 01 unc_m_sb_canary.nmrd_starved uncore memory Near Mem Read Starved event=0xd9,umask=0x10 01 unc_m_sb_canary.nmwr_starved uncore memory Near Mem Write Starved event=0xd9,umask=0x20 01 unc_m_sb_canary.rej uncore memory Reject event=0xd9,umask=0x4 01 unc_m_sb_canary.vld uncore memory Valid event=0xd9,umask=0x8 01 unc_m_sb_cycles_full uncore memory Scoreboard Cycles Full event=0xd1 01 unc_m_sb_cycles_ne uncore memory Scoreboard Cycles Not-Empty event=0xd0 01 unc_m_sb_inserts.block_rds uncore memory Scoreboard Inserts; Block region reads event=0xd6,umask=0x10 01 unc_m_sb_inserts.block_wrs uncore memory Scoreboard Inserts; Block region writes event=0xd6,umask=0x20 01 unc_m_sb_inserts.dealloc uncore memory Scoreboard Inserts; Dealloc all commands (for error flows) event=0xd6,umask=0x40 01 unc_m_sb_inserts.patrol uncore memory Scoreboard Inserts; Patrol inserts event=0xd6,umask=0x80 01 unc_m_sb_inserts.pmm_rds uncore memory Scoreboard Inserts; Persistent Mem reads event=0xd6,umask=0x4 01 unc_m_sb_inserts.pmm_wrs uncore memory Scoreboard Inserts; Persistent Mem writes event=0xd6,umask=0x8 01 unc_m_sb_inserts.rds uncore memory Scoreboard Inserts; Reads event=0xd6,umask=0x1 01 unc_m_sb_inserts.wrs uncore memory Scoreboard Inserts; Writes event=0xd6,umask=0x2 01 unc_m_sb_occupancy.block_rds uncore memory Scoreboard Occupancy; Block region reads event=0xd5,umask=0x20 01 unc_m_sb_occupancy.block_wrs uncore memory Scoreboard Occupancy; Block region writes event=0xd5,umask=0x40 01 unc_m_sb_occupancy.patrol uncore memory Scoreboard Occupancy; Patrol event=0xd5,umask=0x80 01 unc_m_sb_occupancy.pmm_rds uncore memory Scoreboard Occupancy; Persistent Mem reads event=0xd5,umask=0x4 01 unc_m_sb_occupancy.pmm_wrs uncore memory Scoreboard Occupancy; Persistent Mem writes event=0xd5,umask=0x8 01 unc_m_sb_occupancy.rds uncore memory Scoreboard Occupancy; Reads event=0xd5,umask=0x1 01 unc_m_sb_occupancy.wrs uncore memory Scoreboard Occupancy; Writes event=0xd5,umask=0x2 01 unc_m_sb_reject.fm_addr_cnflt uncore memory Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict event=0xd4,umask=0x2 01 unc_m_sb_reject.nm_set_cnflt uncore memory Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict event=0xd4,umask=0x1 01 unc_m_sb_reject.patrol_set_cnflt uncore memory Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict event=0xd4,umask=0x4 01 unc_m_sb_strv_alloc.fmrd_clr uncore memory Far Mem Read - Clear event=0xd7,umask=0x20 01 unc_m_sb_strv_alloc.fmrd_set uncore memory Far Mem Read - Set event=0xd7,umask=0x2 01 unc_m_sb_strv_alloc.fmwr_clr uncore memory Far Mem Write - Clear event=0xd7,umask=0x80 01 unc_m_sb_strv_alloc.fmwr_set uncore memory Far Mem Write - Set event=0xd7,umask=0x8 01 unc_m_sb_strv_alloc.nmrd_clr uncore memory Near Mem Read - Clear event=0xd7,umask=0x10 01 unc_m_sb_strv_alloc.nmrd_set uncore memory Near Mem Read - Set event=0xd7,umask=0x1 01 unc_m_sb_strv_alloc.nmwr_clr uncore memory Near Mem Write - Clear event=0xd7,umask=0x40 01 unc_m_sb_strv_alloc.nmwr_set uncore memory Near Mem Write - Set event=0xd7,umask=0x4 01 unc_m_sb_strv_occ.fmrd uncore memory Far Mem Read event=0xd8,umask=0x2 01 unc_m_sb_strv_occ.fmwr uncore memory Far Mem Write event=0xd8,umask=0x8 01 unc_m_sb_strv_occ.nmrd uncore memory Near Mem Read event=0xd8,umask=0x1 01 unc_m_sb_strv_occ.nmwr uncore memory Near Mem Write event=0xd8,umask=0x4 01 unc_m_sb_tagged.ddr4_cmp uncore memory UNC_M_SB_TAGGED.DDR4_CMP event=0xdd,umask=0x8 01 unc_m_sb_tagged.new uncore memory UNC_M_SB_TAGGED.NEW event=0xdd,umask=0x1 01 unc_m_sb_tagged.occ uncore memory UNC_M_SB_TAGGED.OCC event=0xdd,umask=0x80 01 unc_m_sb_tagged.pmm0_cmp uncore memory UNC_M_SB_TAGGED.PMM0_CMP event=0xdd,umask=0x10 01 unc_m_sb_tagged.pmm1_cmp uncore memory UNC_M_SB_TAGGED.PMM1_CMP event=0xdd,umask=0x20 01 unc_m_sb_tagged.pmm2_cmp uncore memory UNC_M_SB_TAGGED.PMM2_CMP event=0xdd,umask=0x40 01 unc_m_sb_tagged.rd_hit uncore memory UNC_M_SB_TAGGED.RD_HIT event=0xdd,umask=0x2 01 unc_m_sb_tagged.rd_miss uncore memory UNC_M_SB_TAGGED.RD_MISS event=0xdd,umask=0x4 01 unc_m_tagchk.hit uncore memory All hits to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=0x1 01 Tag Check; Hit unc_m_tagchk.miss_clean uncore memory All Clean line misses to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=0x2 01 Tag Check; Clean unc_m_tagchk.miss_dirty uncore memory All dirty line misses to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=0x4 01 Tag Check; Dirty unc_m_wpq_cycles_full uncore memory Write Pending Queue Full Cycles event=0x22 01 Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21 01 Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20 01 Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_m_wpq_occupancy uncore memory Write Pending Queue Occupancy event=0x81 01 Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_m_wr_cas_rank0.allbanks uncore memory WR_CAS Access to Rank 0; All Banks event=0xb8,umask=0x10 01 unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8 01 unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=0x1 01 unc_m_wr_cas_rank0.bank10 uncore memory WR_CAS Access to Rank 0; Bank 10 event=0xb8,umask=0xa 01 unc_m_wr_cas_rank0.bank11 uncore memory WR_CAS Access to Rank 0; Bank 11 event=0xb8,umask=0xb 01 unc_m_wr_cas_rank0.bank12 uncore memory WR_CAS Access to Rank 0; Bank 12 event=0xb8,umask=0xc 01 unc_m_wr_cas_rank0.bank13 uncore memory WR_CAS Access to Rank 0; Bank 13 event=0xb8,umask=0xd 01 unc_m_wr_cas_rank0.bank14 uncore memory WR_CAS Access to Rank 0; Bank 14 event=0xb8,umask=0xe 01 unc_m_wr_cas_rank0.bank15 uncore memory WR_CAS Access to Rank 0; Bank 15 event=0xb8,umask=0xf 01 unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=0x2 01 unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=0x3 01 unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=0x4 01 unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=0x5 01 unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=0x6 01 unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=0x7 01 unc_m_wr_cas_rank0.bank8 uncore memory WR_CAS Access to Rank 0; Bank 8 event=0xb8,umask=0x8 01 unc_m_wr_cas_rank0.bank9 uncore memory WR_CAS Access to Rank 0; Bank 9 event=0xb8,umask=0x9 01 unc_m_wr_cas_rank0.bankg0 uncore memory WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb8,umask=0x11 01 unc_m_wr_cas_rank0.bankg1 uncore memory WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb8,umask=0x12 01 unc_m_wr_cas_rank0.bankg2 uncore memory WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb8,umask=0x13 01 unc_m_wr_cas_rank0.bankg3 uncore memory WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb8,umask=0x14 01 unc_m_wr_cas_rank1.allbanks uncore memory WR_CAS Access to Rank 1; All Banks event=0xb9,umask=0x10 01 unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9 01 unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=0x1 01 unc_m_wr_cas_rank1.bank10 uncore memory WR_CAS Access to Rank 1; Bank 10 event=0xb9,umask=0xa 01 unc_m_wr_cas_rank1.bank11 uncore memory WR_CAS Access to Rank 1; Bank 11 event=0xb9,umask=0xb 01 unc_m_wr_cas_rank1.bank12 uncore memory WR_CAS Access to Rank 1; Bank 12 event=0xb9,umask=0xc 01 unc_m_wr_cas_rank1.bank13 uncore memory WR_CAS Access to Rank 1; Bank 13 event=0xb9,umask=0xd 01 unc_m_wr_cas_rank1.bank14 uncore memory WR_CAS Access to Rank 1; Bank 14 event=0xb9,umask=0xe 01 unc_m_wr_cas_rank1.bank15 uncore memory WR_CAS Access to Rank 1; Bank 15 event=0xb9,umask=0xf 01 unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=0x2 01 unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=0x3 01 unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=0x4 01 unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=0x5 01 unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=0x6 01 unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=0x7 01 unc_m_wr_cas_rank1.bank8 uncore memory WR_CAS Access to Rank 1; Bank 8 event=0xb9,umask=0x8 01 unc_m_wr_cas_rank1.bank9 uncore memory WR_CAS Access to Rank 1; Bank 9 event=0xb9,umask=0x9 01 unc_m_wr_cas_rank1.bankg0 uncore memory WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb9,umask=0x11 01 unc_m_wr_cas_rank1.bankg1 uncore memory WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb9,umask=0x12 01 unc_m_wr_cas_rank1.bankg2 uncore memory WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb9,umask=0x13 01 unc_m_wr_cas_rank1.bankg3 uncore memory WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb9,umask=0x14 01 unc_m_wr_cas_rank2.allbanks uncore memory WR_CAS Access to Rank 2; All Banks event=0xba,umask=0x10 01 unc_m_wr_cas_rank2.bank0 uncore memory WR_CAS Access to Rank 2; Bank 0 event=0xba 01 unc_m_wr_cas_rank2.bank1 uncore memory WR_CAS Access to Rank 2; Bank 1 event=0xba,umask=0x1 01 unc_m_wr_cas_rank2.bank10 uncore memory WR_CAS Access to Rank 2; Bank 10 event=0xba,umask=0xa 01 unc_m_wr_cas_rank2.bank11 uncore memory WR_CAS Access to Rank 2; Bank 11 event=0xba,umask=0xb 01 unc_m_wr_cas_rank2.bank12 uncore memory WR_CAS Access to Rank 2; Bank 12 event=0xba,umask=0xc 01 unc_m_wr_cas_rank2.bank13 uncore memory WR_CAS Access to Rank 2; Bank 13 event=0xba,umask=0xd 01 unc_m_wr_cas_rank2.bank14 uncore memory WR_CAS Access to Rank 2; Bank 14 event=0xba,umask=0xe 01 unc_m_wr_cas_rank2.bank15 uncore memory WR_CAS Access to Rank 2; Bank 15 event=0xba,umask=0xf 01 unc_m_wr_cas_rank2.bank2 uncore memory WR_CAS Access to Rank 2; Bank 2 event=0xba,umask=0x2 01 unc_m_wr_cas_rank2.bank3 uncore memory WR_CAS Access to Rank 2; Bank 3 event=0xba,umask=0x3 01 unc_m_wr_cas_rank2.bank4 uncore memory WR_CAS Access to Rank 2; Bank 4 event=0xba,umask=0x4 01 unc_m_wr_cas_rank2.bank5 uncore memory WR_CAS Access to Rank 2; Bank 5 event=0xba,umask=0x5 01 unc_m_wr_cas_rank2.bank6 uncore memory WR_CAS Access to Rank 2; Bank 6 event=0xba,umask=0x6 01 unc_m_wr_cas_rank2.bank7 uncore memory WR_CAS Access to Rank 2; Bank 7 event=0xba,umask=0x7 01 unc_m_wr_cas_rank2.bank8 uncore memory WR_CAS Access to Rank 2; Bank 8 event=0xba,umask=0x8 01 unc_m_wr_cas_rank2.bank9 uncore memory WR_CAS Access to Rank 2; Bank 9 event=0xba,umask=0x9 01 unc_m_wr_cas_rank2.bankg0 uncore memory WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3) event=0xba,umask=0x11 01 unc_m_wr_cas_rank2.bankg1 uncore memory WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7) event=0xba,umask=0x12 01 unc_m_wr_cas_rank2.bankg2 uncore memory WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11) event=0xba,umask=0x13 01 unc_m_wr_cas_rank2.bankg3 uncore memory WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15) event=0xba,umask=0x14 01 unc_m_wr_cas_rank3.allbanks uncore memory WR_CAS Access to Rank 3; All Banks event=0xbb,umask=0x10 01 unc_m_wr_cas_rank3.bank0 uncore memory WR_CAS Access to Rank 3; Bank 0 event=0xbb 01 unc_m_wr_cas_rank3.bank1 uncore memory WR_CAS Access to Rank 3; Bank 1 event=0xbb,umask=0x1 01 unc_m_wr_cas_rank3.bank10 uncore memory WR_CAS Access to Rank 3; Bank 10 event=0xbb,umask=0xa 01 unc_m_wr_cas_rank3.bank11 uncore memory WR_CAS Access to Rank 3; Bank 11 event=0xbb,umask=0xb 01 unc_m_wr_cas_rank3.bank12 uncore memory WR_CAS Access to Rank 3; Bank 12 event=0xbb,umask=0xc 01 unc_m_wr_cas_rank3.bank13 uncore memory WR_CAS Access to Rank 3; Bank 13 event=0xbb,umask=0xd 01 unc_m_wr_cas_rank3.bank14 uncore memory WR_CAS Access to Rank 3; Bank 14 event=0xbb,umask=0xe 01 unc_m_wr_cas_rank3.bank15 uncore memory WR_CAS Access to Rank 3; Bank 15 event=0xbb,umask=0xf 01 unc_m_wr_cas_rank3.bank2 uncore memory WR_CAS Access to Rank 3; Bank 2 event=0xbb,umask=0x2 01 unc_m_wr_cas_rank3.bank3 uncore memory WR_CAS Access to Rank 3; Bank 3 event=0xbb,umask=0x3 01 unc_m_wr_cas_rank3.bank4 uncore memory WR_CAS Access to Rank 3; Bank 4 event=0xbb,umask=0x4 01 unc_m_wr_cas_rank3.bank5 uncore memory WR_CAS Access to Rank 3; Bank 5 event=0xbb,umask=0x5 01 unc_m_wr_cas_rank3.bank6 uncore memory WR_CAS Access to Rank 3; Bank 6 event=0xbb,umask=0x6 01 unc_m_wr_cas_rank3.bank7 uncore memory WR_CAS Access to Rank 3; Bank 7 event=0xbb,umask=0x7 01 unc_m_wr_cas_rank3.bank8 uncore memory WR_CAS Access to Rank 3; Bank 8 event=0xbb,umask=0x8 01 unc_m_wr_cas_rank3.bank9 uncore memory WR_CAS Access to Rank 3; Bank 9 event=0xbb,umask=0x9 01 unc_m_wr_cas_rank3.bankg0 uncore memory WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3) event=0xbb,umask=0x11 01 unc_m_wr_cas_rank3.bankg1 uncore memory WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7) event=0xbb,umask=0x12 01 unc_m_wr_cas_rank3.bankg2 uncore memory WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11) event=0xbb,umask=0x13 01 unc_m_wr_cas_rank3.bankg3 uncore memory WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15) event=0xbb,umask=0x14 01 unc_m_wr_cas_rank4.allbanks uncore memory WR_CAS Access to Rank 4; All Banks event=0xbc,umask=0x10 01 unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc 01 unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=0x1 01 unc_m_wr_cas_rank4.bank10 uncore memory WR_CAS Access to Rank 4; Bank 10 event=0xbc,umask=0xa 01 unc_m_wr_cas_rank4.bank11 uncore memory WR_CAS Access to Rank 4; Bank 11 event=0xbc,umask=0xb 01 unc_m_wr_cas_rank4.bank12 uncore memory WR_CAS Access to Rank 4; Bank 12 event=0xbc,umask=0xc 01 unc_m_wr_cas_rank4.bank13 uncore memory WR_CAS Access to Rank 4; Bank 13 event=0xbc,umask=0xd 01 unc_m_wr_cas_rank4.bank14 uncore memory WR_CAS Access to Rank 4; Bank 14 event=0xbc,umask=0xe 01 unc_m_wr_cas_rank4.bank15 uncore memory WR_CAS Access to Rank 4; Bank 15 event=0xbc,umask=0xf 01 unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=0x2 01 unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=0x3 01 unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=0x4 01 unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=0x5 01 unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=0x6 01 unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=0x7 01 unc_m_wr_cas_rank4.bank8 uncore memory WR_CAS Access to Rank 4; Bank 8 event=0xbc,umask=0x8 01 unc_m_wr_cas_rank4.bank9 uncore memory WR_CAS Access to Rank 4; Bank 9 event=0xbc,umask=0x9 01 unc_m_wr_cas_rank4.bankg0 uncore memory WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xbc,umask=0x11 01 unc_m_wr_cas_rank4.bankg1 uncore memory WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xbc,umask=0x12 01 unc_m_wr_cas_rank4.bankg2 uncore memory WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xbc,umask=0x13 01 unc_m_wr_cas_rank4.bankg3 uncore memory WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xbc,umask=0x14 01 unc_m_wr_cas_rank5.allbanks uncore memory WR_CAS Access to Rank 5; All Banks event=0xbd,umask=0x10 01 unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd 01 unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=0x1 01 unc_m_wr_cas_rank5.bank10 uncore memory WR_CAS Access to Rank 5; Bank 10 event=0xbd,umask=0xa 01 unc_m_wr_cas_rank5.bank11 uncore memory WR_CAS Access to Rank 5; Bank 11 event=0xbd,umask=0xb 01 unc_m_wr_cas_rank5.bank12 uncore memory WR_CAS Access to Rank 5; Bank 12 event=0xbd,umask=0xc 01 unc_m_wr_cas_rank5.bank13 uncore memory WR_CAS Access to Rank 5; Bank 13 event=0xbd,umask=0xd 01 unc_m_wr_cas_rank5.bank14 uncore memory WR_CAS Access to Rank 5; Bank 14 event=0xbd,umask=0xe 01 unc_m_wr_cas_rank5.bank15 uncore memory WR_CAS Access to Rank 5; Bank 15 event=0xbd,umask=0xf 01 unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=0x2 01 unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=0x3 01 unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=0x4 01 unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=0x5 01 unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=0x6 01 unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=0x7 01 unc_m_wr_cas_rank5.bank8 uncore memory WR_CAS Access to Rank 5; Bank 8 event=0xbd,umask=0x8 01 unc_m_wr_cas_rank5.bank9 uncore memory WR_CAS Access to Rank 5; Bank 9 event=0xbd,umask=0x9 01 unc_m_wr_cas_rank5.bankg0 uncore memory WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xbd,umask=0x11 01 unc_m_wr_cas_rank5.bankg1 uncore memory WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xbd,umask=0x12 01 unc_m_wr_cas_rank5.bankg2 uncore memory WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xbd,umask=0x13 01 unc_m_wr_cas_rank5.bankg3 uncore memory WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xbd,umask=0x14 01 unc_m_wr_cas_rank6.allbanks uncore memory WR_CAS Access to Rank 6; All Banks event=0xbe,umask=0x10 01 unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe 01 unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=0x1 01 unc_m_wr_cas_rank6.bank10 uncore memory WR_CAS Access to Rank 6; Bank 10 event=0xbe,umask=0xa 01 unc_m_wr_cas_rank6.bank11 uncore memory WR_CAS Access to Rank 6; Bank 11 event=0xbe,umask=0xb 01 unc_m_wr_cas_rank6.bank12 uncore memory WR_CAS Access to Rank 6; Bank 12 event=0xbe,umask=0xc 01 unc_m_wr_cas_rank6.bank13 uncore memory WR_CAS Access to Rank 6; Bank 13 event=0xbe,umask=0xd 01 unc_m_wr_cas_rank6.bank14 uncore memory WR_CAS Access to Rank 6; Bank 14 event=0xbe,umask=0xe 01 unc_m_wr_cas_rank6.bank15 uncore memory WR_CAS Access to Rank 6; Bank 15 event=0xbe,umask=0xf 01 unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=0x2 01 unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=0x3 01 unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=0x4 01 unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=0x5 01 unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=0x6 01 unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=0x7 01 unc_m_wr_cas_rank6.bank8 uncore memory WR_CAS Access to Rank 6; Bank 8 event=0xbe,umask=0x8 01 unc_m_wr_cas_rank6.bank9 uncore memory WR_CAS Access to Rank 6; Bank 9 event=0xbe,umask=0x9 01 unc_m_wr_cas_rank6.bankg0 uncore memory WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xbe,umask=0x11 01 unc_m_wr_cas_rank6.bankg1 uncore memory WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xbe,umask=0x12 01 unc_m_wr_cas_rank6.bankg2 uncore memory WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xbe,umask=0x13 01 unc_m_wr_cas_rank6.bankg3 uncore memory WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xbe,umask=0x14 01 unc_m_wr_cas_rank7.allbanks uncore memory WR_CAS Access to Rank 7; All Banks event=0xbf,umask=0x10 01 unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf 01 unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=0x1 01 unc_m_wr_cas_rank7.bank10 uncore memory WR_CAS Access to Rank 7; Bank 10 event=0xbf,umask=0xa 01 unc_m_wr_cas_rank7.bank11 uncore memory WR_CAS Access to Rank 7; Bank 11 event=0xbf,umask=0xb 01 unc_m_wr_cas_rank7.bank12 uncore memory WR_CAS Access to Rank 7; Bank 12 event=0xbf,umask=0xc 01 unc_m_wr_cas_rank7.bank13 uncore memory WR_CAS Access to Rank 7; Bank 13 event=0xbf,umask=0xd 01 unc_m_wr_cas_rank7.bank14 uncore memory WR_CAS Access to Rank 7; Bank 14 event=0xbf,umask=0xe 01 unc_m_wr_cas_rank7.bank15 uncore memory WR_CAS Access to Rank 7; Bank 15 event=0xbf,umask=0xf 01 unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=0x2 01 unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=0x3 01 unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=0x4 01 unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=0x5 01 unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=0x6 01 unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=0x7 01 unc_m_wr_cas_rank7.bank8 uncore memory WR_CAS Access to Rank 7; Bank 8 event=0xbf,umask=0x8 01 unc_m_wr_cas_rank7.bank9 uncore memory WR_CAS Access to Rank 7; Bank 9 event=0xbf,umask=0x9 01 unc_m_wr_cas_rank7.bankg0 uncore memory WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xbf,umask=0x11 01 unc_m_wr_cas_rank7.bankg1 uncore memory WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xbf,umask=0x12 01 unc_m_wr_cas_rank7.bankg2 uncore memory WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xbf,umask=0x13 01 unc_m_wr_cas_rank7.bankg3 uncore memory WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xbf,umask=0x14 01 unc_p_core_transition_cycles uncore power UNC_P_CORE_TRANSITION_CYCLES event=0x60 01 unc_p_demotions uncore power UNC_P_DEMOTIONS event=0x30 01 unc_p_fivr_ps_ps0_cycles uncore power Phase Shed 0 Cycles event=0x75 01 Cycles spent in phase-shedding power state 0 unc_p_fivr_ps_ps1_cycles uncore power Phase Shed 1 Cycles event=0x76 01 Cycles spent in phase-shedding power state 1 unc_p_fivr_ps_ps2_cycles uncore power Phase Shed 2 Cycles event=0x77 01 Cycles spent in phase-shedding power state 2 unc_p_fivr_ps_ps3_cycles uncore power Phase Shed 3 Cycles event=0x78 01 Cycles spent in phase-shedding power state 3 unc_p_mcp_prochot_cycles uncore power UNC_P_MCP_PROCHOT_CYCLES event=0x6 01 unc_p_pmax_throttled_cycles uncore power UNC_P_PMAX_THROTTLED_CYCLES event=0x7 01 unc_p_vr_hot_cycles uncore power VR Hot event=0x42 01 dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=0x8,period=100003,umask=0x1 00 Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=0x8,period=2000003,umask=0x20 00 Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake event=0x8,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load dtlb_load_misses.walk_completed virtual memory Load miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x8,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_1g virtual memory Page walk completed due to a demand data load to a 1G page event=0x8,period=2000003,umask=0x8 00 Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data load to a 2M/4M page event=0x8,period=2000003,umask=0x4 00 Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walk completed due to a demand data load to a 4K page event=0x8,period=2000003,umask=0x2 00 Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake event=0x8,period=2000003,umask=0x10 00 Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=0x1 00 Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x49,period=100003,umask=0x20 00 Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake event=0x49,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed virtual memory Store misses in all TLB levels causes a page walk that completes. (All page sizes) event=0x49,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walk completed due to a demand data store to a 1G page event=0x49,period=100003,umask=0x8 00 Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=0x4 00 Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walk completed due to a demand data store to a 4K page event=0x49,period=100003,umask=0x2 00 Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake event=0x49,period=2000003,umask=0x10 00 Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture ept.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type event=0x4f,period=2000003,umask=0x10 00 Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=0x1 00 Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=0x1 00 Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x85,period=100003,umask=0x20 00 itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake event=0x85,cmask=1,period=100003,umask=0x10 00 Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture itlb_misses.walk_completed virtual memory Code miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x85,period=100003,umask=0xe 00 Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_1g virtual memory Code miss in all TLB levels causes a page walk that completes. (1G) event=0x85,period=100003,umask=0x8 00 Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x85,period=100003,umask=0x4 00 Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x85,period=100003,umask=0x2 00 Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake event=0x85,period=100003,umask=0x10 00 Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=0x1 00 Counts the number of DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.) core_reject_l2q.any cache Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition event=0x31,period=200003 00 Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis dl1.dirty_eviction cache Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches event=0x51,period=200003,umask=0x1 00 Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back l2_reject_xq.any cache Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition event=0x30,period=200003 00 Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims) l2_request.all cache Counts the total number of L2 Cache accesses. Counts on a per core basis event=0x24,period=200003 00 Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis l2_request.hit cache Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis event=0x24,period=200003,umask=0x2 00 Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis l2_request.miss cache Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis event=0x24,period=200003,umask=0x1 00 Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis l2_request.rejects cache Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis event=0x24,period=200003,umask=0x4 00 Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis mem_bound_stalls.store_buffer_full cache Counts the number of cycles the core is stalled due to a store buffer being full event=0x34,period=200003,umask=0x40 00 mem_load_uops_retired.hitm cache Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x20 00 mem_load_uops_retired.l1_hit cache Counts the number of load uops retired that hit in the L1 data cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x1 00 mem_load_uops_retired.l1_miss cache Counts the number of load uops retired that miss in the L1 data cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x8 00 mem_load_uops_retired.l2_miss cache Counts the number of load uops retired that miss in the L2 cache Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x10 00 mem_uops_retired.all cache Counts the number of memory uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x83 00 Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Supports address when precise (Precise event) mem_uops_retired.lock_loads cache Counts the number of load uops retired that performed one or more locks Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x21 00 mem_uops_retired.split cache Counts the number of memory uops retired that were splits Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x43 00 mem_uops_retired.split_stores cache Counts the number of retired split store uops Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x42 00 ocr.all_code_rd.l3_hit cache Counts all code reads that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0044 00 ocr.all_code_rd.l3_hit.snoop_hitm cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0044 00 ocr.all_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0044 00 ocr.all_code_rd.l3_hit.snoop_hit_with_fwd cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0044 00 ocr.all_code_rd.l3_hit.snoop_miss cache Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0044 00 ocr.all_code_rd.l3_hit.snoop_not_needed cache Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0044 00 ocr.corewb_m.l3_hit cache Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3001F803C0000 00 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0004 00 ocr.demand_code_rd.l3_hit.snoop_miss cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0004 00 ocr.demand_code_rd.l3_hit.snoop_not_needed cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004 00 ocr.demand_data_and_l1pf_rd.l3_hit cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hitm cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_no_fwd cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_with_fwd cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_miss cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001 00 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_not_needed cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 00 ocr.demand_data_rd.l3_hit cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0001 10 ocr.demand_data_rd.l3_hit.snoop_hitm cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 10 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 10 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 10 ocr.demand_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001 10 ocr.demand_data_rd.l3_hit.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 10 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_with_fwd cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0002 00 ocr.demand_rfo.l3_hit.snoop_miss cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0002 00 ocr.demand_rfo.l3_hit.snoop_not_needed cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002 00 ocr.full_streaming_wr.l3_hit cache Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801F803C0000 00 ocr.hwpf_l1d_and_swpf.l3_hit.snoop_hitm cache Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0400 00 ocr.hwpf_l2_code_rd.l3_hit cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0040 00 ocr.hwpf_l2_code_rd.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0040 00 ocr.hwpf_l2_data_rd.l3_hit cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010 00 ocr.hwpf_l2_rfo.l3_hit cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020 00 ocr.l1wb_m.l3_hit cache Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001F803C0000 00 ocr.l2wb_m.l3_hit cache Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001F803C0000 00 ocr.partial_streaming_wr.l3_hit cache Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401F803C0000 00 ocr.reads_to_core.l3_hit cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0477 00 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0477 00 ocr.reads_to_core.l3_hit.snoop_miss cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0477 00 ocr.reads_to_core.l3_hit.snoop_not_needed cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0477 00 ocr.streaming_wr.l3_hit cache Counts streaming stores that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0800 00 ocr.uc_rd.l3_hit cache Counts uncached memory reads that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x101F803C0000 00 ocr.uc_rd.l3_hit.snoop_hitm cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010003C0000 00 ocr.uc_rd.l3_hit.snoop_hit_no_fwd cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004003C0000 00 ocr.uc_rd.l3_hit.snoop_hit_with_fwd cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008003C0000 00 ocr.uc_rd.l3_hit.snoop_miss cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002003C0000 00 ocr.uc_rd.l3_hit.snoop_not_needed cache Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001003C0000 00 ocr.uc_wr.l3_hit cache Counts uncached memory writes that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x201F803C0000 00 cycles_div_busy.fpdiv floating point Counts the number of cycles the floating point divider is busy event=0xcd,period=200003,umask=0x2 00 Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider baclears.any frontend Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xe6,period=200003,umask=0x1 00 Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches baclears.cond frontend Counts the number of BACLEARS due to a conditional jump event=0xe6,period=200003,umask=0x10 00 baclears.indirect frontend Counts the number of BACLEARS due to an indirect branch event=0xe6,period=200003,umask=0x2 00 baclears.return frontend Counts the number of BACLEARS due to a return branch event=0xe6,period=200003,umask=0x8 00 baclears.uncond frontend Counts the number of BACLEARS due to a direct, unconditional jump event=0xe6,period=200003,umask=0x4 00 decode_restriction.predecode_wrong frontend Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction event=0xe9,period=200003,umask=0x1 00 icache.hit frontend Counts the number of instruction cache hits event=0x80,period=200003,umask=0x1 00 Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line misalign_mem_ref.load_page_split memory Counts the number of misaligned load uops that are 4K page splits (Precise event) event=0x13,period=200003,umask=0x2 00 misalign_mem_ref.store_page_split memory Counts the number of misaligned store uops that are 4K page splits (Precise event) event=0x13,period=200003,umask=0x4 00 ocr.all_code_rd.l3_miss memory Counts all code reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000044 00 ocr.all_code_rd.l3_miss_local memory Counts all code reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000044 00 ocr.corewb_m.l3_miss memory Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3002184000000 00 ocr.corewb_m.l3_miss_local memory Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3002184000000 00 ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000004 00 ocr.demand_code_rd.l3_miss_local memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000004 00 ocr.demand_data_and_l1pf_rd.l3_miss memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000001 00 ocr.demand_data_and_l1pf_rd.l3_miss_local memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000001 00 ocr.demand_data_rd.l3_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000001 10 ocr.demand_data_rd.l3_miss_local memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000001 10 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000002 00 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000002 00 ocr.full_streaming_wr.l3_miss memory Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x802184000000 00 ocr.full_streaming_wr.l3_miss_local memory Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x802184000000 00 ocr.hwpf_l2_code_rd.l3_miss memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000040 00 ocr.hwpf_l2_code_rd.l3_miss_local memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000040 00 ocr.hwpf_l2_data_rd.l3_miss memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000010 00 ocr.hwpf_l2_data_rd.l3_miss_local memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000010 00 ocr.hwpf_l2_rfo.l3_miss memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000020 00 ocr.hwpf_l2_rfo.l3_miss_local memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000020 00 ocr.l1wb_m.l3_miss memory Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002184000000 00 ocr.l1wb_m.l3_miss_local memory Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002184000000 00 ocr.l2wb_m.l3_miss memory Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002184000000 00 ocr.l2wb_m.l3_miss_local memory Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002184000000 00 ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184008000 00 ocr.other.l3_miss_local memory Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184008000 00 ocr.partial_streaming_wr.l3_miss memory Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x402184000000 00 ocr.partial_streaming_wr.l3_miss_local memory Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x402184000000 00 ocr.prefetches.l3_miss memory Counts all hardware and software prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000470 00 ocr.reads_to_core.l3_miss memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000477 00 ocr.reads_to_core.l3_miss_local memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000477 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000800 00 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000800 00 ocr.uc_rd.l3_miss memory Counts uncached memory reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x102184000000 00 ocr.uc_rd.l3_miss_local memory Counts uncached memory reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x102184000000 00 ocr.uc_wr.l3_miss memory Counts uncached memory writes that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x202184000000 00 ocr.uc_wr.l3_miss_local memory Counts uncached memory writes that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x202184000000 00 bus_lock.all other This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS event=0x63,edge=1,period=200003 10 bus_lock.block_cycles other Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores event=0x63,period=200003,umask=0x2 00 Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis bus_lock.cycles_other_block other This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES event=0x63,period=200003,umask=0x2 10 bus_lock.cycles_self_block other This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES event=0x63,period=200003,umask=0x1 10 bus_lock.lock_cycles other Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued event=0x63,period=200003,umask=0x1 00 Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis bus_lock.self_locks other Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks event=0x63,edge=1,period=200003 00 Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis c0_stalls.load_dram_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT event=0x34,period=200003,umask=0x4 10 c0_stalls.load_l2_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT event=0x34,period=200003,umask=0x1 10 c0_stalls.load_llc_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT event=0x34,period=200003,umask=0x2 10 hw_interrupts.masked other Counts the number of core cycles during which interrupts are masked (disabled) event=0xcb,period=200003,umask=0x2 00 Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not hw_interrupts.pending_and_masked other Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled) event=0xcb,period=200003,umask=0x4 00 Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important hw_interrupts.received other Counts the number of hardware interrupts received by the processor event=0xcb,period=203,umask=0x1 00 ocr.all_code_rd.any_response other Counts all code reads that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10044 00 ocr.all_code_rd.dram other Counts all code reads that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000044 00 ocr.all_code_rd.local_dram other Counts all code reads that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000044 00 ocr.all_code_rd.outstanding other Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000044 00 ocr.corewb_m.any_response other Counts modified writebacks from L1 cache and L2 cache that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3000000010000 00 ocr.corewb_m.outstanding other Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003000000000000 00 ocr.demand_code_rd.any_response other Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10004 00 ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000004 00 ocr.demand_data_and_l1pf_rd.any_response other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 00 ocr.demand_data_and_l1pf_rd.dram other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 00 ocr.demand_data_and_l1pf_rd.local_dram other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 00 ocr.demand_data_and_l1pf_rd.outstanding other Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000001 00 ocr.demand_data_rd.any_response other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 10 ocr.demand_data_rd.dram other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 10 ocr.demand_data_rd.local_dram other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 10 ocr.demand_data_rd.outstanding other This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000001 10 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000002 00 ocr.demand_rfo.outstanding other Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000002 00 ocr.full_streaming_wr.any_response other Counts streaming stores which modify a full 64 byte cacheline that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800000010000 00 ocr.hwpf_l1d_and_swpf.any_response other Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400 00 ocr.hwpf_l2_code_rd.any_response other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040 00 ocr.hwpf_l2_code_rd.dram other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000040 00 ocr.hwpf_l2_code_rd.local_dram other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000040 00 ocr.hwpf_l2_code_rd.outstanding other Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000040 00 ocr.hwpf_l2_data_rd.any_response other Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010 00 ocr.hwpf_l2_data_rd.dram other Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_data_rd.local_dram other Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_rfo.any_response other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020 00 ocr.hwpf_l2_rfo.dram other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000020 00 ocr.hwpf_l2_rfo.local_dram other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000020 00 ocr.hwpf_l2_rfo.outstanding other Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000020 00 ocr.l1wb_m.any_response other Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000000010000 00 ocr.l2wb_m.any_response other Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000000010000 00 ocr.other.any_response other Counts miscellaneous requests, such as I/O accesses, that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000 00 ocr.partial_streaming_wr.any_response other Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400000010000 00 ocr.prefetches.any_response other Counts all hardware and software prefetches that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10470 00 ocr.reads_to_core.any_response other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10477 00 ocr.reads_to_core.dram other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000477 00 ocr.reads_to_core.local_dram other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000477 00 ocr.reads_to_core.outstanding other Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000477 00 ocr.uc_rd.any_response other Counts uncached memory reads that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100000010000 00 ocr.uc_rd.dram other Counts uncached memory reads that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100184000000 00 ocr.uc_rd.local_dram other Counts uncached memory reads that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100184000000 00 ocr.uc_rd.outstanding other Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000100000000000 00 ocr.uc_wr.any_response other Counts uncached memory writes that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200000010000 00 br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9 00 br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb 00 br_inst_retired.jcc pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event) event=0xc4,period=200003,umask=0x7e 00 br_inst_retired.non_return_ind pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb 00 br_inst_retired.return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7 00 br_inst_retired.taken_jcc pipeline Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe 00 br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb 00 br_misp_retired.jcc pipeline Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e 00 br_misp_retired.non_return_ind pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb 00 br_misp_retired.taken_jcc pipeline Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe 00 btclear.any pipeline Counts the total number of BTCLEARS event=0xe8,period=200003 00 Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch cpu_clk_unhalted.ref pipeline Counts the number of unhalted reference clock cycles at TSC frequency event=0x0,umask=0x03,period=2000003 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2 cycles_div_busy.any pipeline This event is deprecated event=0xcd,period=2000003 10 cycles_div_busy.idiv pipeline Counts the number of cycles the integer divider is busy event=0xcd,period=200003,umask=0x1 00 Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider ld_blocks.4k_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event) event=0x3,period=1000003,umask=0x4 00 ld_blocks.all pipeline Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) (Precise event) event=0x3,period=1000003,umask=0x10 00 ld_blocks.store_forward pipeline Counts the number of retired loads that are blocked because its address partially overlapped with an older store (Precise event) event=0x3,period=1000003,umask=0x2 00 machine_clears.any pipeline Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist event=0xc3,period=20003 00 topdown_bad_speculation.all pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003,umask=0x6 00 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.machine_clears pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation event=0x73,period=1000003,umask=0x2 00 topdown_bad_speculation.monuke pipeline This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE event=0x73,period=1000003,umask=0x2 10 topdown_be_bound.store_buffer pipeline This event is deprecated event=0x74,period=1000003,umask=0x4 10 uops_issued.any pipeline Counts the number of uops issued by the front end every cycle event=0xe,period=200003 00 Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued dtlb_load_misses.pde_cache_miss virtual memory Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache event=0x8,period=200003,umask=0x80 00 dtlb_load_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB event=0x8,period=200003,umask=0x20 00 dtlb_load_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to load DTLB misses to a 1G page event=0x8,period=200003,umask=0x8 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault dtlb_load_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page event=0x8,period=200003,umask=0x4 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault dtlb_load_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to load DTLB misses to a 4K page event=0x8,period=200003,umask=0x2 00 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault dtlb_load_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle event=0x8,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals dtlb_store_misses.pde_cache_miss virtual memory Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache event=0x49,period=2000003,umask=0x80 00 dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x20 00 dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to any page size event=0x49,period=200003,umask=0xe 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_store_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x49,period=200003,umask=0x8 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault dtlb_store_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page event=0x49,period=2000003,umask=0x4 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault dtlb_store_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to store DTLB misses to a 4K page event=0x49,period=2000003,umask=0x2 00 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault dtlb_store_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle event=0x49,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals ept.epde_hit virtual memory Counts the number of Extended Page Directory Entry hits event=0x4f,period=2000003,umask=0x1 00 Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epde_miss virtual memory Counts the number of Extended Page Directory Entry misses event=0x4f,period=2000003,umask=0x2 00 Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epdpe_hit virtual memory Counts the number of Extended Page Directory Pointer Entry hits event=0x4f,period=2000003,umask=0x4 00 Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epdpe_miss virtual memory Counts the number of Extended Page Directory Pointer Entry misses event=0x4f,period=2000003,umask=0x8 00 Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.walk_pending virtual memory Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle event=0x4f,period=200003,umask=0x10 00 Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches itlb.fills virtual memory Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB event=0x81,period=200003,umask=0x4 00 Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB itlb_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB event=0x85,period=2000003,umask=0x20 00 itlb_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to instruction fetch misses to a 1G page event=0x85,period=200003,umask=0x8 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault itlb_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page event=0x85,period=2000003,umask=0x4 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault itlb_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to instruction fetch misses to a 4K page event=0x85,period=2000003,umask=0x2 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault itlb_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle event=0x85,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk) ld_blocks.dtlb_miss virtual memory Counts the number of retired loads that are blocked due to a first level TLB miss (Precise event) event=0x3,period=1000003,umask=0x8 00 mem_uops_retired.dtlb_miss virtual memory Counts the number of memory uops retired that missed in the second level TLB Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x13 00 mem_uops_retired.dtlb_miss_loads virtual memory Counts the number of load uops retired that miss in the second Level TLB Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x11 00 mem_uops_retired.dtlb_miss_stores virtual memory Counts the number of store uops retired that miss in the second level TLB Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x12 00 l2_lines_out.non_silent cache L2_LINES_OUT.NON_SILENT event=0x26,period=200003,umask=0x2 00 l2_lines_out.silent cache Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill event=0x26,period=200003,umask=0x1 00 Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7 00 Counts demand requests to L2 cache mem_load_l3_miss_retired.remote_dram cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Supports address when precise (Precise event) event=0xd3,period=1000003,umask=0x2 00 mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x8 00 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_hitm cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Supports address when precise (Precise event) event=0xd3,period=1000003,umask=0x4 00 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.snc_cache.hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000004 00 ocr.demand_code_rd.snc_cache.hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000004 00 ocr.demand_data_rd.l3_hit cache Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.remote_cache.snoop_hitm cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1030000001 00 ocr.demand_data_rd.remote_cache.snoop_hit_with_fwd cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x830000001 00 ocr.demand_data_rd.snc_cache.hitm cache Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000001 00 ocr.demand_data_rd.snc_cache.hit_with_fwd cache Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000001 00 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.snc_cache.hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000002 00 ocr.demand_rfo.snc_cache.hit_with_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000002 00 ocr.hwpf_l3.l3_hit cache Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x80082380 00 ocr.reads_to_core.l3_hit cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F003C4477 00 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C4477 00 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x4003C4477 00 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x8003C4477 00 ocr.reads_to_core.remote_cache.snoop_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1830004477 00 ocr.reads_to_core.remote_cache.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1030004477 00 ocr.reads_to_core.remote_cache.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x830004477 00 ocr.reads_to_core.snc_cache.hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008004477 00 ocr.reads_to_core.snc_cache.hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808004477 00 ocr.rfo_to_core.l3_hit_m cache Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1F80040022 00 ocr.streaming_wr.l3_hit cache Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x80080800 00 offcore_requests_outstanding.all_data_rd cache This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD event=0x20,period=1000003,umask=0x8 10 offcore_requests_outstanding.cycles_with_data_rd cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD event=0x20,cmask=1,period=1000003,umask=0x8 00 offcore_requests_outstanding.cycles_with_demand_rfo cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO event=0x20,cmask=1,period=1000003,umask=0x4 00 offcore_requests_outstanding.data_rd cache OFFCORE_REQUESTS_OUTSTANDING.DATA_RD event=0x20,period=1000003,umask=0x8 00 fp_arith_dispatched.port_0 floating point FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0] event=0xb3,period=2000003,umask=0x1 00 fp_arith_dispatched.port_1 floating point FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1] event=0xb3,period=2000003,umask=0x2 00 fp_arith_dispatched.port_5 floating point FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2] event=0xb3,period=2000003,umask=0x4 00 fp_arith_dispatched.v0 floating point FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0] event=0xb3,period=2000003,umask=0x1 00 fp_arith_dispatched.v1 floating point FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1] event=0xb3,period=2000003,umask=0x2 00 fp_arith_dispatched.v2 floating point FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5] event=0xb3,period=2000003,umask=0x4 00 fp_arith_inst_retired.512b_packed_double floating point Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x40 00 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x80 00 Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.8_flops floating point Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x60 00 Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired2.128b_packed_half floating point FP_ARITH_INST_RETIRED2.128B_PACKED_HALF event=0xcf,period=100003,umask=0x4 00 fp_arith_inst_retired2.256b_packed_half floating point FP_ARITH_INST_RETIRED2.256B_PACKED_HALF event=0xcf,period=100003,umask=0x8 00 fp_arith_inst_retired2.512b_packed_half floating point FP_ARITH_INST_RETIRED2.512B_PACKED_HALF event=0xcf,period=100003,umask=0x10 00 fp_arith_inst_retired2.complex_scalar_half floating point FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF event=0xcf,period=100003,umask=0x2 00 fp_arith_inst_retired2.scalar floating point Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex event=0xcf,period=100003,umask=0x3 00 FP_ARITH_INST_RETIRED2.SCALAR fp_arith_inst_retired2.scalar_half floating point FP_ARITH_INST_RETIRED2.SCALAR_HALF event=0xcf,period=100003,umask=0x1 00 fp_arith_inst_retired2.vector floating point Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired event=0xcf,period=100003,umask=0x1c 00 FP_ARITH_INST_RETIRED2.VECTOR ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00004 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FC00002 00 ocr.hwpf_l3.l3_miss memory Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches event=0x2a,period=100003,umask=0x1,offcore_rsp=0x94002380 00 ocr.hwpf_l3.l3_miss_local memory Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=0x1,offcore_rsp=0x84002380 00 ocr.reads_to_core.l3_miss memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FC04477 00 ocr.reads_to_core.l3_miss_local memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F04C04477 00 ocr.reads_to_core.l3_miss_local_socket memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x70CC04477 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that missed the local socket's L1, L2, and L3 caches event=0x2a,period=100003,umask=0x1,offcore_rsp=0x94000800 00 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=0x1,offcore_rsp=0x84000800 00 rtm_retired.aborted memory Number of times an RTM execution aborted event=0xc9,period=100003,umask=0x4 00 Counts the number of times RTM abort was triggered rtm_retired.aborted_events memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=100003,umask=0x80 00 Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) rtm_retired.aborted_mem memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=100003,umask=0x8 00 Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) rtm_retired.aborted_memtype memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=100003,umask=0x40 00 Counts the number of times an RTM execution aborted due to incompatible memory type rtm_retired.aborted_unfriendly memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=100003,umask=0x20 00 Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=100003,umask=0x2 00 Counts the number of times RTM commit succeeded rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=100003,umask=0x1 00 Counts the number of times we entered an RTM region. Does not count nested transactions tx_mem.abort_capacity_read memory Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads event=0x54,period=100003,umask=0x80 00 Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads tx_mem.abort_capacity_write memory Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes event=0x54,period=100003,umask=0x2 00 Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=100003,umask=0x1 00 Counts the number of times a TSX line had a cache conflict exe.amx_busy other Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation event=0xb7,period=2000003,umask=0x2 00 ocr.demand_code_rd.any_response other Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10004 00 ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000004 00 ocr.demand_code_rd.snc_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000004 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000001 00 ocr.demand_data_rd.local_dram other Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000001 00 ocr.demand_data_rd.remote_dram other Counts demand data reads that were supplied by DRAM attached to another socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x730000001 00 ocr.demand_data_rd.snc_dram other Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0002 00 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000002 00 ocr.demand_rfo.snc_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000002 00 ocr.hwpf_l1d.any_response other Counts data load hardware prefetch requests to the L1 data cache that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10400 00 ocr.hwpf_l2.any_response other Counts hardware prefetches (which bring data to L2) that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10070 00 ocr.hwpf_l3.any_response other Counts hardware prefetches to the L3 only that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x12380 00 ocr.hwpf_l3.remote other Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x90002380 00 ocr.modified_write.any_response other Counts writebacks of modified cachelines and streaming stores that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10808 00 ocr.reads_to_core.any_response other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FFC4477 00 ocr.reads_to_core.dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C004477 00 ocr.reads_to_core.local_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104004477 00 ocr.reads_to_core.local_socket_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=0x1,offcore_rsp=0x70C004477 00 ocr.reads_to_core.remote other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F33004477 00 ocr.reads_to_core.remote_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x730004477 00 ocr.reads_to_core.remote_memory other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x733004477 00 ocr.reads_to_core.snc_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708004477 00 ocr.write_estimate.memory other Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) event=0x2a,period=100003,umask=0x1,offcore_rsp=0xFBFF80822 00 int_misc.mba_stalls pipeline INT_MISC.MBA_STALLS event=0xad,period=1000003,umask=0x20 00 uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=0x2 00 Counts the number of uops executed from any thread unc_cha_bypass_cha_imc.intermediate uncore cache CHA to iMC Bypass : Intermediate bypass Taken event=0x57,umask=0x2 01 CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass unc_cha_bypass_cha_imc.not_taken uncore cache CHA to iMC Bypass : Not Taken event=0x57,umask=0x4 01 CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted unc_cha_bypass_cha_imc.taken uncore cache CHA to iMC Bypass : Taken event=0x57,umask=0x1 01 CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass unc_cha_clockticks uncore cache CHA Clockticks event=0x1 01 Number of CHA clock cycles while the event is enabled unc_cha_core_snp.any_gtone uncore cache Core Cross Snoops Issued : Any Cycle with Multiple Snoops event=0x33,umask=0xf2 01 Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_one uncore cache Core Cross Snoops Issued : Any Single Snoop event=0x33,umask=0xf1 01 Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_gtone uncore cache Core Cross Snoops Issued : Multiple Core Requests event=0x33,umask=0x42 01 Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_one uncore cache Core Cross Snoops Issued : Single Core Requests event=0x33,umask=0x41 01 Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_gtone uncore cache Core Cross Snoops Issued : Multiple Eviction event=0x33,umask=0x82 01 Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_one uncore cache Core Cross Snoops Issued : Single Eviction event=0x33,umask=0x81 01 Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_gtone uncore cache Core Cross Snoops Issued : Multiple External Snoops event=0x33,umask=0x22 01 Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_one uncore cache Core Cross Snoops Issued : Single External Snoops event=0x33,umask=0x21 01 Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.remote_gtone uncore cache Core Cross Snoops Issued : Multiple Snoop Targets from Remote event=0x33,umask=0x12 01 Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.remote_one uncore cache Core Cross Snoops Issued : Single Snoop Target from Remote event=0x33,umask=0x11 01 Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_direct_go.ha_suppress_drd uncore cache Direct GO event=0x6e,umask=0x4 01 unc_cha_direct_go.ha_suppress_no_d2c uncore cache Direct GO event=0x6e,umask=0x2 01 unc_cha_direct_go.ha_tor_dealloc uncore cache Direct GO event=0x6e,umask=0x1 01 unc_cha_direct_go_opc.extcmp uncore cache Direct GO event=0x6d,umask=0x1 01 unc_cha_direct_go_opc.fast_go uncore cache Direct GO event=0x6d,umask=0x10 01 unc_cha_direct_go_opc.fast_go_pull uncore cache Direct GO event=0x6d,umask=0x20 01 unc_cha_direct_go_opc.go uncore cache Direct GO event=0x6d,umask=0x4 01 unc_cha_direct_go_opc.go_pull uncore cache Direct GO event=0x6d,umask=0x8 01 unc_cha_direct_go_opc.idle_due_suppress uncore cache Direct GO event=0x6d,umask=0x80 01 unc_cha_direct_go_opc.nop uncore cache Direct GO event=0x6d,umask=0x40 01 unc_cha_direct_go_opc.pull uncore cache Direct GO event=0x6d,umask=0x2 01 unc_cha_egress_ordering.iv_snoopgo_dn uncore cache Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_egress_ordering.iv_snoopgo_up uncore cache Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache : Shared hit and op is RdInvOwn, RdInv, Inv* event=0x5f,umask=0x4 01 unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache : op is WbMtoE event=0x5f,umask=0x8 01 unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5f,umask=0x10 01 unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* event=0x5e,umask=0x1 01 unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5e,umask=0x2 01 unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : No SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x40 01 unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* event=0x60,umask=0x80 01 unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x20 01 unc_cha_hitme_update.deallocate uncore cache Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI* event=0x61,umask=0x10 01 unc_cha_hitme_update.deallocate_rspfwdi_loc uncore cache Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request event=0x61,umask=0x1 01 Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry unc_cha_hitme_update.rdinvown uncore cache Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI* event=0x61,umask=0x8 01 unc_cha_hitme_update.rspfwdi_rem uncore cache Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request event=0x61,umask=0x2 01 Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request unc_cha_hitme_update.shared uncore cache Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed event=0x61,umask=0x4 01 unc_cha_imc_reads_count.priority uncore cache HA to iMC Reads Issued : ISOCH event=0x59,umask=0x2 01 HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads unc_cha_imc_writes_count.full_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Full Line event=0x5b,umask=0x4 01 CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_imc_writes_count.partial uncore cache CHA to iMC Full Line Writes Issued : Partial Non-ISOCH event=0x5b,umask=0x2 01 CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_imc_writes_count.partial_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Partial event=0x5b,umask=0x8 01 CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_llc_lookup.all uncore cache Cache and Snoop Filter Lookups; Any Request event=0x34,umask=0x1fffff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_cha_llc_lookup.all_remote uncore cache Cache Lookups : All transactions from Remote Agents event=0x34,umask=0x17e0ff 01 Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.any_f uncore cache Cache Lookups : All Requests event=0x34 01 Cache Lookups : All Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch unc_cha_llc_lookup.code uncore cache Cache Lookups : CRd Requests event=0x34,umask=0x1bd0ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_read_f uncore cache Cache Lookups : CRd Requests event=0x34 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.corepref_or_dmnd_local_f uncore cache Cache Lookups : Local non-prefetch requests event=0x34 01 Cache Lookups : Local non-prefetch requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, not including prefetch unc_cha_llc_lookup.data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=0x1bc1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache Cache Lookups : Data Reads event=0x34,umask=0x1fc1ff 01 Cache Lookups : Data Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_f uncore cache Cache Lookups : Data Read Request event=0x34 01 Cache Lookups : Data Read Request : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Read transactions unc_cha_llc_lookup.data_read_local uncore cache Cache Lookups : Demand Data Reads, Core and LLC prefetches event=0x34,umask=0x841ff 01 Cache Lookups : Demand Data Reads, Core and LLC prefetches : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups : Data Read Misses event=0x34,umask=0x1fc101 01 Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.e uncore cache Cache Lookups : E State event=0x34,umask=0x20 01 Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Exclusive State unc_cha_llc_lookup.f uncore cache Cache Lookups : F State event=0x34,umask=0x80 01 Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Forward State unc_cha_llc_lookup.flush_inv uncore cache Cache Lookups : Flush or Invalidate Requests event=0x34,umask=0x1a44ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.flush_or_inv_f uncore cache Cache Lookups : Flush event=0x34 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.i uncore cache Cache Lookups : I State event=0x34,umask=0x1 01 Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Miss unc_cha_llc_lookup.llcpref_local_f uncore cache Cache Lookups : Local LLC prefetch requests (from LLC) event=0x34 01 Cache Lookups : Local LLC prefetch requests (from LLC) : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC unc_cha_llc_lookup.locally_homed_address uncore cache Cache Lookups : Transactions homed locally event=0x34,umask=0xbdfff 01 Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.local_code uncore cache Cache Lookups : CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x19d0ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.local_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core) event=0x34,umask=0x19c1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_code uncore cache Cache Lookups : Demand CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x1850ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.local_dmnd_data_rd uncore cache Cache and Snoop Filter Lookups; Demand Data Reads that come from the local socket (usually the core) event=0x34,umask=0x1841ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_rfo uncore cache Cache Lookups : Demand RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x1848ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.local_f uncore cache Cache Lookups : Transactions homed locally event=0x34 01 Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.local_flush_inv uncore cache Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core) event=0x34,umask=0x1844ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.local_llc_pf uncore cache Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core) event=0x34,umask=0x189dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf uncore cache Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core) event=0x34,umask=0x199dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_code uncore cache Cache Lookups : CRd Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1910ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.local_pf_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1981ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_rfo uncore cache Cache Lookups : RFO Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1908ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.local_rfo uncore cache Cache Lookups : RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x19c8ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.m uncore cache Cache Lookups : M State event=0x34,umask=0x40 01 Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Modified State unc_cha_llc_lookup.miss_all uncore cache Cache Lookups : All Misses event=0x34,umask=0x1fe001 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.other_req_f uncore cache Cache Lookups : Write Requests event=0x34 01 Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.pref_or_dmnd_remote_f uncore cache Cache Lookups : Remote non-snoop requests event=0x34 01 Cache Lookups : Remote non-snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote non-snoop transactions to the LLC unc_cha_llc_lookup.remotely_homed_address uncore cache Cache Lookups : Transactions homed remotely event=0x34,umask=0x15dfff 01 Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_code uncore cache Cache Lookups : CRd Requests that come from a Remote socket event=0x34,umask=0x1a10ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.remote_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket event=0x34,umask=0x1a01ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.remote_f uncore cache Cache Lookups : Transactions homed remotely event=0x34 01 Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_flush_inv uncore cache Cache Lookups : Flush or Invalidate requests that come from a Remote socket event=0x34,umask=0x1a04ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.remote_other uncore cache Cache Lookups : Filters Requests for those that write info into the cache that come from a remote socket event=0x34,umask=0x1a02ff 01 Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.remote_rfo uncore cache Cache Lookups : RFO Requests that come from a Remote socket event=0x34,umask=0x1a08ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.remote_snoop_f uncore cache Cache Lookups : Remote snoop requests event=0x34 01 Cache Lookups : Remote snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote snoop transactions to the LLC unc_cha_llc_lookup.remote_snp uncore cache Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket event=0x34,umask=0x1c19ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_cha_llc_lookup.rfo uncore cache Cache Lookups : RFO Requests event=0x34,umask=0x1bc8ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_f uncore cache Cache Lookups : RFO Request Filter event=0x34 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups : Locally HOMed RFOs - Demand and Prefetches event=0x34,umask=0x9c8ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.s uncore cache Cache Lookups : S State event=0x34,umask=0x10 01 Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Shared State unc_cha_llc_lookup.sf_e uncore cache Cache Lookups : SnoopFilter - E State event=0x34,umask=0x4 01 Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Exclusive State unc_cha_llc_lookup.sf_h uncore cache Cache Lookups : SnoopFilter - H State event=0x34,umask=0x8 01 Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit HitMe State unc_cha_llc_lookup.sf_s uncore cache Cache Lookups : SnoopFilter - S State event=0x34,umask=0x2 01 Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Shared State unc_cha_llc_lookup.write_local uncore cache Cache Lookups : Writes event=0x34,umask=0x842ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Requests that install or change a line in the LLC. Examples: Writebacks from Core L2's and UPI. Prefetches into the LLC unc_cha_llc_lookup.write_remote uncore cache Cache Lookups : Remote Writes event=0x34,umask=0x17c2ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_victims.e_state uncore cache Lines Victimized : Lines in E state event=0x37,umask=0x2 01 Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.ia uncore cache Lines Victimized : IA traffic event=0x37,umask=0x20 01 Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io uncore cache Lines Victimized : IO traffic event=0x37,umask=0x10 01 Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_e uncore cache All LLC lines in E state that are victimized on a fill from an IO device event=0x37,umask=0x12 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_fs uncore cache All LLC lines in F or S state that are victimized on a fill from an IO device event=0x37,umask=0x1c 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_m uncore cache All LLC lines in M state that are victimized on a fill from an IO device event=0x37,umask=0x11 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.io_mesf uncore cache All LLC lines in any state that are victimized on a fill from an IO device event=0x37,umask=0x1f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_all uncore cache Lines Victimized; Local - All Lines event=0x37,umask=0x200f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized event=0x37,umask=0x2002 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized event=0x37,umask=0x2001 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_only uncore cache Lines Victimized : Local Only event=0x37 01 Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized event=0x37,umask=0x2004 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.m_state uncore cache Lines Victimized : Lines in M state event=0x37,umask=0x1 01 Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_all uncore cache Lines Victimized; Remote - All Lines event=0x37,umask=0x800f 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized event=0x37,umask=0x8002 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized event=0x37,umask=0x8001 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_only uncore cache Lines Victimized : Remote Only event=0x37 01 Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized event=0x37,umask=0x8004 01 Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.s_state uncore cache Lines Victimized : Lines in S State event=0x37,umask=0x4 01 Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_e uncore cache All LLC lines in E state that are victimized on a fill event=0x37,umask=0x2 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_m uncore cache All LLC lines in M state that are victimized on a fill event=0x37,umask=0x1 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_s uncore cache All LLC lines in S state that are victimized on a fill event=0x37,umask=0x4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_misc.cv0_pref_miss uncore cache Cbo Misc : CV0 Prefetch Miss event=0x39,umask=0x20 01 Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo unc_cha_misc.cv0_pref_vic uncore cache Cbo Misc : CV0 Prefetch Victim event=0x39,umask=0x10 01 Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo unc_cha_misc.rspi_was_fse uncore cache Cbo Misc : Silent Snoop Eviction event=0x39,umask=0x1 01 Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings unc_cha_misc.wc_aliasing uncore cache Cbo Misc : Write Combining Aliasing event=0x39,umask=0x2 01 Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing unc_cha_osb.local_invitoe uncore cache OSB Snoop Broadcast : Local InvItoE event=0x55,umask=0x1 01 OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.local_read uncore cache OSB Snoop Broadcast : Local Rd event=0x55,umask=0x2 01 OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.off_pwrheuristic uncore cache OSB Snoop Broadcast : Off event=0x55,umask=0x20 01 OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.remote_read uncore cache OSB Snoop Broadcast : Remote Rd event=0x55,umask=0x4 01 OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.remote_readinvitoe uncore cache OSB Snoop Broadcast : Remote Rd InvItoE event=0x55,umask=0x8 01 OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.rfo_hits_snp_bcast uncore cache OSB Snoop Broadcast : RFO HitS Snoop Broadcast event=0x55,umask=0x10 01 OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_pmm_memmode_nm_invitox.local uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL event=0x65,umask=0x1 01 unc_cha_pmm_memmode_nm_invitox.remote uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE event=0x65,umask=0x2 01 unc_cha_pmm_memmode_nm_invitox.setconflict uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT event=0x65,umask=0x4 01 unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in SF/LLC event=0x64,umask=0x2 01 Near Memory evictions due to another read to the same Near Memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache Memory Mode related events; Counts the number of times CHA saw a Near memory set conflict in SF/LLC event=0x64,umask=0x1 01 Near Memory evictions due to another read to the same Near Memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in TOR event=0x64,umask=0x4 01 No Reject in the CHA due to a pending read to the same Near Memory set in the TOR unc_cha_pmm_memmode_nm_setconflicts2.iodc uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC event=0x70,umask=0x1 01 unc_cha_pmm_memmode_nm_setconflicts2.memwr uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR event=0x70,umask=0x2 01 unc_cha_pmm_memmode_nm_setconflicts2.memwrni uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI event=0x70,umask=0x4 01 unc_cha_pmm_qos.ddr4_fast_insert uncore cache UNC_CHA_PMM_QOS.DDR4_FAST_INSERT event=0x66,umask=0x2 01 unc_cha_pmm_qos.rej_irq uncore cache UNC_CHA_PMM_QOS.REJ_IRQ event=0x66,umask=0x8 01 unc_cha_pmm_qos.slowtorq_skip uncore cache UNC_CHA_PMM_QOS.SLOWTORQ_SKIP event=0x66,umask=0x40 01 unc_cha_pmm_qos.slow_insert uncore cache UNC_CHA_PMM_QOS.SLOW_INSERT event=0x66,umask=0x1 01 unc_cha_pmm_qos.throttle uncore cache UNC_CHA_PMM_QOS.THROTTLE event=0x66,umask=0x4 01 unc_cha_pmm_qos.throttle_irq uncore cache UNC_CHA_PMM_QOS.THROTTLE_IRQ event=0x66,umask=0x20 01 unc_cha_pmm_qos.throttle_prq uncore cache UNC_CHA_PMM_QOS.THROTTLE_PRQ event=0x66,umask=0x10 01 unc_cha_pmm_qos_occupancy.ddr_fast_fifo uncore cache UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO event=0x67,umask=0x2 01 : count # of FAST TOR Request inserted to ha_tor_req_fifo unc_cha_pmm_qos_occupancy.ddr_slow_fifo uncore cache Number of SLOW TOR Request inserted to ha_pmm_tor_req_fifo event=0x67,umask=0x1 01 unc_cha_read_no_credits.mc0 uncore cache CHA iMC CHNx READ Credits Empty : MC0 event=0x58,umask=0x1 01 CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only unc_cha_read_no_credits.mc1 uncore cache CHA iMC CHNx READ Credits Empty : MC1 event=0x58,umask=0x2 01 CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only unc_cha_read_no_credits.mc2 uncore cache CHA iMC CHNx READ Credits Empty : MC2 event=0x58,umask=0x4 01 CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only unc_cha_read_no_credits.mc3 uncore cache CHA iMC CHNx READ Credits Empty : MC3 event=0x58,umask=0x8 01 CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only unc_cha_read_no_credits.mc4 uncore cache CHA iMC CHNx READ Credits Empty : MC4 event=0x58,umask=0x10 01 CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only unc_cha_read_no_credits.mc5 uncore cache CHA iMC CHNx READ Credits Empty : MC5 event=0x58,umask=0x20 01 CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only unc_cha_requests.invitoe uncore cache Requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x30 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Remote requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x20 01 Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Read requests made into the CHA event=0x50,umask=0x3 01 Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.writes uncore cache Write requests made into the CHA event=0x50,umask=0xc 01 Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_rxc_inserts.ipq uncore cache Ingress (from CMS) Allocations : IPQ event=0x13,umask=0x4 01 Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq uncore cache Ingress (from CMS) Allocations : IRQ event=0x13,umask=0x1 01 Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq_rej uncore cache Ingress (from CMS) Allocations : IRQ Rejected event=0x13,umask=0x2 01 Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq uncore cache Ingress (from CMS) Allocations : PRQ event=0x13,umask=0x10 01 Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq_rej uncore cache Ingress (from CMS) Allocations : PRQ event=0x13,umask=0x20 01 Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.rrq uncore cache Ingress (from CMS) Allocations : RRQ event=0x13,umask=0x40 01 Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.wbq uncore cache Ingress (from CMS) Allocations : WBQ event=0x13,umask=0x80 01 Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_ipq0_reject.ad_req_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x22,umask=0x1 01 IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_ipq0_reject.ad_rsp_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x22,umask=0x2 01 IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_ipq0_reject.ak_non_upi uncore cache IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x22,umask=0x40 01 IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_ipq0_reject.bl_ncb_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x22,umask=0x10 01 IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_ipq0_reject.bl_ncs_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x22,umask=0x20 01 IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_ipq0_reject.bl_rsp_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x22,umask=0x4 01 IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_ipq0_reject.bl_wb_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x22,umask=0x8 01 IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_ipq0_reject.iv_non_upi uncore cache IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x22,umask=0x80 01 IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_ipq1_reject.allow_snp uncore cache IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x23,umask=0x40 01 unc_cha_rxc_ipq1_reject.any0 uncore cache IPQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x23,umask=0x1 01 IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true unc_cha_rxc_ipq1_reject.ha uncore cache IPQ Requests (from CMS) Rejected - Set 1 : HA event=0x23,umask=0x2 01 unc_cha_rxc_ipq1_reject.llc_or_sf_way uncore cache IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way event=0x23,umask=0x20 01 IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject unc_cha_rxc_ipq1_reject.llc_victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x23,umask=0x4 01 unc_cha_rxc_ipq1_reject.pa_match uncore cache IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match event=0x23,umask=0x80 01 IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected unc_cha_rxc_ipq1_reject.sf_victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x23,umask=0x8 01 IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_ipq1_reject.victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : Victim event=0x23,umask=0x10 01 unc_cha_rxc_irq0_reject.ad_req_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x18,umask=0x1 01 IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_irq0_reject.ad_rsp_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x18,umask=0x2 01 IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_irq0_reject.ak_non_upi uncore cache IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x18,umask=0x40 01 IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_irq0_reject.bl_ncb_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x18,umask=0x10 01 IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_irq0_reject.bl_ncs_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x18,umask=0x20 01 IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_irq0_reject.bl_rsp_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x18,umask=0x4 01 IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_irq0_reject.bl_wb_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x18,umask=0x8 01 IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_irq0_reject.iv_non_upi uncore cache IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x18,umask=0x80 01 IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_irq1_reject.allow_snp uncore cache IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x19,umask=0x40 01 unc_cha_rxc_irq1_reject.any0 uncore cache IRQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x19,umask=0x1 01 IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true unc_cha_rxc_irq1_reject.ha uncore cache IRQ Requests (from CMS) Rejected - Set 1 : HA event=0x19,umask=0x2 01 unc_cha_rxc_irq1_reject.llc_or_sf_way uncore cache IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way event=0x19,umask=0x20 01 IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject unc_cha_rxc_irq1_reject.llc_victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x19,umask=0x4 01 unc_cha_rxc_irq1_reject.sf_victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x19,umask=0x8 01 IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_irq1_reject.victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : Victim event=0x19,umask=0x10 01 unc_cha_rxc_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects - Set 0 : AD REQ on VN0 event=0x24,umask=0x1 01 ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request unc_cha_rxc_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects - Set 0 : AD RSP on VN0 event=0x24,umask=0x2 01 ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response unc_cha_rxc_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects - Set 0 : Non UPI AK Request event=0x24,umask=0x40 01 ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message unc_cha_rxc_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects - Set 0 : BL NCB on VN0 event=0x24,umask=0x10 01 ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB unc_cha_rxc_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects - Set 0 : BL NCS on VN0 event=0x24,umask=0x20 01 ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS unc_cha_rxc_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects - Set 0 : BL RSP on VN0 event=0x24,umask=0x4 01 ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response unc_cha_rxc_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects - Set 0 : BL WB on VN0 event=0x24,umask=0x8 01 ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback unc_cha_rxc_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects - Set 0 : Non UPI IV Request event=0x24,umask=0x80 01 ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message unc_cha_rxc_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries - Set 0 : AD REQ on VN0 event=0x2c,umask=0x1 01 ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request unc_cha_rxc_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries - Set 0 : AD RSP on VN0 event=0x2c,umask=0x2 01 ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response unc_cha_rxc_ismq0_retry.ak_non_upi uncore cache ISMQ Retries - Set 0 : Non UPI AK Request event=0x2c,umask=0x40 01 ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message unc_cha_rxc_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries - Set 0 : BL NCB on VN0 event=0x2c,umask=0x10 01 ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB unc_cha_rxc_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries - Set 0 : BL NCS on VN0 event=0x2c,umask=0x20 01 ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS unc_cha_rxc_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries - Set 0 : BL RSP on VN0 event=0x2c,umask=0x4 01 ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response unc_cha_rxc_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries - Set 0 : BL WB on VN0 event=0x2c,umask=0x8 01 ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback unc_cha_rxc_ismq0_retry.iv_non_upi uncore cache ISMQ Retries - Set 0 : Non UPI IV Request event=0x2c,umask=0x80 01 ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message unc_cha_rxc_ismq1_reject.any0 uncore cache ISMQ Rejects - Set 1 : ANY0 event=0x25,umask=0x1 01 ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true unc_cha_rxc_ismq1_reject.ha uncore cache ISMQ Rejects - Set 1 : HA event=0x25,umask=0x2 01 ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.any0 uncore cache ISMQ Retries - Set 1 : ANY0 event=0x2d,umask=0x1 01 ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true unc_cha_rxc_ismq1_retry.ha uncore cache ISMQ Retries - Set 1 : HA event=0x2d,umask=0x2 01 ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_occupancy.ipq uncore cache Ingress (from CMS) Occupancy : IPQ event=0x11,umask=0x4 01 Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.rrq uncore cache Ingress (from CMS) Occupancy : RRQ event=0x11,umask=0x40 01 Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.wbq uncore cache Ingress (from CMS) Occupancy : WBQ event=0x11,umask=0x80 01 Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_other0_retry.ad_req_vn0 uncore cache Other Retries - Set 0 : AD REQ on VN0 event=0x2e,umask=0x1 01 Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request unc_cha_rxc_other0_retry.ad_rsp_vn0 uncore cache Other Retries - Set 0 : AD RSP on VN0 event=0x2e,umask=0x2 01 Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response unc_cha_rxc_other0_retry.ak_non_upi uncore cache Other Retries - Set 0 : Non UPI AK Request event=0x2e,umask=0x40 01 Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message unc_cha_rxc_other0_retry.bl_ncb_vn0 uncore cache Other Retries - Set 0 : BL NCB on VN0 event=0x2e,umask=0x10 01 Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB unc_cha_rxc_other0_retry.bl_ncs_vn0 uncore cache Other Retries - Set 0 : BL NCS on VN0 event=0x2e,umask=0x20 01 Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS unc_cha_rxc_other0_retry.bl_rsp_vn0 uncore cache Other Retries - Set 0 : BL RSP on VN0 event=0x2e,umask=0x4 01 Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response unc_cha_rxc_other0_retry.bl_wb_vn0 uncore cache Other Retries - Set 0 : BL WB on VN0 event=0x2e,umask=0x8 01 Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback unc_cha_rxc_other0_retry.iv_non_upi uncore cache Other Retries - Set 0 : Non UPI IV Request event=0x2e,umask=0x80 01 Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message unc_cha_rxc_other1_retry.allow_snp uncore cache Other Retries - Set 1 : Allow Snoop event=0x2f,umask=0x40 01 Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.any0 uncore cache Other Retries - Set 1 : ANY0 event=0x2f,umask=0x1 01 Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true unc_cha_rxc_other1_retry.ha uncore cache Other Retries - Set 1 : HA event=0x2f,umask=0x2 01 Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_or_sf_way uncore cache Other Retries - Set 1 : LLC OR SF Way event=0x2f,umask=0x20 01 Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject unc_cha_rxc_other1_retry.llc_victim uncore cache Other Retries - Set 1 : LLC Victim event=0x2f,umask=0x4 01 Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.pa_match uncore cache Other Retries - Set 1 : PhyAddr Match event=0x2f,umask=0x80 01 Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected unc_cha_rxc_other1_retry.sf_victim uncore cache Other Retries - Set 1 : SF Victim event=0x2f,umask=0x8 01 Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim unc_cha_rxc_other1_retry.victim uncore cache Other Retries - Set 1 : Victim event=0x2f,umask=0x10 01 Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_prq0_reject.ad_req_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x20,umask=0x1 01 PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_prq0_reject.ad_rsp_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x20,umask=0x2 01 PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_prq0_reject.ak_non_upi uncore cache PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x20,umask=0x40 01 PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_prq0_reject.bl_ncb_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x20,umask=0x10 01 PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_prq0_reject.bl_ncs_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x20,umask=0x20 01 PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_prq0_reject.bl_rsp_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x20,umask=0x4 01 PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_prq0_reject.bl_wb_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x20,umask=0x8 01 PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_prq0_reject.iv_non_upi uncore cache PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x20,umask=0x80 01 PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_prq1_reject.allow_snp uncore cache PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x21,umask=0x40 01 unc_cha_rxc_prq1_reject.any0 uncore cache PRQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x21,umask=0x1 01 PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true unc_cha_rxc_prq1_reject.ha uncore cache PRQ Requests (from CMS) Rejected - Set 1 : HA event=0x21,umask=0x2 01 unc_cha_rxc_prq1_reject.llc_or_sf_way uncore cache PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way event=0x21,umask=0x20 01 PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject unc_cha_rxc_prq1_reject.llc_victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x21,umask=0x4 01 unc_cha_rxc_prq1_reject.pa_match uncore cache PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match event=0x21,umask=0x80 01 PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected unc_cha_rxc_prq1_reject.sf_victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x21,umask=0x8 01 PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_prq1_reject.victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : Victim event=0x21,umask=0x10 01 unc_cha_rxc_req_q0_retry.ad_req_vn0 uncore cache Request Queue Retries - Set 0 : AD REQ on VN0 event=0x2a,umask=0x1 01 Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request unc_cha_rxc_req_q0_retry.ad_rsp_vn0 uncore cache Request Queue Retries - Set 0 : AD RSP on VN0 event=0x2a,umask=0x2 01 Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response unc_cha_rxc_req_q0_retry.ak_non_upi uncore cache Request Queue Retries - Set 0 : Non UPI AK Request event=0x2a,umask=0x40 01 Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message unc_cha_rxc_req_q0_retry.bl_ncb_vn0 uncore cache Request Queue Retries - Set 0 : BL NCB on VN0 event=0x2a,umask=0x10 01 Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB unc_cha_rxc_req_q0_retry.bl_ncs_vn0 uncore cache Request Queue Retries - Set 0 : BL NCS on VN0 event=0x2a,umask=0x20 01 Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS unc_cha_rxc_req_q0_retry.bl_rsp_vn0 uncore cache Request Queue Retries - Set 0 : BL RSP on VN0 event=0x2a,umask=0x4 01 Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response unc_cha_rxc_req_q0_retry.bl_wb_vn0 uncore cache Request Queue Retries - Set 0 : BL WB on VN0 event=0x2a,umask=0x8 01 Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback unc_cha_rxc_req_q0_retry.iv_non_upi uncore cache Request Queue Retries - Set 0 : Non UPI IV Request event=0x2a,umask=0x80 01 Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message unc_cha_rxc_req_q1_retry.allow_snp uncore cache Request Queue Retries - Set 1 : Allow Snoop event=0x2b,umask=0x40 01 Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.any0 uncore cache Request Queue Retries - Set 1 : ANY0 event=0x2b,umask=0x1 01 Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true unc_cha_rxc_req_q1_retry.ha uncore cache Request Queue Retries - Set 1 : HA event=0x2b,umask=0x2 01 Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_or_sf_way uncore cache Request Queue Retries - Set 1 : LLC OR SF Way event=0x2b,umask=0x20 01 Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject unc_cha_rxc_req_q1_retry.llc_victim uncore cache Request Queue Retries - Set 1 : LLC Victim event=0x2b,umask=0x4 01 Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.pa_match uncore cache Request Queue Retries - Set 1 : PhyAddr Match event=0x2b,umask=0x80 01 Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected unc_cha_rxc_req_q1_retry.sf_victim uncore cache Request Queue Retries - Set 1 : SF Victim event=0x2b,umask=0x8 01 Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim unc_cha_rxc_req_q1_retry.victim uncore cache Request Queue Retries - Set 1 : Victim event=0x2b,umask=0x10 01 Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_rrq0_reject.ad_req_vn0 uncore cache RRQ Rejects - Set 0 : AD REQ on VN0 event=0x26,umask=0x1 01 RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request unc_cha_rxc_rrq0_reject.ad_rsp_vn0 uncore cache RRQ Rejects - Set 0 : AD RSP on VN0 event=0x26,umask=0x2 01 RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response unc_cha_rxc_rrq0_reject.ak_non_upi uncore cache RRQ Rejects - Set 0 : Non UPI AK Request event=0x26,umask=0x40 01 RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message unc_cha_rxc_rrq0_reject.bl_ncb_vn0 uncore cache RRQ Rejects - Set 0 : BL NCB on VN0 event=0x26,umask=0x10 01 RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB unc_cha_rxc_rrq0_reject.bl_ncs_vn0 uncore cache RRQ Rejects - Set 0 : BL NCS on VN0 event=0x26,umask=0x20 01 RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS unc_cha_rxc_rrq0_reject.bl_rsp_vn0 uncore cache RRQ Rejects - Set 0 : BL RSP on VN0 event=0x26,umask=0x4 01 RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response unc_cha_rxc_rrq0_reject.bl_wb_vn0 uncore cache RRQ Rejects - Set 0 : BL WB on VN0 event=0x26,umask=0x8 01 RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback unc_cha_rxc_rrq0_reject.iv_non_upi uncore cache RRQ Rejects - Set 0 : Non UPI IV Request event=0x26,umask=0x80 01 RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message unc_cha_rxc_rrq1_reject.allow_snp uncore cache RRQ Rejects - Set 1 : Allow Snoop event=0x27,umask=0x40 01 RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.any0 uncore cache RRQ Rejects - Set 1 : ANY0 event=0x27,umask=0x1 01 RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true unc_cha_rxc_rrq1_reject.ha uncore cache RRQ Rejects - Set 1 : HA event=0x27,umask=0x2 01 RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_or_sf_way uncore cache RRQ Rejects - Set 1 : LLC OR SF Way event=0x27,umask=0x20 01 RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject unc_cha_rxc_rrq1_reject.llc_victim uncore cache RRQ Rejects - Set 1 : LLC Victim event=0x27,umask=0x4 01 RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.pa_match uncore cache RRQ Rejects - Set 1 : PhyAddr Match event=0x27,umask=0x80 01 RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected unc_cha_rxc_rrq1_reject.sf_victim uncore cache RRQ Rejects - Set 1 : SF Victim event=0x27,umask=0x8 01 RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim unc_cha_rxc_rrq1_reject.victim uncore cache RRQ Rejects - Set 1 : Victim event=0x27,umask=0x10 01 RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_wbq0_reject.ad_req_vn0 uncore cache WBQ Rejects - Set 0 : AD REQ on VN0 event=0x28,umask=0x1 01 WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request unc_cha_rxc_wbq0_reject.ad_rsp_vn0 uncore cache WBQ Rejects - Set 0 : AD RSP on VN0 event=0x28,umask=0x2 01 WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response unc_cha_rxc_wbq0_reject.ak_non_upi uncore cache WBQ Rejects - Set 0 : Non UPI AK Request event=0x28,umask=0x40 01 WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message unc_cha_rxc_wbq0_reject.bl_ncb_vn0 uncore cache WBQ Rejects - Set 0 : BL NCB on VN0 event=0x28,umask=0x10 01 WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB unc_cha_rxc_wbq0_reject.bl_ncs_vn0 uncore cache WBQ Rejects - Set 0 : BL NCS on VN0 event=0x28,umask=0x20 01 WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS unc_cha_rxc_wbq0_reject.bl_rsp_vn0 uncore cache WBQ Rejects - Set 0 : BL RSP on VN0 event=0x28,umask=0x4 01 WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response unc_cha_rxc_wbq0_reject.bl_wb_vn0 uncore cache WBQ Rejects - Set 0 : BL WB on VN0 event=0x28,umask=0x8 01 WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback unc_cha_rxc_wbq0_reject.iv_non_upi uncore cache WBQ Rejects - Set 0 : Non UPI IV Request event=0x28,umask=0x80 01 WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message unc_cha_rxc_wbq1_reject.allow_snp uncore cache WBQ Rejects - Set 1 : Allow Snoop event=0x29,umask=0x40 01 WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.any0 uncore cache WBQ Rejects - Set 1 : ANY0 event=0x29,umask=0x1 01 WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true unc_cha_rxc_wbq1_reject.ha uncore cache WBQ Rejects - Set 1 : HA event=0x29,umask=0x2 01 WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_or_sf_way uncore cache WBQ Rejects - Set 1 : LLC OR SF Way event=0x29,umask=0x20 01 WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject unc_cha_rxc_wbq1_reject.llc_victim uncore cache WBQ Rejects - Set 1 : LLC Victim event=0x29,umask=0x4 01 WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.pa_match uncore cache WBQ Rejects - Set 1 : PhyAddr Match event=0x29,umask=0x80 01 WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected unc_cha_rxc_wbq1_reject.sf_victim uncore cache WBQ Rejects - Set 1 : SF Victim event=0x29,umask=0x8 01 WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim unc_cha_rxc_wbq1_reject.victim uncore cache WBQ Rejects - Set 1 : Victim event=0x29,umask=0x10 01 WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_snoops_sent.all uncore cache Snoops Sent : All event=0x51,umask=0x1 01 Snoops Sent : All : Counts the number of snoops issued by the HA unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent : Broadcast snoop for Local Requests event=0x51,umask=0x10 01 Snoops Sent : Broadcast snoop for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent : Broadcast snoops for Remote Requests event=0x51,umask=0x20 01 Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets unc_cha_snoops_sent.direct_local uncore cache Snoops Sent : Directed snoops for Local Requests event=0x51,umask=0x40 01 Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent : Directed snoops for Remote Requests event=0x51,umask=0x80 01 Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets unc_cha_snoops_sent.local uncore cache Snoops Sent : Broadcast or directed Snoops sent for Local Requests event=0x51,umask=0x4 01 Snoops Sent : Broadcast or directed Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket unc_cha_snoops_sent.remote uncore cache Snoops Sent : Broadcast or directed Snoops sent for Remote Requests event=0x51,umask=0x8 01 Snoops Sent : Broadcast or directed Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket unc_cha_snoop_resp.rspcnflct uncore cache Snoop Responses Received : RSPCNFLCT* event=0x5c,umask=0x40 01 Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp.rspfwd uncore cache Snoop Responses Received : RspFwd event=0x5c,umask=0x80 01 Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp.rspfwdwb uncore cache Snoop Responses Received : Rsp*Fwd*WB event=0x5c,umask=0x20 01 Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp.rsps uncore cache RspS Snoop Responses Received event=0x5c,umask=0x2 01 Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp.rspwb uncore cache Snoop Responses Received : Rsp*WB event=0x5c,umask=0x10 01 Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_snoop_resp_local.rspcnflct uncore cache Snoop Responses Received Local : RspCnflct event=0x5d,umask=0x40 01 Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp_local.rspfwd uncore cache Snoop Responses Received Local : RspFwd event=0x5d,umask=0x80 01 Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp_local.rspfwdwb uncore cache Snoop Responses Received Local : Rsp*FWD*WB event=0x5d,umask=0x20 01 Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp_local.rspi uncore cache Snoop Responses Received Local : RspI event=0x5d,umask=0x1 01 Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_cha_snoop_resp_local.rspifwd uncore cache Snoop Responses Received Local : RspIFwd event=0x5d,umask=0x4 01 Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE unc_cha_snoop_resp_local.rsps uncore cache Snoop Responses Received Local : RspS event=0x5d,umask=0x2 01 Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local : RspSFwd event=0x5d,umask=0x8 01 Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state unc_cha_snoop_resp_local.rspwb uncore cache Snoop Responses Received Local : Rsp*WB event=0x5d,umask=0x10 01 Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_snoop_rsp_misc.mtoi_rspdatam uncore cache Misc Snoop Responses Received : MtoI RspIDataM event=0x6b,umask=0x2 01 unc_cha_snoop_rsp_misc.mtoi_rspifwdm uncore cache Misc Snoop Responses Received : MtoI RspIFwdM event=0x6b,umask=0x1 01 unc_cha_snoop_rsp_misc.pulldataptl_hitllc uncore cache Misc Snoop Responses Received : Pull Data Partial - Hit LLC event=0x6b,umask=0x20 01 unc_cha_snoop_rsp_misc.pulldataptl_hitsf uncore cache Misc Snoop Responses Received : Pull Data Partial - Hit SF event=0x6b,umask=0x10 01 unc_cha_snoop_rsp_misc.rspifwdmptl_hitllc uncore cache Misc Snoop Responses Received : RspIFwdPtl Hit LLC event=0x6b,umask=0x8 01 unc_cha_snoop_rsp_misc.rspifwdmptl_hitsf uncore cache Misc Snoop Responses Received : RspIFwdPtl Hit SF event=0x6b,umask=0x4 01 unc_cha_tor_inserts.all uncore cache TOR Inserts : All event=0x35,umask=0xc001ffff 01 TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ddr uncore cache TOR Inserts : DDR Access event=0x35 01 TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.evict uncore cache TOR Inserts : SF/LLC Evictions event=0x35,umask=0x2 01 TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts : Just Hits event=0x35 01 TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia uncore cache TOR Inserts; All from Local IA event=0x35,umask=0xc001ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores unc_cha_tor_inserts.ia_clflush uncore cache TOR Inserts;CLFlush from Local IA event=0x35,umask=0xc8c7ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core unc_cha_tor_inserts.ia_clflushopt uncore cache TOR Inserts;CLFlushOpt from Local IA event=0x35,umask=0xc8d7ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core unc_cha_tor_inserts.ia_crd uncore cache TOR Inserts; CRd from local IA event=0x35,umask=0xc80fff01 01 TOR Inserts; Code read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_crd_pref uncore cache TOR Inserts; CRd Pref from local IA event=0x35,umask=0xc88fff01 01 TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd uncore cache TOR Inserts; DRd from local IA event=0x35,umask=0xc817ff01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores event=0x35,umask=0xc837ff01 01 TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt uncore cache TOR Inserts; DRd Opt from local IA event=0x35,umask=0xc827ff01 01 TOR Inserts; Data read opt from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref from local IA event=0x35,umask=0xc8a7ff01 01 TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_pref uncore cache TOR Inserts; DRd Pref from local IA event=0x35,umask=0xc897ff01 01 TOR Inserts; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts; Hits from Local IA event=0x35,umask=0xc001fd01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts; CRd hits from local IA event=0x35,umask=0xc80ffd01 01 TOR Inserts; Code read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_crd_pref uncore cache TOR Inserts; CRd Pref hits from local IA event=0x35,umask=0xc88ffd01 01 TOR Inserts; Code read prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_cxl_acc uncore cache All requests issued from IA cores to CXL accelerator memory regions that hit the LLC event=0x35,umask=0x10c0018101 01 unc_cha_tor_inserts.ia_hit_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c0008101 01 unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts; DRd hits from local IA event=0x35,umask=0xc817fd01 01 TOR Inserts; Data read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC event=0x35,umask=0xc837fd01 01 TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt uncore cache TOR Inserts; DRd Opt hits from local IA event=0x35,umask=0xc827fd01 01 TOR Inserts; Data read opt from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref hits from local IA event=0x35,umask=0xc8a7fd01 01 TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drd_pref uncore cache TOR Inserts; DRd Pref hits from local IA event=0x35,umask=0xc897fd01 01 TOR Inserts; Data read prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Hit LLC event=0x35,umask=0xcc47fd01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache TOR Inserts; LLCPrefCode hits from local IA event=0x35,umask=0xcccffd01 01 TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache TOR Inserts; LLCPrefData hits from local IA event=0x35,umask=0xccd7fd01 01 TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO hits from local IA event=0x35,umask=0xccc7fd01 01 TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts; RFO hits from local IA event=0x35,umask=0xc807fd01 01 TOR Inserts; Read for ownership from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache TOR Inserts; RFO Pref hits from local IA event=0x35,umask=0xc887fd01 01 TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_itom uncore cache TOR Inserts;ItoM from Local IA event=0x35,umask=0xcc47ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core unc_cha_tor_inserts.ia_itomcachenear uncore cache TOR Inserts : ItoMCacheNears issued by iA Cores event=0x35,umask=0xcd47ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefcode uncore cache TOR Inserts; LLCPrefCode from local IA event=0x35,umask=0xcccfff01 01 TOR Inserts; Last level cache prefetch code read from local IA unc_cha_tor_inserts.ia_llcprefdata uncore cache TOR Inserts; LLCPrefData from local IA event=0x35,umask=0xccd7ff01 01 TOR Inserts; Last level cache prefetch data read from local IA unc_cha_tor_inserts.ia_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO from local IA event=0x35,umask=0xccc7ff01 01 TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts; misses from Local IA event=0x35,umask=0xc001fe01 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts for CRd misses from local IA event=0x35,umask=0xc80ffe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd unc_cha_tor_inserts.ia_miss_crdmorph_cxl_acc uncore cache CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c80b8201 01 unc_cha_tor_inserts.ia_miss_crd_local uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc80efe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref uncore cache TOR Inserts; CRd Pref misses from local IA event=0x35,umask=0xc88ffe01 01 TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc88efe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc88f7e01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_remote uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc80f7e01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_cxl_acc uncore cache All requests issued from IA cores to CXL accelerator memory regions that miss the LLC event=0x35,umask=0x10c0018201 01 unc_cha_tor_inserts.ia_miss_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c0008201 01 unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts for DRd misses from local IA event=0x35,umask=0xc817fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd unc_cha_tor_inserts.ia_miss_drdmorph_cxl_acc uncore cache DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8138201 01 unc_cha_tor_inserts.ia_miss_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC event=0x35,umask=0xc837fe01 01 TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_cxl_acc uncore cache DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x35,umask=0x10c8178201 01 unc_cha_tor_inserts.ia_miss_drd_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c8168201 01 unc_cha_tor_inserts.ia_miss_drd_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_EXP_LOCAL event=0x35,ch_mask=0x000,umask=0x20c8168201 01 unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory unc_cha_tor_inserts.ia_miss_drd_local uncore cache TOR Inserts for DRd misses from local IA targeting local memory event=0x35,umask=0xc816fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt uncore cache TOR Inserts; DRd Opt misses from local IA event=0x35,umask=0xc827fe01 01 TOR Inserts; Data read opt from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c8268201 01 unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref misses from local IA event=0x35,umask=0xc8a7fe01 01 TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c8a68201 01 unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory unc_cha_tor_inserts.ia_miss_drd_pref uncore cache TOR Inserts for DRd Pref misses from local IA event=0x35,umask=0xc897fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF unc_cha_tor_inserts.ia_miss_drd_pref_cxl_acc uncore cache L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8978201 01 unc_cha_tor_inserts.ia_miss_drd_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c8968201 01 unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8978601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache TOR Inserts for DRd Pref misses from local IA targeting local memory event=0x35,umask=0xc896fe01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8978a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache TOR Inserts for DRd Pref misses from local IA targeting remote memory event=0x35,umask=0xc8977e01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote uncore cache TOR Inserts for DRd misses from local IA targeting remote memory event=0x35,umask=0xc8177e01 01 Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Missed LLC event=0x35,umask=0xcc47fe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache TOR Inserts; LLCPrefCode misses from local IA event=0x35,umask=0xcccffe01 01 TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefcode_cxl_acc uncore cache LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10cccf8201 01 unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache TOR Inserts; LLCPrefData misses from local IA event=0x35,umask=0xccd7fe01 01 TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_acc uncore cache LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10ccd78201 01 unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10ccd68201 01 unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO misses from local IA event=0x35,umask=0xccc7fe01 01 TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_acc uncore cache L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8878201 01 unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c8868201 01 unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc8668601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc8668a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc86e8601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc86e8a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc8670601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc8670a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts; RFO misses from local IA event=0x35,umask=0xc807fe01 01 TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfomorph_cxl_acc uncore cache RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8038201 01 unc_cha_tor_inserts.ia_miss_rfo_cxl_acc uncore cache RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8078201 01 unc_cha_tor_inserts.ia_miss_rfo_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10c8068201 01 unc_cha_tor_inserts.ia_miss_rfo_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_EXP_LOCAL event=0x35,ch_mask=0x000,umask=0x20c8068201 01 unc_cha_tor_inserts.ia_miss_rfo_local uncore cache TOR Inserts RFO misses from local IA event=0x35,umask=0xc806fe01 01 TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache TOR Inserts; RFO pref misses from local IA event=0x35,umask=0xc887fe01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_acc uncore cache LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10ccc78201 01 unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL event=0x35,ch_mask=0x000,umask=0x10ccc68201 01 unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache TOR Inserts; RFO prefetch misses from local IA event=0x35,umask=0xc886fe01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache TOR Inserts; RFO prefetch misses from local IA event=0x35,umask=0xc8877e01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache TOR Inserts; RFO misses from local IA event=0x35,umask=0xc8077e01 01 TOR Inserts Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_ucrdf uncore cache TOR Inserts : UCRdFs issued by iA Cores that Missed LLC event=0x35,umask=0xc877de01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores that Missed the LLC event=0x35,umask=0xc86ffe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores that Missed the LLC event=0x35,umask=0xc867fe01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc8678601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc8678a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc86f8601 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc86f8a01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wil uncore cache TOR Inserts : WiLs issued by iA Cores that Missed LLC event=0x35,umask=0xc87fde01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo uncore cache TOR Inserts; RFO from local IA event=0x35,umask=0xc807ff01 01 TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_rfo_pref uncore cache TOR Inserts; RFO pref from local IA event=0x35,umask=0xc887ff01 01 TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_specitom uncore cache TOR Inserts;SpecItoM from Local IA event=0x35,umask=0xcc57ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core unc_cha_tor_inserts.ia_wbeftoe uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc3fff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbeftoi uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc37ff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoe uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc2fff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs event=0x35,umask=0xcc27ff01 01 WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbstoi uncore cache TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc67ff01 01 WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores event=0x35,umask=0xc86fff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores event=0x35,umask=0xc867ff01 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts; All from local IO event=0x35,umask=0xc001ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_clflush uncore cache TOR Inserts : CLFlushes issued by IO Devices event=0x35,umask=0xc8c3ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit uncore cache TOR Inserts; Hits from local IO event=0x35,umask=0xc001fd04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itom uncore cache TOR Inserts; ItoM hits from local IO event=0x35,umask=0xcc43fd04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x35,umask=0xcd43fd04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_pcirdcur uncore cache TOR Inserts; RdCur and FsRdCur hits from local IO event=0x35,umask=0xc8f3fd04 01 TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_rfo uncore cache TOR Inserts; RFO hits from local IO event=0x35,umask=0xc803fd04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom uncore cache TOR Inserts for ItoM from local IO event=0x35,umask=0xcc43ff04 01 Inserts into the TOR from local IO with the opcode ItoM unc_cha_tor_inserts.io_itomcachenear uncore cache TOR Inserts for ItoMCacheNears from IO devices event=0x35,umask=0xcd43ff04 01 Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request unc_cha_tor_inserts.io_miss uncore cache TOR Inserts; Misses from local IO event=0x35,umask=0xc001fe04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts; ItoM misses from local IO event=0x35,umask=0xcc43fe04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x35,umask=0xcd43fe04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_pcirdcur uncore cache TOR Inserts; RdCur and FsRdCur misses from local IO event=0x35,umask=0xc8f3fe04 01 TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts; RFO misses from local IO event=0x35,umask=0xc803fe04 01 TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur uncore cache TOR Inserts for RdCur from local IO event=0x35,umask=0xc8f3ff04 01 Inserts into the TOR from local IO with the opcode RdCur unc_cha_tor_inserts.io_rfo uncore cache TOR Inserts; RFO from local IO event=0x35,umask=0xc803ff04 01 TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by IO Devices event=0x35,umask=0xcc23ff04 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ipq uncore cache TOR Inserts : IPQ event=0x35,umask=0x8 01 TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.irq_ia uncore cache TOR Inserts : IRQ - iA event=0x35,umask=0x1 01 TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core unc_cha_tor_inserts.irq_non_ia uncore cache TOR Inserts : IRQ - Non iA event=0x35,umask=0x10 01 TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.isoc uncore cache TOR Inserts : Just ISOC event=0x35 01 TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.local_tgt uncore cache TOR Inserts : Just Local Targets event=0x35 01 TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.loc_all uncore cache TOR Inserts : All from Local iA and IO event=0x35,umask=0xc000ff05 01 TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests unc_cha_tor_inserts.loc_ia uncore cache TOR Inserts : All from Local iA event=0x35,umask=0xc000ff01 01 TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores unc_cha_tor_inserts.loc_io uncore cache TOR Inserts : All from Local IO event=0x35,umask=0xc000ff04 01 TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic unc_cha_tor_inserts.match_opc uncore cache TOR Inserts : Match the Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.miss uncore cache TOR Inserts : Just Misses event=0x35 01 TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.mmcfg uncore cache TOR Inserts : MMCFG Access event=0x35 01 TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.mmio uncore cache TOR Inserts : MMIO Access event=0x35 01 TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.nearmem uncore cache TOR Inserts : Just NearMem event=0x35 01 TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.noncoh uncore cache TOR Inserts : Just NonCoherent event=0x35 01 TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.not_nearmem uncore cache TOR Inserts : Just NotNearMem event=0x35 01 TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.pmm uncore cache TOR Inserts : PMM Access event=0x35 01 TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.premorph_opc uncore cache TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.prq_iosf uncore cache TOR Inserts : PRQ - IOSF event=0x35,umask=0x4 01 TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device unc_cha_tor_inserts.prq_non_iosf uncore cache TOR Inserts : PRQ - Non IOSF event=0x35,umask=0x20 01 TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.remote_tgt uncore cache TOR Inserts : Just Remote Targets event=0x35 01 TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rem_all uncore cache TOR Inserts : All from Remote event=0x35,umask=0xc001ffc8 01 TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets unc_cha_tor_inserts.rem_snps uncore cache TOR Inserts : All Snoops from Remote event=0x35,umask=0xc001ff08 01 TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets unc_cha_tor_inserts.rrq uncore cache TOR Inserts : RRQ event=0x35,umask=0x40 01 TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.snps_from_rem uncore cache TOR Inserts; All Snoops from Remote event=0x35,umask=0xc001ff08 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets unc_cha_tor_inserts.wbq uncore cache TOR Inserts : WBQ event=0x35,umask=0x80 01 TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.all uncore cache TOR Occupancy : All event=0x36,umask=0xc001ffff 01 TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ddr uncore cache TOR Occupancy : DDR Access event=0x36 01 TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.evict uncore cache TOR Occupancy : SF/LLC Evictions event=0x36,umask=0x2 01 TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy : Just Hits event=0x36 01 TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.ia uncore cache TOR Occupancy; All from local IA event=0x36,umask=0xc001ff01 01 TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_clflush uncore cache TOR Occupancy : CLFlushes issued by iA Cores event=0x36,umask=0xc8c7ff01 01 TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_clflushopt uncore cache TOR Occupancy : CLFlushOpts issued by iA Cores event=0x36,umask=0xc8d7ff01 01 TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy; CRd from local IA event=0x36,umask=0xc80fff01 01 TOR Occupancy; Code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_crd_pref uncore cache TOR Occupancy; CRd Pref from local IA event=0x36,umask=0xc88fff01 01 TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy; DRd from local IA event=0x36,umask=0xc817ff01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk event=0x36,ch_mask=0x00000000,fc_mask=0x00000000,umask=0xc837ff01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy; DRd Opt from local IA event=0x36,umask=0xc827ff01 01 TOR Occupancy; Data read opt from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref from local IA event=0x36,umask=0xc8a7ff01 01 TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy; DRd Pref from local IA event=0x36,umask=0xc897ff01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy; Hits from local IA event=0x36,umask=0xc001fd01 01 TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy; CRd hits from local IA event=0x36,umask=0xc80ffd01 01 TOR Occupancy; Code read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy; CRd Pref hits from local IA event=0x36,umask=0xc88ffd01 01 TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_cxl_acc uncore cache TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC event=0x36,umask=0x10c0018101 01 unc_cha_tor_occupancy.ia_hit_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c0008101 01 unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy; DRd hits from local IA event=0x36,umask=0xc817fd01 01 TOR Occupancy; Data read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC event=0x36,ch_mask=0x00000000,fc_mask=0x00000000,umask=0xc837fd01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy; DRd Opt hits from local IA event=0x36,umask=0xc827fd01 01 TOR Occupancy; Data read opt from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref hits from local IA event=0x36,umask=0xc8a7fd01 01 TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy; DRd Pref hits from local IA event=0x36,umask=0xc897fd01 01 TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores that Hit LLC event=0x36,umask=0xcc47fd01 01 TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy; LLCPrefCode hits from local IA event=0x36,umask=0xcccffd01 01 TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy; LLCPrefData hits from local IA event=0x36,umask=0xccd7fd01 01 TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO hits from local IA event=0x36,umask=0xccc7fd01 01 TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy; RFO hits from local IA event=0x36,umask=0xc807fd01 01 TOR Occupancy; Read for ownership from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy; RFO Pref hits from local IA event=0x36,umask=0xc887fd01 01 TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores event=0x36,umask=0xcc47ff01 01 TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears issued by iA Cores event=0x36,umask=0xcd47ff01 01 TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy; LLCPrefCode from local IA event=0x36,umask=0xcccfff01 01 TOR Occupancy; Last level cache prefetch data read from local IA unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy; LLCPrefData from local IA event=0x36,umask=0xccd7ff01 01 TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO from local IA event=0x36,umask=0xccc7ff01 01 TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy; Misses from Local IA event=0x36,umask=0xc001fe01 01 TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy; CRd misses from local IA event=0x36,umask=0xc80ffe01 01 TOR Occupancy; Code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_crdmorph_cxl_acc uncore cache TOR Occupancy for CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c80b8201 01 unc_cha_tor_occupancy.ia_miss_crd_local uncore cache TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc80efe01 01 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy; CRd Pref misses from local IA event=0x36,umask=0xc88ffe01 01 TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_crd_pref_local uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc88efe01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref_remote uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc88f7e01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_remote uncore cache TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc80f7e01 01 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_cxl_acc uncore cache TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC event=0x36,umask=0x10c0018201 01 unc_cha_tor_occupancy.ia_miss_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c0008201 01 unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy for DRd misses from local IA event=0x36,umask=0xc817fe01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd unc_cha_tor_occupancy.ia_miss_drdmorph_cxl_acc uncore cache TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8138201 01 unc_cha_tor_occupancy.ia_miss_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC event=0x36,ch_mask=0x00000000,fc_mask=0x00000000,umask=0xc837fe01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_cxl_acc uncore cache TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x36,umask=0x10c8178201 01 unc_cha_tor_occupancy.ia_miss_drd_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c8168201 01 unc_cha_tor_occupancy.ia_miss_drd_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_EXP_LOCAL event=0x36,ch_mask=0x000,umask=0x20c8168201 01 unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy for DRd misses from local IA targeting local memory event=0x36,umask=0xc816fe01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory unc_cha_tor_occupancy.ia_miss_drd_local_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8168601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_local_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8168a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy; DRd Opt misses from local IA event=0x36,umask=0xc827fe01 01 TOR Occupancy; Data read opt from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_opt_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c8268201 01 unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref misses from local IA event=0x36,umask=0xc8a7fe01 01 TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_opt_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c8a68201 01 unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc897fe01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_acc uncore cache TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8978201 01 unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c8968201 01 unc_cha_tor_occupancy.ia_miss_drd_pref_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8978601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_local uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc896fe01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_local_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8968601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_local_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8968a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8978a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_remote uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc8977e01 01 TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_remote_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8970601 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_remote_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8970a01 01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy for DRd misses from local IA targeting remote memory event=0x36,umask=0xc8177e01 01 Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory unc_cha_tor_occupancy.ia_miss_drd_remote_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8170601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8170a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores that Missed LLC event=0x36,umask=0xcc47fe01 01 TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy; LLCPrefCode misses from local IA event=0x36,umask=0xcccffe01 01 TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefcode_cxl_acc uncore cache TOR Occupancy for LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10cccf8201 01 unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy; LLCPrefData misses from local IA event=0x36,umask=0xccd7fe01 01 TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_acc uncore cache TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10ccd78201 01 unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10ccd68201 01 unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO misses from local IA event=0x36,umask=0xccc7fe01 01 TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_acc uncore cache TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8878201 01 unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c8868201 01 unc_cha_tor_occupancy.ia_miss_local_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x36,umask=0xc8668601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x36,umask=0xc8668a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x36,umask=0xc86e8601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x36,umask=0xc86e8a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x36,umask=0xc8670601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x36,umask=0xc8670a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x36,umask=0xc86f0601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x36,umask=0xc86f0a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc807fe01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfomorph_cxl_acc uncore cache TOR Occupancy for RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8038201 01 unc_cha_tor_occupancy.ia_miss_rfo_cxl_acc uncore cache TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8078201 01 unc_cha_tor_occupancy.ia_miss_rfo_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10c8068201 01 unc_cha_tor_occupancy.ia_miss_rfo_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_EXP_LOCAL event=0x36,ch_mask=0x000,umask=0x20c8068201 01 unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc806fe01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc887fe01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_acc uncore cache TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10ccc78201 01 unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL event=0x36,ch_mask=0x000,umask=0x10ccc68201 01 unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc886fe01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc8877e01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc8077e01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_ucrdf uncore cache TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC event=0x36,umask=0xc877de01 01 TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil uncore cache TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC event=0x36,umask=0xc86ffe01 01 TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf uncore cache TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC event=0x36,umask=0xc867fe01 01 TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x36,umask=0xc8678601 01 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x36,umask=0xc8678a01 01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x36,umask=0xc86f8601 01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x36,umask=0xc86f8a01 01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wil uncore cache TOR Occupancy : WiLs issued by iA Cores that Missed LLC event=0x36,umask=0xc87fde01 01 TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy; RFO from local IA event=0x36,umask=0xc807ff01 01 TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy; RFO prefetch from local IA event=0x36,umask=0xc887ff01 01 TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_specitom uncore cache TOR Occupancy : SpecItoMs issued by iA Cores event=0x36,umask=0xcc57ff01 01 TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wbmtoi uncore cache TOR Occupancy : WbMtoIs issued by iA Cores event=0x36,umask=0xcc27ff01 01 TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wcil uncore cache TOR Occupancy : WCiLs issued by iA Cores event=0x36,umask=0xc86fff01 01 TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wcilf uncore cache TOR Occupancy : WCiLF issued by iA Cores event=0x36,umask=0xc867ff01 01 TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy; All from local IO event=0x36,umask=0xc001ff04 01 TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_clflush uncore cache TOR Occupancy : CLFlushes issued by IO Devices event=0x36,umask=0xc8c3ff04 01 TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy; Hits from local IO event=0x36,umask=0xc001fd04 01 TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy; ITOM hits from local IO event=0x36,umask=0xcc43fd04 01 TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x36,umask=0xcd43fd04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur hits from local IO event=0x36,umask=0xc8f3fd04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy; RFO hits from local IO event=0x36,umask=0xc803fd04 01 TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy; ITOM from local IO event=0x36,umask=0xcc43ff04 01 TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices event=0x36,ch_mask=0x00000000,fc_mask=0x00000000,umask=0xcd43ff04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy; Misses from local IO event=0x36,umask=0xc001fe04 01 TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy; ITOM misses from local IO event=0x36,umask=0xcc43fe04 01 TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x36,umask=0xcd43fe04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur misses from local IO event=0x36,umask=0xc8f3fe04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy; RFO misses from local IO event=0x36,umask=0xc803fe04 01 TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur from local IO event=0x36,umask=0xc8f3ff04 01 TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy; ItoM from local IO event=0x36,umask=0xc803ff04 01 TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_wbmtoi uncore cache TOR Occupancy : WbMtoIs issued by IO Devices event=0x36,umask=0xcc23ff04 01 TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy : IPQ event=0x36,umask=0x8 01 TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.irq_ia uncore cache TOR Occupancy : IRQ - iA event=0x36,umask=0x1 01 TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From an iA Core unc_cha_tor_occupancy.irq_non_ia uncore cache TOR Occupancy : IRQ - Non iA event=0x36,umask=0x10 01 TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.isoc uncore cache TOR Occupancy : Just ISOC event=0x36 01 TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.local_tgt uncore cache TOR Occupancy : Just Local Targets event=0x36 01 TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy : All from Local iA and IO event=0x36,umask=0xc000ff05 01 TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy : All from Local iA event=0x36,umask=0xc000ff01 01 TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests from iA Cores unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy : All from Local IO event=0x36,umask=0xc000ff04 01 TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally generated IO traffic unc_cha_tor_occupancy.match_opc uncore cache TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.miss uncore cache TOR Occupancy : Just Misses event=0x36 01 TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.mmcfg uncore cache TOR Occupancy : MMCFG Access event=0x36 01 TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.mmio uncore cache TOR Occupancy : MMIO Access event=0x36 01 TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.nearmem uncore cache TOR Occupancy : Just NearMem event=0x36 01 TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.noncoh uncore cache TOR Occupancy : Just NonCoherent event=0x36 01 TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.not_nearmem uncore cache TOR Occupancy : Just NotNearMem event=0x36 01 TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.pmm uncore cache TOR Occupancy : PMM Access event=0x36 01 TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.premorph_opc uncore cache TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.prq uncore cache TOR Occupancy : PRQ - IOSF event=0x36,umask=0x4 01 TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From a PCIe Device unc_cha_tor_occupancy.prq_non_iosf uncore cache TOR Occupancy : PRQ - Non IOSF event=0x36,umask=0x20 01 TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.remote_tgt uncore cache TOR Occupancy : Just Remote Targets event=0x36 01 TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.rem_all uncore cache TOR Occupancy : All from Remote event=0x36,umask=0xc001ffc8 01 TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All remote requests (e.g. snoops, writebacks) that came from remote sockets unc_cha_tor_occupancy.rem_snps uncore cache TOR Occupancy : All Snoops from Remote event=0x36,umask=0xc001ff08 01 TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All snoops to this LLC that came from remote sockets unc_cha_tor_occupancy.rrq uncore cache TOR Occupancy : RRQ event=0x36,umask=0x40 01 TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_tor_occupancy.snps_from_rem uncore cache TOR Occupancy; All Snoops from Remote event=0x36,umask=0xc001ff08 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets unc_cha_tor_occupancy.wbq uncore cache TOR Occupancy : WBQ event=0x36,umask=0x80 01 TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T unc_cha_wb_push_mtoi.llc uncore cache WbPushMtoI : Pushed to LLC event=0x56,umask=0x1 01 WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC unc_cha_wb_push_mtoi.mem uncore cache WbPushMtoI : Pushed to Memory event=0x56,umask=0x2 01 WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM) unc_cha_write_no_credits.mc0 uncore cache CHA iMC CHNx WRITE Credits Empty : MC0 event=0x5a,umask=0x1 01 CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only unc_cha_write_no_credits.mc1 uncore cache CHA iMC CHNx WRITE Credits Empty : MC1 event=0x5a,umask=0x2 01 CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only unc_cha_write_no_credits.mc2 uncore cache CHA iMC CHNx WRITE Credits Empty : MC2 event=0x5a,umask=0x4 01 CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only unc_cha_write_no_credits.mc3 uncore cache CHA iMC CHNx WRITE Credits Empty : MC3 event=0x5a,umask=0x8 01 CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only unc_cha_write_no_credits.mc4 uncore cache CHA iMC CHNx WRITE Credits Empty : MC4 event=0x5a,umask=0x10 01 CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only unc_cha_write_no_credits.mc5 uncore cache CHA iMC CHNx WRITE Credits Empty : MC5 event=0x5a,umask=0x20 01 CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only unc_cha_xpt_pref.drop0_conflict uncore cache XPT Prefetches : Dropped (on 0?) - Conflict event=0x6f,umask=0x8 01 XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention unc_cha_xpt_pref.drop0_nocrd uncore cache XPT Prefetches : Dropped (on 0?) - No Credits event=0x6f,umask=0x4 01 XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits unc_cha_xpt_pref.drop1_conflict uncore cache XPT Prefetches : Dropped (on 1?) - Conflict event=0x6f,umask=0x80 01 XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention unc_cha_xpt_pref.drop1_nocrd uncore cache XPT Prefetches : Dropped (on 1?) - No Credits event=0x6f,umask=0x40 01 XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits unc_cha_xpt_pref.sent0 uncore cache XPT Prefetches : Sent (on 0?) event=0x6f,umask=0x1 01 XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent unc_cha_xpt_pref.sent1 uncore cache XPT Prefetches : Sent (on 1?) event=0x6f,umask=0x10 01 XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent uncore_cxlcm unc_cxlcm_clockticks uncore cxl Counts the number of lfclk ticks event=0x1,umask=0x2 01 unc_cxlcm_rxc_agf_inserts.cache_data uncore cxl Number of Allocation to Mem Rxx AGF 0 event=0x43,umask=0x8 01 unc_cxlcm_rxc_agf_inserts.cache_req0 uncore cxl Number of Allocation to Cache Req AGF0 event=0x43,umask=0x1 01 unc_cxlcm_rxc_agf_inserts.cache_req1 uncore cxl Number of Allocation to Cache Rsp AGF event=0x43,umask=0x2 01 unc_cxlcm_rxc_agf_inserts.cache_rsp0 uncore cxl Number of Allocation to Cache Data AGF event=0x43,umask=0x4 01 unc_cxlcm_rxc_agf_inserts.cache_rsp1 uncore cxl Number of Allocation to Cache Rsp AGF event=0x43,umask=0x40 01 unc_cxlcm_rxc_agf_inserts.mem_data uncore cxl Number of Allocation to Cache Req AGF 1 event=0x43,umask=0x20 01 unc_cxlcm_rxc_agf_inserts.mem_req uncore cxl Number of Allocation to Mem Data AGF event=0x43,umask=0x10 01 unc_cxlcm_rxc_flits.ak_hdr uncore cxl Count the number of Flits with AK set event=0x4b,umask=0x10 01 unc_cxlcm_rxc_flits.be_hdr uncore cxl Count the number of Flits with BE set event=0x4b,umask=0x20 01 unc_cxlcm_rxc_flits.ctrl uncore cxl Count the number of control flits received event=0x4b,umask=0x4 01 unc_cxlcm_rxc_flits.no_hdr uncore cxl Count the number of Headerless flits received event=0x4b,umask=0x8 01 unc_cxlcm_rxc_flits.prot uncore cxl Count the number of protocol flits received event=0x4b,umask=0x2 01 unc_cxlcm_rxc_flits.sz_hdr uncore cxl Count the number of Flits with SZ set event=0x4b,umask=0x40 01 unc_cxlcm_rxc_flits.valid uncore cxl Count the number of flits received event=0x4b,umask=0x1 01 unc_cxlcm_rxc_flits.valid_msg uncore cxl Count the number of valid messages in the flit event=0x4b,umask=0x80 01 unc_cxlcm_rxc_misc.crc_errors uncore cxl Count the number of CRC errors detected event=0x40,umask=0x8 01 unc_cxlcm_rxc_misc.init uncore cxl Count the number of Init flits sent event=0x40,umask=0x4 01 unc_cxlcm_rxc_misc.llcrd uncore cxl Count the number of LLCRD flits sent event=0x40,umask=0x1 01 unc_cxlcm_rxc_misc.retry uncore cxl Count the number of Retry flits sent event=0x40,umask=0x2 01 unc_cxlcm_rxc_pack_buf_full.cache_data uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=0x4 01 unc_cxlcm_rxc_pack_buf_full.cache_req uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=0x1 01 unc_cxlcm_rxc_pack_buf_full.cache_rsp uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=0x2 01 unc_cxlcm_rxc_pack_buf_full.mem_data uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=0x10 01 unc_cxlcm_rxc_pack_buf_full.mem_req uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=0x8 01 unc_cxlcm_rxc_pack_buf_inserts.cache_data uncore cxl Number of Allocation to Cache Data Packing buffer event=0x41,umask=0x4 01 unc_cxlcm_rxc_pack_buf_inserts.cache_req uncore cxl Number of Allocation to Cache Req Packing buffer event=0x41,umask=0x1 01 unc_cxlcm_rxc_pack_buf_inserts.cache_rsp uncore cxl Number of Allocation to Cache Rsp Packing buffer event=0x41,umask=0x2 01 unc_cxlcm_rxc_pack_buf_inserts.mem_data uncore cxl Number of Allocation to Mem Data Packing buffer event=0x41,umask=0x10 01 unc_cxlcm_rxc_pack_buf_inserts.mem_req uncore cxl Number of Allocation to Mem Rxx Packing buffer event=0x41,umask=0x8 01 unc_cxlcm_rxc_pack_buf_ne.cache_data uncore cxl Number of cycles of Not Empty for Cache Data Packing buffer event=0x42,umask=0x4 01 unc_cxlcm_rxc_pack_buf_ne.cache_req uncore cxl Number of cycles of Not Empty for Cache Req Packing buffer event=0x42,umask=0x1 01 unc_cxlcm_rxc_pack_buf_ne.cache_rsp uncore cxl Number of cycles of Not Empty for Cache Rsp Packing buffer event=0x42,umask=0x2 01 unc_cxlcm_rxc_pack_buf_ne.mem_data uncore cxl Number of cycles of Not Empty for Mem Data Packing buffer event=0x42,umask=0x10 01 unc_cxlcm_rxc_pack_buf_ne.mem_req uncore cxl Number of cycles of Not Empty for Mem Rxx Packing buffer event=0x42,umask=0x8 01 unc_cxlcm_txc_flits.ak_hdr uncore cxl Count the number of Flits with AK set event=0x5,umask=0x10 01 unc_cxlcm_txc_flits.be_hdr uncore cxl Count the number of Flits with BE set event=0x5,umask=0x20 01 unc_cxlcm_txc_flits.ctrl uncore cxl Count the number of control flits packed event=0x5,umask=0x4 01 unc_cxlcm_txc_flits.no_hdr uncore cxl Count the number of Headerless flits packed event=0x5,umask=0x8 01 unc_cxlcm_txc_flits.prot uncore cxl Count the number of protocol flits packed event=0x5,umask=0x2 01 unc_cxlcm_txc_flits.sz_hdr uncore cxl Count the number of Flits with SZ set event=0x5,umask=0x40 01 unc_cxlcm_txc_flits.valid uncore cxl Count the number of flits packed event=0x5,umask=0x1 01 unc_cxlcm_txc_pack_buf_inserts.cache_data uncore cxl Number of Allocation to Cache Data Packing buffer event=0x2,umask=0x4 01 unc_cxlcm_txc_pack_buf_inserts.cache_req0 uncore cxl Number of Allocation to Cache Req Packing buffer event=0x2,umask=0x1 01 unc_cxlcm_txc_pack_buf_inserts.cache_req1 uncore cxl Number of Allocation to Cache Rsp1 Packing buffer event=0x2,umask=0x40 01 unc_cxlcm_txc_pack_buf_inserts.cache_rsp0 uncore cxl Number of Allocation to Cache Rsp0 Packing buffer event=0x2,umask=0x2 01 unc_cxlcm_txc_pack_buf_inserts.cache_rsp1 uncore cxl Number of Allocation to Cache Req Packing buffer event=0x2,umask=0x20 01 unc_cxlcm_txc_pack_buf_inserts.mem_data uncore cxl Number of Allocation to Mem Data Packing buffer event=0x2,umask=0x10 01 unc_cxlcm_txc_pack_buf_inserts.mem_req uncore cxl Number of Allocation to Mem Rxx Packing buffer event=0x2,umask=0x8 01 uncore_cxldp unc_cxldp_clockticks uncore cxl Counts the number of uclk ticks event=0x1,umask=0x1 01 unc_cxldp_txc_agf_inserts.m2s_data uncore cxl Number of Allocation to M2S Data AGF event=0x2,umask=0x20 01 unc_cxldp_txc_agf_inserts.m2s_req uncore cxl Number of Allocation to M2S Req AGF event=0x2,umask=0x10 01 unc_cxldp_txc_agf_inserts.u2c_data uncore cxl Number of Allocation to U2C Data AGF event=0x2,umask=0x8 01 unc_cxldp_txc_agf_inserts.u2c_req uncore cxl Number of Allocation to U2C Req AGF event=0x2,umask=0x1 01 unc_cxldp_txc_agf_inserts.u2c_rsp0 uncore cxl Number of Allocation to U2C Rsp AGF 0 event=0x2,umask=0x2 01 unc_cxldp_txc_agf_inserts.u2c_rsp1 uncore cxl Number of Allocation to U2C Rsp AGF 1 event=0x2,umask=0x4 01 unc_i_cache_total_occupancy.mem uncore interconnect Total IRP occupancy of inbound read and write requests to coherent memory event=0xf,umask=0x4 01 Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy unc_i_clockticks uncore interconnect IRP Clockticks event=0x1 01 Number of IRP clock cycles while the event is enabled unc_i_faf_inserts uncore interconnect FAF - request insert from TC event=0x18 01 unc_i_faf_occupancy uncore interconnect FAF occupancy event=0x19 01 unc_i_irp_all.evicts uncore interconnect : All Inserts Outbound (BL, AK, Snoops) event=0x20,umask=0x4 01 unc_i_irp_all.inbound_inserts uncore interconnect : All Inserts Inbound (p2p + faf + cset) event=0x20,umask=0x1 01 unc_i_irp_all.outbound_inserts uncore interconnect : All Inserts Outbound (BL, AK, Snoops) event=0x20,umask=0x2 01 unc_i_misc0.2nd_atomic_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary event=0x1e,umask=0x10 01 unc_i_misc0.2nd_rd_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary event=0x1e,umask=0x4 01 unc_i_misc0.2nd_wr_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary event=0x1e,umask=0x8 01 unc_i_misc0.fast_rej uncore interconnect Counts Timeouts - Set 0 : Fastpath Rejects event=0x1e,umask=0x2 01 unc_i_misc0.fast_req uncore interconnect Counts Timeouts - Set 0 : Fastpath Requests event=0x1e,umask=0x1 01 unc_i_misc0.fast_xfer uncore interconnect Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary event=0x1e,umask=0x20 01 unc_i_misc0.pf_ack_hint uncore interconnect Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary event=0x1e,umask=0x40 01 unc_i_misc0.slowpath_fwpf_no_prf uncore interconnect Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch event=0x1e,umask=0x80 01 unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 : Lost Forward event=0x1f,umask=0x10 01 Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1 : Received Invalid event=0x1f,umask=0x20 01 Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1 : Received Valid event=0x1f,umask=0x40 01 Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1 : Slow Transfer of E Line event=0x1f,umask=0x4 01 Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1 : Slow Transfer of I Line event=0x1f,umask=0x1 01 Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1 : Slow Transfer of M Line event=0x1f,umask=0x8 01 Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1 : Slow Transfer of S Line event=0x1f,umask=0x2 01 Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses : Hit E or S event=0x12,umask=0x4 01 unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses : Hit I event=0x12,umask=0x2 01 unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses : Hit M event=0x12,umask=0x8 01 unc_i_snoop_resp.miss uncore interconnect Snoop Responses : Miss event=0x12,umask=0x1 01 unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses : SnpCode event=0x12,umask=0x10 01 unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses : SnpData event=0x12,umask=0x20 01 unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses : SnpInv event=0x12,umask=0x40 01 unc_i_txr2_ad01_stall_credit_cycles uncore interconnect UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES event=0x1c 01 : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0AD1 both. Stalls on both AD0 and AD1 will count as 2 unc_i_txr2_ad0_stall_credit_cycles uncore interconnect No AD0 Egress Credits Stalls event=0x1a 01 No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available unc_i_txr2_ad1_stall_credit_cycles uncore interconnect No AD1 Egress Credits Stalls event=0x1b 01 No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available unc_i_txr2_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x1d 01 No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txs_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xd 01 Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices) unc_i_txs_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xe 01 Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices) unc_i_txs_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xc 01 Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests unc_m2m_clockticks uncore interconnect M2M Clockticks event=0x1 01 Clockticks of the mesh to memory (M2M) unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x17,umask=0x7 01 unc_m2m_direct2core_not_taken_dirstate.non_cisgress uncore interconnect Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress event=0x17,umask=0x2 01 Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress : Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints unc_m2m_direct2core_not_taken_notforked uncore interconnect Counts the time when FM didn't do d2c for fill reads (cross tile case) event=0x4a 01 unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction were overridden event=0x18,umask=0x3 01 unc_m2m_direct2core_txn_override.cisgress uncore interconnect Number of reads in which direct to core transaction was overridden : Cisgress event=0x18,umask=0x2 01 unc_m2m_direct2core_txn_override.pmm_hit uncore interconnect Number of reads in which direct to core transaction was overridden : 2LM Hit? event=0x18,umask=0x1 01 unc_m2m_direct2upitxn_override.pmm_hit uncore interconnect Number of times a direct to UPI transaction was overridden event=0x1c,umask=0x1 01 Number of times a direct to UPI transaction was overridden. : Counts the number of times D2K wasn't honored even though the incoming request had d2k set unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel UPI transactions were overridden event=0x1b,umask=0x7 01 unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when direct to Intel UPI was disabled event=0x1a,umask=0x7 01 unc_m2m_direct2upi_not_taken_dirstate.cisgress uncore interconnect Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored event=0x1a,umask=0x4 01 Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored : Counts cisgress d2K that was not honored due to directory constraints unc_m2m_direct2upi_not_taken_dirstate.egress uncore interconnect Cycles when Direct2UPI was Disabled : Egress Ignored D2U event=0x1a,umask=0x1 01 Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints unc_m2m_direct2upi_not_taken_dirstate.non_cisgress uncore interconnect Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored event=0x1a,umask=0x2 01 Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored : Counts non cisgress d2K that was not honored due to directory constraints unc_m2m_direct2upi_taken uncore interconnect Messages sent direct to the Intel UPI event=0x19,umask=0x7 01 Counts the number of times egress did D2K (Direct to KTI) unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel UPI was overridden event=0x1c,umask=0x3 01 unc_m2m_direct2upi_txn_override.cisgress uncore interconnect Number of times a direct to UPI transaction was overridden event=0x1c,umask=0x2 01 unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x80 01 unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x1d,umask=0x10 01 unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit : On NonDirty Line in L State event=0x1d,umask=0x40 01 unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x20 01 unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x1d,umask=0x8 01 unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x1d,umask=0x1 01 unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit : On Dirty Line in L State event=0x1d,umask=0x4 01 unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x1d,umask=0x2 01 unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory lookups (any state found) event=0x20,umask=0x1 01 Counts the number of hit data returns to egress with any directory to non persistent memory unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x20,umask=0x8 01 Counts the number of hit data returns to egress with directory A to non persistent memory unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x20,umask=0x2 01 Counts the number of hit data returns to egress with directory I to non persistent memory unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x20,umask=0x4 01 Counts the number of hit data returns to egress with directory S to non persistent memory unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x80 01 unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x1e,umask=0x10 01 unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss : On NonDirty Line in L State event=0x1e,umask=0x40 01 unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x20 01 unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x1e,umask=0x8 01 unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x1e,umask=0x1 01 unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss : On Dirty Line in L State event=0x1e,umask=0x4 01 unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x1e,umask=0x2 01 unc_m2m_directory_update.a2i uncore interconnect Multi-socket cacheline Directory update from A to I event=0x21,umask=0x320 01 unc_m2m_directory_update.a2s uncore interconnect Multi-socket cacheline Directory update from A to S event=0x21,umask=0x340 01 unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory update from/to Any state event=0x21,umask=0x301 01 unc_m2m_directory_update.a_to_i_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x120 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_i_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x220 01 Counts 2lm miss data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_s_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x140 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_s_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x240 01 Counts 2lm miss data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x101 01 Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i2a uncore interconnect Multi-socket cacheline Directory update from I to A event=0x21,umask=0x304 01 unc_m2m_directory_update.i2s uncore interconnect Multi-socket cacheline Directory update from I to S event=0x21,umask=0x302 01 unc_m2m_directory_update.i_to_a_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x104 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_a_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x204 01 Counts 2lm miss data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_s_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x102 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_s_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x202 01 Counts 2lm miss data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x201 01 Counts any 2lm miss data return that would result in directory update to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s2a uncore interconnect Multi-socket cacheline Directory update from S to A event=0x21,umask=0x310 01 unc_m2m_directory_update.s2i uncore interconnect Multi-socket cacheline Directory update from S to I event=0x21,umask=0x308 01 unc_m2m_directory_update.s_to_a_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x110 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_a_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x210 01 Counts 2lm miss data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_i_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x108 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_i_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x208 01 Counts 2lm miss data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM) unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x80000004 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x80000001 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_igr_starve_winner.mask7 uncore interconnect Count when Starve Glocab counter is at 7 event=0x44,umask=0x80 01 unc_m2m_imc_reads.all uncore interconnect Reads to iMC issued event=0x24,umask=0x304 01 unc_m2m_imc_reads.ch0.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.CH0.TO_NM1LM event=0x24,umask=0x108 01 unc_m2m_imc_reads.ch0.to_nmcache uncore interconnect UNC_M2M_IMC_READS.CH0.TO_NMCache event=0x24,umask=0x110 01 unc_m2m_imc_reads.ch0_all uncore interconnect UNC_M2M_IMC_READS.CH0_ALL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x104 01 unc_m2m_imc_reads.ch0_from_tgr uncore interconnect UNC_M2M_IMC_READS.CH0_FROM_TGR event=0x24,umask=0x140 01 unc_m2m_imc_reads.ch0_isoch uncore interconnect UNC_M2M_IMC_READS.CH0_ISOCH event=0x24,umask=0x102 01 unc_m2m_imc_reads.ch0_normal uncore interconnect UNC_M2M_IMC_READS.CH0_NORMAL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x101 01 unc_m2m_imc_reads.ch0_to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE event=0x24,umask=0x110 01 unc_m2m_imc_reads.ch0_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM event=0x24,umask=0x108 01 unc_m2m_imc_reads.ch0_to_pmm uncore interconnect UNC_M2M_IMC_READS.CH0_TO_PMM event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x120 01 unc_m2m_imc_reads.ch1.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.CH1.TO_NM1LM event=0x24,umask=0x208 01 unc_m2m_imc_reads.ch1.to_nmcache uncore interconnect UNC_M2M_IMC_READS.CH1.TO_NMCache event=0x24,umask=0x210 01 unc_m2m_imc_reads.ch1_all uncore interconnect UNC_M2M_IMC_READS.CH1_ALL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x204 01 unc_m2m_imc_reads.ch1_from_tgr uncore interconnect UNC_M2M_IMC_READS.CH1_FROM_TGR event=0x24,umask=0x240 01 unc_m2m_imc_reads.ch1_isoch uncore interconnect UNC_M2M_IMC_READS.CH1_ISOCH event=0x24,umask=0x202 01 unc_m2m_imc_reads.ch1_normal uncore interconnect UNC_M2M_IMC_READS.CH1_NORMAL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x201 01 unc_m2m_imc_reads.ch1_to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE event=0x24,umask=0x210 01 unc_m2m_imc_reads.ch1_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM event=0x24,umask=0x208 01 unc_m2m_imc_reads.ch1_to_pmm uncore interconnect UNC_M2M_IMC_READS.CH1_TO_PMM event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x220 01 unc_m2m_imc_reads.from_tgr uncore interconnect UNC_M2M_IMC_READS.FROM_TGR event=0x24,umask=0x340 01 unc_m2m_imc_reads.isoch uncore interconnect UNC_M2M_IMC_READS.ISOCH event=0x24,umask=0x302 01 unc_m2m_imc_reads.normal uncore interconnect UNC_M2M_IMC_READS.NORMAL event=0x24,umask=0x301 01 unc_m2m_imc_reads.to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.TO_DDR_AS_CACHE event=0x24,umask=0x310 01 unc_m2m_imc_reads.to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.TO_DDR_AS_MEM event=0x24,umask=0x308 01 unc_m2m_imc_reads.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.TO_NM1LM event=0x24,umask=0x308 01 unc_m2m_imc_reads.to_nmcache uncore interconnect UNC_M2M_IMC_READS.TO_NMCACHE event=0x24,umask=0x310 01 unc_m2m_imc_reads.to_pmm uncore interconnect UNC_M2M_IMC_READS.TO_PMM event=0x24,umask=0x320 01 unc_m2m_imc_writes.all uncore interconnect All Writes - All Channels event=0x25,umask=0x1810 01 unc_m2m_imc_writes.ch0.ni uncore interconnect Non-Inclusive - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_all uncore interconnect UNC_M2M_IMC_WRITES.CH0_ALL event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x810 01 unc_m2m_imc_writes.ch0_from_tgr uncore interconnect From TGR - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_full uncore interconnect UNC_M2M_IMC_WRITES.CH0_FULL event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x801 01 unc_m2m_imc_writes.ch0_full_isoch uncore interconnect UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH event=0x25,umask=0x804 01 unc_m2m_imc_writes.ch0_ni uncore interconnect Non-Inclusive - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_ni_miss uncore interconnect Non-Inclusive Miss - Ch0 event=0x25 01 unc_m2m_imc_writes.ch0_partial uncore interconnect UNC_M2M_IMC_WRITES.CH0_PARTIAL event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x802 01 unc_m2m_imc_writes.ch0_partial_isoch uncore interconnect UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH event=0x25,umask=0x808 01 unc_m2m_imc_writes.ch0_to_ddr_as_cache uncore interconnect DDR, acting as Cache - Ch0 event=0x25,umask=0x840 01 unc_m2m_imc_writes.ch0_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM event=0x25,umask=0x820 01 unc_m2m_imc_writes.ch0_to_pmm uncore interconnect PMM - Ch0 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x880 01 PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.ch1.ni uncore interconnect Non-Inclusive - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_all uncore interconnect All Writes - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1010 01 unc_m2m_imc_writes.ch1_from_tgr uncore interconnect From TGR - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_full uncore interconnect Full Line Non-ISOCH - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1001 01 unc_m2m_imc_writes.ch1_full_isoch uncore interconnect ISOCH Full Line - Ch1 event=0x25,umask=0x1004 01 unc_m2m_imc_writes.ch1_ni uncore interconnect Non-Inclusive - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_ni_miss uncore interconnect Non-Inclusive Miss - Ch1 event=0x25 01 unc_m2m_imc_writes.ch1_partial uncore interconnect Partial Non-ISOCH - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1002 01 unc_m2m_imc_writes.ch1_partial_isoch uncore interconnect ISOCH Partial - Ch1 event=0x25,umask=0x1008 01 unc_m2m_imc_writes.ch1_to_ddr_as_cache uncore interconnect DDR, acting as Cache - Ch1 event=0x25,umask=0x1040 01 unc_m2m_imc_writes.ch1_to_ddr_as_mem uncore interconnect DDR - Ch1 event=0x25,umask=0x1020 01 unc_m2m_imc_writes.ch1_to_pmm uncore interconnect PMM - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1080 01 PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.from_tgr uncore interconnect From TGR - All Channels event=0x25 01 unc_m2m_imc_writes.full uncore interconnect Full Non-ISOCH - All Channels event=0x25,umask=0x1801 01 unc_m2m_imc_writes.full_isoch uncore interconnect ISOCH Full Line - All Channels event=0x25,umask=0x1804 01 unc_m2m_imc_writes.ni uncore interconnect Non-Inclusive - All Channels event=0x25 01 unc_m2m_imc_writes.ni_miss uncore interconnect Non-Inclusive Miss - All Channels event=0x25 01 unc_m2m_imc_writes.partial uncore interconnect Partial Non-ISOCH - All Channels event=0x25,umask=0x1802 01 unc_m2m_imc_writes.partial_isoch uncore interconnect ISOCH Partial - All Channels event=0x25,umask=0x1808 01 unc_m2m_imc_writes.to_ddr_as_cache uncore interconnect DDR, acting as Cache - All Channels event=0x25,umask=0x1840 01 unc_m2m_imc_writes.to_ddr_as_mem uncore interconnect DDR - All Channels event=0x25,umask=0x1820 01 unc_m2m_imc_writes.to_pmm uncore interconnect PMM - All Channels event=0x25,umask=0x1880 01 unc_m2m_prefcam_cis_drops uncore interconnect UNC_M2M_PREFCAM_CIS_DROPS event=0x5c 01 unc_m2m_prefcam_demand_drops.ch0_upi uncore interconnect Data Prefetches Dropped event=0x58,umask=0x2 01 unc_m2m_prefcam_demand_drops.ch0_xpt uncore interconnect Data Prefetches Dropped event=0x58,umask=0x1 01 unc_m2m_prefcam_demand_drops.ch1_upi uncore interconnect Data Prefetches Dropped event=0x58,umask=0x8 01 unc_m2m_prefcam_demand_drops.ch1_xpt uncore interconnect Data Prefetches Dropped event=0x58,umask=0x4 01 unc_m2m_prefcam_demand_drops.upi_allch uncore interconnect Data Prefetches Dropped : UPI - All Channels event=0x58,umask=0xa 01 unc_m2m_prefcam_demand_drops.xpt_allch uncore interconnect Data Prefetches Dropped event=0x58,umask=0x5 01 unc_m2m_prefcam_demand_merge.upi_allch uncore interconnect : UPI - All Channels event=0x5d,umask=0xa 01 unc_m2m_prefcam_demand_merge.xpt_allch uncore interconnect : XPT - All Channels event=0x5d,umask=0x5 01 unc_m2m_prefcam_demand_no_merge.rd_merged uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x40 01 unc_m2m_prefcam_demand_no_merge.wr_merged uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x20 01 unc_m2m_prefcam_demand_no_merge.wr_squashed uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x10 01 unc_m2m_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=0x2 01 unc_m2m_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=0x1 01 unc_m2m_prefcam_inserts.ch1_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 1 event=0x56,umask=0x8 01 unc_m2m_prefcam_inserts.ch1_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 1 event=0x56,umask=0x4 01 unc_m2m_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=0xa 01 unc_m2m_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT - All Channels event=0x56,umask=0x5 01 Prefetch CAM Inserts : XPT -All Channels unc_m2m_prefcam_occupancy.allch uncore interconnect Prefetch CAM Occupancy : All Channels event=0x54,umask=0x3 01 unc_m2m_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x54,umask=0x1 01 unc_m2m_prefcam_occupancy.ch1 uncore interconnect Prefetch CAM Occupancy : Channel 1 event=0x54,umask=0x2 01 unc_m2m_prefcam_resp_miss.allch uncore interconnect All Channels event=0x5f,umask=0x3 01 unc_m2m_prefcam_resp_miss.ch0 uncore interconnect : Channel 0 event=0x5f,umask=0x1 01 unc_m2m_prefcam_resp_miss.ch1 uncore interconnect : Channel 1 event=0x5f,umask=0x2 01 unc_m2m_prefcam_rxc_deallocs.1lm_posted uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x62,umask=0x2 01 unc_m2m_prefcam_rxc_deallocs.cis uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS event=0x62,umask=0x8 01 unc_m2m_prefcam_rxc_deallocs.pmm_memmode_accept uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT event=0x62,umask=0x4 01 unc_m2m_prefcam_rxc_deallocs.squashed uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x62,umask=0x1 01 unc_m2m_prefcam_rxc_occupancy uncore interconnect AD Ingress (from CMS) Occupancy - Prefetches event=0x60 01 unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=0x2,umask=0x1 01 unc_m2m_rxc_ad_occupancy uncore interconnect AD Ingress (from CMS) Occupancy event=0x3 01 unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Clean NearMem Read Hit event=0x1f,umask=0x1 01 Counts clean full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Dirty NearMem Read Hit event=0x1f,umask=0x2 01 Counts dirty full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Tag Hit : Clean NearMem Underfill Hit event=0x1f,umask=0x4 01 Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Underfill Hit event=0x1f,umask=0x8 01 Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write unc_m2m_tag_miss uncore interconnect UNC_M2M_TAG_MISS event=0x4b,umask=0x3 01 unc_m2m_tgr_ad_credits uncore interconnect Number AD Ingress Credits event=0x2e 01 unc_m2m_tgr_bl_credits uncore interconnect Number BL Ingress Credits event=0x2f 01 unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x32,umask=0x104 01 unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts : Channel 1 event=0x32,umask=0x204 01 unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x33,umask=0x1 01 unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy : Channel 1 event=0x33,umask=0x2 01 unc_m2m_wpq_flush.ch0 uncore interconnect WPQ Flush : Channel 0 event=0x42,umask=0x1 01 unc_m2m_wpq_flush.ch1 uncore interconnect WPQ Flush : Channel 1 event=0x42,umask=0x2 01 unc_m2m_wpq_no_reg_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x37,umask=0x1 01 unc_m2m_wpq_no_reg_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x37,umask=0x2 01 unc_m2m_wpq_no_spec_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x38,umask=0x1 01 unc_m2m_wpq_no_spec_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x38,umask=0x2 01 unc_m2m_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x40,umask=0x1 01 unc_m2m_wr_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts : Channel 1 event=0x40,umask=0x2 01 unc_m2m_wr_tracker_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty : Channel 0 event=0x35,umask=0x1 01 unc_m2m_wr_tracker_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty : Channel 1 event=0x35,umask=0x2 01 unc_m2m_wr_tracker_ne.mirr uncore interconnect Write Tracker Cycles Not Empty : Mirror event=0x35,umask=0x4 01 unc_m2m_wr_tracker_ne.mirr_nontgr uncore interconnect Write Tracker Cycles Not Empty event=0x35,umask=0x8 01 unc_m2m_wr_tracker_ne.mirr_pwr uncore interconnect Write Tracker Cycles Not Empty event=0x35,umask=0x10 01 unc_m2m_wr_tracker_nonposted_inserts.ch0 uncore interconnect Write Tracker Non-Posted Inserts : Channel 0 event=0x4d,umask=0x1 01 unc_m2m_wr_tracker_nonposted_inserts.ch1 uncore interconnect Write Tracker Non-Posted Inserts : Channel 1 event=0x4d,umask=0x2 01 unc_m2m_wr_tracker_nonposted_occupancy.ch0 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 0 event=0x4c,umask=0x1 01 unc_m2m_wr_tracker_nonposted_occupancy.ch1 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 1 event=0x4c,umask=0x2 01 unc_m2m_wr_tracker_posted_inserts.ch0 uncore interconnect Write Tracker Posted Inserts : Channel 0 event=0x48,umask=0x1 01 unc_m2m_wr_tracker_posted_inserts.ch1 uncore interconnect Write Tracker Posted Inserts : Channel 1 event=0x48,umask=0x2 01 unc_m2m_wr_tracker_posted_occupancy.ch0 uncore interconnect Write Tracker Posted Occupancy : Channel 0 event=0x47,umask=0x1 01 unc_m2m_wr_tracker_posted_occupancy.ch1 uncore interconnect Write Tracker Posted Occupancy : Channel 1 event=0x47,umask=0x2 01 unc_m3upi_cha_ad_credits_empty.req uncore interconnect CBox AD Credits Empty : Requests event=0x22,umask=0x4 01 CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.snp uncore interconnect CBox AD Credits Empty : Snoops event=0x22,umask=0x8 01 CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.vna uncore interconnect CBox AD Credits Empty : VNA Messages event=0x22,umask=0x1 01 CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.wb uncore interconnect CBox AD Credits Empty : Writebacks event=0x22,umask=0x2 01 CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_clockticks uncore interconnect M3UPI Clockticks event=0x1 01 Number of M2UPI clock cycles while the event is enabled unc_m3upi_cms_clockticks uncore interconnect M3UPI CMS Clockticks event=0xc0 01 unc_m3upi_d2c_sent uncore interconnect D2C Sent event=0x2b 01 D2C Sent : Count cases BL sends direct to core unc_m3upi_d2u_sent uncore interconnect D2U Sent event=0x2a 01 D2U Sent : Cases where SMI3 sends D2U command unc_m3upi_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_m2_bl_credits_empty.iio1_ncb uncore interconnect M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) event=0x23,umask=0x1 01 M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio2_ncb uncore interconnect M2 BL Credits Empty : IIO2 event=0x23,umask=0x2 01 M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio3_ncb uncore interconnect M2 BL Credits Empty : IIO3 event=0x23,umask=0x4 01 M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio4_ncb uncore interconnect M2 BL Credits Empty : IIO4 event=0x23,umask=0x8 01 M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio5_ncb uncore interconnect M2 BL Credits Empty : IIO5 event=0x23,umask=0x10 01 M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs uncore interconnect M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together event=0x23,umask=0x40 01 M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs_sel uncore interconnect M2 BL Credits Empty : Selected M2p BL NCS credits event=0x23,umask=0x80 01 M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ubox_ncb uncore interconnect M2 BL Credits Empty : IIO5 event=0x23,umask=0x20 01 M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2 unc_m3upi_multi_slot_rcvd.ad_slot0 uncore interconnect Multi Slot Flit Received : AD - Slot 0 event=0x3e,umask=0x1 01 Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot1 uncore interconnect Multi Slot Flit Received : AD - Slot 1 event=0x3e,umask=0x2 01 Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot2 uncore interconnect Multi Slot Flit Received : AD - Slot 2 event=0x3e,umask=0x4 01 Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot0 uncore interconnect Multi Slot Flit Received : AK - Slot 0 event=0x3e,umask=0x10 01 Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot2 uncore interconnect Multi Slot Flit Received : AK - Slot 2 event=0x3e,umask=0x20 01 Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.bl_slot0 uncore interconnect Multi Slot Flit Received : BL - Slot 0 event=0x3e,umask=0x8 01 Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_rxc_arb_lost_vn0.ad_req uncore interconnect Lost Arb for VN0 : REQ on AD event=0x4b,umask=0x1 01 Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn0.ad_rsp uncore interconnect Lost Arb for VN0 : RSP on AD event=0x4b,umask=0x4 01 Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.ad_snp uncore interconnect Lost Arb for VN0 : SNP on AD event=0x4b,umask=0x2 01 Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn0.bl_ncb uncore interconnect Lost Arb for VN0 : NCB on BL event=0x4b,umask=0x20 01 Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn0.bl_ncs uncore interconnect Lost Arb for VN0 : NCS on BL event=0x4b,umask=0x40 01 Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn0.bl_rsp uncore interconnect Lost Arb for VN0 : RSP on BL event=0x4b,umask=0x8 01 Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.bl_wb uncore interconnect Lost Arb for VN0 : WB on BL event=0x4b,umask=0x10 01 Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_lost_vn1.ad_req uncore interconnect Lost Arb for VN1 : REQ on AD event=0x4c,umask=0x1 01 Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn1.ad_rsp uncore interconnect Lost Arb for VN1 : RSP on AD event=0x4c,umask=0x4 01 Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.ad_snp uncore interconnect Lost Arb for VN1 : SNP on AD event=0x4c,umask=0x2 01 Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn1.bl_ncb uncore interconnect Lost Arb for VN1 : NCB on BL event=0x4c,umask=0x20 01 Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn1.bl_ncs uncore interconnect Lost Arb for VN1 : NCS on BL event=0x4c,umask=0x40 01 Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn1.bl_rsp uncore interconnect Lost Arb for VN1 : RSP on BL event=0x4c,umask=0x8 01 Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.bl_wb uncore interconnect Lost Arb for VN1 : WB on BL event=0x4c,umask=0x10 01 Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_misc.adbl_parallel_win_vn0 uncore interconnect Arb Miscellaneous : AD, BL Parallel Win VN0 event=0x4d,umask=0x10 01 Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.adbl_parallel_win_vn1 uncore interconnect Arb Miscellaneous : AD, BL Parallel Win VN1 event=0x4d,umask=0x20 01 Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.all_parallel_win uncore interconnect Arb Miscellaneous : Max Parallel Win event=0x4d,umask=0x80 01 Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners) unc_m3upi_rxc_arb_misc.no_prog_ad_vn0 uncore interconnect Arb Miscellaneous : No Progress on Pending AD VN0 event=0x4d,umask=0x1 01 Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_ad_vn1 uncore interconnect Arb Miscellaneous : No Progress on Pending AD VN1 event=0x4d,umask=0x2 01 Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn0 uncore interconnect Arb Miscellaneous : No Progress on Pending BL VN0 event=0x4d,umask=0x4 01 Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn1 uncore interconnect Arb Miscellaneous : No Progress on Pending BL VN1 event=0x4d,umask=0x8 01 Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.vn01_parallel_win uncore interconnect Arb Miscellaneous : VN0, VN1 Parallel Win event=0x4d,umask=0x40 01 Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side) unc_m3upi_rxc_arb_nocrd_vn0.ad_req uncore interconnect No Credits to Arb for VN0 : REQ on AD event=0x47,umask=0x1 01 No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocrd_vn0.ad_rsp uncore interconnect No Credits to Arb for VN0 : RSP on AD event=0x47,umask=0x4 01 No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn0.ad_snp uncore interconnect No Credits to Arb for VN0 : SNP on AD event=0x47,umask=0x2 01 No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocrd_vn0.bl_ncb uncore interconnect No Credits to Arb for VN0 : NCB on BL event=0x47,umask=0x20 01 No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocrd_vn0.bl_ncs uncore interconnect No Credits to Arb for VN0 : NCS on BL event=0x47,umask=0x40 01 No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocrd_vn0.bl_rsp uncore interconnect No Credits to Arb for VN0 : RSP on BL event=0x47,umask=0x8 01 No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn0.bl_wb uncore interconnect No Credits to Arb for VN0 : WB on BL event=0x47,umask=0x10 01 No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocrd_vn1.ad_req uncore interconnect No Credits to Arb for VN1 : REQ on AD event=0x48,umask=0x1 01 No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocrd_vn1.ad_rsp uncore interconnect No Credits to Arb for VN1 : RSP on AD event=0x48,umask=0x4 01 No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn1.ad_snp uncore interconnect No Credits to Arb for VN1 : SNP on AD event=0x48,umask=0x2 01 No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocrd_vn1.bl_ncb uncore interconnect No Credits to Arb for VN1 : NCB on BL event=0x48,umask=0x20 01 No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_nocrd_vn1.bl_ncs uncore interconnect No Credits to Arb for VN1 : NCS on BL event=0x48,umask=0x40 01 No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocrd_vn1.bl_rsp uncore interconnect No Credits to Arb for VN1 : RSP on BL event=0x48,umask=0x8 01 No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn1.bl_wb uncore interconnect No Credits to Arb for VN1 : WB on BL event=0x48,umask=0x10 01 No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noreq_vn0.ad_req uncore interconnect Can't Arb for VN0 : REQ on AD event=0x49,umask=0x1 01 Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noreq_vn0.ad_rsp uncore interconnect Can't Arb for VN0 : RSP on AD event=0x49,umask=0x4 01 Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn0.ad_snp uncore interconnect Can't Arb for VN0 : SNP on AD event=0x49,umask=0x2 01 Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noreq_vn0.bl_ncb uncore interconnect Can't Arb for VN0 : NCB on BL event=0x49,umask=0x20 01 Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noreq_vn0.bl_ncs uncore interconnect Can't Arb for VN0 : NCS on BL event=0x49,umask=0x40 01 Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noreq_vn0.bl_rsp uncore interconnect Can't Arb for VN0 : RSP on BL event=0x49,umask=0x8 01 Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn0.bl_wb uncore interconnect Can't Arb for VN0 : WB on BL event=0x49,umask=0x10 01 Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noreq_vn1.ad_req uncore interconnect Can't Arb for VN1 : REQ on AD event=0x4a,umask=0x1 01 Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noreq_vn1.ad_rsp uncore interconnect Can't Arb for VN1 : RSP on AD event=0x4a,umask=0x4 01 Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn1.ad_snp uncore interconnect Can't Arb for VN1 : SNP on AD event=0x4a,umask=0x2 01 Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_arb_noreq_vn1.bl_ncb uncore interconnect Can't Arb for VN1 : NCB on BL event=0x4a,umask=0x20 01 Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_arb_noreq_vn1.bl_ncs uncore interconnect Can't Arb for VN1 : NCS on BL event=0x4a,umask=0x40 01 Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noreq_vn1.bl_rsp uncore interconnect Can't Arb for VN1 : RSP on BL event=0x4a,umask=0x8 01 Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn1.bl_wb uncore interconnect Can't Arb for VN1 : WB on BL event=0x4a,umask=0x10 01 Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_bypassed.ad_s0_bl_arb uncore interconnect Ingress Queue Bypasses : AD to Slot 0 on BL Arb event=0x40,umask=0x2 01 Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration unc_m3upi_rxc_bypassed.ad_s0_idle uncore interconnect Ingress Queue Bypasses : AD to Slot 0 on Idle event=0x40,umask=0x1 01 Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle unc_m3upi_rxc_bypassed.ad_s1_bl_slot uncore interconnect Ingress Queue Bypasses : AD + BL to Slot 1 event=0x40,umask=0x4 01 Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit unc_m3upi_rxc_bypassed.ad_s2_bl_slot uncore interconnect Ingress Queue Bypasses : AD + BL to Slot 2 event=0x40,umask=0x8 01 Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit unc_m3upi_rxc_crd_misc.any_bgf_fifo uncore interconnect Miscellaneous Credit Events : Any In BGF FIFO event=0x5f,umask=0x1 01 Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only) unc_m3upi_rxc_crd_misc.any_bgf_path uncore interconnect Miscellaneous Credit Events : Any in BGF Path event=0x5f,umask=0x2 01 Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo) unc_m3upi_rxc_crd_misc.lt1_for_d2k uncore interconnect Miscellaneous Credit Events event=0x5f,umask=0x10 01 Miscellaneous Credit Events : d2k credit count is less than 1 unc_m3upi_rxc_crd_misc.lt2_for_d2k uncore interconnect Miscellaneous Credit Events event=0x5f,umask=0x20 01 Miscellaneous Credit Events : d2k credit count is less than 2 unc_m3upi_rxc_crd_misc.vn0_no_d2k_for_arb uncore interconnect Miscellaneous Credit Events : No D2K For Arb event=0x5f,umask=0x4 01 Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit unc_m3upi_rxc_crd_misc.vn1_no_d2k_for_arb uncore interconnect Miscellaneous Credit Events event=0x5f,umask=0x8 01 Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits unc_m3upi_rxc_crd_occ.consumed uncore interconnect Credit Occupancy : Credits Consumed event=0x60,umask=0x80 01 Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle unc_m3upi_rxc_crd_occ.d2k_crd uncore interconnect Credit Occupancy : D2K Credits event=0x60,umask=0x10 01 Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.flits_in_fifo uncore interconnect Credit Occupancy : Packets in BGF FIFO event=0x60,umask=0x2 01 Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo unc_m3upi_rxc_crd_occ.flits_in_path uncore interconnect Credit Occupancy : Packets in BGF Path event=0x60,umask=0x4 01 Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo) unc_m3upi_rxc_crd_occ.p1p_fifo uncore interconnect Credit Occupancy event=0x60,umask=0x40 01 Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only unc_m3upi_rxc_crd_occ.p1p_total uncore interconnect Credit Occupancy event=0x60,umask=0x20 01 Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo unc_m3upi_rxc_crd_occ.txq_crd uncore interconnect Credit Occupancy : Transmit Credits event=0x60,umask=0x8 01 Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.vna_in_use uncore interconnect Credit Occupancy : VNA In Use event=0x60,umask=0x1 01 Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles unc_m3upi_rxc_cycles_ne_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD event=0x43,umask=0x1 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD event=0x43,umask=0x4 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD event=0x43,umask=0x2 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL event=0x43,umask=0x20 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL event=0x43,umask=0x40 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL event=0x43,umask=0x8 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL event=0x43,umask=0x10 01 VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_data_flits_not_sent.all uncore interconnect Data Flit Not Sent : All event=0x55,umask=0x1 01 Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection unc_m3upi_rxc_data_flits_not_sent.no_bgf uncore interconnect Data Flit Not Sent : No BGF Credits event=0x55,umask=0x8 01 Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent unc_m3upi_rxc_data_flits_not_sent.no_txq uncore interconnect Data Flit Not Sent : No TxQ Credits event=0x55,umask=0x10 01 Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent unc_m3upi_rxc_data_flits_not_sent.tsv_hi uncore interconnect Data Flit Not Sent : TSV High event=0x55,umask=0x2 01 Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high unc_m3upi_rxc_data_flits_not_sent.valid_for_flit uncore interconnect Data Flit Not Sent : Cycle valid for Flit event=0x55,umask=0x4 01 Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission unc_m3upi_rxc_flits_gen_bl.p0_wait uncore interconnect Generating BL Data Flit Sequence : Wait on Pump 0 event=0x57,umask=0x1 01 Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0 unc_m3upi_rxc_flits_gen_bl.p1p_at_limit uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x10 01 Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit) unc_m3upi_rxc_flits_gen_bl.p1p_busy uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x8 01 Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message unc_m3upi_rxc_flits_gen_bl.p1p_fifo_full uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x40 01 Generating BL Data Flit Sequence : pump-1-pending completion fifo is full unc_m3upi_rxc_flits_gen_bl.p1p_hold_p0 uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x20 01 Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage unc_m3upi_rxc_flits_gen_bl.p1p_to_limbo uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x4 01 Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic unc_m3upi_rxc_flits_gen_bl.p1_wait uncore interconnect Generating BL Data Flit Sequence : Wait on Pump 1 event=0x57,umask=0x2 01 Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1 unc_m3upi_rxc_flits_misc.s2req_in_holdoff uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF event=0x58,umask=0x4 01 : slot 2 request naturally serviced during hold-off period unc_m3upi_rxc_flits_misc.s2req_in_service uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE event=0x58,umask=0x8 01 : slot 2 request forcibly serviced during service window unc_m3upi_rxc_flits_misc.s2req_received uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED event=0x58,umask=0x1 01 : slot 2 request received from link layer while idle (with no slot 2 request active immediately prior) unc_m3upi_rxc_flits_misc.s2req_withdrawn uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN event=0x58,umask=0x2 01 : slot 2 request withdrawn during hold-off period or service window unc_m3upi_rxc_flits_slot_bl.all uncore interconnect Slotting BL Message Into Header Flit : All event=0x56,umask=0x1 01 unc_m3upi_rxc_flits_slot_bl.need_data uncore interconnect Slotting BL Message Into Header Flit : Needs Data Flit event=0x56,umask=0x2 01 Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence unc_m3upi_rxc_flits_slot_bl.p0_wait uncore interconnect Slotting BL Message Into Header Flit : Wait on Pump 0 event=0x56,umask=0x4 01 Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0 unc_m3upi_rxc_flits_slot_bl.p1_not_req uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 event=0x56,umask=0x10 01 Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit unc_m3upi_rxc_flits_slot_bl.p1_not_req_but_bubble uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble event=0x56,umask=0x20 01 Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed unc_m3upi_rxc_flits_slot_bl.p1_not_req_not_avail uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail event=0x56,umask=0x40 01 Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available unc_m3upi_rxc_flits_slot_bl.p1_wait uncore interconnect Slotting BL Message Into Header Flit : Wait on Pump 1 event=0x56,umask=0x8 01 Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1 unc_m3upi_rxc_flit_gen_hdr1.accum uncore interconnect Flit Gen - Header 1 : Accumulate event=0x51,umask=0x1 01 Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles unc_m3upi_rxc_flit_gen_hdr1.accum_read uncore interconnect Flit Gen - Header 1 : Accumulate Ready event=0x51,umask=0x2 01 Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit unc_m3upi_rxc_flit_gen_hdr1.accum_wasted uncore interconnect Flit Gen - Header 1 : Accumulate Wasted event=0x51,umask=0x4 01 Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_blocked uncore interconnect Flit Gen - Header 1 : Run-Ahead - Blocked event=0x51,umask=0x8 01 Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked unc_m3upi_rxc_flit_gen_hdr1.ahead_msg1_after uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x80 01 Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_msg1_during uncore interconnect Flit Gen - Header 1 : Run-Ahead - Message event=0x51,umask=0x10 01 Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead unc_m3upi_rxc_flit_gen_hdr1.ahead_msg2_after uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x20 01 Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success unc_m3upi_rxc_flit_gen_hdr1.ahead_msg2_sent uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x40 01 Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success unc_m3upi_rxc_flit_gen_hdr2.par uncore interconnect Flit Gen - Header 2 : Parallel Ok event=0x52,umask=0x4 01 Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.par_flit uncore interconnect Flit Gen - Header 2 : Parallel Flit Finished event=0x52,umask=0x10 01 Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.par_msg uncore interconnect Flit Gen - Header 2 : Parallel Message event=0x52,umask=0x8 01 Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.rmstall uncore interconnect Flit Gen - Header 2 : Rate-matching Stall event=0x52,umask=0x1 01 Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected unc_m3upi_rxc_flit_gen_hdr2.rmstall_nomsg uncore interconnect Flit Gen - Header 2 : Rate-matching Stall - No Message event=0x52,umask=0x2 01 Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle unc_m3upi_rxc_hdr_flits_sent.1_msg uncore interconnect Sent Header Flit : One Message event=0x54,umask=0x1 01 Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit unc_m3upi_rxc_hdr_flits_sent.1_msg_vnx uncore interconnect Sent Header Flit : One Message in non-VNA event=0x54,umask=0x8 01 Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit unc_m3upi_rxc_hdr_flits_sent.2_msgs uncore interconnect Sent Header Flit : Two Messages event=0x54,umask=0x2 01 Sent Header Flit : Two Messages : Two messages in flit; VNA flit unc_m3upi_rxc_hdr_flits_sent.3_msgs uncore interconnect Sent Header Flit : Three Messages event=0x54,umask=0x4 01 Sent Header Flit : Three Messages : Three messages in flit; VNA flit unc_m3upi_rxc_hdr_flits_sent.slots_1 uncore interconnect Sent Header Flit : One Slot Taken event=0x54,umask=0x10 01 unc_m3upi_rxc_hdr_flits_sent.slots_2 uncore interconnect Sent Header Flit : Two Slots Taken event=0x54,umask=0x20 01 unc_m3upi_rxc_hdr_flits_sent.slots_3 uncore interconnect Sent Header Flit : All Slots Taken event=0x54,umask=0x40 01 unc_m3upi_rxc_hdr_flit_not_sent.all uncore interconnect Header Not Sent : All event=0x53,umask=0x1 01 Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection unc_m3upi_rxc_hdr_flit_not_sent.no_bgf_crd uncore interconnect Header Not Sent : No BGF Credits event=0x53,umask=0x8 01 Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available unc_m3upi_rxc_hdr_flit_not_sent.no_bgf_no_msg uncore interconnect Header Not Sent : No BGF Credits + No Extra Message Slotted event=0x53,umask=0x20 01 Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit unc_m3upi_rxc_hdr_flit_not_sent.no_txq_crd uncore interconnect Header Not Sent : No TxQ Credits event=0x53,umask=0x10 01 Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available unc_m3upi_rxc_hdr_flit_not_sent.no_txq_no_msg uncore interconnect Header Not Sent : No TxQ Credits + No Extra Message Slotted event=0x53,umask=0x40 01 Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit unc_m3upi_rxc_hdr_flit_not_sent.tsv_hi uncore interconnect Header Not Sent : TSV High event=0x53,umask=0x2 01 Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high unc_m3upi_rxc_hdr_flit_not_sent.valid_for_flit uncore interconnect Header Not Sent : Cycle valid for Flit event=0x53,umask=0x4 01 Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission unc_m3upi_rxc_held.cant_slot_ad uncore interconnect Message Held : Can't Slot AD event=0x50,umask=0x10 01 Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.cant_slot_bl uncore interconnect Message Held : Can't Slot BL event=0x50,umask=0x20 01 Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_attempt uncore interconnect Message Held : Parallel Attempt event=0x50,umask=0x4 01 Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel unc_m3upi_rxc_held.parallel_success uncore interconnect Message Held : Parallel Success event=0x50,umask=0x8 01 Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel unc_m3upi_rxc_held.vn0 uncore interconnect Message Held : VN0 event=0x50,umask=0x1 01 Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit unc_m3upi_rxc_held.vn1 uncore interconnect Message Held : VN1 event=0x50,umask=0x2 01 Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit unc_m3upi_rxc_packing_miss_vn0.ad_req uncore interconnect VN0 message can't slot into flit : REQ on AD event=0x4e,umask=0x1 01 VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn0.ad_rsp uncore interconnect VN0 message can't slot into flit : RSP on AD event=0x4e,umask=0x4 01 VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.ad_snp uncore interconnect VN0 message can't slot into flit : SNP on AD event=0x4e,umask=0x2 01 VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn0.bl_ncb uncore interconnect VN0 message can't slot into flit : NCB on BL event=0x4e,umask=0x20 01 VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn0.bl_ncs uncore interconnect VN0 message can't slot into flit : NCS on BL event=0x4e,umask=0x40 01 VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn0.bl_rsp uncore interconnect VN0 message can't slot into flit : RSP on BL event=0x4e,umask=0x8 01 VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.bl_wb uncore interconnect VN0 message can't slot into flit : WB on BL event=0x4e,umask=0x10 01 VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn1.ad_req uncore interconnect VN1 message can't slot into flit : REQ on AD event=0x4f,umask=0x1 01 VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn1.ad_rsp uncore interconnect VN1 message can't slot into flit : RSP on AD event=0x4f,umask=0x4 01 VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.ad_snp uncore interconnect VN1 message can't slot into flit : SNP on AD event=0x4f,umask=0x2 01 VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn1.bl_ncb uncore interconnect VN1 message can't slot into flit : NCB on BL event=0x4f,umask=0x20 01 VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn1.bl_ncs uncore interconnect VN1 message can't slot into flit : NCS on BL event=0x4f,umask=0x40 01 VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn1.bl_rsp uncore interconnect VN1 message can't slot into flit : RSP on BL event=0x4f,umask=0x8 01 VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.bl_wb uncore interconnect VN1 message can't slot into flit : WB on BL event=0x4f,umask=0x10 01 VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_vna_crd.any_in_use uncore interconnect Remote VNA Credits : Any In Use event=0x5a,umask=0x20 01 Remote VNA Credits : Any In Use : At least one remote vna credit is in use unc_m3upi_rxc_vna_crd.corrected uncore interconnect Remote VNA Credits : Corrected event=0x5a,umask=0x1 01 Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle unc_m3upi_rxc_vna_crd.lt1 uncore interconnect Remote VNA Credits : Level < 1 event=0x5a,umask=0x2 01 Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available) unc_m3upi_rxc_vna_crd.lt10 uncore interconnect Remote VNA Credits : Level < 10 event=0x5a,umask=0x10 01 Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible unc_m3upi_rxc_vna_crd.lt4 uncore interconnect Remote VNA Credits : Level < 4 event=0x5a,umask=0x4 01 Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna unc_m3upi_rxc_vna_crd.lt5 uncore interconnect Remote VNA Credits : Level < 5 event=0x5a,umask=0x8 01 Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible unc_m3upi_rxc_vna_crd_misc.req_adbl_alloc_l5 uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5 event=0x59,umask=0x2 01 : remote vna credit count was less than 5 and allocation to ad or bl messages was required unc_m3upi_rxc_vna_crd_misc.req_vn01_alloc_lt10 uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10 event=0x59,umask=0x1 01 : remote vna credit count was less than 10 and allocation to vn0 or vn1 was required unc_m3upi_rxc_vna_crd_misc.vn0_just_ad uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD event=0x59,umask=0x10 01 : on vn0, remote vna credits were allocated only to ad messages, not to bl unc_m3upi_rxc_vna_crd_misc.vn0_just_bl uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL event=0x59,umask=0x20 01 : on vn0, remote vna credits were allocated only to bl messages, not to ad unc_m3upi_rxc_vna_crd_misc.vn0_only uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY event=0x59,umask=0x4 01 : remote vna credits were allocated only to vn0, not to vn1 unc_m3upi_rxc_vna_crd_misc.vn1_just_ad uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD event=0x59,umask=0x40 01 : on vn1, remote vna credits were allocated only to ad messages, not to bl unc_m3upi_rxc_vna_crd_misc.vn1_just_bl uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL event=0x59,umask=0x80 01 : on vn1, remote vna credits were allocated only to bl messages, not to ad unc_m3upi_rxc_vna_crd_misc.vn1_only uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY event=0x59,umask=0x8 01 : remote vna credits were allocated only to vn1, not to vn0 unc_m3upi_txc_ad_arb_fail.vn0_req uncore interconnect Failed ARB for AD : VN0 REQ Messages event=0x30,umask=0x1 01 Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_rsp uncore interconnect Failed ARB for AD : VN0 RSP Messages event=0x30,umask=0x4 01 Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_snp uncore interconnect Failed ARB for AD : VN0 SNP Messages event=0x30,umask=0x2 01 Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_wb uncore interconnect Failed ARB for AD : VN0 WB Messages event=0x30,umask=0x8 01 Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_req uncore interconnect Failed ARB for AD : VN1 REQ Messages event=0x30,umask=0x10 01 Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_rsp uncore interconnect Failed ARB for AD : VN1 RSP Messages event=0x30,umask=0x40 01 Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_snp uncore interconnect Failed ARB for AD : VN1 SNP Messages event=0x30,umask=0x20 01 Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_wb uncore interconnect Failed ARB for AD : VN1 WB Messages event=0x30,umask=0x80 01 Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_flq_bypass uncore interconnect AD FlowQ Bypass event=0x2c,ch_mask=0x00000000,fc_mask=0x00000000 01 Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot0 uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x1 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot1 uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x2 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot2 uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x4 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.bl_early_rsp uncore interconnect AD FlowQ Bypass event=0x2c,umask=0x8 01 AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_cycles_ne.vn0_req uncore interconnect AD Flow Q Not Empty : VN0 REQ Messages event=0x27,umask=0x1 01 AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_rsp uncore interconnect AD Flow Q Not Empty : VN0 RSP Messages event=0x27,umask=0x4 01 AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_snp uncore interconnect AD Flow Q Not Empty : VN0 SNP Messages event=0x27,umask=0x2 01 AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_wb uncore interconnect AD Flow Q Not Empty : VN0 WB Messages event=0x27,umask=0x8 01 AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_req uncore interconnect AD Flow Q Not Empty : VN1 REQ Messages event=0x27,umask=0x10 01 AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_rsp uncore interconnect AD Flow Q Not Empty : VN1 RSP Messages event=0x27,umask=0x40 01 AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_snp uncore interconnect AD Flow Q Not Empty : VN1 SNP Messages event=0x27,umask=0x20 01 AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_wb uncore interconnect AD Flow Q Not Empty : VN1 WB Messages event=0x27,umask=0x80 01 AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_inserts.vn0_req uncore interconnect AD Flow Q Inserts : VN0 REQ Messages event=0x2d,umask=0x1 01 AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_rsp uncore interconnect AD Flow Q Inserts : VN0 RSP Messages event=0x2d,umask=0x4 01 AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_snp uncore interconnect AD Flow Q Inserts : VN0 SNP Messages event=0x2d,umask=0x2 01 AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_wb uncore interconnect AD Flow Q Inserts : VN0 WB Messages event=0x2d,umask=0x8 01 AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_req uncore interconnect AD Flow Q Inserts : VN1 REQ Messages event=0x2d,umask=0x10 01 AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_rsp uncore interconnect AD Flow Q Inserts : VN1 RSP Messages event=0x2d,umask=0x40 01 AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_snp uncore interconnect AD Flow Q Inserts : VN1 SNP Messages event=0x2d,umask=0x20 01 AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_occupancy.vn0_req uncore interconnect AD Flow Q Occupancy : VN0 REQ Messages event=0x1c,umask=0x1 01 unc_m3upi_txc_ad_flq_occupancy.vn0_rsp uncore interconnect AD Flow Q Occupancy : VN0 RSP Messages event=0x1c,umask=0x4 01 unc_m3upi_txc_ad_flq_occupancy.vn0_snp uncore interconnect AD Flow Q Occupancy : VN0 SNP Messages event=0x1c,umask=0x2 01 unc_m3upi_txc_ad_flq_occupancy.vn0_wb uncore interconnect AD Flow Q Occupancy : VN0 WB Messages event=0x1c,umask=0x8 01 unc_m3upi_txc_ad_flq_occupancy.vn1_req uncore interconnect AD Flow Q Occupancy : VN1 REQ Messages event=0x1c,umask=0x10 01 unc_m3upi_txc_ad_flq_occupancy.vn1_rsp uncore interconnect AD Flow Q Occupancy : VN1 RSP Messages event=0x1c,umask=0x40 01 unc_m3upi_txc_ad_flq_occupancy.vn1_snp uncore interconnect AD Flow Q Occupancy : VN1 SNP Messages event=0x1c,umask=0x20 01 unc_m3upi_txc_bl_arb_fail.vn0_ncb uncore interconnect Failed ARB for BL : VN0 NCB Messages event=0x35,umask=0x4 01 Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_ncs uncore interconnect Failed ARB for BL : VN0 NCS Messages event=0x35,umask=0x8 01 Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_rsp uncore interconnect Failed ARB for BL : VN0 RSP Messages event=0x35,umask=0x1 01 Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_wb uncore interconnect Failed ARB for BL : VN0 WB Messages event=0x35,umask=0x2 01 Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncb uncore interconnect Failed ARB for BL : VN1 NCS Messages event=0x35,umask=0x40 01 Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncs uncore interconnect Failed ARB for BL : VN1 NCB Messages event=0x35,umask=0x80 01 Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_rsp uncore interconnect Failed ARB for BL : VN1 RSP Messages event=0x35,umask=0x10 01 Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_wb uncore interconnect Failed ARB for BL : VN1 WB Messages event=0x35,umask=0x20 01 Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_flq_cycles_ne.vn0_req uncore interconnect BL Flow Q Not Empty : VN0 REQ Messages event=0x28,umask=0x1 01 BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_rsp uncore interconnect BL Flow Q Not Empty : VN0 RSP Messages event=0x28,umask=0x4 01 BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_snp uncore interconnect BL Flow Q Not Empty : VN0 SNP Messages event=0x28,umask=0x2 01 BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_wb uncore interconnect BL Flow Q Not Empty : VN0 WB Messages event=0x28,umask=0x8 01 BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_req uncore interconnect BL Flow Q Not Empty : VN1 REQ Messages event=0x28,umask=0x10 01 BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_rsp uncore interconnect BL Flow Q Not Empty : VN1 RSP Messages event=0x28,umask=0x40 01 BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_snp uncore interconnect BL Flow Q Not Empty : VN1 SNP Messages event=0x28,umask=0x20 01 BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_wb uncore interconnect BL Flow Q Not Empty : VN1 WB Messages event=0x28,umask=0x80 01 BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_inserts.vn0_ncb uncore interconnect BL Flow Q Inserts : VN0 RSP Messages event=0x2e,umask=0x1 01 BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_ncs uncore interconnect BL Flow Q Inserts : VN0 WB Messages event=0x2e,umask=0x2 01 BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_rsp uncore interconnect BL Flow Q Inserts : VN0 NCS Messages event=0x2e,umask=0x8 01 BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_wb uncore interconnect BL Flow Q Inserts : VN0 NCB Messages event=0x2e,umask=0x4 01 BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncb uncore interconnect BL Flow Q Inserts : VN1 RSP Messages event=0x2e,umask=0x10 01 BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncs uncore interconnect BL Flow Q Inserts : VN1 WB Messages event=0x2e,umask=0x20 01 BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_rsp uncore interconnect BL Flow Q Inserts : VN1_NCB Messages event=0x2e,umask=0x80 01 BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_wb uncore interconnect BL Flow Q Inserts : VN1_NCS Messages event=0x2e,umask=0x40 01 BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_occupancy.vn0_ncb uncore interconnect BL Flow Q Occupancy : VN0 NCB Messages event=0x1d,umask=0x4 01 unc_m3upi_txc_bl_flq_occupancy.vn0_ncs uncore interconnect BL Flow Q Occupancy : VN0 NCS Messages event=0x1d,umask=0x8 01 unc_m3upi_txc_bl_flq_occupancy.vn0_rsp uncore interconnect BL Flow Q Occupancy : VN0 RSP Messages event=0x1d,umask=0x1 01 unc_m3upi_txc_bl_flq_occupancy.vn0_wb uncore interconnect BL Flow Q Occupancy : VN0 WB Messages event=0x1d,umask=0x2 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncb uncore interconnect BL Flow Q Occupancy : VN1_NCS Messages event=0x1d,umask=0x40 01 unc_m3upi_txc_bl_flq_occupancy.vn1_ncs uncore interconnect BL Flow Q Occupancy : VN1_NCB Messages event=0x1d,umask=0x80 01 unc_m3upi_txc_bl_flq_occupancy.vn1_rsp uncore interconnect BL Flow Q Occupancy : VN1 RSP Messages event=0x1d,umask=0x10 01 unc_m3upi_txc_bl_flq_occupancy.vn1_wb uncore interconnect BL Flow Q Occupancy : VN1 WB Messages event=0x1d,umask=0x20 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn0_local uncore interconnect BL Flow Q Occupancy : VN0 RSP Messages event=0x1f,umask=0x1 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn0_through uncore interconnect BL Flow Q Occupancy : VN0 WB Messages event=0x1f,umask=0x2 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn0_wrpull uncore interconnect BL Flow Q Occupancy : VN0 NCB Messages event=0x1f,umask=0x4 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn1_local uncore interconnect BL Flow Q Occupancy : VN1 RSP Messages event=0x1f,umask=0x10 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn1_through uncore interconnect BL Flow Q Occupancy : VN1 WB Messages event=0x1f,umask=0x20 01 unc_m3upi_txc_bl_wb_flq_occupancy.vn1_wrpull uncore interconnect BL Flow Q Occupancy : VN1_NCS Messages event=0x1f,umask=0x40 01 unc_m3upi_upi_peer_ad_credits_empty.vn0_req uncore interconnect UPI0 AD Credits Empty : VN0 REQ Messages event=0x20,umask=0x2 01 UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_rsp uncore interconnect UPI0 AD Credits Empty : VN0 RSP Messages event=0x20,umask=0x8 01 UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_snp uncore interconnect UPI0 AD Credits Empty : VN0 SNP Messages event=0x20,umask=0x4 01 UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_req uncore interconnect UPI0 AD Credits Empty : VN1 REQ Messages event=0x20,umask=0x10 01 UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_rsp uncore interconnect UPI0 AD Credits Empty : VN1 RSP Messages event=0x20,umask=0x40 01 UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_snp uncore interconnect UPI0 AD Credits Empty : VN1 SNP Messages event=0x20,umask=0x20 01 UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vna uncore interconnect UPI0 AD Credits Empty : VNA event=0x20,umask=0x1 01 UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_bl_credits_empty.vn0_ncs_ncb uncore interconnect UPI0 BL Credits Empty : VN0 RSP Messages event=0x21,umask=0x4 01 UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_rsp uncore interconnect UPI0 BL Credits Empty : VN0 REQ Messages event=0x21,umask=0x2 01 UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_wb uncore interconnect UPI0 BL Credits Empty : VN0 SNP Messages event=0x21,umask=0x8 01 UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_ncs_ncb uncore interconnect UPI0 BL Credits Empty : VN1 RSP Messages event=0x21,umask=0x20 01 UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_rsp uncore interconnect UPI0 BL Credits Empty : VN1 REQ Messages event=0x21,umask=0x10 01 UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_wb uncore interconnect UPI0 BL Credits Empty : VN1 SNP Messages event=0x21,umask=0x40 01 UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vna uncore interconnect UPI0 BL Credits Empty : VNA event=0x21,umask=0x1 01 UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_prefetch_spawn uncore interconnect FlowQ Generated Prefetch event=0x29 01 FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target unc_m3upi_vn0_credits_used.ncb uncore interconnect VN0 Credit Used : WB on BL event=0x5b,umask=0x10 01 VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_credits_used.ncs uncore interconnect VN0 Credit Used : NCB on BL event=0x5b,umask=0x20 01 VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_credits_used.req uncore interconnect VN0 Credit Used : REQ on AD event=0x5b,umask=0x1 01 VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_credits_used.rsp uncore interconnect VN0 Credit Used : RSP on AD event=0x5b,umask=0x4 01 VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_credits_used.snp uncore interconnect VN0 Credit Used : SNP on AD event=0x5b,umask=0x2 01 VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_credits_used.wb uncore interconnect VN0 Credit Used : RSP on BL event=0x5b,umask=0x8 01 VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.ncb uncore interconnect VN0 No Credits : WB on BL event=0x5d,umask=0x10 01 VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_no_credits.ncs uncore interconnect VN0 No Credits : NCB on BL event=0x5d,umask=0x20 01 VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn0_no_credits.req uncore interconnect VN0 No Credits : REQ on AD event=0x5d,umask=0x1 01 VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_no_credits.rsp uncore interconnect VN0 No Credits : RSP on AD event=0x5d,umask=0x4 01 VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.snp uncore interconnect VN0 No Credits : SNP on AD event=0x5d,umask=0x2 01 VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn0_no_credits.wb uncore interconnect VN0 No Credits : RSP on BL event=0x5d,umask=0x8 01 VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.ncb uncore interconnect VN1 Credit Used : WB on BL event=0x5c,umask=0x10 01 VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_credits_used.ncs uncore interconnect VN1 Credit Used : NCB on BL event=0x5c,umask=0x20 01 VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_credits_used.req uncore interconnect VN1 Credit Used : REQ on AD event=0x5c,umask=0x1 01 VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_credits_used.rsp uncore interconnect VN1 Credit Used : RSP on AD event=0x5c,umask=0x4 01 VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.snp uncore interconnect VN1 Credit Used : SNP on AD event=0x5c,umask=0x2 01 VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_credits_used.wb uncore interconnect VN1 Credit Used : RSP on BL event=0x5c,umask=0x8 01 VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.ncb uncore interconnect VN1 No Credits : WB on BL event=0x5e,umask=0x10 01 VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_no_credits.ncs uncore interconnect VN1 No Credits : NCB on BL event=0x5e,umask=0x20 01 VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_vn1_no_credits.req uncore interconnect VN1 No Credits : REQ on AD event=0x5e,umask=0x1 01 VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_no_credits.rsp uncore interconnect VN1 No Credits : RSP on AD event=0x5e,umask=0x4 01 VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.snp uncore interconnect VN1 No Credits : SNP on AD event=0x5e,umask=0x2 01 VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_vn1_no_credits.wb uncore interconnect VN1 No Credits : RSP on BL event=0x5e,umask=0x8 01 VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_wb_occ_compare.bothnonzero_rt_eq_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0 event=0x7e,umask=0x82 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_eq_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1 event=0x7e,umask=0xa0 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_gt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0 event=0x7e,umask=0x81 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_gt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1 event=0x7e,umask=0x90 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_lt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0 event=0x7e,umask=0x84 01 unc_m3upi_wb_occ_compare.bothnonzero_rt_lt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1 event=0x7e,umask=0xc0 01 unc_m3upi_wb_occ_compare.rt_eq_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0 event=0x7e,umask=0x2 01 unc_m3upi_wb_occ_compare.rt_eq_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1 event=0x7e,umask=0x20 01 unc_m3upi_wb_occ_compare.rt_gt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0 event=0x7e,umask=0x1 01 unc_m3upi_wb_occ_compare.rt_gt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1 event=0x7e,umask=0x10 01 unc_m3upi_wb_occ_compare.rt_lt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0 event=0x7e,umask=0x4 01 unc_m3upi_wb_occ_compare.rt_lt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1 event=0x7e,umask=0x40 01 unc_m3upi_wb_pending.localdest_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.LOCALDEST_VN0 event=0x7d,umask=0x1 01 unc_m3upi_wb_pending.localdest_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.LOCALDEST_VN1 event=0x7d,umask=0x10 01 unc_m3upi_wb_pending.local_and_rt_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0 event=0x7d,umask=0x4 01 unc_m3upi_wb_pending.local_and_rt_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1 event=0x7d,umask=0x40 01 unc_m3upi_wb_pending.routethru_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0 event=0x7d,umask=0x2 01 unc_m3upi_wb_pending.routethru_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1 event=0x7d,umask=0x20 01 unc_m3upi_wb_pending.waiting4pull_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0 event=0x7d,umask=0x8 01 unc_m3upi_wb_pending.waiting4pull_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1 event=0x7d,umask=0x80 01 unc_m3upi_xpt_pftch.arb uncore interconnect UNC_M3UPI_XPT_PFTCH.ARB event=0x61,umask=0x4 01 : xpt prefetch message is making arbitration request unc_m3upi_xpt_pftch.arrived uncore interconnect UNC_M3UPI_XPT_PFTCH.ARRIVED event=0x61,umask=0x1 01 : xpt prefetch message arrived in ingress pipeline unc_m3upi_xpt_pftch.bypass uncore interconnect UNC_M3UPI_XPT_PFTCH.BYPASS event=0x61,umask=0x2 01 : xpt prefetch message took bypass path unc_m3upi_xpt_pftch.flitted uncore interconnect UNC_M3UPI_XPT_PFTCH.FLITTED event=0x61,umask=0x10 01 : xpt prefetch message was slotted into flit (non bypass) unc_m3upi_xpt_pftch.lost_arb uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_ARB event=0x61,umask=0x8 01 : xpt prefetch message lost arbitration unc_m3upi_xpt_pftch.lost_old uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_OLD event=0x61,umask=0x20 01 : xpt prefetch message was dropped because it became too old unc_m3upi_xpt_pftch.lost_qfull uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_QFULL event=0x61,umask=0x40 01 : xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full uncore_mdf unc_mdf_crs_txr_inserts.ad_bnc uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bounceable) event=0x47,umask=0x1 01 AD Bounceable : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.ad_crd uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD credited) event=0x47,umask=0x2 01 AD credited : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.ak uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AK) event=0x47,umask=0x10 01 AK : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.akc uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AKC) event=0x47,umask=0x40 01 AKC : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.bl_bnc uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bounceable) event=0x47,umask=0x4 01 BL Bounceable : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.bl_crd uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL credited) event=0x47,umask=0x8 01 BL credited : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.iv uncore interconnect Number of allocations into the CRS Egress used to queue up requests destined to the mesh (IV) event=0x47,umask=0x20 01 IV : Number of allocations into the CRS Egress unc_mdf_crs_txr_v_bounces.ad uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AD) event=0x4b,umask=0x1 01 AD : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.ak uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AK) event=0x4b,umask=0x4 01 AK : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.akc uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC) event=0x4b,umask=0x10 01 AKC : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.bl uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (BL) event=0x4b,umask=0x2 01 BL : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.iv uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (IV) event=0x4b,umask=0x8 01 IV : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_fast_asserted.ad_bnc uncore interconnect Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold event=0x15,umask=0x1 01 AD bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold unc_mdf_fast_asserted.bl_crd uncore interconnect Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold event=0x15,umask=0x2 01 BL bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold unc_upi_clockticks uncore interconnect UPI Clockticks event=0x1 01 Number of UPI LL clock cycles while the event is enabled unc_upi_direct_attempts.d2c uncore interconnect Direct packet attempts : D2C event=0x12,umask=0x1 01 Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_upi_direct_attempts.d2k uncore interconnect Direct packet attempts : D2K event=0x12,umask=0x2 01 Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_upi_l1_power_cycles uncore interconnect Cycles in L1 event=0x21 01 Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode unc_upi_power_l1_nack uncore interconnect L1 Req Nack event=0x23 01 L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_power_l1_req uncore interconnect L1 Req (same as L1 Ack) event=0x22 01 L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_rxl0p_power_cycles uncore interconnect Cycles in L0p event=0x25 01 Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_upi_rxl0_power_cycles uncore interconnect Cycles in L0 event=0x24 01 Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_rxl_any_flits.data uncore interconnect UNC_UPI_RxL_ANY_FLITS.DATA event=0x4b,umask=0x8 01 unc_upi_rxl_any_flits.llcrd uncore interconnect UNC_UPI_RxL_ANY_FLITS.LLCRD event=0x4b,umask=0x10 01 unc_upi_rxl_any_flits.llctrl uncore interconnect UNC_UPI_RxL_ANY_FLITS.LLCTRL event=0x4b,umask=0x40 01 unc_upi_rxl_any_flits.null uncore interconnect UNC_UPI_RxL_ANY_FLITS.NULL event=0x4b,umask=0x20 01 unc_upi_rxl_any_flits.prothdr uncore interconnect UNC_UPI_RxL_ANY_FLITS.PROTHDR event=0x4b,umask=0x80 01 unc_upi_rxl_any_flits.slot0 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT0 event=0x4b,umask=0x1 01 unc_upi_rxl_any_flits.slot1 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT1 event=0x4b,umask=0x2 01 unc_upi_rxl_any_flits.slot2 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT2 event=0x4b,umask=0x4 01 unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass event=0x5,umask=0xe 01 Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode event=0x5,umask=0x10e 01 Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard event=0x5,umask=0xf 01 Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode event=0x5,umask=0x10f 01 Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_bypassed.slot0 uncore interconnect RxQ Flit Buffer Bypassed : Slot 0 event=0x31,umask=0x1 01 RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot1 uncore interconnect RxQ Flit Buffer Bypassed : Slot 1 event=0x31,umask=0x2 01 RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot2 uncore interconnect RxQ Flit Buffer Bypassed : Slot 2 event=0x31,umask=0x4 01 RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_crc_errors uncore interconnect CRC Errors Detected event=0xb 01 CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=0x8 01 LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs. unc_upi_rxl_credits_consumed_vn0 uncore interconnect VN0 Credit Consumed event=0x39 01 VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vn1 uncore interconnect VN1 Credit Consumed event=0x3a 01 VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x38,ch_mask=0x00000000,fc_mask=0x00000000 01 Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_data uncore interconnect Valid Flits Received : All Data event=0x3,umask=0xf 01 Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=0x3,umask=0x27 01 unc_upi_rxl_flits.data uncore interconnect Valid Flits Received : Data event=0x3,umask=0x8 01 Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Idle event=0x3,umask=0x47 01 Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received : LLCRD Not Empty event=0x3,umask=0x10 01 Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received : LLCTRL event=0x3,umask=0x40 01 Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_rxl_flits.non_data uncore interconnect Valid Flits Received : All Non Data event=0x3,umask=0x97 01 Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.null uncore interconnect Valid Flits Received : Slot NULL or LLCRD Empty event=0x3,umask=0x20 01 Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received : Protocol Header event=0x3,umask=0x80 01 Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received : Slot 0 event=0x3,umask=0x1 01 Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received : Slot 1 event=0x3,umask=0x2 01 Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received : Slot 2 event=0x3,umask=0x4 01 Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations : Slot 0 event=0x30,umask=0x1 01 RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations : Slot 1 event=0x30,umask=0x2 01 RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations : Slot 2 event=0x30,umask=0x4 01 RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets : Slot 0 event=0x32,umask=0x1 01 RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets : Slot 1 event=0x32,umask=0x2 01 RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets : Slot 2 event=0x32,umask=0x4 01 RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_txl0p_power_cycles uncore interconnect Cycles in L0p event=0x27 01 Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_upi_txl0_power_cycles uncore interconnect Cycles in L0 event=0x26 01 Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event unc_upi_txl_any_flits.data uncore interconnect UNC_UPI_TxL_ANY_FLITS.DATA event=0x4a,umask=0x8 01 unc_upi_txl_any_flits.llcrd uncore interconnect UNC_UPI_TxL_ANY_FLITS.LLCRD event=0x4a,umask=0x10 01 unc_upi_txl_any_flits.llctrl uncore interconnect UNC_UPI_TxL_ANY_FLITS.LLCTRL event=0x4a,umask=0x40 01 unc_upi_txl_any_flits.null uncore interconnect UNC_UPI_TxL_ANY_FLITS.NULL event=0x4a,umask=0x20 01 unc_upi_txl_any_flits.prothdr uncore interconnect UNC_UPI_TxL_ANY_FLITS.PROTHDR event=0x4a,umask=0x80 01 unc_upi_txl_any_flits.slot0 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT0 event=0x4a,umask=0x1 01 unc_upi_txl_any_flits.slot1 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT1 event=0x4a,umask=0x2 01 unc_upi_txl_any_flits.slot2 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT2 event=0x4a,umask=0x4 01 unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass event=0x4,umask=0xe 01 Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode event=0x4,umask=0x10e 01 Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard event=0x4,umask=0xf 01 Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode event=0x4,umask=0x10f 01 Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_bypassed uncore interconnect Tx Flit Buffer Bypassed event=0x41 01 Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data event=0x2,umask=0xf 01 Valid Flits Sent : All Data : Counts number of data flits across this UPI link unc_upi_txl_flits.all_llcrd uncore interconnect Valid Flits Sent : All LLCRD Not Empty event=0x2,umask=0x17 01 Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_llctrl uncore interconnect Valid Flits Sent : All LLCTRL event=0x2,umask=0x47 01 Valid Flits Sent : All LLCTRL : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_null uncore interconnect All Null Flits event=0x2,umask=0x27 01 unc_upi_txl_flits.all_prothdr uncore interconnect Valid Flits Sent : All Protocol Header event=0x2,umask=0x87 01 Valid Flits Sent : All ProtDDR : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.data uncore interconnect Valid Flits Sent : Data event=0x2,umask=0x8 01 Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_txl_flits.idle uncore interconnect Valid Flits Sent : Idle event=0x2,umask=0x47 01 Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent : LLCRD Not Empty event=0x2,umask=0x10 01 Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent : LLCTRL event=0x2,umask=0x40 01 Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages unc_upi_txl_flits.non_data uncore interconnect Valid Flits Sent : All Non Data event=0x2,umask=0x97 01 Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.null uncore interconnect Valid Flits Sent : Slot NULL or LLCRD Empty event=0x2,umask=0x20 01 Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent : Protocol Header event=0x2,umask=0x80 01 Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent : Slot 0 event=0x2,umask=0x1 01 Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent : Slot 1 event=0x2,umask=0x2 01 Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent : Slot 2 event=0x2,umask=0x4 01 Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count unc_upi_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=0x40 01 Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=0x42 01 Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_upi_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x44 01 VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link unc_u_event_msg.doorbell_rcvd uncore interconnect Message Received : Doorbell event=0x42,umask=0x8 01 unc_u_event_msg.int_prio uncore interconnect Message Received : Interrupt event=0x42,umask=0x10 01 Message Received : Interrupt : Interrupts unc_u_event_msg.ipi_rcvd uncore interconnect Message Received : IPI event=0x42,umask=0x4 01 Message Received : IPI : Inter Processor Interrupts unc_u_event_msg.msi_rcvd uncore interconnect Message Received : MSI event=0x42,umask=0x2 01 Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only) unc_u_event_msg.vlw_rcvd uncore interconnect Message Received : VLW event=0x42,umask=0x1 01 Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore unc_u_m2u_misc1.rxc_cycles_ne_cbo_ncb uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB event=0x4d,umask=0x1 01 unc_u_m2u_misc1.rxc_cycles_ne_cbo_ncs uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS event=0x4d,umask=0x2 01 unc_u_m2u_misc1.rxc_cycles_ne_upi_ncb uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB event=0x4d,umask=0x4 01 unc_u_m2u_misc1.rxc_cycles_ne_upi_ncs uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS event=0x4d,umask=0x8 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_cbo_ncb uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB event=0x4d,umask=0x10 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_cbo_ncs uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS event=0x4d,umask=0x20 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_upi_ncb uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB event=0x4d,umask=0x40 01 unc_u_m2u_misc1.txc_cycles_crd_ovf_upi_ncs uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS event=0x4d,umask=0x80 01 unc_u_m2u_misc2.rxc_cycles_empty_bl uncore interconnect UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL event=0x4e,umask=0x2 01 unc_u_m2u_misc2.rxc_cycles_full_bl uncore interconnect UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL event=0x4e,umask=0x1 01 unc_u_m2u_misc2.txc_cycles_crd_ovf_vn0_ncb uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB event=0x4e,umask=0x4 01 unc_u_m2u_misc2.txc_cycles_crd_ovf_vn0_ncs uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS event=0x4e,umask=0x8 01 unc_u_m2u_misc2.txc_cycles_empty_ak uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK event=0x4e,umask=0x20 01 unc_u_m2u_misc2.txc_cycles_empty_akc uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC event=0x4e,umask=0x40 01 unc_u_m2u_misc2.txc_cycles_empty_bl uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL event=0x4e,umask=0x10 01 unc_u_m2u_misc2.txc_cycles_full_bl uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL event=0x4e,umask=0x80 01 unc_u_m2u_misc3.txc_cycles_full_ak uncore interconnect UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK event=0x4f,umask=0x1 01 unc_u_m2u_misc3.txc_cycles_full_akc uncore interconnect UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC event=0x4f,umask=0x2 01 unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack : Assert to ACK event=0x45,umask=0x1 01 Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles unc_u_racu_requests uncore interconnect RACU Request event=0x46 01 RACU Request : Number outstanding register requests within message channel tracker uncore_iio_free_running unc_iio_bandwidth_in.part0_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x20 01 unc_iio_bandwidth_in.part1_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x21 01 unc_iio_bandwidth_in.part2_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x22 01 unc_iio_bandwidth_in.part3_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x23 01 unc_iio_bandwidth_in.part4_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x24 01 unc_iio_bandwidth_in.part5_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x25 01 unc_iio_bandwidth_in.part6_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x26 01 unc_iio_bandwidth_in.part7_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x27 01 unc_iio_clockticks uncore io IIO Clockticks event=0x1,ch_mask=0x0000 01 Number of IIO clock cycles while the event is enabled unc_iio_clockticks_freerun uncore io Free running counter that increments for IIO clocktick event=0xff,umask=0x10 01 unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-7 event=0xc2,ch_mask=0xff,fc_mask=0x07,umask=0x4 01 PCIe Completion Buffer Inserts of completions with data : Part 0-7 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=0x0001,fc_mask=0x07,umask=0x7001004 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=0x0002,fc_mask=0x07,umask=0x7002004 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=0x0004,fc_mask=0x07,umask=0x7004004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=0x0008,fc_mask=0x07,umask=0x7008004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIe Completion Buffer Inserts of completions with data: Part 4 event=0xc2,ch_mask=0x0010,fc_mask=0x07,umask=0x7010004 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIe Completion Buffer Inserts of completions with data: Part 5 event=0xc2,ch_mask=0x0020,fc_mask=0x07,umask=0x7020004 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIe Completion Buffer Inserts of completions with data: Part 6 event=0xc2,ch_mask=0x0040,fc_mask=0x07,umask=0x7040004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIe Completion Buffer Inserts of completions with data: Part 7 event=0xc2,ch_mask=0x0080,fc_mask=0x07,umask=0x7080004 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS event=0xd5,fc_mask=0x07,umask=0xff 01 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer Occupancy : Part 0 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000001 01 x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer Occupancy : Part 1 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000002 01 x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer Occupancy : Part 2 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000004 01 x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer Occupancy : Part 3 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000008 01 x4 card is plugged in to slot 3 unc_iio_comp_buf_occupancy.cmpd.part4 uncore io PCIe Completion Buffer Occupancy : Part 4 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000010 01 x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part5 uncore io PCIe Completion Buffer Occupancy : Part 5 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000020 01 x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part6 uncore io PCIe Completion Buffer Occupancy : Part 6 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000040 01 x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part7 uncore io PCIe Completion Buffer Occupancy : Part 7 event=0xd5,ch_mask=0x0000,fc_mask=0x07,umask=0x7000080 01 x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.all_parts uncore io Read request for 4 bytes made by the CPU to IIO Part0-7 event=0xc0,ch_mask=0x00ff,fc_mask=0x07,umask=0x4 01 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Read request for 4 bytes made by the CPU to IIO Part0 event=0xc0,ch_mask=0x0001,fc_mask=0x07,umask=0x7001004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part1 uncore io Read request for 4 bytes made by the CPU to IIO Part1 event=0xc0,ch_mask=0x0002,fc_mask=0x07,umask=0x7002004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part2 uncore io Read request for 4 bytes made by the CPU to IIO Part2 event=0xc0,ch_mask=0x0004,fc_mask=0x07,umask=0x7004004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part3 uncore io Read request for 4 bytes made by the CPU to IIO Part3 event=0xc0,ch_mask=0x0008,fc_mask=0x07,umask=0x7008004 01 Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x0010,fc_mask=0x07,umask=0x7010004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x0020,fc_mask=0x07,umask=0x7020004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x0040,fc_mask=0x07,umask=0x7040004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x0080,fc_mask=0x07,umask=0x7080004 01 Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.all_parts uncore io Write request of 4 bytes made to IIO Part0-7 by the CPU event=0xc0,ch_mask=0x00ff,fc_mask=0x07,umask=0x1 01 unc_iio_data_req_by_cpu.mem_write.iommu0 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x0100,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_write.iommu1 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x0200,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Write request of 4 bytes made to IIO Part0 by the CPU event=0xc0,ch_mask=0x0001,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part1 uncore io Write request of 4 bytes made to IIO Part1 by the CPU event=0xc0,ch_mask=0x0002,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part2 uncore io Write request of 4 bytes made to IIO Part2 by the CPU event=0xc0,ch_mask=0x0004,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part3 uncore io Write request of 4 bytes made to IIO Part3 by the CPU event=0xc0,ch_mask=0x0008,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x0010,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x0020,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x0040,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x0080,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=0x0001,fc_mask=0x07,umask=0x7001008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=0x0002,fc_mask=0x07,umask=0x7002008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=0x0004,fc_mask=0x07,umask=0x7004008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=0x0008,fc_mask=0x07,umask=0x7008008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part4 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x0010,fc_mask=0x07,umask=0x7010008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part5 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x0020,fc_mask=0x07,umask=0x7020008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part6 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x0040,fc_mask=0x07,umask=0x7040008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part7 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x0080,fc_mask=0x07,umask=0x7080008 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=0x0001,fc_mask=0x07,umask=0x7001002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=0x0002,fc_mask=0x07,umask=0x7002002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=0x0004,fc_mask=0x07,umask=0x7004002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=0x0008,fc_mask=0x07,umask=0x7008002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part4 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x0010,fc_mask=0x07,umask=0x7010002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part5 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x0020,fc_mask=0x07,umask=0x7020002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part6 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x0040,fc_mask=0x07,umask=0x7040002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part7 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x0080,fc_mask=0x07,umask=0x7080002 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.cmpd.all_parts uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0xff,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.cmpd.part0 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.cmpd.part1 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.cmpd.part2 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.cmpd.part3 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.cmpd.part4 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.cmpd.part5 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.cmpd.part6 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.cmpd.part7 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.mem_read.all_parts uncore io Read request for 4 bytes made by IIO Part0-7 to Memory event=0x83,ch_mask=0x00ff,fc_mask=0x07,umask=0x4 01 unc_iio_data_req_of_cpu.mem_read.part0 uncore io Read request for 4 bytes made by IIO Part0 to Memory event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io Read request for 4 bytes made by IIO Part1 to Memory event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io Read request for 4 bytes made by IIO Part2 to Memory event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part3 uncore io Read request for 4 bytes made by IIO Part3 to Memory event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part4 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part5 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part6 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part7 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.all_parts uncore io Write request of 4 bytes made by IIO Part0-7 to Memory event=0x83,ch_mask=0x00ff,fc_mask=0x07,umask=0x1 01 unc_iio_data_req_of_cpu.mem_write.part0 uncore io Write request of 4 bytes made by IIO Part0 to Memory event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io Write request of 4 bytes made by IIO Part1 to Memory event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io Write request of 4 bytes made by IIO Part2 to Memory event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part3 uncore io Write request of 4 bytes made by IIO Part3 to Memory event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part4 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part5 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part6 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part7 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_inbound_arb_req.data uncore io Incoming arbitration requests : Passing data to be written event=0x86,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff020 01 Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.final_rd_wr uncore io Incoming arbitration requests : Issuing final read or write of line event=0x86,ch_mask=0x00FF,fc_mask=0x07,umask=0x8 01 Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_hit uncore io Incoming arbitration requests : Processing response from IOMMU event=0x86,ch_mask=0x00FF,fc_mask=0x07,umask=0x2 01 Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_req uncore io Incoming arbitration requests : Issuing to IOMMU event=0x86,ch_mask=0x00FF,fc_mask=0x07,umask=0x1 01 Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.req_own uncore io Incoming arbitration requests : Request Ownership event=0x86,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff004 01 Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.wr uncore io Incoming arbitration requests : Writing line event=0x86,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff010 01 Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.data uncore io Incoming arbitration requests granted : Passing data to be written event=0x87,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff020 01 Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.final_rd_wr uncore io Incoming arbitration requests granted : Issuing final read or write of line event=0x87,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff008 01 Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_hit uncore io Incoming arbitration requests granted : Processing response from IOMMU event=0x87,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff002 01 Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_req uncore io Incoming arbitration requests granted : Issuing to IOMMU event=0x87,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff001 01 Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.req_own uncore io Incoming arbitration requests granted : Request Ownership event=0x87,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff004 01 Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.wr uncore io Incoming arbitration requests granted : Writing line event=0x87,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff010 01 Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_iommu0.1g_hits uncore io : IOTLB Hits to a 1G Page event=0x40,ch_mask=0x0000,umask=0x10 01 : IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB unc_iio_iommu0.2m_hits uncore io : IOTLB Hits to a 2M Page event=0x40,ch_mask=0x0000,umask=0x8 01 : IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB unc_iio_iommu0.4k_hits uncore io : IOTLB Hits to a 4K Page event=0x40,ch_mask=0x0000,umask=0x4 01 : IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB unc_iio_iommu0.ctxt_cache_hits uncore io : Context cache hits event=0x40,ch_mask=0x0000,umask=0x80 01 : Context cache hits : Counts each time a first look up of the transaction hits the RCC unc_iio_iommu0.ctxt_cache_lookups uncore io : Context cache lookups event=0x40,ch_mask=0x0000,umask=0x40 01 : Context cache lookups : Counts each time a transaction looks up root context cache unc_iio_iommu0.first_lookups uncore io : IOTLB lookups first event=0x40,ch_mask=0x0000,umask=0x1 01 : IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB unc_iio_iommu0.misses uncore io IOTLB Fills (same as IOTLB miss) event=0x40,ch_mask=0x0000,umask=0x20 01 IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB unc_iio_iommu1.num_mem_accesses uncore io : IOMMU memory access event=0x41,umask=0xc0 01 : IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel unc_iio_iommu1.pwc_1g_hits uncore io : PWC Hit to a 2M page event=0x41,umask=0x4 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.pwc_256t_hits uncore io : PWT Hit to a 256T page event=0x41,umask=0x10 01 : PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level unc_iio_iommu1.pwc_2m_hits uncore io : PWC Hit to a 4K page event=0x41,umask=0x2 01 : PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level unc_iio_iommu1.pwc_512g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=0x8 01 : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu1.pwc_cache_fills uncore io : PageWalk cache fill event=0x41,umask=0x20 01 : PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted unc_iio_iommu1.pwt_cache_lookups uncore io : PageWalk cache lookup event=0x41,umask=0x1 01 : PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache unc_iio_iommu1.slpwc_1g_hits uncore io : PWC Hit to a 2M page event=0x41,umask=0x4 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.slpwc_256t_hits uncore io : PWC Hit to a 2M page event=0x41,umask=0x10 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.slpwc_512g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=0x8 01 : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu3.pwt_occupancy_msb uncore io : Global IOTLB invalidation cycles event=0x43,ch_mask=0x0000,umask=0x1 01 : Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation unc_iio_mask_match_and.bus0 uncore io AND Mask/match for debug bus : Non-PCIE bus event=0x2,ch_mask=0x0000,umask=0x1 01 AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and PCIE bus event=0x2,ch_mask=0x0000,umask=0x8 01 AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_not_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=0x2,ch_mask=0x0000,umask=0x4 01 AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus1 uncore io AND Mask/match for debug bus : PCIE bus event=0x2,ch_mask=0x0000,umask=0x2 01 AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=0x2,ch_mask=0x0000,umask=0x10 01 AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_not_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=0x2,ch_mask=0x0000,umask=0x20 01 AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_or.bus0 uncore io OR Mask/match for debug bus : Non-PCIE bus event=0x3,ch_mask=0x0000,umask=0x1 01 OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and PCIE bus event=0x3,ch_mask=0x0000,umask=0x8 01 OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_not_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=0x3,ch_mask=0x0000,umask=0x4 01 OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus1 uncore io OR Mask/match for debug bus : PCIE bus event=0x3,ch_mask=0x0000,umask=0x2 01 OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=0x3,ch_mask=0x0000,umask=0x10 01 OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_not_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=0x3,ch_mask=0x0000,umask=0x20 01 OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_num_req_of_cpu.commit.all uncore io Number requests PCIe makes of the main die : All event=0x85,ch_mask=0x0FFF,fc_mask=0x07,umask=0x1 01 Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU unc_iio_num_req_of_cpu_by_tgt.abort uncore io Num requests sent by PCIe - by target : Abort event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x80 01 unc_iio_num_req_of_cpu_by_tgt.confined_p2p uncore io Num requests sent by PCIe - by target : Confined P2P event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x40 01 unc_iio_num_req_of_cpu_by_tgt.loc_p2p uncore io Num requests sent by PCIe - by target : Local P2P event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x20 01 unc_iio_num_req_of_cpu_by_tgt.mcast uncore io Num requests sent by PCIe - by target : Multi-cast event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x2 01 unc_iio_num_req_of_cpu_by_tgt.mem uncore io Num requests sent by PCIe - by target : Memory event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x8 01 unc_iio_num_req_of_cpu_by_tgt.msgb uncore io Num requests sent by PCIe - by target : MsgB event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x1 01 unc_iio_num_req_of_cpu_by_tgt.rem_p2p uncore io Num requests sent by PCIe - by target : Remote P2P event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x10 01 unc_iio_num_req_of_cpu_by_tgt.ubox uncore io Num requests sent by PCIe - by target : Ubox event=0x8e,ch_mask=0x00FF,fc_mask=0x07,umask=0x4 01 unc_iio_num_tgt_matched_req_of_cpu uncore io ITC address map 1 event=0x8f,ch_mask=0x0000 01 UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU unc_iio_outbound_cl_reqs_issued.to_io uncore io Outbound cacheline requests issued : 64B requests issued to device event=0xd0,ch_mask=0x00FF,fc_mask=0x07,umask=0x8 01 Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line unc_iio_outbound_tlp_reqs_issued.to_io uncore io Outbound TLP (transaction layer packet) requests issued : To device event=0xd1,ch_mask=0x00FF,fc_mask=0x07,umask=0x8 01 Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer unc_iio_pwt_occupancy uncore io PWT occupancy. Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle) event=0x42,ch_mask=0x0000,umask=0xff 01 PWT occupancy : Indicates how many page walks are outstanding at any point in time unc_iio_req_from_pcie_cl_cmpl.data uncore io Request Ownership : PCIe Request complete event=0x91,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff020 01 Request Ownership : PCIe Request complete : Only for posted requests : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cl_cmpl.final_rd_wr uncore io Request Ownership : Writing line event=0x91,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff008 01 Request Ownership : Writing line : Only for posted requests : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.req_own uncore io Request Ownership : Issuing final read or write of line event=0x91,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff004 01 Request Ownership : Issuing final read or write of line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.wr uncore io Request Ownership : Passing data to be written event=0x91,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff010 01 Request Ownership : Passing data to be written : Only for posted requests : Only for posted requests unc_iio_req_from_pcie_cmpl.final_rd_wr uncore io Processing response from IOMMU : Passing data to be written event=0x92,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff008 01 Processing response from IOMMU : Passing data to be written : Only for posted requests unc_iio_req_from_pcie_cmpl.iommu_hit uncore io Processing response from IOMMU : Issuing final read or write of line event=0x92,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff002 01 unc_iio_req_from_pcie_cmpl.iommu_req uncore io Processing response from IOMMU : Request Ownership event=0x92,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff001 01 Processing response from IOMMU : Request Ownership : Only for posted requests unc_iio_req_from_pcie_cmpl.req_own uncore io Processing response from IOMMU : Writing line event=0x92,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff004 01 Processing response from IOMMU : Writing line : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.data uncore io PCIe Request - pass complete : Passing data to be written event=0x90,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff020 01 PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.final_rd_wr uncore io PCIe Request - pass complete : Issuing final read or write of line event=0x90,ch_mask=0x00FF,fc_mask=0x07,umask=0x8 01 PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state unc_iio_req_from_pcie_pass_cmpl.req_own uncore io PCIe Request - pass complete : Request Ownership event=0x90,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff004 01 PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.wr uncore io PCIe Request - pass complete : Writing line event=0x90,ch_mask=0x00FF,fc_mask=0x07,umask=0x70ff010 01 PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part0 event=0xc1,ch_mask=0x0001,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part1 event=0xc1,ch_mask=0x0002,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part2 event=0xc1,ch_mask=0x0004,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part3 event=0xc1,ch_mask=0x0008,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x0010,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x0020,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x0040,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x0080,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU event=0xc1,ch_mask=0x0001,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU event=0xc1,ch_mask=0x0002,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU event=0xc1,ch_mask=0x0004,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU event=0xc1,ch_mask=0x0008,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x0010,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x0020,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x0040,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x0080,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0001,fc_mask=0x07,umask=0x7001002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0002,fc_mask=0x07,umask=0x7002002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0004,fc_mask=0x07,umask=0x7004002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0008,fc_mask=0x07,umask=0x7008002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0010,fc_mask=0x07,umask=0x7010002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_write.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0020,fc_mask=0x07,umask=0x7020002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_write.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0040,fc_mask=0x07,umask=0x7040002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_write.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x0080,fc_mask=0x07,umask=0x7080002 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.cmpd.part0 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.cmpd.part1 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.cmpd.part2 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.cmpd.part3 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.cmpd.part4 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.cmpd.part5 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.cmpd.part6 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.cmpd.part7 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_write.part4 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.peer_write.part5 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.peer_write.part6 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.peer_write.part7 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 uncore_m2pcie unc_m2p_clockticks uncore io M2P Clockticks event=0x1 01 Number of M2P clock cycles while the event is enabled unc_m2p_cms_clockticks uncore io CMS Clockticks event=0xc0 01 unc_m2p_egress_ordering.iv_snoopgo_dn uncore io Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2p_egress_ordering.iv_snoopgo_up uncore io Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2p_iio_credits_acquired.drs_0 uncore io M2PCIe IIO Credit Acquired : DRS event=0x33,umask=0x1 01 M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_acquired.drs_1 uncore io M2PCIe IIO Credit Acquired : DRS event=0x33,umask=0x2 01 M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_acquired.ncb_0 uncore io M2PCIe IIO Credit Acquired : NCB event=0x33,umask=0x4 01 M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_acquired.ncb_1 uncore io M2PCIe IIO Credit Acquired : NCB event=0x33,umask=0x8 01 M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_acquired.ncs_0 uncore io M2PCIe IIO Credit Acquired : NCS event=0x33,umask=0x10 01 M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class unc_m2p_iio_credits_acquired.ncs_1 uncore io M2PCIe IIO Credit Acquired : NCS event=0x33,umask=0x20 01 M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class unc_m2p_iio_credits_reject.drs uncore io M2PCIe IIO Failed to Acquire a Credit : DRS event=0x34,umask=0x8 01 M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class unc_m2p_iio_credits_reject.ncb uncore io M2PCIe IIO Failed to Acquire a Credit : NCB event=0x34,umask=0x10 01 M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class unc_m2p_iio_credits_reject.ncs uncore io M2PCIe IIO Failed to Acquire a Credit : NCS event=0x34,umask=0x20 01 M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class unc_m2p_iio_credits_used.drs_0 uncore io M2PCIe IIO Credits in Use : DRS to CMS Port 0 event=0x32,umask=0x1 01 M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_used.drs_1 uncore io M2PCIe IIO Credits in Use : DRS to CMS Port 1 event=0x32,umask=0x2 01 M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_used.ncb_0 uncore io M2PCIe IIO Credits in Use : NCB to CMS Port 0 event=0x32,umask=0x4 01 M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_used.ncb_1 uncore io M2PCIe IIO Credits in Use : NCB to CMS Port 1 event=0x32,umask=0x8 01 M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_used.ncs_0 uncore io M2PCIe IIO Credits in Use : NCS to CMS Port 0 event=0x32,umask=0x10 01 M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class unc_m2p_iio_credits_used.ncs_1 uncore io M2PCIe IIO Credits in Use : NCS to CMS Port 1 event=0x32,umask=0x20 01 M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class unc_m2p_local_ded_p2p_crd_taken_0.m2iosf0_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB event=0x46,umask=0x1 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf0_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS event=0x46,umask=0x2 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf1_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB event=0x46,umask=0x4 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf1_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS event=0x46,umask=0x8 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf2_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB event=0x46,umask=0x10 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf2_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS event=0x46,umask=0x20 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf3_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB event=0x46,umask=0x40 01 unc_m2p_local_ded_p2p_crd_taken_0.m2iosf3_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS event=0x46,umask=0x80 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf4_ncb uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB event=0x47,umask=0x1 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf4_ncs uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS event=0x47,umask=0x2 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf5_ncb uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB event=0x47,umask=0x4 01 unc_m2p_local_ded_p2p_crd_taken_1.m2iosf5_ncs uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS event=0x47,umask=0x8 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf0_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB event=0x19,umask=0x1 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf0_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS event=0x19,umask=0x2 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf1_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB event=0x19,umask=0x4 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf1_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS event=0x19,umask=0x8 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf2_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB event=0x19,umask=0x10 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf2_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS event=0x19,umask=0x20 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB event=0x19,umask=0x40 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS event=0x19,umask=0x80 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf4_ncb uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB event=0x1a,umask=0x1 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf4_ncs uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS event=0x1a,umask=0x2 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf5_ncb uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB event=0x1a,umask=0x4 01 unc_m2p_local_p2p_ded_returned_1.ms2iosf5_ncs uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS event=0x1a,umask=0x8 01 unc_m2p_local_p2p_shar_returned.agent_0 uncore io Local P2P Shared Credits Returned : Agent0 event=0x17,umask=0x1 01 unc_m2p_local_p2p_shar_returned.agent_1 uncore io Local P2P Shared Credits Returned : Agent1 event=0x17,umask=0x2 01 unc_m2p_local_p2p_shar_returned.agent_2 uncore io Local P2P Shared Credits Returned : Agent2 event=0x17,umask=0x4 01 unc_m2p_local_shar_p2p_crd_returned.agent_0 uncore io Local Shared P2P Credit Returned to credit ring : Agent0 event=0x44,umask=0x1 01 unc_m2p_local_shar_p2p_crd_returned.agent_1 uncore io Local Shared P2P Credit Returned to credit ring : Agent1 event=0x44,umask=0x2 01 unc_m2p_local_shar_p2p_crd_returned.agent_2 uncore io Local Shared P2P Credit Returned to credit ring : Agent2 event=0x44,umask=0x4 01 unc_m2p_local_shar_p2p_crd_returned.agent_3 uncore io Local Shared P2P Credit Returned to credit ring : Agent3 event=0x44,umask=0x8 01 unc_m2p_local_shar_p2p_crd_returned.agent_4 uncore io Local Shared P2P Credit Returned to credit ring : Agent4 event=0x44,umask=0x10 01 unc_m2p_local_shar_p2p_crd_returned.agent_5 uncore io Local Shared P2P Credit Returned to credit ring : Agent5 event=0x44,umask=0x20 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf0_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB event=0x40,umask=0x1 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf0_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS event=0x40,umask=0x2 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf1_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB event=0x40,umask=0x4 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf1_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS event=0x40,umask=0x8 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf2_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB event=0x40,umask=0x10 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf2_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS event=0x40,umask=0x20 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf3_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB event=0x40,umask=0x40 01 unc_m2p_local_shar_p2p_crd_taken_0.m2iosf3_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS event=0x40,umask=0x80 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf4_ncb uncore io Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB event=0x41,umask=0x1 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf4_ncs uncore io Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS event=0x41,umask=0x2 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf5_ncb uncore io Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB event=0x41,umask=0x4 01 unc_m2p_local_shar_p2p_crd_taken_1.m2iosf5_ncs uncore io Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS event=0x41,umask=0x8 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf0_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB event=0x4a,umask=0x1 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf0_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS event=0x4a,umask=0x2 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf1_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB event=0x4a,umask=0x4 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf1_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS event=0x4a,umask=0x8 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf2_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB event=0x4a,umask=0x10 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf2_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS event=0x4a,umask=0x20 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf3_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB event=0x4a,umask=0x40 01 unc_m2p_local_shar_p2p_crd_wait_0.m2iosf3_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS event=0x4a,umask=0x80 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf4_ncb uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB event=0x4b,umask=0x1 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf4_ncs uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS event=0x4b,umask=0x2 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf5_ncb uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB event=0x4b,umask=0x4 01 unc_m2p_local_shar_p2p_crd_wait_1.m2iosf5_ncs uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS event=0x4b,umask=0x8 01 unc_m2p_p2p_crd_occupancy.all uncore io P2P Credit Occupancy : All event=0x14,umask=0x10 01 unc_m2p_p2p_crd_occupancy.local_ncb uncore io P2P Credit Occupancy : Local NCB event=0x14,umask=0x1 01 unc_m2p_p2p_crd_occupancy.local_ncs uncore io P2P Credit Occupancy : Local NCS event=0x14,umask=0x2 01 unc_m2p_p2p_crd_occupancy.remote_ncb uncore io P2P Credit Occupancy : Remote NCB event=0x14,umask=0x4 01 unc_m2p_p2p_crd_occupancy.remote_ncs uncore io P2P Credit Occupancy : Remote NCS event=0x14,umask=0x8 01 unc_m2p_p2p_ded_received.all uncore io Dedicated Credits Received : All event=0x16,umask=0x10 01 unc_m2p_p2p_ded_received.local_ncb uncore io Dedicated Credits Received : Local NCB event=0x16,umask=0x1 01 unc_m2p_p2p_ded_received.local_ncs uncore io Dedicated Credits Received : Local NCS event=0x16,umask=0x2 01 unc_m2p_p2p_ded_received.remote_ncb uncore io Dedicated Credits Received : Remote NCB event=0x16,umask=0x4 01 unc_m2p_p2p_ded_received.remote_ncs uncore io Dedicated Credits Received : Remote NCS event=0x16,umask=0x8 01 unc_m2p_p2p_shar_received.all uncore io Shared Credits Received : All event=0x15,umask=0x10 01 unc_m2p_p2p_shar_received.local_ncb uncore io Shared Credits Received : Local NCB event=0x15,umask=0x1 01 unc_m2p_p2p_shar_received.local_ncs uncore io Shared Credits Received : Local NCS event=0x15,umask=0x2 01 unc_m2p_p2p_shar_received.remote_ncb uncore io Shared Credits Received : Remote NCB event=0x15,umask=0x4 01 unc_m2p_p2p_shar_received.remote_ncs uncore io Shared Credits Received : Remote NCS event=0x15,umask=0x8 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi0_drs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS event=0x48,umask=0x1 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi0_ncb uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB event=0x48,umask=0x2 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi0_ncs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS event=0x48,umask=0x4 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi1_drs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS event=0x48,umask=0x8 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi1_ncb uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB event=0x48,umask=0x10 01 unc_m2p_remote_ded_p2p_crd_taken_0.upi1_ncs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS event=0x48,umask=0x20 01 unc_m2p_remote_ded_p2p_crd_taken_1.upi2_drs uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS event=0x49,umask=0x1 01 unc_m2p_remote_ded_p2p_crd_taken_1.upi2_ncb uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB event=0x49,umask=0x2 01 unc_m2p_remote_ded_p2p_crd_taken_1.upi2_ncs uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS event=0x49,umask=0x4 01 unc_m2p_remote_p2p_ded_returned.upi0_ncb uncore io Remote P2P Dedicated Credits Returned : UPI0 - NCB event=0x1b,umask=0x1 01 unc_m2p_remote_p2p_ded_returned.upi0_ncs uncore io Remote P2P Dedicated Credits Returned : UPI0 - NCS event=0x1b,umask=0x2 01 unc_m2p_remote_p2p_ded_returned.upi1_ncb uncore io Remote P2P Dedicated Credits Returned : UPI1 - NCB event=0x1b,umask=0x4 01 unc_m2p_remote_p2p_ded_returned.upi1_ncs uncore io Remote P2P Dedicated Credits Returned : UPI1 - NCS event=0x1b,umask=0x8 01 unc_m2p_remote_p2p_ded_returned.upi2_ncb uncore io Remote P2P Dedicated Credits Returned : UPI2 - NCB event=0x1b,umask=0x10 01 unc_m2p_remote_p2p_ded_returned.upi2_ncs uncore io Remote P2P Dedicated Credits Returned : UPI2 - NCS event=0x1b,umask=0x20 01 unc_m2p_remote_p2p_shar_returned.agent_0 uncore io Remote P2P Shared Credits Returned : Agent0 event=0x18,umask=0x1 01 unc_m2p_remote_p2p_shar_returned.agent_1 uncore io Remote P2P Shared Credits Returned : Agent1 event=0x18,umask=0x2 01 unc_m2p_remote_p2p_shar_returned.agent_2 uncore io Remote P2P Shared Credits Returned : Agent2 event=0x18,umask=0x4 01 unc_m2p_remote_shar_p2p_crd_returned.agent_0 uncore io Remote Shared P2P Credit Returned to credit ring : Agent0 event=0x45,umask=0x1 01 unc_m2p_remote_shar_p2p_crd_returned.agent_1 uncore io Remote Shared P2P Credit Returned to credit ring : Agent1 event=0x45,umask=0x2 01 unc_m2p_remote_shar_p2p_crd_returned.agent_2 uncore io Remote Shared P2P Credit Returned to credit ring : Agent2 event=0x45,umask=0x4 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi0_drs uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - DRS event=0x42,umask=0x1 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi0_ncb uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - NCB event=0x42,umask=0x2 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi0_ncs uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - NCS event=0x42,umask=0x4 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi1_drs uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - DRS event=0x42,umask=0x8 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi1_ncb uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - NCB event=0x42,umask=0x10 01 unc_m2p_remote_shar_p2p_crd_taken_0.upi1_ncs uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - NCS event=0x42,umask=0x20 01 unc_m2p_remote_shar_p2p_crd_taken_1.upi2_drs uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - DRS event=0x43,umask=0x1 01 unc_m2p_remote_shar_p2p_crd_taken_1.upi2_ncb uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - NCB event=0x43,umask=0x2 01 unc_m2p_remote_shar_p2p_crd_taken_1.upi2_ncs uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - NCS event=0x43,umask=0x4 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi0_drs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS event=0x4c,umask=0x1 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi0_ncb uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB event=0x4c,umask=0x2 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi0_ncs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS event=0x4c,umask=0x4 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi1_drs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS event=0x4c,umask=0x8 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi1_ncb uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB event=0x4c,umask=0x10 01 unc_m2p_remote_shar_p2p_crd_wait_0.upi1_ncs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS event=0x4c,umask=0x20 01 unc_m2p_remote_shar_p2p_crd_wait_1.upi2_drs uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS event=0x4d,umask=0x1 01 unc_m2p_remote_shar_p2p_crd_wait_1.upi2_ncb uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB event=0x4d,umask=0x2 01 unc_m2p_remote_shar_p2p_crd_wait_1.upi2_ncs uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS event=0x4d,umask=0x4 01 unc_m2p_rxc_cycles_ne.all uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x80 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_idi uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x1 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x2 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x4 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.iio_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x20 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.iio_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x40 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.upi_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x8 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.upi_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x10 01 Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_inserts.all uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x80 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_idi uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x1 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x2 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x4 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.iio_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x20 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.iio_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x40 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.upi_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x8 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.upi_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x10 01 Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_txc_credits.pmm uncore io UNC_M2P_TxC_CREDITS.PMM event=0x2d,umask=0x2 01 unc_m2p_txc_credits.prq uncore io UNC_M2P_TxC_CREDITS.PRQ event=0x2d,umask=0x1 01 unc_m2p_txc_cycles_full.pmm_block_0 uncore io Egress (to CMS) Cycles Full event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x80 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.pmm_block_1 uncore io Egress (to CMS) Cycles Full event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x8 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_ne.pmm_distress_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x80 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.pmm_distress_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x8 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters uncore_m2hbm unc_m2hbm_clockticks uncore memory Cycles - at UCLK event=0x1 01 unc_m2hbm_cms_clockticks uncore memory CMS Clockticks event=0xc0 01 unc_m2hbm_direct2core_not_taken_dirstate uncore memory Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x17,umask=0x7 01 unc_m2hbm_direct2core_not_taken_dirstate.non_cisgress uncore memory Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress event=0x17,umask=0x2 01 Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints unc_m2hbm_direct2core_not_taken_notforked uncore memory Counts the time when FM didn't do d2c for fill reads (cross tile case) event=0x4a 01 unc_m2hbm_direct2core_txn_override uncore memory Number of reads in which direct to core transaction were overridden event=0x18,umask=0x3 01 unc_m2hbm_direct2core_txn_override.cisgress uncore memory Number of reads in which direct to core transaction was overridden : Cisgress event=0x18,umask=0x2 01 unc_m2hbm_direct2upi_not_taken_credits uncore memory Number of reads in which direct to Intel UPI transactions were overridden event=0x1b,umask=0x7 01 unc_m2hbm_direct2upi_not_taken_dirstate uncore memory Cycles when direct to Intel UPI was disabled event=0x1a,umask=0x7 01 unc_m2hbm_direct2upi_not_taken_dirstate.cisgress uncore memory Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored event=0x1a,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x4 01 Counts cisgress d2K that was not honored due to directory constraints unc_m2hbm_direct2upi_not_taken_dirstate.egress uncore memory Cycles when Direct2UPI was Disabled : Egress Ignored D2U event=0x1a,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1 01 Counts the number of time D2K was not honoured by egress due to directory state constraints unc_m2hbm_direct2upi_not_taken_dirstate.non_cisgress uncore memory Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored event=0x1a,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x2 01 Counts non cisgress d2K that was not honored due to directory constraints unc_m2hbm_direct2upi_txn_override uncore memory Number of reads that a message sent direct2 Intel UPI was overridden event=0x1c,umask=0x3 01 unc_m2hbm_direct2upi_txn_override.cisgress uncore memory Number of times a direct to UPI transaction was overridden event=0x1c,umask=0x2 01 unc_m2hbm_directory_hit.clean_a uncore memory Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x80 01 unc_m2hbm_directory_hit.clean_i uncore memory Directory Hit : On NonDirty Line in I State event=0x1d,umask=0x10 01 unc_m2hbm_directory_hit.clean_p uncore memory Directory Hit : On NonDirty Line in L State event=0x1d,umask=0x40 01 unc_m2hbm_directory_hit.clean_s uncore memory Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x20 01 unc_m2hbm_directory_hit.dirty_a uncore memory Directory Hit : On Dirty Line in A State event=0x1d,umask=0x8 01 unc_m2hbm_directory_hit.dirty_i uncore memory Directory Hit : On Dirty Line in I State event=0x1d,umask=0x1 01 unc_m2hbm_directory_hit.dirty_p uncore memory Directory Hit : On Dirty Line in L State event=0x1d,umask=0x4 01 unc_m2hbm_directory_hit.dirty_s uncore memory Directory Hit : On Dirty Line in S State event=0x1d,umask=0x2 01 unc_m2hbm_directory_lookup.any uncore memory Multi-socket cacheline Directory lookups (any state found) event=0x20,umask=0x1 01 Counts the number of hit data returns to egress with any directory to non persistent memory unc_m2hbm_directory_lookup.state_a uncore memory Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x20,umask=0x8 01 Counts the number of hit data returns to egress with directory A to non persistent memory unc_m2hbm_directory_lookup.state_i uncore memory Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x20,umask=0x2 01 Counts the number of hit data returns to egress with directory I to non persistent memory unc_m2hbm_directory_lookup.state_s uncore memory Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x20,umask=0x4 01 Counts the number of hit data returns to egress with directory S to non persistent memory unc_m2hbm_directory_miss.clean_a uncore memory Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x80 01 unc_m2hbm_directory_miss.clean_i uncore memory Directory Miss : On NonDirty Line in I State event=0x1e,umask=0x10 01 unc_m2hbm_directory_miss.clean_p uncore memory Directory Miss : On NonDirty Line in L State event=0x1e,umask=0x40 01 unc_m2hbm_directory_miss.clean_s uncore memory Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x20 01 unc_m2hbm_directory_miss.dirty_a uncore memory Directory Miss : On Dirty Line in A State event=0x1e,umask=0x8 01 unc_m2hbm_directory_miss.dirty_i uncore memory Directory Miss : On Dirty Line in I State event=0x1e,umask=0x1 01 unc_m2hbm_directory_miss.dirty_p uncore memory Directory Miss : On Dirty Line in L State event=0x1e,umask=0x4 01 unc_m2hbm_directory_miss.dirty_s uncore memory Directory Miss : On Dirty Line in S State event=0x1e,umask=0x2 01 unc_m2hbm_directory_update.a2i uncore memory Multi-socket cacheline Directory update from A to I event=0x21,umask=0x320 01 unc_m2hbm_directory_update.a2s uncore memory Multi-socket cacheline Directory update from A to S event=0x21,umask=0x340 01 unc_m2hbm_directory_update.any uncore memory Multi-socket cacheline Directory update from/to Any state event=0x21,umask=0x301 01 unc_m2hbm_directory_update.a_to_i_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x120 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to I to non persistent memory unc_m2hbm_directory_update.a_to_i_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x220 01 Counts 2lm miss data returns that would result in directory update from A to I to non persistent memory unc_m2hbm_directory_update.a_to_s_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x140 01 Counts 1lm or 2lm hit data returns that would result in directory update from A to S to non persistent memory unc_m2hbm_directory_update.a_to_s_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x240 01 Counts 2lm miss data returns that would result in directory update from A to S to non persistent memory unc_m2hbm_directory_update.hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x101 01 Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory unc_m2hbm_directory_update.i2a uncore memory Multi-socket cacheline Directory update from I to A event=0x21,umask=0x304 01 unc_m2hbm_directory_update.i2s uncore memory Multi-socket cacheline Directory update from I to S event=0x21,umask=0x302 01 unc_m2hbm_directory_update.i_to_a_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x104 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to A to non persistent memory unc_m2hbm_directory_update.i_to_a_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x204 01 Counts 2lm miss data returns that would result in directory update from I to A to non persistent memory unc_m2hbm_directory_update.i_to_s_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x102 01 Counts 1lm or 2lm hit data returns that would result in directory update from I to S to non persistent memory unc_m2hbm_directory_update.i_to_s_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x202 01 Counts 2lm miss data returns that would result in directory update from I to S to non persistent memory unc_m2hbm_directory_update.miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x201 01 Counts any 2lm miss data return that would result in directory update to non persistent memory unc_m2hbm_directory_update.s2a uncore memory Multi-socket cacheline Directory update from S to A event=0x21,umask=0x310 01 unc_m2hbm_directory_update.s2i uncore memory Multi-socket cacheline Directory update from S to I event=0x21,umask=0x308 01 unc_m2hbm_directory_update.s_to_a_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x110 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to A to non persistent memory unc_m2hbm_directory_update.s_to_a_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x210 01 Counts 2lm miss data returns that would result in directory update from S to A to non persistent memory unc_m2hbm_directory_update.s_to_i_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x108 01 Counts 1lm or 2lm hit data returns that would result in directory update from S to I to non persistent memory unc_m2hbm_directory_update.s_to_i_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x208 01 Counts 2lm miss data returns that would result in directory update from S to I to non persistent memory unc_m2hbm_distress.ad uncore memory Count distress signalled on AkAd cmp message event=0x67,umask=0x20 01 unc_m2hbm_distress.all uncore memory Count distress signalled on any packet type event=0x67,umask=0x1 01 unc_m2hbm_distress.bl_cmp uncore memory Count distress signalled on Bl Cmp message event=0x67,umask=0x40 01 unc_m2hbm_distress.crosstile_nmwr uncore memory Count distress signalled on NM fill write message event=0x67,umask=0x10 01 unc_m2hbm_distress.d2cha uncore memory Count distress signalled on D2Cha message event=0x67,umask=0x8 01 unc_m2hbm_distress.d2core uncore memory Count distress signalled on D2c message event=0x67,umask=0x2 01 unc_m2hbm_distress.d2upi uncore memory Count distress signalled on D2k message event=0x67,umask=0x4 01 unc_m2hbm_egress_ordering.iv_snoopgo_dn uncore memory Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x80000004 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2hbm_egress_ordering.iv_snoopgo_up uncore memory Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x80000001 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2hbm_igr_starve_winner.mask7 uncore memory Count when Starve Glocab counter is at 7 event=0x44,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x80 01 unc_m2hbm_imc_reads.all uncore memory Reads to iMC issued event=0x24,umask=0x304 01 unc_m2hbm_imc_reads.ch0.all uncore memory UNC_M2HBM_IMC_READS.CH0.ALL event=0x24,umask=0x104 01 unc_m2hbm_imc_reads.ch0.normal uncore memory UNC_M2HBM_IMC_READS.CH0.NORMAL event=0x24,umask=0x101 01 unc_m2hbm_imc_reads.ch0_all uncore memory UNC_M2HBM_IMC_READS.CH0_ALL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x104 01 unc_m2hbm_imc_reads.ch0_from_tgr uncore memory UNC_M2HBM_IMC_READS.CH0_FROM_TGR event=0x24,umask=0x140 01 unc_m2hbm_imc_reads.ch0_isoch uncore memory Critical Priority - Ch0 event=0x24,umask=0x102 01 unc_m2hbm_imc_reads.ch0_normal uncore memory UNC_M2HBM_IMC_READS.CH0_NORMAL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x101 01 unc_m2hbm_imc_reads.ch1.all uncore memory UNC_M2HBM_IMC_READS.CH1.ALL event=0x24,umask=0x204 01 unc_m2hbm_imc_reads.ch1.normal uncore memory UNC_M2HBM_IMC_READS.CH1.NORMAL event=0x24,umask=0x201 01 unc_m2hbm_imc_reads.ch1_all uncore memory UNC_M2HBM_IMC_READS.CH1_ALL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x204 01 unc_m2hbm_imc_reads.ch1_from_tgr uncore memory From TGR - Ch1 event=0x24,umask=0x240 01 unc_m2hbm_imc_reads.ch1_isoch uncore memory Critical Priority - Ch1 event=0x24,umask=0x202 01 unc_m2hbm_imc_reads.ch1_normal uncore memory UNC_M2HBM_IMC_READS.CH1_NORMAL event=0x24,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x201 01 unc_m2hbm_imc_reads.from_tgr uncore memory From TGR - All Channels event=0x24,umask=0x340 01 unc_m2hbm_imc_reads.isoch uncore memory Critical Priority - All Channels event=0x24,umask=0x302 01 unc_m2hbm_imc_reads.normal uncore memory UNC_M2HBM_IMC_READS.NORMAL event=0x24,umask=0x301 01 unc_m2hbm_imc_writes.all uncore memory All Writes - All Channels event=0x25,umask=0x1810 01 unc_m2hbm_imc_writes.ch0.all uncore memory UNC_M2HBM_IMC_WRITES.CH0.ALL event=0x25,umask=0x810 01 unc_m2hbm_imc_writes.ch0.full uncore memory UNC_M2HBM_IMC_WRITES.CH0.FULL event=0x25,umask=0x801 01 unc_m2hbm_imc_writes.ch0.partial uncore memory UNC_M2HBM_IMC_WRITES.CH0.PARTIAL event=0x25,umask=0x802 01 unc_m2hbm_imc_writes.ch0_all uncore memory UNC_M2HBM_IMC_WRITES.CH0_ALL event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x810 01 unc_m2hbm_imc_writes.ch0_from_tgr uncore memory From TGR - Ch0 event=0x25 01 unc_m2hbm_imc_writes.ch0_full uncore memory UNC_M2HBM_IMC_WRITES.CH0_FULL event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x801 01 unc_m2hbm_imc_writes.ch0_full_isoch uncore memory ISOCH Full Line - Ch0 event=0x25,umask=0x804 01 unc_m2hbm_imc_writes.ch0_ni uncore memory Non-Inclusive - Ch0 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000 01 unc_m2hbm_imc_writes.ch0_ni_miss uncore memory Non-Inclusive Miss - Ch0 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000 01 unc_m2hbm_imc_writes.ch0_partial uncore memory UNC_M2HBM_IMC_WRITES.CH0_PARTIAL event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x802 01 unc_m2hbm_imc_writes.ch0_partial_isoch uncore memory ISOCH Partial - Ch0 event=0x25,umask=0x808 01 unc_m2hbm_imc_writes.ch1.all uncore memory All Writes - Ch1 event=0x25,umask=0x1010 01 unc_m2hbm_imc_writes.ch1.full uncore memory Full Line Non-ISOCH - Ch1 event=0x25,umask=0x1001 01 unc_m2hbm_imc_writes.ch1.partial uncore memory Partial Non-ISOCH - Ch1 event=0x25,umask=0x1002 01 unc_m2hbm_imc_writes.ch1_all uncore memory All Writes - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1010 01 unc_m2hbm_imc_writes.ch1_from_tgr uncore memory From TGR - Ch1 event=0x25 01 unc_m2hbm_imc_writes.ch1_full uncore memory Full Line Non-ISOCH - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1001 01 unc_m2hbm_imc_writes.ch1_full_isoch uncore memory ISOCH Full Line - Ch1 event=0x25,umask=0x1004 01 unc_m2hbm_imc_writes.ch1_ni uncore memory Non-Inclusive - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000 01 unc_m2hbm_imc_writes.ch1_ni_miss uncore memory Non-Inclusive Miss - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000 01 unc_m2hbm_imc_writes.ch1_partial uncore memory Partial Non-ISOCH - Ch1 event=0x25,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1002 01 unc_m2hbm_imc_writes.ch1_partial_isoch uncore memory ISOCH Partial - Ch1 event=0x25,umask=0x1008 01 unc_m2hbm_imc_writes.from_tgr uncore memory From TGR - All Channels event=0x25 01 unc_m2hbm_imc_writes.full uncore memory Full Non-ISOCH - All Channels event=0x25,umask=0x1801 01 unc_m2hbm_imc_writes.full_isoch uncore memory ISOCH Full Line - All Channels event=0x25,umask=0x1804 01 unc_m2hbm_imc_writes.ni uncore memory Non-Inclusive - All Channels event=0x25,ch_mask=0x00000000,fc_mask=0x00000000 01 unc_m2hbm_imc_writes.ni_miss uncore memory Non-Inclusive Miss - All Channels event=0x25,ch_mask=0x00000000,fc_mask=0x00000000 01 unc_m2hbm_imc_writes.partial uncore memory Partial Non-ISOCH - All Channels event=0x25,umask=0x1802 01 unc_m2hbm_imc_writes.partial_isoch uncore memory ISOCH Partial - All Channels event=0x25,umask=0x1808 01 unc_m2hbm_prefcam_cis_drops uncore memory UNC_M2HBM_PREFCAM_CIS_DROPS event=0x5c 01 unc_m2hbm_prefcam_demand_drops.ch0_upi uncore memory Data Prefetches Dropped event=0x58,umask=0x2 01 unc_m2hbm_prefcam_demand_drops.ch0_xpt uncore memory Data Prefetches Dropped event=0x58,umask=0x1 01 unc_m2hbm_prefcam_demand_drops.ch1_upi uncore memory Data Prefetches Dropped event=0x58,umask=0x8 01 unc_m2hbm_prefcam_demand_drops.ch1_xpt uncore memory Data Prefetches Dropped event=0x58,umask=0x4 01 unc_m2hbm_prefcam_demand_drops.upi_allch uncore memory Data Prefetches Dropped : UPI - All Channels event=0x58,umask=0xa 01 unc_m2hbm_prefcam_demand_drops.xpt_allch uncore memory Data Prefetches Dropped event=0x58,umask=0x5 01 unc_m2hbm_prefcam_demand_merge.upi_allch uncore memory : UPI - All Channels event=0x5d,umask=0xa 01 unc_m2hbm_prefcam_demand_merge.xpt_allch uncore memory : XPT - All Channels event=0x5d,umask=0x5 01 unc_m2hbm_prefcam_demand_no_merge.rd_merged uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x40 01 unc_m2hbm_prefcam_demand_no_merge.wr_merged uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x20 01 unc_m2hbm_prefcam_demand_no_merge.wr_squashed uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x10 01 unc_m2hbm_prefcam_inserts.ch0_upi uncore memory Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=0x2 01 unc_m2hbm_prefcam_inserts.ch0_xpt uncore memory Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=0x1 01 unc_m2hbm_prefcam_inserts.ch1_upi uncore memory Prefetch CAM Inserts : UPI - Ch 1 event=0x56,umask=0x8 01 unc_m2hbm_prefcam_inserts.ch1_xpt uncore memory Prefetch CAM Inserts : XPT - Ch 1 event=0x56,umask=0x4 01 unc_m2hbm_prefcam_inserts.upi_allch uncore memory Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=0xa 01 unc_m2hbm_prefcam_inserts.xpt_allch uncore memory Prefetch CAM Inserts : XPT - All Channels event=0x56,umask=0x5 01 Prefetch CAM Inserts : XPT -All Channels unc_m2hbm_prefcam_occupancy.allch uncore memory Prefetch CAM Occupancy : All Channels event=0x54,umask=0x3 01 unc_m2hbm_prefcam_occupancy.ch0 uncore memory Prefetch CAM Occupancy : Channel 0 event=0x54,umask=0x1 01 unc_m2hbm_prefcam_occupancy.ch1 uncore memory Prefetch CAM Occupancy : Channel 1 event=0x54,umask=0x2 01 unc_m2hbm_prefcam_resp_miss.allch uncore memory All Channels event=0x5f,umask=0x3 01 unc_m2hbm_prefcam_resp_miss.ch0 uncore memory : Channel 0 event=0x5f,umask=0x1 01 unc_m2hbm_prefcam_resp_miss.ch1 uncore memory : Channel 1 event=0x5f,umask=0x2 01 unc_m2hbm_prefcam_rxc_deallocs.1lm_posted uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x62,umask=0x2 01 unc_m2hbm_prefcam_rxc_deallocs.cis uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS event=0x62,umask=0x8 01 unc_m2hbm_prefcam_rxc_deallocs.squashed uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x62,umask=0x1 01 unc_m2hbm_prefcam_rxc_occupancy uncore memory UNC_M2HBM_PREFCAM_RxC_OCCUPANCY event=0x60,ch_mask=0x00000000,fc_mask=0x00000000 01 unc_m2hbm_rxc_ad.inserts uncore memory AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=0x2,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1 01 unc_m2hbm_rxc_ad_inserts uncore memory AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=0x2,umask=0x1 01 unc_m2hbm_rxc_ad_occupancy uncore memory AD Ingress (from CMS) Occupancy event=0x3 01 unc_m2hbm_rxc_bl.inserts uncore memory BL Ingress (from CMS) : BL Ingress (from CMS) Allocations event=0x4,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1 01 Counts anytime a BL packet is added to Ingress unc_m2hbm_rxc_bl_inserts uncore memory BL Ingress (from CMS) : BL Ingress (from CMS) Allocations event=0x4,umask=0x1 01 Counts anytime a BL packet is added to Ingress unc_m2hbm_rxc_bl_occupancy uncore memory BL Ingress (from CMS) Occupancy event=0x5 01 unc_m2hbm_tgr_ad_credits uncore memory Number AD Ingress Credits event=0x2e 01 unc_m2hbm_tgr_bl_credits uncore memory Number BL Ingress Credits event=0x2f 01 unc_m2hbm_tracker_inserts.ch0 uncore memory Tracker Inserts : Channel 0 event=0x32,umask=0x104 01 unc_m2hbm_tracker_inserts.ch1 uncore memory Tracker Inserts : Channel 1 event=0x32,umask=0x204 01 unc_m2hbm_tracker_occupancy.ch0 uncore memory Tracker Occupancy : Channel 0 event=0x33,umask=0x1 01 unc_m2hbm_tracker_occupancy.ch1 uncore memory Tracker Occupancy : Channel 1 event=0x33,umask=0x2 01 unc_m2hbm_txc_ad.inserts uncore memory AD Egress (to CMS) : AD Egress (to CMS) Allocations event=0x6,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x1 01 Counts anytime a AD packet is added to Egress unc_m2hbm_txc_ad_inserts uncore memory AD Egress (to CMS) : AD Egress (to CMS) Allocations event=0x6,umask=0x1 01 Counts anytime a AD packet is added to Egress unc_m2hbm_txc_ad_occupancy uncore memory AD Egress (to CMS) Occupancy event=0x7 01 unc_m2hbm_txc_bl.inserts_cms0 uncore memory BL Egress (to CMS) : Inserts - CMS0 - Near Side event=0xe,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x101 01 Counts the number of BL transactions to CMS add port 0 unc_m2hbm_txc_bl.inserts_cms1 uncore memory BL Egress (to CMS) : Inserts - CMS1 - Far Side event=0xe,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x201 01 Counts the number of BL transactions to CMS add port 1 unc_m2hbm_txc_bl_occupancy.all uncore memory BL Egress (to CMS) Occupancy : All event=0xf,umask=0x3 01 unc_m2hbm_txc_bl_occupancy.cms0 uncore memory BL Egress (to CMS) Occupancy : Common Mesh Stop - Near Side event=0xf,umask=0x1 01 unc_m2hbm_txc_bl_occupancy.cms1 uncore memory BL Egress (to CMS) Occupancy : Common Mesh Stop - Far Side event=0xf,umask=0x2 01 unc_m2hbm_wpq_flush.ch0 uncore memory WPQ Flush : Channel 0 event=0x42,umask=0x1 01 unc_m2hbm_wpq_flush.ch1 uncore memory WPQ Flush : Channel 1 event=0x42,umask=0x2 01 unc_m2hbm_wpq_no_reg_crd.chn0 uncore memory M2M and iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x37,umask=0x1 01 unc_m2hbm_wpq_no_reg_crd.chn1 uncore memory M2M and iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x37,umask=0x2 01 unc_m2hbm_wpq_no_spec_crd.chn0 uncore memory M2M and iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x38,umask=0x1 01 unc_m2hbm_wpq_no_spec_crd.chn1 uncore memory M2M and iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x38,umask=0x2 01 unc_m2hbm_wr_tracker_inserts.ch0 uncore memory Write Tracker Inserts : Channel 0 event=0x40,umask=0x1 01 unc_m2hbm_wr_tracker_inserts.ch1 uncore memory Write Tracker Inserts : Channel 1 event=0x40,umask=0x2 01 unc_m2hbm_wr_tracker_nonposted_inserts.ch0 uncore memory Write Tracker Non-Posted Inserts : Channel 0 event=0x4d,umask=0x1 01 unc_m2hbm_wr_tracker_nonposted_inserts.ch1 uncore memory Write Tracker Non-Posted Inserts : Channel 1 event=0x4d,umask=0x2 01 unc_m2hbm_wr_tracker_nonposted_occupancy.ch0 uncore memory Write Tracker Non-Posted Occupancy : Channel 0 event=0x4c,umask=0x1 01 unc_m2hbm_wr_tracker_nonposted_occupancy.ch1 uncore memory Write Tracker Non-Posted Occupancy : Channel 1 event=0x4c,umask=0x2 01 unc_m2hbm_wr_tracker_posted_inserts.ch0 uncore memory Write Tracker Posted Inserts : Channel 0 event=0x48,umask=0x1 01 unc_m2hbm_wr_tracker_posted_inserts.ch1 uncore memory Write Tracker Posted Inserts : Channel 1 event=0x48,umask=0x2 01 unc_m2hbm_wr_tracker_posted_occupancy.ch0 uncore memory Write Tracker Posted Occupancy : Channel 0 event=0x47,umask=0x1 01 unc_m2hbm_wr_tracker_posted_occupancy.ch1 uncore memory Write Tracker Posted Occupancy : Channel 1 event=0x47,umask=0x2 01 uncore_mchbm unc_mchbm_act_count.all uncore memory Activate due to read, write, underfill, or bypass event=0x2,umask=0xff 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd uncore memory Activate due to read event=0x2,umask=0x11 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd_pch0 uncore memory HBM Activate Count : Activate due to Read in PCH0 event=0x2,umask=0x1 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd_pch1 uncore memory HBM Activate Count : Activate due to Read in PCH1 event=0x2,umask=0x10 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill uncore memory HBM Activate Count : Underfill Read transaction on Page Empty or Page Miss event=0x2,umask=0x44 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill_pch0 uncore memory HBM Activate Count event=0x2,umask=0x4 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill_pch1 uncore memory HBM Activate Count event=0x2,umask=0x40 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr uncore memory Activate due to write event=0x2,umask=0x22 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr_pch0 uncore memory HBM Activate Count : Activate due to Write in PCH0 event=0x2,umask=0x2 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr_pch1 uncore memory HBM Activate Count : Activate due to Write in PCH1 event=0x2,umask=0x20 01 Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_cas_count.all uncore memory All CAS commands issued event=0x5,umask=0xff 01 unc_mchbm_cas_count.pch0 uncore memory Pseudo Channel 0 event=0x5,umask=0x40 01 HBM RD_CAS and WR_CAS Commands unc_mchbm_cas_count.pch1 uncore memory Pseudo Channel 1 event=0x5,umask=0x80 01 HBM RD_CAS and WR_CAS Commands unc_mchbm_cas_count.rd uncore memory Read CAS commands issued (regular and underfill) event=0x5,umask=0xcf 01 unc_mchbm_cas_count.rd_pre_reg uncore memory Regular read CAS commands with precharge event=0x5,umask=0xc2 01 unc_mchbm_cas_count.rd_pre_underfill uncore memory Underfill read CAS commands with precharge event=0x5,umask=0xc8 01 unc_mchbm_cas_count.rd_reg uncore memory Regular read CAS commands issued (does not include underfills) event=0x5,umask=0xc1 01 unc_mchbm_cas_count.rd_underfill uncore memory Underfill read CAS commands issued event=0x5,umask=0xc4 01 unc_mchbm_cas_count.wr uncore memory Write CAS commands issued event=0x5,umask=0xf0 01 unc_mchbm_cas_count.wr_nonpre uncore memory HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS commands w/o auto-pre event=0x5,umask=0xd0 01 unc_mchbm_cas_count.wr_pre uncore memory Write CAS commands with precharge event=0x5,umask=0xe0 01 unc_mchbm_cas_issued_req_len.pch0 uncore memory Pseudo Channel 0 event=0x6,umask=0x40 01 unc_mchbm_cas_issued_req_len.pch1 uncore memory Pseudo Channel 1 event=0x6,umask=0x80 01 unc_mchbm_cas_issued_req_len.rd_32b uncore memory Read CAS Command in Interleaved Mode (32B) event=0x6,umask=0xc8 01 unc_mchbm_cas_issued_req_len.rd_64b uncore memory Read CAS Command in Regular Mode (64B) in Pseudochannel 0 event=0x6,umask=0xc1 01 unc_mchbm_cas_issued_req_len.rd_ufill_32b uncore memory Underfill Read CAS Command in Interleaved Mode (32B) event=0x6,umask=0xd0 01 unc_mchbm_cas_issued_req_len.rd_ufill_64b uncore memory Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1 event=0x6,umask=0xc2 01 unc_mchbm_cas_issued_req_len.wr_32b uncore memory Write CAS Command in Interleaved Mode (32B) event=0x6,umask=0xe0 01 unc_mchbm_cas_issued_req_len.wr_64b uncore memory Write CAS Command in Regular Mode (64B) in Pseudochannel 0 event=0x6,umask=0xc4 01 unc_mchbm_clockticks uncore memory IMC Clockticks at DCLK frequency event=0x1,umask=0x1 01 unc_mchbm_hbm_preall.pch0 uncore memory HBM Precharge All Commands event=0x44,umask=0x1 01 Counts the number of times that the precharge all command was sent unc_mchbm_hbm_preall.pch1 uncore memory HBM Precharge All Commands event=0x44,umask=0x2 01 Counts the number of times that the precharge all command was sent unc_mchbm_hbm_pre_all uncore memory All Precharge Commands event=0x44,umask=0x3 01 Precharge All Commands: Counts the number of times that the precharge all command was sent unc_mchbm_hclockticks uncore memory IMC Clockticks at HCLK frequency event=0x1 01 unc_mchbm_pre_count.all uncore memory All precharge events event=0x3,umask=0xff 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.pgt uncore memory Precharge from MC page table event=0x3,umask=0x88 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.pgt_pch0 uncore memory HBM Precharge commands. : Precharges from Page Table event=0x3,umask=0x8 01 Counts the number of HBM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY unc_mchbm_pre_count.pgt_pch1 uncore memory HBM Precharge commands event=0x3,umask=0x80 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.rd uncore memory Precharge due to read on page miss event=0x3,umask=0x11 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.rd_pch0 uncore memory HBM Precharge commands. : Precharge due to read event=0x3,umask=0x1 01 Counts the number of HBM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_mchbm_pre_count.rd_pch1 uncore memory HBM Precharge commands event=0x3,umask=0x10 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill uncore memory HBM Precharge commands event=0x3,umask=0x44 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill_pch0 uncore memory HBM Precharge commands event=0x3,umask=0x4 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill_pch1 uncore memory HBM Precharge commands event=0x3,umask=0x40 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.wr uncore memory Precharge due to write on page miss event=0x3,umask=0x22 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.wr_pch0 uncore memory HBM Precharge commands. : Precharge due to write event=0x3,umask=0x2 01 Counts the number of HBM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_mchbm_pre_count.wr_pch1 uncore memory HBM Precharge commands event=0x3,umask=0x20 01 Counts the number of HBM Precharge commands sent on this channel unc_mchbm_rdb_full uncore memory Counts the number of cycles where the read buffer has greater than UMASK elements. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR) event=0x19 01 unc_mchbm_rdb_inserts uncore memory Counts the number of inserts into the read buffer event=0x17,umask=0x3 01 unc_mchbm_rdb_inserts.pch0 uncore memory Read Data Buffer Inserts event=0x17,umask=0x1 01 unc_mchbm_rdb_inserts.pch1 uncore memory Read Data Buffer Inserts event=0x17,umask=0x2 01 unc_mchbm_rdb_occupancy uncore memory Counts the number of elements in the read buffer per cycle event=0x1a 01 unc_mchbm_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations event=0x10,umask=0x1 01 Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_mchbm_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations event=0x10,umask=0x2 01 Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_mchbm_rpq_occupancy_pch0 uncore memory Read Pending Queue Occupancy event=0x80 01 Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_mchbm_rpq_occupancy_pch1 uncore memory Read Pending Queue Occupancy event=0x81 01 Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_mchbm_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x20,umask=0x1 01 Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_mchbm_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x20,umask=0x2 01 Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_mchbm_wpq_occupancy_pch0 uncore memory Write Pending Queue Occupancy event=0x82 01 Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_mchbm_wpq_occupancy_pch1 uncore memory Write Pending Queue Occupancy event=0x83 01 Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_mchbm_wpq_read_hit uncore memory Write Pending Queue CAM Match event=0x23,ch_mask=0x00000000,fc_mask=0x00000000 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_read_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x23,umask=0x1 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_read_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x23,umask=0x2 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit uncore memory Write Pending Queue CAM Match event=0x24,ch_mask=0x00000000,fc_mask=0x00000000 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x24,umask=0x1 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x24,umask=0x2 01 Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_act_count.all uncore memory Activate due to read, write, underfill, or bypass event=0x2,umask=0xff 01 DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory All DRAM CAS commands issued event=0x5,umask=0xff 01 DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.pch0 uncore memory DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 event=0x5,umask=0x40 01 DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.pch1 uncore memory DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 event=0x5,umask=0x80 01 DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd uncore memory All DRAM read CAS commands issued (including underfills) event=0x5,umask=0xcf 01 DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills unc_m_cas_count.rd_pre_reg uncore memory DRAM RD_CAS and WR_CAS Commands event=0x5,umask=0xc2 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_pre_underfill uncore memory DRAM RD_CAS and WR_CAS Commands event=0x5,umask=0xc8 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_reg uncore memory All DRAM read CAS commands issued (does not include underfills) event=0x5,umask=0xc1 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_underfill uncore memory DRAM underfill read CAS commands issued event=0x5,umask=0xc4 01 DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr uncore memory All DRAM write CAS commands issued event=0x5,umask=0xf0 01 DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel unc_m_cas_count.wr_nonpre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre event=0x5,umask=0xd0 01 DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr_pre uncore memory DRAM RD_CAS and WR_CAS Commands event=0x5,umask=0xe0 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_issued_req_len.pch0 uncore memory Pseudo Channel 0 event=0x6,umask=0x40 01 unc_m_cas_issued_req_len.pch1 uncore memory Pseudo Channel 1 event=0x6,umask=0x80 01 unc_m_cas_issued_req_len.rd_32b uncore memory Read CAS Command in Interleaved Mode (32B) event=0x6,umask=0xc8 01 unc_m_cas_issued_req_len.rd_64b uncore memory Read CAS Command in Regular Mode (64B) in Pseudochannel 0 event=0x6,umask=0xc1 01 unc_m_cas_issued_req_len.rd_ufill_32b uncore memory Underfill Read CAS Command in Interleaved Mode (32B) event=0x6,umask=0xd0 01 unc_m_cas_issued_req_len.rd_ufill_64b uncore memory Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1 event=0x6,umask=0xc2 01 unc_m_cas_issued_req_len.wr_32b uncore memory Write CAS Command in Interleaved Mode (32B) event=0x6,umask=0xe0 01 unc_m_cas_issued_req_len.wr_64b uncore memory Write CAS Command in Regular Mode (64B) in Pseudochannel 0 event=0x6,umask=0xc4 01 unc_m_clockticks uncore memory IMC Clockticks at DCLK frequency event=0x1,umask=0x1 01 Number of DRAM DCLK clock cycles while the event is enabled unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=0x44,umask=0x3 01 DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent unc_m_hclockticks uncore memory IMC Clockticks at HCLK frequency event=0x1 01 Number of DRAM HCLK clock cycles while the event is enabled unc_m_pcls.rd uncore memory UNC_M_PCLS.RD event=0xa0,umask=0x5 01 unc_m_pcls.total uncore memory UNC_M_PCLS.TOTAL event=0xa0,umask=0xf 01 unc_m_pcls.wr uncore memory UNC_M_PCLS.WR event=0xa0,umask=0xa 01 unc_m_pmm_rpq_inserts uncore memory PMM Read Pending Queue inserts event=0xe3 01 Counts number of read requests allocated in the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.all_sch0 uncore memory PMM Read Pending Queue occupancy event=0xe0,umask=0x1 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.all_sch1 uncore memory PMM Read Pending Queue occupancy event=0xe0,umask=0x2 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait_sch0 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x10 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait_sch1 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x20 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt_sch0 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x4 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt_sch1 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x8 01 Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_wpq_cycles_ne uncore memory PMM (for IXP) Write Queue Cycles Not Empty event=0xe5 01 unc_m_pmm_wpq_inserts uncore memory PMM Write Pending Queue inserts event=0xe7 01 Counts number of write requests allocated in the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=0x3 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM unc_m_pmm_wpq_occupancy.all_sch0 uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=0x1 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all_sch1 uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=0x2 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.cas uncore memory PMM (for IXP) Write Pending Queue Occupancy event=0xe4,umask=0xc 01 PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM unc_m_pmm_wpq_occupancy.pwr uncore memory PMM (for IXP) Write Pending Queue Occupancy event=0xe4,umask=0x30 01 PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM unc_m_power_channel_ppd uncore memory Channel PPD Cycles event=0x85 01 Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_cke_cycles.low_0 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=0x1 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_1 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=0x2 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_2 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=0x4 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_3 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=0x8 01 CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_crit_throttle_cycles.slot0 uncore memory Throttle Cycles for Rank 0 event=0x86,umask=0x1 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID unc_m_power_crit_throttle_cycles.slot1 uncore memory Throttle Cycles for Rank 0 event=0x86,umask=0x2 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_self_refresh uncore memory Clock-Enabled Self-Refresh event=0x43 01 Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.all uncore memory Precharge due to read, write, underfill, or PGT event=0x3,umask=0xff 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.pgt uncore memory DRAM Precharge commands event=0x3,umask=0x88 01 DRAM Precharge commands. Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.pgt_pch0 uncore memory DRAM Precharge commands. : Precharges from Page Table event=0x3,umask=0x8 01 DRAM Precharge commands. : Precharges from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY unc_m_pre_count.pgt_pch1 uncore memory DRAM Precharge commands event=0x3,umask=0x80 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.rd uncore memory Precharge due to read on page miss event=0x3,umask=0x11 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.rd_pch0 uncore memory DRAM Precharge commands. : Precharge due to read event=0x3,umask=0x1 01 DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.rd_pch1 uncore memory DRAM Precharge commands event=0x3,umask=0x10 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill uncore memory DRAM Precharge commands event=0x3,umask=0x44 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill_pch0 uncore memory DRAM Precharge commands event=0x3,umask=0x4 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill_pch1 uncore memory DRAM Precharge commands event=0x3,umask=0x40 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr uncore memory Precharge due to write on page miss event=0x3,umask=0x22 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr_pch0 uncore memory DRAM Precharge commands. : Precharge due to write event=0x3,umask=0x2 01 DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_m_pre_count.wr_pch1 uncore memory DRAM Precharge commands event=0x3,umask=0x20 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_rdb_full uncore memory Counts the number of cycles where the read buffer has greater than UMASK elements. This includes reads to both DDR and PMEM. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR) event=0x19 01 unc_m_rdb_inserts uncore memory Counts the number of inserts into the read buffer destined for DDR. Does not count reads destined for PMEM event=0x17,umask=0x3 01 unc_m_rdb_inserts.pch0 uncore memory Read Data Buffer Inserts event=0x17,umask=0x1 01 unc_m_rdb_inserts.pch1 uncore memory Read Data Buffer Inserts event=0x17,umask=0x2 01 unc_m_rdb_ne uncore memory Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM event=0x18,umask=0x3 01 unc_m_rdb_ne.pch0 uncore memory Read Data Buffer Not Empty event=0x18,umask=0x1 01 unc_m_rdb_ne.pch1 uncore memory Read Data Buffer Not Empty event=0x18,umask=0x2 01 unc_m_rdb_not_empty uncore memory Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM event=0x18,umask=0x3 01 unc_m_rdb_occupancy uncore memory Counts the number of elements in the read buffer, including reads to both DDR and PMEM event=0x1a 01 unc_m_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations event=0x10,umask=0x1 01 Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_m_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations event=0x10,umask=0x2 01 Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_m_rpq_occupancy_pch0 uncore memory Read Pending Queue Occupancy event=0x80 01 Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_rpq_occupancy_pch1 uncore memory Read Pending Queue Occupancy event=0x81 01 Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_sb_accesses.accepts uncore memory Scoreboard accepts event=0xd2,umask=0x5 01 unc_m_sb_accesses.fm_rd_cmps uncore memory Scoreboard Accesses : Write Accepts event=0xd2,umask=0x40 01 unc_m_sb_accesses.fm_wr_cmps uncore memory Scoreboard Accesses : Write Rejects event=0xd2,umask=0x80 01 unc_m_sb_accesses.nm_rd_cmps uncore memory Scoreboard Accesses : FM read completions event=0xd2,umask=0x10 01 unc_m_sb_accesses.nm_wr_cmps uncore memory Scoreboard Accesses : FM write completions event=0xd2,umask=0x20 01 unc_m_sb_accesses.rd_accepts uncore memory Scoreboard Accesses : Read Accepts event=0xd2,umask=0x1 01 unc_m_sb_accesses.rd_rejects uncore memory Scoreboard Accesses : Read Rejects event=0xd2,umask=0x2 01 unc_m_sb_accesses.rejects uncore memory Scoreboard rejects event=0xd2,umask=0xa 01 unc_m_sb_accesses.wr_accepts uncore memory Scoreboard Accesses : NM read completions event=0xd2,umask=0x4 01 unc_m_sb_accesses.wr_rejects uncore memory Scoreboard Accesses : NM write completions event=0xd2,umask=0x8 01 unc_m_sb_canary.alloc uncore memory : Alloc event=0xd9,umask=0x1 01 unc_m_sb_canary.dealloc uncore memory : Dealloc event=0xd9,umask=0x2 01 unc_m_sb_canary.fm_rd_starved uncore memory : Near Mem Write Starved event=0xd9,umask=0x20 01 unc_m_sb_canary.fm_tgr_wr_starved uncore memory : Far Mem Write Starved event=0xd9,umask=0x80 01 unc_m_sb_canary.fm_wr_starved uncore memory : Far Mem Read Starved event=0xd9,umask=0x40 01 unc_m_sb_canary.nm_rd_starved uncore memory : Valid event=0xd9,umask=0x8 01 unc_m_sb_canary.nm_wr_starved uncore memory : Near Mem Read Starved event=0xd9,umask=0x10 01 unc_m_sb_canary.vld uncore memory : Reject event=0xd9,umask=0x4 01 unc_m_sb_inserts.block_rds uncore memory Scoreboard Inserts : Block region reads event=0xd6,umask=0x10 01 unc_m_sb_inserts.block_wrs uncore memory Scoreboard Inserts : Block region writes event=0xd6,umask=0x20 01 unc_m_sb_inserts.pmm_rds uncore memory Scoreboard Inserts : Persistent Mem reads event=0xd6,umask=0x4 01 unc_m_sb_inserts.pmm_wrs uncore memory Scoreboard Inserts : Persistent Mem writes event=0xd6,umask=0x8 01 unc_m_sb_inserts.rds uncore memory Scoreboard Inserts : Reads event=0xd6,umask=0x1 01 unc_m_sb_inserts.wrs uncore memory Scoreboard Inserts : Writes event=0xd6,umask=0x2 01 unc_m_sb_occupancy.block_rds uncore memory Scoreboard Occupancy : Block region reads event=0xd5,umask=0x20 01 unc_m_sb_occupancy.block_wrs uncore memory Scoreboard Occupancy : Block region writes event=0xd5,umask=0x40 01 unc_m_sb_occupancy.pmm_rds uncore memory Scoreboard Occupancy : Persistent Mem reads event=0xd5,umask=0x4 01 unc_m_sb_occupancy.pmm_wrs uncore memory Scoreboard Occupancy : Persistent Mem writes event=0xd5,umask=0x8 01 unc_m_sb_occupancy.rds uncore memory Scoreboard Occupancy : Reads event=0xd5,umask=0x1 01 unc_m_sb_pref_inserts.all uncore memory Scoreboard Prefetch Inserts : All event=0xda,umask=0x1 01 unc_m_sb_pref_inserts.ddr uncore memory Scoreboard Prefetch Inserts : DDR4 event=0xda,umask=0x2 01 unc_m_sb_pref_inserts.pmm uncore memory Scoreboard Prefetch Inserts : PMM event=0xda,umask=0x4 01 unc_m_sb_pref_occupancy.all uncore memory Scoreboard Prefetch Occupancy : All event=0xdb,umask=0x1 01 unc_m_sb_pref_occupancy.ddr uncore memory Scoreboard Prefetch Occupancy : DDR4 event=0xdb,umask=0x2 01 unc_m_sb_pref_occupancy.pmm uncore memory Scoreboard Prefetch Occupancy : Persistent Mem event=0xdb,ch_mask=0x00000000,fc_mask=0x00000000,umask=0x4 01 unc_m_sb_reject.canary uncore memory Number of Scoreboard Requests Rejected event=0xd4,umask=0x8 01 unc_m_sb_reject.ddr_early_cmp uncore memory Number of Scoreboard Requests Rejected event=0xd4,umask=0x20 01 unc_m_sb_reject.fm_addr_cnflt uncore memory Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict event=0xd4,umask=0x2 01 unc_m_sb_reject.nm_set_cnflt uncore memory Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict event=0xd4,umask=0x1 01 unc_m_sb_reject.patrol_set_cnflt uncore memory Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict event=0xd4,umask=0x4 01 unc_m_sb_strv_alloc.fm_rd uncore memory : Far Mem Read - Set event=0xd7,umask=0x2 01 unc_m_sb_strv_alloc.fm_tgr uncore memory : Near Mem Read - Clear event=0xd7,umask=0x10 01 unc_m_sb_strv_alloc.fm_wr uncore memory : Far Mem Write - Set event=0xd7,umask=0x8 01 unc_m_sb_strv_alloc.nm_rd uncore memory : Near Mem Read - Set event=0xd7,umask=0x1 01 unc_m_sb_strv_alloc.nm_wr uncore memory : Near Mem Write - Set event=0xd7,umask=0x4 01 unc_m_sb_strv_dealloc.fm_rd uncore memory : Far Mem Read - Set event=0xde,umask=0x2 01 unc_m_sb_strv_dealloc.fm_tgr uncore memory : Near Mem Read - Clear event=0xde,umask=0x10 01 unc_m_sb_strv_dealloc.fm_wr uncore memory : Far Mem Write - Set event=0xde,umask=0x8 01 unc_m_sb_strv_dealloc.nm_rd uncore memory : Near Mem Read - Set event=0xde,umask=0x1 01 unc_m_sb_strv_dealloc.nm_wr uncore memory : Near Mem Write - Set event=0xde,umask=0x4 01 unc_m_sb_strv_occ.fm_rd uncore memory : Far Mem Read event=0xd8,umask=0x2 01 unc_m_sb_strv_occ.fm_tgr uncore memory : Near Mem Read - Clear event=0xd8,umask=0x10 01 unc_m_sb_strv_occ.fm_wr uncore memory : Far Mem Write event=0xd8,umask=0x8 01 unc_m_sb_strv_occ.nm_rd uncore memory : Near Mem Read event=0xd8,umask=0x1 01 unc_m_sb_strv_occ.nm_wr uncore memory : Near Mem Write event=0xd8,umask=0x4 01 unc_m_tagchk.hit uncore memory 2LM Tag check hit in near memory cache (DDR4) event=0xd3,umask=0x1 01 unc_m_tagchk.miss_clean uncore memory 2LM Tag check miss, no data at this line event=0xd3,umask=0x2 01 unc_m_tagchk.miss_dirty uncore memory 2LM Tag check miss, existing data may be evicted to PMM event=0xd3,umask=0x4 01 unc_m_tagchk.nm_rd_hit uncore memory 2LM Tag check hit due to memory read event=0xd3,umask=0x8 01 unc_m_tagchk.nm_wr_hit uncore memory 2LM Tag check hit due to memory write event=0xd3,umask=0x10 01 unc_m_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x20,umask=0x1 01 Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x20,umask=0x2 01 Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wpq_occupancy_pch0 uncore memory Write Pending Queue Occupancy event=0x82 01 Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_m_wpq_occupancy_pch1 uncore memory Write Pending Queue Occupancy event=0x83 01 Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_m_wpq_read_hit uncore memory Write Pending Queue CAM Match event=0x23,ch_mask=0x00000000,fc_mask=0x00000000 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit uncore memory Write Pending Queue CAM Match event=0x24,ch_mask=0x00000000,fc_mask=0x00000000 01 Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_p_clockticks uncore power PCU PCLK Clockticks event=0x1 01 Number of PCU PCLK Clock cycles while the event is enabled unc_p_fivr_ps_ps0_cycles uncore power Phase Shed 0 Cycles event=0x75 01 Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0 unc_p_fivr_ps_ps1_cycles uncore power Phase Shed 1 Cycles event=0x76 01 Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1 unc_p_fivr_ps_ps2_cycles uncore power Phase Shed 2 Cycles event=0x77 01 Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2 unc_p_fivr_ps_ps3_cycles uncore power Phase Shed 3 Cycles event=0x78 01 Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3 unc_p_freq_clip_avx256 uncore power AVX256 Frequency Clipping event=0x49 01 unc_p_freq_clip_avx512 uncore power AVX512 Frequency Clipping event=0x4a 01 unc_p_freq_max_limit_thermal_cycles uncore power Thermal Strongest Upper Limit Cycles event=0x4 01 Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring unc_p_freq_max_power_cycles uncore power Power Strongest Upper Limit Cycles event=0x5 01 Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x73 01 IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x74 01 Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_memory_phase_shedding_cycles uncore power Memory Phase Shedding Cycles event=0x2f 01 Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency unc_p_pkg_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a 01 Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c2e_cycles uncore power Package C State Residency - C2E event=0x2b 01 Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times unc_p_pkg_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d 01 Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times unc_p_pmax_throttled_cycles uncore power UNC_P_PMAX_THROTTLED_CYCLES event=0x6 01 unc_p_power_state_occupancy_cores_c0 uncore power Number of cores in C0 event=0x35 01 Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy_cores_c3 uncore power Number of cores in C3 event=0x36 01 Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy_cores_c6 uncore power Number of cores in C6 event=0x37 01 Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_prochot_external_cycles uncore power External Prochot event=0xa 01 External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip unc_p_prochot_internal_cycles uncore power Internal Prochot event=0x9 01 Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x72 01 Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores core_reject_l2q.all cache Requests rejected by the L2Q event=0x31,period=200003 00 Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.dirty_eviction cache L1 Cache evictions for dirty data event=0x51,period=200003,umask=0x1 00 Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback fetch_stall.icache_fill_pending_cycles cache Cycles code-fetch stalled due to an outstanding ICache miss event=0x86,period=200003,umask=0x2 00 Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy l2_reject_xq.all cache Requests rejected by the XQ event=0x30,period=200003 00 Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims longest_lat_cache.miss cache L2 cache request misses event=0x2e,period=200003,umask=0x41 00 Counts memory requests originating from the core that miss in the L2 cache longest_lat_cache.reference cache L2 cache requests event=0x2e,period=200003,umask=0x4f 00 Counts memory requests originating from the core that reference a cache line in the L2 cache mem_load_uops_retired.dram_hit cache Loads retired that came from DRAM (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x80 00 Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response Supports address when precise (Must be precise) mem_load_uops_retired.hitm cache Memory uop retired where cross core or cross module HITM occurred (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x20 00 Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks Supports address when precise (Must be precise) mem_load_uops_retired.l1_hit cache Load uops retired that hit L1 data cache (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x1 00 Counts load uops retired that hit the L1 data cache Supports address when precise (Must be precise) mem_load_uops_retired.l1_miss cache Load uops retired that missed L1 data cache (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x8 00 Counts load uops retired that miss the L1 data cache Supports address when precise (Must be precise) mem_load_uops_retired.l2_hit cache Load uops retired that hit L2 (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x2 00 Counts load uops retired that hit in the L2 cache Supports address when precise (Must be precise) mem_load_uops_retired.l2_miss cache Load uops retired that missed L2 (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x10 00 Counts load uops retired that miss in the L2 cache Supports address when precise (Must be precise) mem_load_uops_retired.wcb_hit cache Loads retired that hit WCB (Precise event capable) Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x40 00 Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs Supports address when precise (Must be precise) mem_uops_retired.all cache Memory uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x83 00 Counts the number of memory uops retired that is either a loads or a store or both Supports address when precise (Must be precise) mem_uops_retired.all_loads cache Load uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x81 00 Counts the number of load uops retired Supports address when precise (Must be precise) mem_uops_retired.all_stores cache Store uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x82 00 Counts the number of store uops retired Supports address when precise (Must be precise) mem_uops_retired.lock_loads cache Locked load uops retired (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x21 00 Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks Supports address when precise (Must be precise) mem_uops_retired.split cache Memory uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x43 00 Counts memory uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) mem_uops_retired.split_loads cache Load uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x41 00 Counts load uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) mem_uops_retired.split_stores cache Stores uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x42 00 Counts store uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) offcore_response cache Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1 00 offcore_response.any_data_rd.l2_hit cache Counts data reads (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043091 00 Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.any cache Counts data reads (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600003091 00 Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003091 00 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400003091 00 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003091 00 Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit cache Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043010 00 Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.any cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600003010 00 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003010 00 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400003010 00 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003010 00 Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000432b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.any cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x36000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x10000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hit_other_core_no_fwd cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x04000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x02000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.any_response cache Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018000 00 Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit cache Counts requests to the uncore subsystem that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000048000 00 Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core cache Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000008000 00 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hit_other_core_no_fwd cache Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400008000 00 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed cache Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200008000 00 Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_hit cache Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.any cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.any_response cache Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010400 00 Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_hit cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.any cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hitm_other_core cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hit_other_core_no_fwd cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_hit cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.any cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_hit cache Counts demand cacheable data reads of full cache lines that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040001 00 Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.any cache Counts demand cacheable data reads of full cache lines that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000001 00 Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000001 00 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd cache Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000001 00 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000001 00 Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000001 00 Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.any cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.outstanding cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_hit cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.any cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwd cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_reads.l2_miss.any cache Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000080 00 Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_hit cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000044000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.any cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hitm_other_core cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwd cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200004000 00 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_writes.l2_miss.any cache Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000100 00 Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit cache Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000042000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.any cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_hit cache Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.any cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.any cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit cache Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000044800 00 Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.any cache Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600004800 00 Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_hit cache Counts data cache lines requests by software prefetch instructions that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000041000 00 Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.any cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600001000 00 Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hitm_other_core cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000001000 00 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwd cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400001000 00 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200001000 00 Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) cycles_div_busy.fpdiv floating point Cycles the FP divide unit is busy event=0xcd,period=200003,umask=0x2 00 Counts core cycles the floating point divide unit is busy machine_clears.fp_assist floating point Machine clears due to FP assists event=0xc3,period=200003,umask=0x4 00 Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result uops_retired.fpdiv floating point Floating point divide uops retired. (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x8 00 Counts the number of floating point divide uops retired (Must be precise) baclears.all frontend BACLEARs asserted for any branch type event=0xe6,period=200003,umask=0x1 00 Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns baclears.cond frontend BACLEARs asserted for conditional branch event=0xe6,period=200003,umask=0x10 00 Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches baclears.return frontend BACLEARs asserted for return branch event=0xe6,period=200003,umask=0x8 00 Counts BACLEARS on return instructions decode_restriction.predecode_wrong frontend Decode restrictions due to predicting wrong instruction length event=0xe9,period=200003,umask=0x1 00 Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect icache.accesses frontend References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=0x3 00 Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line. This event counts differently than Intel processors based on Silvermont microarchitecture icache.hit frontend References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=0x1 00 Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture icache.misses frontend References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=0x2 00 Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture ms_decoded.ms_entry frontend MS decode starts event=0xe7,period=200003,umask=0x1 00 Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear machine_clears.memory_ordering memory Machine clears due to memory ordering issue event=0xc3,period=200003,umask=0x2 00 Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data misalign_mem_ref.load_page_split memory Load uops that split a page (Precise event capable) (Must be precise) event=0x13,period=200003,umask=0x2 00 Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise) misalign_mem_ref.store_page_split memory Store uops that split a page (Precise event capable) (Must be precise) event=0x13,period=200003,umask=0x4 00 Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise) fetch_stall.all other Cycles code-fetch stalled due to any reason event=0x86,period=200003 00 Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events fetch_stall.itlb_fill_pending_cycles other Cycles code-fetch stalled due to an outstanding ITLB miss event=0x86,period=200003,umask=0x1 00 Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation hw_interrupts.masked other Cycles hardware interrupts are masked event=0xcb,period=200003,umask=0x2 00 Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not hw_interrupts.pending_and_masked other Cycles pending interrupts are masked event=0xcb,period=200003,umask=0x4 00 Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0) hw_interrupts.received other Hardware interrupts received event=0xcb,period=203,umask=0x1 00 Counts hardware interrupts received by the processor br_inst_retired.all_branches pipeline Retired branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003 00 Counts branch instructions retired for all branch types. This is an architectural performance event (Must be precise) br_inst_retired.all_taken_branches pipeline Retired taken branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0x80 00 Counts the number of taken branch instructions retired (Must be precise) br_inst_retired.call pipeline Retired near call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xf9 00 Counts near CALL branch instructions retired (Must be precise) br_inst_retired.far_branch pipeline Retired far branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xbf 00 Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return (Must be precise) br_inst_retired.ind_call pipeline Retired near indirect call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfb 00 Counts near indirect CALL branch instructions retired (Must be precise) br_inst_retired.jcc pipeline Retired conditional branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0x7e 00 Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise) br_inst_retired.non_return_ind pipeline Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xeb 00 Counts near indirect call or near indirect jmp branch instructions retired (Must be precise) br_inst_retired.rel_call pipeline Retired near relative call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfd 00 Counts near relative CALL branch instructions retired (Must be precise) br_inst_retired.return pipeline Retired near return instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xf7 00 Counts near return branch instructions retired (Must be precise) br_inst_retired.taken_jcc pipeline Retired conditional branch instructions that were taken (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfe 00 Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise) br_misp_retired.all_branches pipeline Retired mispredicted branch instructions (Precise event capable) (Must be precise) event=0xc5,period=200003 00 Counts mispredicted branch instructions retired including all branch types (Must be precise) br_misp_retired.ind_call pipeline Retired mispredicted near indirect call instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xfb 00 Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.jcc pipeline Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0x7e 00 Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise) br_misp_retired.non_return_ind pipeline Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xeb 00 Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.return pipeline Retired mispredicted near return instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xf7 00 Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise) br_misp_retired.taken_jcc pipeline Retired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xfe 00 Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise) cpu_clk_unhalted.core pipeline Core cycles when core is not halted (Fixed event) event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000003 00 Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 Reference cycles when core is not halted. This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc pipeline Reference cycles when core is not halted (Fixed event) event=0,period=2000003,umask=0x3 00 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event cycles_div_busy.all pipeline Cycles a divider is busy event=0xcd,period=2000003 00 Counts core cycles if either divide unit is busy cycles_div_busy.idiv pipeline Cycles the integer divide unit is busy event=0xcd,period=200003,umask=0x1 00 Counts core cycles the integer divide unit is busy inst_retired.any pipeline Instructions retired (Fixed event) event=0xc0,period=2000003 00 Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event inst_retired.any_p pipeline Instructions retired (Precise event capable) (Must be precise) event=0xc0,period=2000003 00 Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise) issue_slots_not_consumed.any pipeline Unfilled issue slots per cycle event=0xca,period=200003 00 Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY) issue_slots_not_consumed.recovery pipeline Unfilled issue slots per cycle to recover event=0xca,period=200003,umask=0x2 00 Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue issue_slots_not_consumed.resource_full pipeline Unfilled issue slots per cycle because of a full resource in the backend event=0xca,period=200003,umask=0x1 00 Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count ld_blocks.4k_alias pipeline Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise) event=0x3,period=200003,umask=0x4 00 Counts loads that block because their address modulo 4K matches a pending store (Must be precise) ld_blocks.all_block pipeline Loads blocked (Precise event capable) (Must be precise) event=0x3,period=200003,umask=0x10 00 Counts anytime a load that retires is blocked for any reason (Must be precise) ld_blocks.data_unknown pipeline Loads blocked due to store data not ready (Precise event capable) (Must be precise) event=0x3,period=200003,umask=0x1 00 Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available (Must be precise) ld_blocks.store_forward pipeline Loads blocked due to store forward restriction (Precise event capable) (Must be precise) event=0x3,period=200003,umask=0x2 00 Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise) ld_blocks.utlb_miss pipeline Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise) event=0x3,period=200003,umask=0x8 00 Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise) machine_clears.all pipeline All machine clears event=0xc3,period=200003 00 Counts machine clears for any reason machine_clears.disambiguation pipeline Machine clears due to memory disambiguation event=0xc3,period=200003,umask=0x8 00 Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200003,umask=0x1 00 Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors uops_issued.any pipeline Uops issued to the back end per cycle event=0xe,period=200003 00 Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear uops_not_delivered.any pipeline Uops requested but not-delivered to the back-end per cycle event=0x9c,period=200003 00 This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue uops_retired.any pipeline Uops retired (Precise event capable) (Must be precise) event=0xc2,period=2000003 00 Counts uops which retired (Must be precise) uops_retired.idiv pipeline Integer divide uops retired. (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x10 00 Counts the number of integer divide uops retired (Must be precise) uops_retired.ms pipeline MS uops retired (Precise event capable) (Must be precise) event=0xc2,period=2000003,umask=0x1 00 Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise) itlb.miss virtual memory ITLB misses event=0x81,period=200003,umask=0x4 00 Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB mem_uops_retired.dtlb_miss virtual memory Memory uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x13 00 Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_loads virtual memory Load uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x11 00 Counts load uops retired that caused a DTLB miss Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_stores virtual memory Store uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x12 00 Counts store uops retired that caused a DTLB miss Supports address when precise (Must be precise) page_walks.cycles virtual memory Duration of page-walks in cycles event=0x5,period=200003,umask=0x3 00 Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch page_walks.d_side_cycles virtual memory Duration of D-side page-walks in cycles event=0x5,period=200003,umask=0x1 00 Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress page_walks.i_side_cycles virtual memory Duration of I-side pagewalks in cycles event=0x5,period=200003,umask=0x2 00 Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress core_reject_l2q.all cache Requests rejected by the L2Q event=0x31,period=200003 00 Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.replacement cache L1 Cache evictions for dirty data event=0x51,period=200003,umask=0x1 00 Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback offcore_response.any_data_rd.any_response cache Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013091 00 Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_hit cache Counts data reads (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043091 00 Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003091 00 Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003091 00 Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.outstanding cache Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000003091 00 Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.any_response cache Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013010 00 Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit cache Counts data reads generated by L1 or L2 prefetchers hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043010 00 Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core cache Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003010 00 Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003010 00 Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.outstanding cache Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000003010 00 Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.any_response cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000132b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000432b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x10000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x02000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.outstanding cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x40000032b7 00 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.any_response cache Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018000 00 Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit cache Counts requests to the uncore subsystem hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000048000 00 Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core cache Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000008000 00 Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed cache Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200008000 00 Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.outstanding cache Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000008000 00 Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.any_response cache Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010022 00 Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_hit cache Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040022 00 Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.outstanding cache Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000022 00 Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.any_response cache Counts bus lock and split lock requests have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010400 00 Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_hit cache Counts bus lock and split lock requests hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040400 00 Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.hitm_other_core cache Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000400 00 Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_needed cache Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000400 00 Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.outstanding cache Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000400 00 Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.any_response cache Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_hit cache Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hitm_other_core cache Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed cache Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.outstanding cache Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000008 00 Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.any_response cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_hit cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hitm_other_core cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000004 00 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.any_response cache Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010001 00 Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_hit cache Counts demand cacheable data reads of full cache lines hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040001 00 Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000001 00 Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000001 00 Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000001 00 Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.any_response cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.outstanding cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000002 00 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.any_response cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_hit cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.outstanding cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000800 00 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.any_response cache Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000012000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit cache Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000042000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.outstanding cache Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000002000 00 Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.any_response cache Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_hit cache Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.outstanding cache Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000010 00 Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.any_response cache Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit cache Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.outstanding cache Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000020 00 Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.any_response cache Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000014800 00 Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit cache Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000044800 00 Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.hitm_other_core cache Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000004800 00 Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200004800 00 Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.outstanding cache Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000004800 00 Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.any_response cache Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000011000 00 Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_hit cache Counts data cache lines requests by software prefetch instructions hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000041000 00 Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hitm_other_core cache Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000001000 00 Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200001000 00 Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.outstanding cache Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000001000 00 Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) machine_clears.fp_assist floating point Machine clears due to FP assists event=0xc3,period=20003,umask=0x4 00 Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result uops_retired.fpdiv floating point Floating point divide uops retired (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x8 00 Counts the number of floating point divide uops retired (Must be precise) machine_clears.memory_ordering memory Machine clears due to memory ordering issue event=0xc3,period=20003,umask=0x2 00 Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data fetch_stall.itlb_fill_pending_cycles other Cycles the code-fetch stalls and an ITLB miss is outstanding event=0x86,period=200003,umask=0x1 00 Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation br_misp_retired.non_return_ind pipeline Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xeb 00 Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter inst_retired.any pipeline Instructions retired (Fixed event) (Must be precise) event=0xc0,period=2000003 00 Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event (Must be precise) inst_retired.prec_dist pipeline Instructions retired - using Reduced Skid PEBS feature (Must be precise) event=0xc0,period=2000003 00 Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise) machine_clears.all pipeline All machine clears event=0xc3,period=20003 00 Counts machine clears for any reason machine_clears.disambiguation pipeline Machine clears due to memory disambiguation event=0xc3,period=20003,umask=0x8 00 Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address machine_clears.page_fault pipeline Machines clear due to a page fault event=0xc3,period=20003,umask=0x20 00 Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=20003,umask=0x1 00 Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors uops_retired.idiv pipeline Integer divide uops retired (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x10 00 Counts the number of integer divide uops retired (Must be precise) dtlb_load_misses.walk_completed_1gb virtual memory Page walk completed due to a demand load to a 1GB page event=0x8,period=200003,umask=0x8 00 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand load to a 2M or 4M page event=0x8,period=200003,umask=0x4 00 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault dtlb_load_misses.walk_completed_4k virtual memory Page walk completed due to a demand load to a 4K page event=0x8,period=200003,umask=0x2 00 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault dtlb_load_misses.walk_pending virtual memory Page walks outstanding due to a demand load every cycle event=0x8,period=200003,umask=0x10 00 Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks dtlb_store_misses.walk_completed_1gb virtual memory Page walk completed due to a demand data store to a 1GB page event=0x49,period=2000003,umask=0x8 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data store to a 2M or 4M page event=0x49,period=2000003,umask=0x4 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault dtlb_store_misses.walk_completed_4k virtual memory Page walk completed due to a demand data store to a 4K page event=0x49,period=2000003,umask=0x2 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault dtlb_store_misses.walk_pending virtual memory Page walks outstanding due to a demand data store every cycle event=0x49,period=200003,umask=0x10 00 Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks ept.walk_pending virtual memory Page walks outstanding due to walking the EPT every cycle event=0x4f,period=200003,umask=0x10 00 Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks itlb_misses.walk_completed_1gb virtual memory Page walk completed due to an instruction fetch in a 1GB page event=0x85,period=2000003,umask=0x8 00 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault itlb_misses.walk_completed_2m_4m virtual memory Page walk completed due to an instruction fetch in a 2M or 4M page event=0x85,period=2000003,umask=0x4 00 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault itlb_misses.walk_completed_4k virtual memory Page walk completed due to an instruction fetch in a 4K page event=0x85,period=2000003,umask=0x2 00 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault itlb_misses.walk_pending virtual memory Page walks outstanding due to an instruction fetch every cycle event=0x85,period=200003,umask=0x10 00 Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks tlb_flushes.stlb_any virtual memory STLB flushes event=0xbd,period=20003,umask=0x20 00 Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3 mem_uops_retired.all_loads cache Counts the number of load ops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x81 00 mem_uops_retired.all_stores cache Counts the number of store ops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x82 00 mem_uops_retired.load_latency_gt_1024 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x400 00 mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x80 00 mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x10 00 mem_uops_retired.load_latency_gt_2048 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x800 00 mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x100 00 mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x20 00 mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x4 00 mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x200 00 mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x40 00 mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x5,ldlat=0x8 00 mem_uops_retired.store_latency cache Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES Supports address when precise (Must be precise) event=0xd0,period=1000003,umask=0x6 00 icache.accesses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump event=0x80,period=200003,umask=0x3 00 icache.misses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - event=0x80,period=200003,umask=0x2 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002 00 cpu_clk_unhalted.core pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P] event=0x3c,period=2000003 00 cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=2000003,umask=0x3 00 cpu_clk_unhalted.thread pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P] event=0x3c,period=2000003 00 inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired (Precise event) event=0xc0,period=2000003 00 inst_retired.any_p pipeline Counts the number of instructions retired (Precise event) event=0xc0,period=2000003 00 topdown_bad_speculation.all pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003 00 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_be_bound.all pipeline Counts the number of retirement slots not consumed due to backend stalls event=0x74,period=1000003 00 topdown_fe_bound.all pipeline Counts the number of retirement slots not consumed due to front end stalls event=0x71,period=1000003 00 topdown_retiring.all pipeline Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL (Precise event) event=0x72,period=1000003 00 dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses to a 1G page event=0x8,period=1000003,umask=0xe 00 dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x49,period=1000003,umask=0xe 00 idq_bubbles.core frontend This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations event=0x9c,period=1000003,umask=0x1 00 This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method topdown.backend_bound_slots pipeline This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions event=0xa4,period=10000003,umask=0x2 00 This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method uops_retired.slots pipeline This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric event=0xc2,period=2000003,umask=0x2 00 This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=0x1 00 This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache l1d_pend_miss.pending cache L1D miss outstanding duration in cycles event=0x48,period=2000003,umask=0x1 00 Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=0x1 00 l1d_pend_miss.request_fb_full cache Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e event=0x48,period=2000003,umask=0x2 00 l2_demand_rqsts.wb_hit cache Not rejected writebacks that hit L2 cache event=0x27,period=200003,umask=0x50 00 Not rejected writebacks that hit L2 cache l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=0x7 00 This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=0x4 00 L2 cache lines in E state filling L2 l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=0x1 00 L2 cache lines in I state filling L2 l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=0x2 00 L2 cache lines in S state filling L2 l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=0x5 00 Clean L2 cache lines evicted by demand l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=0x6 00 Dirty L2 cache lines evicted by demand l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4 00 Counts all L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xe1 00 Counts any demand and L1 HW prefetch data load requests to L2 Spec update: HSD78, HSM80 l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x27 00 Demand requests that miss L2 cache Spec update: HSD78, HSM80 l2_rqsts.all_demand_references cache Demand requests to L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xe7 00 Demand requests to L2 cache Spec update: HSD78, HSM80 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xf8 00 Counts all L2 HW prefetcher requests l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2 00 Counts all L2 store RFO requests l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4 00 Number of instruction fetches that hit the L2 cache l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24 00 Number of instruction fetches that missed the L2 cache l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xc1 00 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache Spec update: HSD78, HSM80 l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x21 00 Demand data read requests that missed L2, no rejects Spec update: HSD78, HSM80 l2_rqsts.l2_pf_hit cache L2 prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xd0 00 Counts all L2 HW prefetcher requests that hit L2 l2_rqsts.l2_pf_miss cache L2 prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x30 00 Counts all L2 HW prefetcher requests that missed L2 l2_rqsts.miss cache All requests that miss L2 cache Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x3f 00 All requests that missed L2 Spec update: HSD78, HSM80 l2_rqsts.references cache All L2 requests Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xff 00 All requests to L2 cache Spec update: HSD78, HSM80 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2 00 Counts the number of store RFO requests that hit the L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22 00 Counts the number of store RFO requests that miss the L2 cache l2_trans.all_pf cache L2 or L3 HW prefetches that access L2 cache event=0xf0,period=200003,umask=0x8 00 Any MLC or L3 HW prefetch accessing L2, including rejects l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80 00 Transactions accessing L2 pipe l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=0x4 00 L2 cache accesses when fetching instructions l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=0x1 00 Demand data read requests that access L2 cache l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10 00 L1D writebacks that access L2 cache l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20 00 L2 fill requests that access L2 cache l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 L2 writebacks that access L2 cache l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=0x2 00 RFO requests that access L2 cache lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=0x2 00 Cycles in which the L1D is locked longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 event=0x2e,period=100003,umask=0x41 00 This event counts each cache miss condition for references to the last level cache longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 event=0x2e,period=100003,umask=0x4f 00 This event counts requests originating from the core that reference a cache line in the last level cache mem_load_uops_l3_hit_retired.xsnp_hit cache Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=0x2 00 mem_load_uops_l3_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=0x4 00 mem_load_uops_l3_hit_retired.xsnp_miss cache Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=0x1 00 mem_load_uops_l3_hit_retired.xsnp_none cache Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=100003,umask=0x8 00 mem_load_uops_l3_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) event=0xd3,period=100003,umask=0x1 00 This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise. Spec update: HSM30 (Precise event) event=0xd1,period=100003,umask=0x40 00 mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd1,period=2000003,umask=0x1 00 mem_load_uops_retired.l1_miss cache Retired load uops misses in L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) event=0xd1,period=100003,umask=0x8 00 Retired load uops missed L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) event=0xd1,period=100003,umask=0x2 00 mem_load_uops_retired.l2_miss cache Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd1,period=50021,umask=0x10 00 Retired load uops missed L2. Unknown data source excluded Supports address when precise. Spec update: HSD29, HSM30 (Precise event) mem_load_uops_retired.l3_hit cache Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd1,period=50021,umask=0x4 00 Retired load uops with L3 cache hits as data sources Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) mem_load_uops_retired.l3_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd1,period=100003,umask=0x20 00 Retired load uops missed L3. Excludes unknown data source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) mem_uops_retired.all_loads cache Retired load uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=2000003,umask=0x81 00 Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW Supports address when precise. Spec update: HSD29, HSM30 (Precise event) mem_uops_retired.all_stores cache Retired store uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=2000003,umask=0x82 00 Counts all retired store uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x41 00 mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x42 00 mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=0x8 00 Data read requests sent to uncore (demand and prefetch) offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0xb0,period=100003,umask=0x2 00 Demand code read requests sent to uncore offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore Spec update: HSD78, HSM80 event=0xb0,period=100003,umask=0x1 00 Demand data read requests sent to uncore Spec update: HSD78, HSM80 offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=0x4 00 Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=0x1 00 offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=0x8 00 Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 event=0x60,cmask=1,period=2000003,umask=0x8 00 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,cmask=1,period=2000003,umask=0x1 00 offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61, HSM63 event=0x60,cmask=1,period=2000003,umask=0x4 00 offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=0x2 00 Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,period=2000003,umask=0x1 00 Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,cmask=6,period=2000003,umask=0x1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=0x4 00 Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0244 00 offcore_response.all_data_rd.l3_hit.hitm_other_core cache Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0091 00 offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0091 00 offcore_response.all_reads.l3_hit.hitm_other_core cache hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C07F7 00 offcore_response.all_reads.l3_hit.hit_other_core_no_fwd cache hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C07F7 00 offcore_response.all_requests.l3_hit.any_response cache Counts all requests hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8FFF 00 offcore_response.all_rfo.l3_hit.hitm_other_core cache Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122 00 offcore_response.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 00 offcore_response.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 offcore_response.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 00 offcore_response.pf_l2_code_rd.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0040 00 offcore_response.pf_l2_data_rd.l3_hit.any_response cache Counts prefetch (that bring data to L2) data reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_rfo.l3_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_l3_code_rd.l3_hit.any_response cache Counts prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0200 00 offcore_response.pf_l3_data_rd.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080 00 offcore_response.pf_l3_rfo.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100 00 sq_misc.split_lock cache Split locks in SQ event=0xf4,period=100003,umask=0x10 00 avx_insts.all floating point Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX event=0xc6,period=2000003,umask=0x7 00 Note that a whole rep string only counts AVX_INST.ALL once fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 Cycles with any input/output SSE* or FP assists fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10 00 Number of SIMD FP assists due to input values fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=0x8 00 Number of SIMD FP assists due to output values fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=0x4 00 Number of X87 FP assists due to input values fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=0x2 00 Number of X87 FP assists due to output values move_elimination.simd_eliminated floating point Number of SIMD Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=0x2 00 Number of SIMD move elimination candidate uops that were eliminated move_elimination.simd_not_eliminated floating point Number of SIMD Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=0x8 00 Number of SIMD move elimination candidate uops that were not eliminated other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: HSD56, HSM57 event=0xc1,period=100003,umask=0x8 00 other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable Spec update: HSD56, HSM57 event=0xc1,period=100003,umask=0x10 00 baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=0x1f 00 Number of front end re-steers due to BPU misprediction dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=0x2 00 icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=0x1 00 icache.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=0x4 00 icache.ifetch_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=0x4 00 icache.misses frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses event=0x80,period=200003,umask=0x2 00 This event counts Instruction Cache (ICACHE) misses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18 00 Counts cycles DSB is delivered four uops. Set Cmask = 4 idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18 00 Counts cycles DSB is delivered at least one uops. Set Cmask = 1 idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 Counts cycles MITE is delivered four uops. Set Cmask = 4 idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 Counts cycles MITE is delivered at least one uop. Set Cmask = 1 idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=0x8 00 idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=0x8 00 Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles idq.empty frontend Instruction Decode Queue (IDQ) empty cycles Spec update: HSD135 event=0x79,period=2000003,umask=0x2 00 Counts cycles the IDQ is empty Spec update: HSD135 idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c 00 Number of uops delivered to IDQ from any path idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=0x4 00 idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x4 00 Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10 00 idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10 00 Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled Spec update: HSD135 event=0x9c,period=2000003,umask=0x1 00 This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis Spec update: HSD135 idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 event=0x9c,cmask=4,period=2000003,umask=0x1 00 This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis Spec update: HSD135 idq_uops_not_delivered.cycles_fe_was_ok frontend Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE Spec update: HSD135 event=0x9c,cmask=1,inv=1,period=2000003,umask=0x1 00 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 event=0x9c,cmask=3,period=2000003,umask=0x1 00 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end Spec update: HSD135 event=0x9c,cmask=2,period=2000003,umask=0x1 00 idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end Spec update: HSD135 event=0x9c,cmask=1,period=2000003,umask=0x1 00 hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc8,period=2000003,umask=0x4 00 hle_retired.aborted_misc1 memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=0x8 00 hle_retired.aborted_misc2 memory Number of times an HLE execution aborted due to uncommon conditions event=0xc8,period=2000003,umask=0x10 00 hle_retired.aborted_misc3 memory Number of times an HLE execution aborted due to HLE-unfriendly instructions event=0xc8,period=2000003,umask=0x20 00 hle_retired.aborted_misc4 memory Number of times an HLE execution aborted due to incompatible memory type Spec update: HSD65 event=0xc8,period=2000003,umask=0x40 00 hle_retired.aborted_misc5 memory Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) event=0xc8,period=2000003,umask=0x80 00 Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=2000003,umask=0x2 00 hle_retired.start memory Number of times an HLE execution started event=0xc8,period=2000003,umask=0x1 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=0x2 00 This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently mem_trans_retired.load_latency_gt_128 memory Randomly selected loads with latency value being above 128 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=1009,umask=0x1,ldlat=0x80 00 mem_trans_retired.load_latency_gt_16 memory Randomly selected loads with latency value being above 16 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=20011,umask=0x1,ldlat=0x10 00 mem_trans_retired.load_latency_gt_256 memory Randomly selected loads with latency value being above 256 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=503,umask=0x1,ldlat=0x100 00 mem_trans_retired.load_latency_gt_32 memory Randomly selected loads with latency value being above 32 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=100003,umask=0x1,ldlat=0x20 00 mem_trans_retired.load_latency_gt_4 memory Randomly selected loads with latency value being above 4 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=100003,umask=0x1,ldlat=0x4 00 mem_trans_retired.load_latency_gt_512 memory Randomly selected loads with latency value being above 512 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=101,umask=0x1,ldlat=0x200 00 mem_trans_retired.load_latency_gt_64 memory Randomly selected loads with latency value being above 64 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=2003,umask=0x1,ldlat=0x40 00 mem_trans_retired.load_latency_gt_8 memory Randomly selected loads with latency value being above 8 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=50021,umask=0x1,ldlat=0x8 00 misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=0x5,period=2000003,umask=0x1 00 Speculative cache-line split load uops dispatched to L1D misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=0x5,period=2000003,umask=0x2 00 Speculative cache-line split store-address uops dispatched to L1D offcore_response.all_code_rd.l3_miss.any_response memory Counts all demand & prefetch code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00244 00 offcore_response.all_code_rd.l3_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400244 00 offcore_response.all_data_rd.l3_miss.any_response memory Counts all demand & prefetch data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00091 00 offcore_response.all_data_rd.l3_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400091 00 offcore_response.all_reads.l3_miss.any_response memory miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC007F7 00 offcore_response.all_reads.l3_miss.local_dram memory miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004007F7 00 offcore_response.all_requests.l3_miss.any_response memory Counts all requests miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC08FFF 00 offcore_response.all_rfo.l3_miss.any_response memory Counts all demand & prefetch RFOs miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00122 00 offcore_response.all_rfo.l3_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400122 00 offcore_response.demand_code_rd.l3_miss.any_response memory Counts all demand code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00004 00 offcore_response.demand_code_rd.l3_miss.local_dram memory Counts all demand code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400004 00 offcore_response.demand_data_rd.l3_miss.any_response memory Counts demand data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00001 00 offcore_response.demand_data_rd.l3_miss.local_dram memory Counts demand data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400001 00 offcore_response.demand_rfo.l3_miss.any_response memory Counts all demand data writes (RFOs) miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00002 00 offcore_response.demand_rfo.l3_miss.local_dram memory Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400002 00 offcore_response.pf_l2_code_rd.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00040 00 offcore_response.pf_l2_data_rd.l3_miss.any_response memory Counts prefetch (that bring data to L2) data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00010 00 offcore_response.pf_l2_rfo.l3_miss.any_response memory Counts all prefetch (that bring data to L2) RFOs miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00020 00 offcore_response.pf_l3_code_rd.l3_miss.any_response memory Counts prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00200 00 offcore_response.pf_l3_data_rd.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00080 00 offcore_response.pf_l3_rfo.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00100 00 rtm_retired.aborted memory Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc9,period=2000003,umask=0x4 00 rtm_retired.aborted_misc1 memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x8 00 Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) rtm_retired.aborted_misc2 memory Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x10 00 rtm_retired.aborted_misc3 memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20 00 rtm_retired.aborted_misc4 memory Number of times an RTM execution aborted due to incompatible memory type Spec update: HSD65 event=0xc9,period=2000003,umask=0x40 00 rtm_retired.aborted_misc5 memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80 00 Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=2000003,umask=0x2 00 rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=2000003,umask=0x1 00 tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=0x2 00 tx_exec.misc3 memory Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=2000003,umask=0x4 00 tx_exec.misc4 memory Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region event=0x5d,period=2000003,umask=0x8 00 tx_mem.abort_capacity_write memory Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes event=0x54,period=2000003,umask=0x2 00 tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=2000003,umask=0x1 00 tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=2000003,umask=0x10 00 tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=2000003,umask=0x8 00 tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=2000003,umask=0x20 00 tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=2000003,umask=0x4 00 tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=2000003,umask=0x40 00 cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=0x1 00 Unhalted core cycles when the thread is in ring 0 cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100003,umask=0x1 00 cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=0x2 00 Unhalted core cycles when the thread is not in ring 0 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=0x1 00 Cycles in which the L1D and L2 are locked, due to a UC lock or split lock arith.divider_uops pipeline Any uop executed by the Divider. (This includes all divide uops, sqrt, ...) event=0x14,period=2000003,umask=0x2 00 br_inst_exec.all_branches pipeline Speculative and retired branches event=0x88,period=200003,umask=0xff 00 Counts all near executed branches (not necessarily retired) br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1 00 br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2 00 br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0 00 br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4 00 br_inst_exec.all_indirect_near_return pipeline Speculative and retired indirect return branches event=0x88,period=200003,umask=0xc8 00 br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41 00 br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81 00 br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82 00 br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90 00 br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84 00 br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0 00 br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88 00 br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009 00 Branch instructions at retirement br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired (Must be precise) event=0xc4,period=400009,umask=0x4 00 br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x1 00 Counts the number of conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100003,umask=0x40 00 Number of far branches retired br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100003,umask=0x2 00 br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100003,umask=0x2 00 br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100003,umask=0x8 00 Counts the number of near return instructions retired (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 Number of near taken branches retired (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10 00 Counts the number of not taken branch instructions retired br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff 00 Counts all near executed branches (not necessarily retired) br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1 00 br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4 00 br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41 00 br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81 00 br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84 00 br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88 00 br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 Mispredicted branch instructions at retirement br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=0x4 00 This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise) br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x1 00 br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 Number of near branch instructions retired that were taken but mispredicted (Precise event) cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=0x1 00 Increments at the frequency of XCLK (100 MHz) when not halted cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=0x1 00 Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=0x1 00 Reference cycles when the thread is unhalted. (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=0x1 00 Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003 00 Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling cycle_activity.cycles_l1d_pending pipeline Cycles with pending L1 cache miss loads event=0xa3,cmask=8,period=2000003,umask=0x8 00 Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle cycle_activity.cycles_l2_pending pipeline Cycles with pending L2 cache miss loads Spec update: HSD78, HSM63, HSM80 event=0xa3,cmask=1,period=2000003,umask=0x1 00 Cycles with pending L2 miss loads. Set Cmask=2 to count cycle Spec update: HSD78, HSM63, HSM80 cycle_activity.cycles_ldm_pending pipeline Cycles with pending memory loads event=0xa3,cmask=2,period=2000003,umask=0x2 00 Cycles with pending memory loads. Set Cmask=2 to count cycle cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=0x4 00 This event counts cycles during which no instructions were executed in the execution stage of the pipeline cycle_activity.stalls_l1d_pending pipeline Execution stalls due to L1 data cache misses event=0xa3,cmask=12,period=2000003,umask=0xc 00 Execution stalls due to L1 data cache miss loads. Set Cmask=0CH cycle_activity.stalls_l2_pending pipeline Execution stalls due to L2 cache misses Spec update: HSM63, HSM80 event=0xa3,cmask=5,period=2000003,umask=0x5 00 Number of loads missed L2 Spec update: HSM63, HSM80 cycle_activity.stalls_ldm_pending pipeline Execution stalls due to memory subsystem event=0xa3,cmask=6,period=2000003,umask=0x6 00 This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data) ild_stall.iq_full pipeline Stall cycles because IQ is full event=0x87,period=2000003,umask=0x4 00 Stall cycles due to IQ is full ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=0x1 00 This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP) inst_retired.any pipeline Instructions retired from execution Spec update: HSD140, HSD143 event=0xc0,period=2000003 00 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Spec update: HSD140, HSD143 inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event Spec update: HSD11, HSD140 event=0xc0,period=2000003 00 Number of instructions at retirement Spec update: HSD11, HSD140 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: HSD140 (Must be precise) event=0xc0,period=2000003,umask=0x1 00 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: HSD140 (Must be precise) inst_retired.x87 pipeline FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling event=0xc0,period=2000003,umask=0x2 00 This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,cmask=1,period=2000003,umask=0x3 00 This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,cmask=1,period=2000003,umask=0x3 00 Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) ld_blocks.store_forward pipeline loads blocked by overlapping with store buffer that cannot be forwarded event=0x3,period=100003,umask=0x2 00 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=0x7,period=100003,umask=0x1 00 Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=0x2 00 Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=0x1 00 Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=0x1 00 Number of uops delivered by the LSD machine_clears.cycles pipeline Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes event=0xc3,period=2000003,umask=0x1 00 machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20 00 machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=0x4 00 This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently move_elimination.int_eliminated pipeline Number of integer Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=0x1 00 Number of integer move elimination candidate uops that were eliminated move_elimination.int_not_eliminated pipeline Number of integer Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=0x4 00 Number of integer move elimination candidate uops that were not eliminated other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x40 00 Number of microcode assists invoked by HW upon uop writeback resource_stalls.any pipeline Resource-related stall cycles Spec update: HSD135 event=0xa2,period=2000003,umask=0x1 00 Cycles allocation is stalled due to resource related reason Spec update: HSD135 resource_stalls.rob pipeline Cycles stalled due to re-order buffer full event=0xa2,period=2000003,umask=0x10 00 resource_stalls.rs pipeline Cycles stalled due to no eligible RS entry available event=0xa2,period=2000003,umask=0x4 00 resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=0x8 00 This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20 00 Count cases of saving new LBR records by hardware rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=0x1 00 This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=0x1 00 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=0x2 00 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=0x4 00 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=0x8 00 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 uops_executed.core pipeline Number of uops executed on the core Spec update: HSD30, HSM31 event=0xb1,period=2000003,umask=0x2 00 Counts total number of uops to be executed per-core each cycle Spec update: HSD30, HSM31 uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=1,period=2000003,umask=0x2 00 uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=2,period=2000003,umask=0x2 00 uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=3,period=2000003,umask=0x2 00 uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,cmask=4,period=2000003,umask=0x2 00 uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core Spec update: HSD30, HSM31 event=0xb1,inv=1,period=2000003,umask=0x2 00 uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=1,period=2000003,umask=0x1 00 This events counts the cycles where at least one uop was executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=2,period=2000003,umask=0x1 00 This events counts the cycles where at least two uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=3,period=2000003,umask=0x1 00 This events counts the cycles where at least three uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=4,period=2000003,umask=0x1 00 uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=1,inv=1,period=2000003,umask=0x1 00 uops_executed_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=0x1 00 Cycles which a uop is dispatched on port 0 in this thread uops_executed_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=0x2 00 Cycles which a uop is dispatched on port 1 in this thread uops_executed_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=0x4 00 Cycles which a uop is dispatched on port 2 in this thread uops_executed_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=0x8 00 Cycles which a uop is dispatched on port 3 in this thread uops_executed_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10 00 Cycles which a uop is dispatched on port 4 in this thread uops_executed_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20 00 Cycles which a uop is dispatched on port 5 in this thread uops_executed_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40 00 Cycles which a uop is dispatched on port 6 in this thread uops_executed_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80 00 Cycles which a uop is dispatched on port 7 in this thread uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=0x1 00 This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops uops_issued.core_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads event=0xe,any=1,cmask=1,inv=1,period=2000003,umask=0x1 00 uops_issued.flags_merge pipeline Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch event=0xe,period=2000003,umask=0x10 00 Number of flags-merge uops allocated. Such uops add delay uops_issued.single_mul pipeline Number of Multiply packed/scalar single precision uops allocated event=0xe,period=2000003,umask=0x40 00 Number of multiply packed/scalar single precision uops allocated uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20 00 Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=0x1 00 uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=0x1 00 Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles (Precise event) uops_retired.core_stall_cycles pipeline Cycles without actually retired uops event=0xc2,any=1,cmask=1,inv=1,period=2000003,umask=0x1 00 uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=0x2 00 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event) uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=0x1 00 uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=0x1 00 unc_cbo_cache_lookup.any_es uncore cache L3 Lookup any request that access cache and found line in E or S-state event=0x34,umask=0x86 01 unc_cbo_cache_lookup.any_i uncore cache L3 Lookup any request that access cache and found line in I-state event=0x34,umask=0x88 01 unc_cbo_cache_lookup.any_m uncore cache L3 Lookup any request that access cache and found line in M-state event=0x34,umask=0x81 01 unc_cbo_cache_lookup.any_mesi uncore cache L3 Lookup any request that access cache and found line in MESI-state event=0x34,umask=0x8f 01 unc_cbo_cache_lookup.extsnp_es uncore cache L3 Lookup external snoop request that access cache and found line in E or S-state event=0x34,umask=0x46 01 unc_cbo_cache_lookup.extsnp_i uncore cache L3 Lookup external snoop request that access cache and found line in I-state event=0x34,umask=0x48 01 unc_cbo_cache_lookup.extsnp_m uncore cache L3 Lookup external snoop request that access cache and found line in M-state event=0x34,umask=0x41 01 unc_cbo_cache_lookup.extsnp_mesi uncore cache L3 Lookup external snoop request that access cache and found line in MESI-state event=0x34,umask=0x4f 01 unc_cbo_cache_lookup.read_es uncore cache L3 Lookup read request that access cache and found line in E or S-state event=0x34,umask=0x16 01 unc_cbo_cache_lookup.read_i uncore cache L3 Lookup read request that access cache and found line in I-state event=0x34,umask=0x18 01 unc_cbo_cache_lookup.read_m uncore cache L3 Lookup read request that access cache and found line in M-state event=0x34,umask=0x11 01 unc_cbo_cache_lookup.read_mesi uncore cache L3 Lookup read request that access cache and found line in any MESI-state event=0x34,umask=0x1f 01 unc_cbo_cache_lookup.write_es uncore cache L3 Lookup write request that access cache and found line in E or S-state event=0x34,umask=0x26 01 unc_cbo_cache_lookup.write_i uncore cache L3 Lookup write request that access cache and found line in I-state event=0x34,umask=0x28 01 unc_cbo_cache_lookup.write_m uncore cache L3 Lookup write request that access cache and found line in M-state event=0x34,umask=0x21 01 unc_cbo_cache_lookup.write_mesi uncore cache L3 Lookup write request that access cache and found line in MESI-state event=0x34,umask=0x2f 01 unc_cbo_xsnp_response.hitm_eviction uncore cache A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core event=0x22,umask=0x88 01 unc_cbo_xsnp_response.hitm_external uncore cache An external snoop hits a modified line in some processor core event=0x22,umask=0x28 01 unc_cbo_xsnp_response.hit_eviction uncore cache A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core event=0x22,umask=0x84 01 unc_cbo_xsnp_response.hit_external uncore cache An external snoop hits a non-modified line in some processor core event=0x22,umask=0x24 01 unc_cbo_xsnp_response.miss_external uncore cache An external snoop misses in some processor core event=0x22,umask=0x21 01 unc_arb_coh_trk_occupancy.all uncore interconnect Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) event=0x83,umask=0x1 01 Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) unc_arb_trk_occupancy.cycles_with_any_request uncore interconnect Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC event=0x80,cmask=1,umask=0x1 01 dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=0x8,period=100003,umask=0x1 00 Misses in all TLB levels that cause a page walk of any page size dtlb_load_misses.pde_cache_miss virtual memory DTLB demand load misses with low part of linear-to-physical address translation missed event=0x8,period=100003,umask=0x80 00 DTLB demand load misses with low part of linear-to-physical address translation missed dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=0x8,period=2000003,umask=0x60 00 Number of cache load STLB hits. No page walk dtlb_load_misses.stlb_hit_2m virtual memory Load misses that miss the DTLB and hit the STLB (2M) event=0x8,period=2000003,umask=0x40 00 This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks dtlb_load_misses.stlb_hit_4k virtual memory Load misses that miss the DTLB and hit the STLB (4K) event=0x8,period=2000003,umask=0x20 00 This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=0x8,period=100003,umask=0xe 00 Completed page walks in any TLB of any page size due to demand load misses dtlb_load_misses.walk_completed_1g virtual memory Load miss in all TLB levels causes a page walk that completes. (1G) event=0x8,period=2000003,umask=0x8 00 dtlb_load_misses.walk_completed_2m_4m virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) event=0x8,period=2000003,umask=0x4 00 Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels dtlb_load_misses.walk_completed_4k virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) event=0x8,period=2000003,umask=0x2 00 Completed page walks due to demand load misses that caused 4K page walks in any TLB levels dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x8,period=2000003,umask=0x10 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=0x1 00 Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G) dtlb_store_misses.pde_cache_miss virtual memory DTLB store misses with low part of linear-to-physical address translation missed event=0x49,period=100003,umask=0x80 00 DTLB store misses with low part of linear-to-physical address translation missed dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x60 00 Store operations that miss the first TLB level but hit the second and do not cause page walks dtlb_store_misses.stlb_hit_2m virtual memory Store misses that miss the DTLB and hit the STLB (2M) event=0x49,period=100003,umask=0x40 00 This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.stlb_hit_4k virtual memory Store misses that miss the DTLB and hit the STLB (4K) event=0x49,period=100003,umask=0x20 00 This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=0xe 00 Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G) dtlb_store_misses.walk_completed_1g virtual memory Store misses in all DTLB levels that cause completed page walks. (1G) event=0x49,period=100003,umask=0x8 00 dtlb_store_misses.walk_completed_2m_4m virtual memory Store misses in all DTLB levels that cause completed page walks (2M/4M) event=0x49,period=100003,umask=0x4 00 Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure dtlb_store_misses.walk_completed_4k virtual memory Store miss in all TLB levels causes a page walk that completes. (4K) event=0x49,period=100003,umask=0x2 00 Completed page walks due to store misses in one or more TLB levels of 4K page structure dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=100003,umask=0x10 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses ept.walk_cycles virtual memory Cycle count for an Extended Page table walk event=0x4f,period=2000003,umask=0x10 00 itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100003,umask=0x1 00 Counts the number of ITLB flushes, includes 4k/2M/4M pages itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=0x1 00 Misses in ITLB that causes a page walk of any page size itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x60 00 ITLB misses that hit STLB. No page walk itlb_misses.stlb_hit_2m virtual memory Code misses that miss the DTLB and hit the STLB (2M) event=0x85,period=100003,umask=0x40 00 ITLB misses that hit STLB (2M) itlb_misses.stlb_hit_4k virtual memory Core misses that miss the DTLB and hit the STLB (4K) event=0x85,period=100003,umask=0x20 00 ITLB misses that hit STLB (4K) itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=0xe 00 Completed page walks in ITLB of any page size itlb_misses.walk_completed_1g virtual memory Store miss in all TLB levels causes a page walk that completes. (1G) event=0x85,period=100003,umask=0x8 00 itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x85,period=100003,umask=0x4 00 Completed page walks due to misses in ITLB 2M/4M page entries itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x85,period=100003,umask=0x2 00 Completed page walks due to misses in ITLB 4K page entries itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=100003,umask=0x10 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses page_walker_loads.dtlb_l1 virtual memory Number of DTLB page walker hits in the L1+FB event=0xbc,period=2000003,umask=0x11 00 Number of DTLB page walker loads that hit in the L1+FB page_walker_loads.dtlb_l2 virtual memory Number of DTLB page walker hits in the L2 event=0xbc,period=2000003,umask=0x12 00 Number of DTLB page walker loads that hit in the L2 page_walker_loads.dtlb_l3 virtual memory Number of DTLB page walker hits in the L3 + XSNP Spec update: HSD25 event=0xbc,period=2000003,umask=0x14 00 Number of DTLB page walker loads that hit in the L3 Spec update: HSD25 page_walker_loads.dtlb_memory virtual memory Number of DTLB page walker hits in Memory Spec update: HSD25 event=0xbc,period=2000003,umask=0x18 00 Number of DTLB page walker loads from memory Spec update: HSD25 page_walker_loads.ept_dtlb_l1 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB event=0xbc,period=2000003,umask=0x41 00 page_walker_loads.ept_dtlb_l2 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L2 event=0xbc,period=2000003,umask=0x42 00 page_walker_loads.ept_dtlb_l3 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L3 event=0xbc,period=2000003,umask=0x44 00 page_walker_loads.ept_dtlb_memory virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in memory event=0xbc,period=2000003,umask=0x48 00 page_walker_loads.ept_itlb_l1 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB event=0xbc,period=2000003,umask=0x81 00 page_walker_loads.ept_itlb_l2 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L2 event=0xbc,period=2000003,umask=0x82 00 page_walker_loads.ept_itlb_l3 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L2 event=0xbc,period=2000003,umask=0x84 00 page_walker_loads.ept_itlb_memory virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in memory event=0xbc,period=2000003,umask=0x88 00 page_walker_loads.itlb_l1 virtual memory Number of ITLB page walker hits in the L1+FB event=0xbc,period=2000003,umask=0x21 00 Number of ITLB page walker loads that hit in the L1+FB page_walker_loads.itlb_l2 virtual memory Number of ITLB page walker hits in the L2 event=0xbc,period=2000003,umask=0x22 00 Number of ITLB page walker loads that hit in the L2 page_walker_loads.itlb_l3 virtual memory Number of ITLB page walker hits in the L3 + XSNP Spec update: HSD25 event=0xbc,period=2000003,umask=0x24 00 Number of ITLB page walker loads that hit in the L3 Spec update: HSD25 page_walker_loads.itlb_memory virtual memory Number of ITLB page walker hits in Memory Spec update: HSD25 event=0xbc,period=2000003,umask=0x28 00 Number of ITLB page walker loads from memory Spec update: HSD25 tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100003,umask=0x1 00 DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100003,umask=0x20 00 Count number of STLB flush attempts mem_load_uops_l3_miss_retired.remote_dram cache Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD29, HSM30 (Precise event) event=0xd3,period=100003,umask=0x4 00 mem_load_uops_l3_miss_retired.remote_fwd cache Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: HSM30 (Precise event) event=0xd3,period=100003,umask=0x20 00 mem_load_uops_l3_miss_retired.remote_hitm cache Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: HSM30 (Precise event) event=0xd3,period=100003,umask=0x10 00 offcore_response.demand_code_rd.llc_hit.hitm_other_core cache Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 00 offcore_response.demand_data_rd.llc_hit.hitm_other_core cache Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 00 offcore_response.pf_l2_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0040 00 offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to L2) data reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080 00 offcore_response.all_code_rd.llc_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400244 00 offcore_response.all_data_rd.llc_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400091 00 offcore_response.all_data_rd.llc_miss.remote_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63F800091 00 offcore_response.all_data_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00091 00 offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004007F7 00 offcore_response.all_reads.llc_miss.remote_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63F8007F7 00 offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC007F7 00 offcore_response.all_rfo.llc_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400122 00 offcore_response.demand_code_rd.llc_miss.any_response memory Counts all demand code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00004 00 offcore_response.demand_code_rd.llc_miss.local_dram memory Counts all demand code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400004 00 offcore_response.demand_data_rd.llc_miss.any_response memory Counts demand data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 00 offcore_response.demand_data_rd.llc_miss.local_dram memory Counts demand data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400001 00 offcore_response.demand_rfo.llc_miss.local_dram memory Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400002 00 offcore_response.pf_l2_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00040 00 offcore_response.pf_l2_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to L2) data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00010 00 offcore_response.pf_l2_rfo.llc_miss.any_response memory Counts all prefetch (that bring data to L2) RFOs miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00020 00 offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00080 00 unc_c_llc_victims.s_state uncore cache Lines in S State event=0x37,umask=0x4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_ring_ad_used.all uncore cache AD Ring In Use; All event=0x1b,umask=0xf 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_ak_used.all uncore cache AK Ring In Use; All event=0x1c,umask=0xf 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bl_used.all uncore cache BL Ring in Use; Down event=0x1d,umask=0xf 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.dn uncore cache BL Ring in Use; Any event=0x1e,umask=0xc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.down uncore cache BL Ring in Use; Down event=0x1e,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache BL Ring in Use; Any event=0x1e,umask=0x3 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_sink_starved.ad uncore cache UNC_C_RING_SINK_STARVED.AD event=0x6,umask=0x1 01 unc_c_ring_sink_starved.ak uncore cache UNC_C_RING_SINK_STARVED.AK event=0x6,umask=0x2 01 unc_c_ring_sink_starved.bl uncore cache UNC_C_RING_SINK_STARVED.BL event=0x6,umask=0x4 01 unc_c_ring_sink_starved.iv uncore cache UNC_C_RING_SINK_STARVED.IV event=0x6,umask=0x8 01 unc_c_tor_inserts.local_opcode uncore cache TOR Inserts; Local Memory - Opcode Matched event=0x35,umask=0x21 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory unc_h_snoop_resp.rspsfwd uncore cache Shared line forwarded from remote cache event=0x21,umask=0x8 0164Bytes Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_snp_resp_recv_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x60,umask=0x8 01 Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x16,umask=0x2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. HSX does not support dynamic link speeds, so this frequency is fixed unc_q_rxl_crc_errors.normal_op uncore interconnect CRC Errors Detected; Normal Operations event=0x3,umask=0x2 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation unc_s_ring_ad_used.down_even uncore interconnect AD Ring In Use; Down and Event event=0x1b,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ad_used.down_odd uncore interconnect AD Ring In Use; Down and Odd event=0x1b,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ad_used.up_even uncore interconnect AD Ring In Use; Up and Even event=0x1b,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ad_used.up_odd uncore interconnect AD Ring In Use; Up and Odd event=0x1b,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_ak_used.down_even uncore interconnect AK Ring In Use; Down and Event event=0x1c,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ak_used.down_odd uncore interconnect AK Ring In Use; Down and Odd event=0x1c,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ak_used.up_even uncore interconnect AK Ring In Use; Up and Even event=0x1c,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ak_used.up_odd uncore interconnect AK Ring In Use; Up and Odd event=0x1c,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bl_used.down_even uncore interconnect BL Ring in Use; Down and Event event=0x1d,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_bl_used.down_odd uncore interconnect BL Ring in Use; Down and Odd event=0x1d,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_bl_used.up_even uncore interconnect BL Ring in Use; Up and Even event=0x1d,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_bl_used.up_odd uncore interconnect BL Ring in Use; Up and Odd event=0x1d,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_u_clockticks uncore interconnect UNC_U_CLOCKTICKS event=0 01 unc_m_clockticks uncore memory DRAM Clockticks event=0 01 unc_p_clockticks uncore power pclk Cycles event=0 01 The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_freq_band0_cycles uncore power Frequency Residency event=0xb 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band1_cycles uncore power Frequency Residency event=0xc 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band2_cycles uncore power Frequency Residency event=0xd 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band3_cycles uncore power Frequency Residency event=0xe 01 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_ufs_transitions_no_change uncore power UNC_P_UFS_TRANSITIONS_NO_CHANGE event=0x79 01 Ring GV with same final and initial frequency l1d_pend_miss.l2_stall cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources event=0x48,period=1000003,umask=0x4 00 Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l2_lines_out.non_silent cache Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=0x2 00 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 l2_lines_out.silent cache Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=0x1 00 Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event l2_lines_out.useless_hwpf cache Cache lines that have been L2 hardware prefetched but not used by demand accesses event=0xf2,period=200003,umask=0x4 00 Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache l2_rqsts.miss cache This event is deprecated event=0x24,period=200003,umask=0x3f 10 l2_rqsts.references cache This event is deprecated event=0x24,period=200003,umask=0xff 10 mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or Bus Lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=0x4 00 Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock) Supports address when precise (Precise event) ocr.demand_code_rd.l3_hit.any cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 00 ocr.demand_code_rd.l3_hit.snoop_miss cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0004 00 ocr.demand_code_rd.l3_hit.snoop_not_needed cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004 00 ocr.demand_code_rd.l3_hit.snoop_sent cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0004 00 ocr.demand_data_rd.l3_hit.any cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001 00 ocr.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 00 ocr.demand_data_rd.l3_hit.snoop_sent cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0001 00 ocr.demand_rfo.l3_hit.any cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 00 ocr.demand_rfo.l3_hit.snoop_miss cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0002 00 ocr.demand_rfo.l3_hit.snoop_not_needed cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002 00 ocr.demand_rfo.l3_hit.snoop_sent cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0002 00 ocr.hwpf_l1d_and_swpf.l3_hit.any cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0400 00 ocr.hwpf_l1d_and_swpf.l3_hit.snoop_miss cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0400 00 ocr.hwpf_l1d_and_swpf.l3_hit.snoop_not_needed cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0400 00 ocr.hwpf_l2_data_rd.l3_hit.any cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hitm cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_miss cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_not_needed cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010 00 ocr.hwpf_l2_data_rd.l3_hit.snoop_sent cache Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0010 00 ocr.hwpf_l2_rfo.l3_hit.any cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hitm cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_miss cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_not_needed cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020 00 ocr.hwpf_l2_rfo.l3_hit.snoop_sent cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0020 00 ocr.hwpf_l3.l3_hit.any cache Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C2380 00 ocr.other.l3_hit.snoop_hit_no_fwd cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C8000 00 ocr.other.l3_hit.snoop_miss cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C8000 00 ocr.other.l3_hit.snoop_not_needed cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C8000 00 ocr.other.l3_hit.snoop_sent cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C8000 00 ocr.streaming_wr.l3_hit.any cache Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0800 00 offcore_requests.all_requests cache Counts memory transactions sent to the uncore event=0xb0,period=100003,umask=0x80 00 Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses offcore_requests_outstanding.all_data_rd cache For every cycle, increments by the number of outstanding data read requests pending event=0x60,period=1000003,umask=0x8 00 For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.cycles_with_data_rd cache Cycles where at least 1 outstanding data read request is pending event=0x60,cmask=1,period=1000003,umask=0x8 00 Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles where at least 1 outstanding Demand RFO request is pending event=0x60,cmask=1,period=1000003,umask=0x4 00 Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_data_rd cache For every cycle, increments by the number of outstanding demand data read requests pending event=0x60,period=1000003,umask=0x1 00 For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_rfo cache Store Read transactions pending for off-core. Highly correlated event=0x60,period=1000003,umask=0x4 00 Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion sq_misc.bus_lock cache Counts bus locks, accounts for cache line split locks and UC locks event=0xf4,period=100003,umask=0x10 00 Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory sq_misc.sq_full cache Cycles the queue waiting for offcore responses is full event=0xf4,period=100003,umask=0x4 00 Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x32,period=100003,umask=0x1 00 Counts the number of PREFETCHNTA instructions executed sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x32,period=100003,umask=0x8 00 Counts the number of PREFETCHW instructions executed sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x32,period=100003,umask=0x2 00 Counts the number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=100003,umask=0x4 00 Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=1000003,umask=0x3 00 Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=1000003,umask=0xfc 00 decode.lcp frontend Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP] event=0x87,period=500009,umask=0x1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP] dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE transitions count event=0xab,cmask=1,edge=1,period=100003,umask=0x2 00 Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions dsb2mite_switches.penalty_cycles frontend DSB-to-MITE switch true penalty cycles event=0xab,period=100003,umask=0x2 00 Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x500106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x508006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x501006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x500206 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x510006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x502006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x500406 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x520006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x504006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x500806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) icache_16b.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS] event=0x80,period=500009,umask=0x4 00 Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS] icache_64b.iftag_hit frontend Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=0x1 00 Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses icache_64b.iftag_miss frontend Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=0x2 00 Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses icache_64b.iftag_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] event=0x83,period=200003,umask=0x4 00 Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] icache_data.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL] event=0x80,period=500009,umask=0x4 00 Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL] icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] event=0x83,period=200003,umask=0x4 00 Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] idq.dsb_cycles_ok frontend Cycles DSB is delivering optimal number of Uops event=0x79,cmask=5,period=2000003,umask=0x8 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles_ok frontend Cycles MITE is delivering optimal number of Uops event=0x79,cmask=5,period=2000003,umask=0x4 00 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles_any frontend Cycles when uops are being delivered to IDQ while MS is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_switches frontend Number of switches from DSB or MITE to the MS event=0x79,cmask=1,edge=1,period=100003,umask=0x30 00 Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to IDQ while MS is busy event=0x79,period=100003,umask=0x30 00 Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS idq_uops_not_delivered.core frontend Uops not delivered by IDQ when backend of the machine is not stalled event=0x9c,period=1000003,umask=0x1 00 Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled event=0x9c,cmask=5,period=1000003,umask=0x1 00 Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle idq_uops_not_delivered.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled event=0x9c,cmask=1,inv=1,period=1000003,umask=0x1 00 Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle cycle_activity.cycles_l3_miss memory Cycles while L3 cache miss demand load is outstanding event=0xa3,cmask=2,period=1000003,umask=0x2 00 hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) event=0xc8,period=100003,umask=0x4 00 Counts the number of times HLE abort was triggered hle_retired.aborted_events memory Number of times an HLE execution aborted due to unfriendly events (such as interrupts) event=0xc8,period=100003,umask=0x80 00 Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts) hle_retired.aborted_mem memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=100003,umask=0x8 00 Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) hle_retired.aborted_unfriendly memory Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) event=0xc8,period=100003,umask=0x20 00 Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=100003,umask=0x2 00 Counts the number of times HLE commit succeeded hle_retired.start memory Number of times an HLE execution started event=0xc8,period=100003,umask=0x1 00 Counts the number of times we entered an HLE region. Does not count nested transactions ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00004 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00002 00 ocr.hwpf_l1d_and_swpf.l3_miss memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00400 00 ocr.hwpf_l2_data_rd.l3_miss memory Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00010 00 ocr.hwpf_l2_rfo.l3_miss memory Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00020 00 ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC08000 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that was not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00800 00 offcore_requests.l3_miss_demand_data_rd memory Counts demand data read requests that miss the L3 cache event=0xb0,period=100003,umask=0x10 00 offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles where at least one demand data read request known to have missed the L3 cache is pending event=0x60,cmask=1,period=1000003,umask=0x10 00 Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache tx_exec.misc2 memory Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region event=0x5d,period=100003,umask=0x2 00 Counts Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc3 memory Number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=100003,umask=0x4 00 Counts Unfriendly TSX abort triggered by a nest count that is too deep tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=100003,umask=0x10 00 Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=100003,umask=0x8 00 Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=100003,umask=0x20 00 Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=100003,umask=0x4 00 Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=100003,umask=0x40 00 Counts the number of times we could not allocate Lock Buffer core_power.lvl0_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule event=0x28,period=200003,umask=0x7 00 Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes core_power.lvl1_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule event=0x28,period=200003,umask=0x18 00 Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions core_power.lvl2_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule event=0x28,period=200003,umask=0x20 00 Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000004 00 ocr.demand_data_rd.dram other Counts demand data reads that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 00 ocr.demand_data_rd.local_dram other Counts demand data reads that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 00 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000002 00 ocr.hwpf_l1d_and_swpf.any_response other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400 00 ocr.hwpf_l1d_and_swpf.dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000400 00 ocr.hwpf_l1d_and_swpf.local_dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000400 00 ocr.hwpf_l2_data_rd.any_response other Counts hardware prefetch data reads (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010 00 ocr.hwpf_l2_data_rd.dram other Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_data_rd.local_dram other Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000010 00 ocr.hwpf_l2_rfo.any_response other Counts hardware prefetch RFOs (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020 00 ocr.hwpf_l2_rfo.dram other Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000020 00 ocr.hwpf_l2_rfo.local_dram other Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000020 00 ocr.other.any_response other Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000 00 ocr.other.dram other Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184008000 00 ocr.other.local_dram other Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184008000 00 ocr.streaming_wr.dram other Counts streaming stores that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000800 00 ocr.streaming_wr.local_dram other Counts streaming stores that DRAM supplied the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000800 00 arith.divider_active pipeline Cycles when divide unit is busy executing divide or square root operations event=0x14,cmask=1,period=1000003,umask=0x9 00 Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations assists.any pipeline Number of occurrences where a microcode assist is invoked by hardware event=0xc1,period=100003,umask=0x7 00 Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists br_misp_retired.all_branches pipeline All mispredicted branch instructions retired (Precise event) event=0xc5,period=50021 00 Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=50021,umask=0x11 00 Counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired (Precise event) event=0xc5,period=50021,umask=0x10 00 Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken (Precise event) br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=50021,umask=0x1 00 Counts taken conditional mispredicted branch instructions retired (Precise event) br_misp_retired.indirect pipeline All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) event=0xc5,period=50021,umask=0x80 00 Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) br_misp_retired.indirect_call pipeline Mispredicted indirect CALL instructions retired (Precise event) event=0xc5,period=50021,umask=0x2 00 Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect (Precise event) br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=50021,umask=0x20 00 Counts number of near branch instructions retired that were mispredicted and taken (Precise event) br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=50021,umask=0x8 00 This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired (Precise event) cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=0x1 00 Counts core crystal clock cycles when the thread is unhalted cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=20,period=1000003,umask=0x14 00 ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP] event=0x87,period=500009,umask=0x1 00 Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP] inst_retired.any pipeline Number of instructions retired. Fixed Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event (Precise event) event=0xc0,period=2000003 00 Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) inst_retired.nop pipeline Number of all retired NOP instructions (Precise event) event=0xc0,period=2000003,umask=0x2 00 inst_retired.prec_dist pipeline Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Precise event) event=0,period=2000003,umask=0x1 00 A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event) inst_retired.stall_cycles pipeline Cycles without actually retired instructions event=0xc0,cmask=1,inv=1,period=1000003,umask=0x1 00 This event counts cycles without actually retired instructions int_misc.all_recovery_cycles pipeline Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall event=0xd,cmask=1,period=2000003,umask=0x3 00 Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall int_misc.clears_count pipeline Clears speculative count event=0xd,cmask=1,edge=1,period=500009,umask=0x1 00 Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path event=0xd,period=500009,umask=0x80 00 Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread event=0xd,period=500009,umask=0x1 00 Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.uop_dropping pipeline TMA slots where uops got dropped event=0xd,period=1000003,umask=0x10 00 Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=0x3,period=100003,umask=0x8 00 Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks_partial.address_alias pipeline False dependencies due to partial compare on address event=0x7,period=100003,umask=0x1 00 Counts the number of times a load got blocked due to false dependencies due to partial compare on address lsd.cycles_ok pipeline Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder event=0xa8,cmask=5,period=2000003,umask=0x1 00 Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) misc_retired.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=100003,umask=0x20 00 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly misc_retired.pause_inst pipeline Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products event=0xcc,period=100003,umask=0x40 00 Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=1000003,umask=0x1 00 Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses) rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty event=0x5e,cmask=1,edge=1,inv=1,period=100003,umask=0x1 00 Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) topdown.backend_bound_slots pipeline TMA slots where no uops were being issued due to lack of back-end resources event=0xa4,period=10000003,umask=0x2 00 Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources topdown.br_mispredict_slots pipeline TMA slots wasted due to incorrect speculation by branch mispredictions event=0xa4,period=10000003,umask=0x8 00 Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the speculative path as well as the out-of-order engine recovery past a branch misprediction uops_decoded.dec0 pipeline Number of uops decoded out of instructions exclusively fetched by decoder 0 event=0x56,period=1000003,umask=0x1 00 Uops exclusively fetched by decoder 0 uops_dispatched.port_0 pipeline Number of uops executed on port 0 event=0xa1,period=2000003,umask=0x1 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 uops_dispatched.port_1 pipeline Number of uops executed on port 1 event=0xa1,period=2000003,umask=0x2 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 uops_dispatched.port_2_3 pipeline Number of uops executed on port 2 and 3 event=0xa1,period=2000003,umask=0x4 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3 uops_dispatched.port_4_9 pipeline Number of uops executed on port 4 and 9 event=0xa1,period=2000003,umask=0x10 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9 uops_dispatched.port_5 pipeline Number of uops executed on port 5 event=0xa1,period=2000003,umask=0x20 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 uops_dispatched.port_6 pipeline Number of uops executed on port 6 event=0xa1,period=2000003,umask=0x40 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 uops_dispatched.port_7_8 pipeline Number of uops executed on port 7 and 8 event=0xa1,period=2000003,umask=0x80 00 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8 uops_issued.any pipeline Uops that RAT issues to RS event=0xe,period=2000003,umask=0x1 00 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.stall_cycles pipeline Cycles when RAT does not issue Uops to RS for the thread event=0xe,cmask=1,inv=1,period=1000003,umask=0x1 00 Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=100003,umask=0x2 00 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=1000003,umask=0x2 00 This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=10,inv=1,period=1000003,umask=0x2 00 Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event unc_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop, etc event=0x84,umask=0x1 01 unc_arb_dat_occupancy.all uncore interconnect Each cycle counts number of any coherent request at memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products event=0x85,umask=0x1 01 unc_arb_dat_occupancy.rd uncore interconnect Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products event=0x85,umask=0x2 01 unc_arb_req_trk_occupancy.drd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products event=0x80,umask=0x2 01 unc_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches event=0x81,umask=0x2 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. This event is not supported on ICL products but is supported on RKL products event=0x80,umask=0x1 01 unc_arb_trk_occupancy.rd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products event=0x80,umask=0x2 01 unc_arb_trk_requests.all uncore interconnect Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=0x1 01 unc_arb_trk_requests.rd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products event=0x81,umask=0x2 01 unc_clock.socket uncore other UNC_CLOCK.SOCKET event=0xff 01 dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=0x8,period=100003,umask=0x20 00 Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a demand load event=0x8,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load dtlb_load_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data load to a 2M/4M page event=0x8,period=100003,umask=0x4 00 Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walks completed due to a demand data load to a 4K page event=0x8,period=100003,umask=0x2 00 Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Number of page walks outstanding for a demand load in the PMH each cycle event=0x8,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x49,period=100003,umask=0x20 00 Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store event=0x49,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=0x4 00 Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x49,period=100003,umask=0x2 00 Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Number of page walks outstanding for a store in the PMH each cycle event=0x49,period=100003,umask=0x10 00 Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x85,period=100003,umask=0x20 00 Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request event=0x85,cmask=1,period=100003,umask=0x10 00 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request itlb_misses.walk_pending virtual memory Number of page walks outstanding for an outstanding code request in the PMH each cycle event=0x85,period=100003,umask=0x10 00 Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle l2_lines_out.non_silent cache Cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=0x2 00 Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities mem_load_l3_hit_retired.xsnp_hit cache This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x2 10 mem_load_l3_hit_retired.xsnp_hitm cache This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x4 10 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 00 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 ocr.demand_code_rd.snc_cache.hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000004 00 ocr.demand_code_rd.snc_cache.hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000004 00 ocr.demand_data_rd.l3_hit cache Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 00 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 ocr.demand_data_rd.remote_cache.snoop_hitm cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1030000001 00 ocr.demand_data_rd.remote_cache.snoop_hit_with_fwd cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x830000001 00 ocr.demand_data_rd.snc_cache.hitm cache Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000001 00 ocr.demand_data_rd.snc_cache.hit_with_fwd cache Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000001 00 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 00 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 ocr.demand_rfo.snc_cache.hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000002 00 ocr.demand_rfo.snc_cache.hit_with_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000002 00 ocr.hwpf_l1d_and_swpf.l3_hit cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0400 00 ocr.hwpf_l3.l3_hit cache Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80082380 00 ocr.prefetches.l3_hit cache Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C27F0 00 ocr.reads_to_core.l3_hit cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F003C0477 00 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0477 00 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0477 00 ocr.reads_to_core.remote_cache.snoop_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1830000477 00 ocr.reads_to_core.remote_cache.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1030000477 00 ocr.reads_to_core.remote_cache.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x830000477 00 ocr.reads_to_core.snc_cache.hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000477 00 ocr.reads_to_core.snc_cache.hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000477 00 ocr.streaming_wr.l3_hit cache Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080800 00 offcore_requests.demand_code_rd cache Counts cacheable and non-cacheable code reads to the core event=0xb0,period=100003,umask=0x2 00 Counts both cacheable and non-cacheable code reads to the core offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with outstanding code read requests pending event=0x60,cmask=1,period=1000003,umask=0x2 00 Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_code_rd cache For every cycle, increments by the number of outstanding code read requests pending event=0x60,period=1000003,umask=0x2 00 For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00004 00 ocr.demand_code_rd.l3_miss_local memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400004 00 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 00 ocr.demand_data_rd.l3_miss_local memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FC00002 00 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F04400002 00 ocr.hwpf_l1d_and_swpf.l3_miss memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00400 00 ocr.hwpf_l1d_and_swpf.l3_miss_local memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400400 00 ocr.hwpf_l3.l3_miss memory Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x94002380 00 ocr.hwpf_l3.l3_miss_local memory Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84002380 00 ocr.itom.l3_miss_local memory Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000002 00 ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC08000 00 ocr.other.l3_miss_local memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84408000 00 ocr.prefetches.l3_miss_local memory Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F844027F0 00 ocr.reads_to_core.l3_miss memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FC00477 00 ocr.reads_to_core.l3_miss_local memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F04400477 00 ocr.reads_to_core.l3_miss_local_socket memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x70CC00477 00 ocr.streaming_wr.l3_miss memory Counts streaming stores that missed the local socket's L1, L2, and L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x94000800 00 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000800 00 offcore_requests_outstanding.l3_miss_demand_data_rd memory This event is deprecated event=0x60,period=2000003,umask=0x10 10 offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 memory Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache event=0x60,cmask=6,period=2000003,umask=0x10 00 Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache core_power.lvl2_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule event=0x28,period=200003,umask=0x20 00 Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions core_snoop_response.i_fwd_fe other Hit snoop reply with data, line invalidated event=0xef,period=1000003,umask=0x20 00 Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_fwd_m other HitM snoop reply with data, line invalidated event=0xef,period=1000003,umask=0x10 00 Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_hit_fse other Hit snoop reply without sending the data, line invalidated event=0xef,period=1000003,umask=0x2 00 Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.miss other Line not found snoop reply event=0xef,period=1000003,umask=0x1 00 Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core core_snoop_response.s_fwd_fe other Hit snoop reply with data, line kept in Shared state event=0xef,period=1000003,umask=0x40 00 Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_fwd_m other HitM snoop reply with data, line kept in Shared state event=0xef,period=1000003,umask=0x8 00 Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_hit_fse other Hit snoop reply without sending the data, line kept in Shared state event=0xef,period=1000003,umask=0x4 00 Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core ocr.demand_code_rd.dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000004 00 ocr.demand_code_rd.local_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000004 00 ocr.demand_code_rd.snc_dram other Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000004 00 ocr.demand_data_rd.dram other Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000001 00 ocr.demand_data_rd.local_dram other Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000001 00 ocr.demand_data_rd.local_pmm other Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400001 00 ocr.demand_data_rd.pmm other Counts demand data reads that were supplied by PMM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703C00001 00 ocr.demand_data_rd.remote_dram other Counts demand data reads that were supplied by DRAM attached to another socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x730000001 00 ocr.demand_data_rd.remote_pmm other Counts demand data reads that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000001 00 ocr.demand_data_rd.snc_dram other Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000001 00 ocr.demand_data_rd.snc_pmm other Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0002 00 ocr.demand_rfo.dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000002 00 ocr.demand_rfo.local_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000002 00 ocr.demand_rfo.local_pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400002 00 ocr.demand_rfo.pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703C00002 00 ocr.demand_rfo.remote_pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000002 00 ocr.demand_rfo.snc_dram other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000002 00 ocr.demand_rfo.snc_pmm other Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800002 00 ocr.hwpf_l1d_and_swpf.dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000400 00 ocr.hwpf_l1d_and_swpf.local_dram other Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000400 00 ocr.hwpf_l2.any_response other Counts hardware prefetch (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10070 00 ocr.hwpf_l3.any_response other Counts hardware prefetches to the L3 only that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x12380 00 ocr.hwpf_l3.remote other Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90002380 00 ocr.itom.remote other Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000002 00 ocr.reads_to_core.any_response other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0477 00 ocr.reads_to_core.dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000477 00 ocr.reads_to_core.local_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000477 00 ocr.reads_to_core.local_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400477 00 ocr.reads_to_core.local_socket_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x70C000477 00 ocr.reads_to_core.local_socket_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700C00477 00 ocr.reads_to_core.remote other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F33000477 00 ocr.reads_to_core.remote_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x730000477 00 ocr.reads_to_core.remote_memory other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x731800477 00 ocr.reads_to_core.remote_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000477 00 ocr.reads_to_core.snc_dram other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000477 00 ocr.reads_to_core.snc_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800477 00 ocr.write_estimate.memory other Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) event=0xb7,period=100003,umask=0x1,offcore_rsp=0xFBFF80822 00 br_misp_retired.indirect_call pipeline Mispredicted indirect CALL instructions retired (Precise event) event=0xc5,period=50021,umask=0x2 00 Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect (Precise event) rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=1000003,umask=0x1 00 Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) unc_cha_2lm_nm_invitox.local uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL event=0x65,umask=0x1 11 unc_cha_2lm_nm_invitox.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE event=0x65,umask=0x2 11 unc_cha_2lm_nm_invitox.setconflict uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT event=0x65,umask=0x4 11 unc_cha_2lm_nm_setconflicts.llc uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC event=0x64,umask=0x2 11 unc_cha_2lm_nm_setconflicts.sf uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF event=0x64,umask=0x1 11 unc_cha_2lm_nm_setconflicts.tor uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR event=0x64,umask=0x4 11 unc_cha_2lm_nm_setconflicts2.memwr uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR event=0x70,umask=0x2 11 unc_cha_2lm_nm_setconflicts2.memwrni uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI event=0x70,umask=0x4 11 unc_cha_ag0_ad_crd_acquired0.tgr0 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr1 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr2 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr3 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=0x8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr4 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr5 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr6 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr7 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr10 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr8 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr9 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr0 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr1 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr2 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr3 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=0x8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr4 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr5 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr6 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr7 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr10 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr8 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr9 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr0 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr1 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr2 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr3 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=0x8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr4 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr5 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr6 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr7 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr10 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr8 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr9 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr0 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr1 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr2 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr3 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=0x8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr4 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr5 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr6 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr7 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr10 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr8 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr9 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr0 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr1 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr2 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr3 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=0x8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr4 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr5 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr6 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr7 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr10 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr8 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr9 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr0 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr1 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr2 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr3 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=0x8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr4 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr5 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr6 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr7 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr10 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr8 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr9 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr0 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr1 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr2 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr3 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=0x8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr4 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr5 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr6 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr7 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr10 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr8 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr9 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr0 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr1 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr2 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr3 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=0x8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr4 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr5 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr6 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr7 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr10 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr8 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr9 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_clockticks uncore cache Clockticks of the uncore caching and home agent (CHA) event=0 01 unc_cha_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f 01 Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_cha_dir_lookup.no_snp uncore cache Multi-socket cacheline directory state lookups : Snoop Not Needed event=0x53,umask=0x2 01 Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean unc_cha_dir_lookup.snp uncore cache Multi-socket cacheline directory state lookups : Snoop Needed event=0x53,umask=0x1 01 Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean unc_cha_dir_update.ha uncore cache Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe event=0x54,umask=0x1 01 Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_dir_update.tor uncore cache Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe event=0x54,umask=0x2 01 Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_distress_asserted.dpt_local uncore cache Distress signal asserted : DPT Local event=0xaf,umask=0x4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_cha_distress_asserted.dpt_nonlocal uncore cache Distress signal asserted : DPT Remote event=0xaf,umask=0x8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_cha_distress_asserted.dpt_stall_iv uncore cache Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_cha_distress_asserted.dpt_stall_nocrd uncore cache Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_cha_distress_asserted.horz uncore cache Distress signal asserted : Horizontal event=0xaf,umask=0x2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_cha_distress_asserted.pmm_local uncore cache Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_cha_distress_asserted.pmm_nonlocal uncore cache Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_cha_distress_asserted.vert uncore cache Distress signal asserted : Vertical event=0xaf,umask=0x1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state event=0x5f,umask=0x4 01 Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv* unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests event=0x5f,umask=0x8 01 unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests event=0x5f,umask=0x10 01 Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed : Remote socket read requests event=0x5e,umask=0x1 01 Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests event=0x5e,umask=0x2 01 Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line event=0x60,umask=0x40 01 Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests event=0x60,umask=0x80 01 Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line event=0x60,umask=0x20 01 Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn unc_cha_horz_ring_ad_in_use.left_even uncore cache Horizontal AD Ring In Use : Left and Even event=0xb6,umask=0x1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.left_odd uncore cache Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=0x2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_even uncore cache Horizontal AD Ring In Use : Right and Even event=0xb6,umask=0x4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_odd uncore cache Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=0x8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.left_even uncore cache Horizontal AK Ring In Use : Left and Even event=0xbb,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.left_odd uncore cache Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.right_even uncore cache Horizontal AK Ring In Use : Right and Even event=0xbb,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.right_odd uncore cache Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_even uncore cache Horizontal AK Ring In Use : Left and Even event=0xb7,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_odd uncore cache Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_even uncore cache Horizontal AK Ring In Use : Right and Even event=0xb7,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_odd uncore cache Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_even uncore cache Horizontal BL Ring in Use : Left and Even event=0xb8,umask=0x1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_odd uncore cache Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=0x2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_even uncore cache Horizontal BL Ring in Use : Right and Even event=0xb8,umask=0x4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_odd uncore cache Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=0x8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_iv_in_use.left uncore cache Horizontal IV Ring in Use : Left event=0xb9,umask=0x1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_horz_ring_iv_in_use.right uncore cache Horizontal IV Ring in Use : Right event=0xb9,umask=0x4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_imc_writes_count.full uncore cache CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH event=0x5b,umask=0x1 01 Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels unc_cha_llc_lookup.all_remote uncore cache Cache Lookups : All transactions from Remote Agents event=0x34,umask=0x1e20ff 01 Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.any_f uncore cache Cache Lookups : All Request Filter event=0x34 01 Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch unc_cha_llc_lookup.code uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ event=0x34,umask=0x1bd0ff 11 unc_cha_llc_lookup.code_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL event=0x34,umask=0x19d0ff 11 unc_cha_llc_lookup.code_read uncore cache Cache Lookups : Code Reads event=0x34,umask=0x1bd0ff 01 Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.code_read_f uncore cache Cache Lookups : CRd Request Filter event=0x34 01 Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_read_local uncore cache Cache Lookups : CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x19d0ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_read_miss uncore cache Cache Lookups : Code Read Misses event=0x34,umask=0x1bd001 01 Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.code_read_remote uncore cache Cache Lookups : CRd Requests that come from a Remote socket event=0x34,umask=0x1a10ff 01 Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch unc_cha_llc_lookup.code_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE event=0x34,umask=0x1a10ff 11 unc_cha_llc_lookup.corepref_or_dmnd_local_f uncore cache Cache Lookups : Local request Filter event=0x34 01 Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core unc_cha_llc_lookup.data_rd uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ event=0x34,umask=0x1bc1ff 11 unc_cha_llc_lookup.data_read uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=0x1bc1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ event=0x34,umask=0x1fc1ff 11 unc_cha_llc_lookup.data_read_f uncore cache Cache Lookups : Data Read Request Filter event=0x34 01 Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions unc_cha_llc_lookup.data_read_local uncore cache Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core) event=0x34,umask=0x19c1ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups : Data Read Misses event=0x34,umask=0x1bc101 01 Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_remote uncore cache Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket event=0x34,umask=0x1a01ff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.dmnd_read_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL event=0x34,umask=0x841ff 11 unc_cha_llc_lookup.e uncore cache Cache Lookups : E State event=0x34,umask=0x20 01 Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State unc_cha_llc_lookup.f uncore cache Cache Lookups : F State event=0x34,umask=0x80 01 Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State unc_cha_llc_lookup.flush_inv_local uncore cache Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core) event=0x34,umask=0x1844ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.flush_inv_remote uncore cache Cache Lookups : Flush or Invalidate requests that come from a Remote socket event=0x34,umask=0x1a04ff 01 Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing unc_cha_llc_lookup.flush_or_inv_f uncore cache Cache Lookups : Flush or Invalidate Filter event=0x34 01 Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.i uncore cache Cache Lookups : I State event=0x34,umask=0x1 01 Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss unc_cha_llc_lookup.llcpref_local uncore cache Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core) event=0x34,umask=0x189dff 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.llcpref_local_f uncore cache Cache Lookups : Local LLC prefetch requests (from LLC) Filter event=0x34 01 Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC unc_cha_llc_lookup.llc_pf_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL event=0x34,umask=0x189dff 11 unc_cha_llc_lookup.locally_homed_address uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM event=0x34,umask=0xbdfff 11 unc_cha_llc_lookup.local_f uncore cache Cache Lookups : Transactions homed locally Filter event=0x34 01 Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.loc_hom uncore cache Cache Lookups : Transactions homed locally event=0x34,umask=0xbdfff 01 Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.m uncore cache Cache Lookups : M State event=0x34,umask=0x40 01 Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State unc_cha_llc_lookup.miss_all uncore cache Cache Lookups : All Misses event=0x34,umask=0x1fe001 01 Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.other_req_f uncore cache Cache Lookups : Write Request Filter event=0x34 01 Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.pref_or_dmnd_remote_f uncore cache Cache Lookups : Remote non-snoop request Filter event=0x34 01 Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent unc_cha_llc_lookup.read uncore cache Cache Lookups : Reads event=0x34,umask=0x1bd9ff 01 Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_local_loc_hom uncore cache Cache Lookups : Locally Requested Reads that are Locally HOMed event=0x34,umask=0x9d9ff 01 Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_local_rem_hom uncore cache Cache Lookups : Locally Requested Reads that are Remotely HOMed event=0x34,umask=0x11d9ff 01 Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss uncore cache Cache Lookups : Read Misses event=0x34,umask=0x1bd901 01 Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss_loc_hom uncore cache Cache Lookups : Locally HOMed Read Misses event=0x34,umask=0xbd901 01 Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss_rem_hom uncore cache Cache Lookups : Remotely HOMed Read Misses event=0x34,umask=0x13d901 01 Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_or_snoop_remote_miss_rem_hom uncore cache Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed event=0x34,umask=0x161901 01 Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_remote_loc_hom uncore cache Cache Lookups : Remotely Requested Reads that are Locally HOMed event=0x34,umask=0xa19ff 01 Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.read_sf_hit uncore cache Cache Lookups : Reads that Hit the Snoop Filter event=0x34,umask=0x1bd90e 01 Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.remotely_homed_address uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM event=0x34,umask=0x15dfff 11 unc_cha_llc_lookup.remote_f uncore cache Cache Lookups : Transactions homed remotely Filter event=0x34 01 Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_snoop_f uncore cache Cache Lookups : Remote snoop request Filter event=0x34 01 Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent unc_cha_llc_lookup.rem_hom uncore cache Cache Lookups : Transactions homed remotely event=0x34,umask=0x15dfff 01 Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.rfo_f uncore cache Cache Lookups : RFO Request Filter event=0x34 01 Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups : RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x19c8ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.rfo_miss uncore cache Cache Lookups : RFO Misses event=0x34,umask=0x1bc801 01 Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing unc_cha_llc_lookup.rfo_pref_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL event=0x34,umask=0x888ff 11 unc_cha_llc_lookup.rfo_remote uncore cache Cache Lookups : RFO Requests that come from a Remote socket event=0x34,umask=0x1a08ff 01 Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch unc_cha_llc_lookup.s uncore cache Cache Lookups : S State event=0x34,umask=0x10 01 Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State unc_cha_llc_lookup.sf_e uncore cache Cache Lookups : SnoopFilter - E State event=0x34,umask=0x4 01 Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State unc_cha_llc_lookup.sf_h uncore cache Cache Lookups : SnoopFilter - H State event=0x34,umask=0x8 01 Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State unc_cha_llc_lookup.sf_s uncore cache Cache Lookups : SnoopFilter - S State event=0x34,umask=0x2 01 Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State unc_cha_llc_lookup.writes_and_other uncore cache Cache Lookups : Filters Requests for those that write info into the cache event=0x34,umask=0x1a42ff 01 Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.write_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER event=0x34,umask=0x842ff 11 unc_cha_llc_lookup.write_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER event=0x34,umask=0x17c2ff 11 unc_cha_llc_victims.all uncore cache Lines Victimized : All Lines Victimized event=0x37,umask=0xf 01 Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_all uncore cache Lines Victimized : Local - All Lines event=0x37,umask=0x200f 01 Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized : Local - Lines in E State event=0x37,umask=0x2002 01 Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized : Local - Lines in M State event=0x37,umask=0x2001 01 Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized : Local - Lines in S State event=0x37,umask=0x2004 01 Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_all uncore cache Lines Victimized : Remote - All Lines event=0x37,umask=0x800f 01 Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized : Remote - Lines in E State event=0x37,umask=0x8002 01 Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized : Remote - Lines in M State event=0x37,umask=0x8001 01 Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized : Remote - Lines in S State event=0x37,umask=0x8004 01 Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_misc_external.mbe_inst0 uncore cache Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=0x1 01 unc_cha_misc_external.mbe_inst1 uncore cache Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=0x2 01 unc_cha_pipe_reject.adegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.akegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.allrsfways_res uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.blegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.fsf_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_allowsnp uncore cache Pipe Rejects event=0x42,umask=0x4 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_allwayrsv uncore cache Pipe Rejects event=0x42,umask=0x10 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_pamatch uncore cache Pipe Rejects event=0x42,umask=0x2 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_waymatch uncore cache Pipe Rejects event=0x42,umask=0x8 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.hacredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.idx_inpipe uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ipq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.irq_pmm uncore cache Pipe Rejects event=0x42,umask=0x20 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.irq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ismq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ivegrcredit uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.llc_ways_res uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.notallowsnoop uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.one_fsf_vic uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.one_rsp_con uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.pmm_memmode_tormatch_multi uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.pmm_memmode_tor_match uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.prq_pmm uncore cache Pipe Rejects event=0x42,umask=0x40 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ptl_inpipe uncore cache Pipe Rejects event=0x42,umask=0x80 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.rmw_setmatch uncore cache Pipe Rejects event=0x42,umask=0x1 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.rrq_setmatch_vicp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.setmatchentrywsct uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.sf_ways_res uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.topa_match uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.torid_match_go_p uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_ad_req uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_ad_rsp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_bl_ncb uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_bl_ncs uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_bl_rsp uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_bl_wb uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.way_match uncore cache Pipe Rejects event=0x42 01 Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=0x2 01 PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=0x1 01 PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR event=0x64,umask=0x4 01 PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR unc_cha_pmm_qos_occupancy.ddr_slow_fifo uncore cache UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO event=0x67,umask=0x1 01 : count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo unc_cha_read_no_credits.mc10 uncore cache CHA iMC CHNx READ Credits Empty : MC10 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only unc_cha_read_no_credits.mc11 uncore cache CHA iMC CHNx READ Credits Empty : MC11 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only unc_cha_read_no_credits.mc12 uncore cache CHA iMC CHNx READ Credits Empty : MC12 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only unc_cha_read_no_credits.mc13 uncore cache CHA iMC CHNx READ Credits Empty : MC13 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only unc_cha_read_no_credits.mc6 uncore cache CHA iMC CHNx READ Credits Empty : MC6 event=0x58,umask=0x40 01 CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only unc_cha_read_no_credits.mc7 uncore cache CHA iMC CHNx READ Credits Empty : MC7 event=0x58,umask=0x80 01 CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only unc_cha_read_no_credits.mc8 uncore cache CHA iMC CHNx READ Credits Empty : MC8 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only unc_cha_read_no_credits.mc9 uncore cache CHA iMC CHNx READ Credits Empty : MC9 event=0x58 01 CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only unc_cha_requests.invitoe uncore cache Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent event=0x50,umask=0x30 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_local uncore cache Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=0x10 01 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent event=0x50,umask=0x20 01 Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent event=0x50,umask=0x3 01 Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_local uncore cache Local read requests that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=0x1 01 Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.reads_remote uncore cache Remote read requests sent to the CHA's home agent event=0x50,umask=0x2 01 Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) unc_cha_requests.writes uncore cache Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent event=0x50,umask=0xc 01 Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_local uncore cache Local write requests that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=0x4 01 Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_remote uncore cache Remote write requests sent to the CHA's home agent event=0x50,umask=0x8 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_cha_ring_bounces_horz.ad uncore cache Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=0x1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.ak uncore cache Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=0x2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.bl uncore cache Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=0x4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.iv uncore cache Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=0x8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_vert.ad uncore cache Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=0x1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.ak uncore cache Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=0x2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.akc uncore cache Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.bl uncore cache Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=0x4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.iv uncore cache Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=0x8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_sink_starved_horz.ad uncore cache Sink Starvation on Horizontal Ring : AD event=0xad,umask=0x1 01 unc_cha_ring_sink_starved_horz.ak uncore cache Sink Starvation on Horizontal Ring : AK event=0xad,umask=0x2 01 unc_cha_ring_sink_starved_horz.ak_ag1 uncore cache Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_cha_ring_sink_starved_horz.bl uncore cache Sink Starvation on Horizontal Ring : BL event=0xad,umask=0x4 01 unc_cha_ring_sink_starved_horz.iv uncore cache Sink Starvation on Horizontal Ring : IV event=0xad,umask=0x8 01 unc_cha_ring_sink_starved_vert.ad uncore cache Sink Starvation on Vertical Ring : AD event=0xab,umask=0x1 01 unc_cha_ring_sink_starved_vert.ak uncore cache Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=0x2 01 unc_cha_ring_sink_starved_vert.akc uncore cache Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_cha_ring_sink_starved_vert.bl uncore cache Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=0x4 01 unc_cha_ring_sink_starved_vert.iv uncore cache Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=0x8 01 unc_cha_ring_src_thrtl uncore cache Source Throttle event=0xae 01 unc_cha_rxc_occupancy.irq uncore cache Ingress (from CMS) Occupancy : IRQ event=0x11,umask=0x1 01 Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxr_busy_starved.ad_all uncore cache Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_cha_rxr_busy_starved.ad_crd uncore cache Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.ad_uncrd uncore cache Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_all uncore cache Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_cha_rxr_busy_starved.bl_crd uncore cache Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_uncrd uncore cache Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_cha_rxr_bypass.ad_all uncore cache Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_cha_rxr_bypass.ad_crd uncore cache Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ad_uncrd uncore cache Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=0x1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ak uncore cache Transgress Ingress Bypass : AK event=0xe2,umask=0x2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.akc_uncrd uncore cache Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_all uncore cache Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_cha_rxr_bypass.bl_crd uncore cache Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_uncrd uncore cache Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=0x4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.iv uncore cache Transgress Ingress Bypass : IV event=0xe2,umask=0x8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_cha_rxr_crd_starved.ad_all uncore cache Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_cha_rxr_crd_starved.ad_crd uncore cache Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ad_uncrd uncore cache Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ak uncore cache Transgress Injection Starvation : AK event=0xe3,umask=0x2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_all uncore cache Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_cha_rxr_crd_starved.bl_crd uncore cache Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_uncrd uncore cache Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ifv uncore cache Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.iv uncore cache Transgress Injection Starvation : IV event=0xe3,umask=0x8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved_1 uncore cache Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_inserts.ad_all uncore cache Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_inserts.ad_crd uncore cache Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ad_uncrd uncore cache Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=0x1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ak uncore cache Transgress Ingress Allocations : AK event=0xe1,umask=0x2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.akc_uncrd uncore cache Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_all uncore cache Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_inserts.bl_crd uncore cache Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_uncrd uncore cache Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=0x4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.iv uncore cache Transgress Ingress Allocations : IV event=0xe1,umask=0x8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_all uncore cache Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_occupancy.ad_crd uncore cache Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_uncrd uncore cache Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=0x1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ak uncore cache Transgress Ingress Occupancy : AK event=0xe0,umask=0x2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.akc_uncrd uncore cache Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_all uncore cache Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_occupancy.bl_crd uncore cache Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_uncrd uncore cache Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=0x4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.iv uncore cache Transgress Ingress Occupancy : IV event=0xe0,umask=0x8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_cha_sf_eviction.e_state uncore cache Snoop filter capacity evictions for E-state entries event=0x3d,umask=0x2 01 Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.m_state uncore cache Snoop filter capacity evictions for M-state entries event=0x3d,umask=0x1 01 Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.s_state uncore cache Snoop filter capacity evictions for S-state entries event=0x3d,umask=0x4 01 Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent : Broadcast snoops for Local Requests event=0x51,umask=0x10 01 Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent : Broadcast snoops for Remote Requests event=0x51,umask=0x20 01 Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests unc_cha_snoops_sent.direct_local uncore cache Snoops Sent : Directed snoops for Local Requests event=0x51,umask=0x40 01 Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent : Directed snoops for Remote Requests event=0x51,umask=0x80 01 Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests unc_cha_snoops_sent.local uncore cache Snoops Sent : Snoops sent for Local Requests event=0x51,umask=0x4 01 Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests unc_cha_snoops_sent.remote uncore cache Snoops Sent : Snoops sent for Remote Requests event=0x51,umask=0x8 01 Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests unc_cha_snoop_resp.rspi uncore cache Snoop Responses Received : RspI event=0x5c,umask=0x1 01 Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) unc_cha_snoop_resp.rspifwd uncore cache Snoop Responses Received : RspIFwd event=0x5c,umask=0x4 01 Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states unc_cha_snoop_resp.rsps uncore cache Snoop Responses Received : RspS event=0x5c,umask=0x2 01 Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS unc_cha_snoop_resp.rspsfwd uncore cache Snoop Responses Received : RspSFwd event=0x5c,umask=0x8 01 Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local : RspSFwd event=0x5d,umask=0x8 01 Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=0x8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=0x8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=0x8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=0x8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_tor_inserts.all uncore cache TOR Inserts : All event=0x35,umask=0xc001ffff 01 TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ddr uncore cache TOR Inserts : DDR4 Access event=0x35 01 TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ddr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR event=0x35 11 unc_cha_tor_inserts.evict uncore cache TOR Inserts : SF/LLC Evictions event=0x35,umask=0x2 01 TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts : Just Hits event=0x35 01 TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia uncore cache TOR Inserts : All requests from iA Cores event=0x35,umask=0xc001ff01 01 TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_clflush uncore cache TOR Inserts : CLFlushes issued by iA Cores event=0x35,umask=0xc8c7ff01 01 TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_clflushopt uncore cache TOR Inserts : CLFlushOpts issued by iA Cores event=0x35,umask=0xc8d7ff01 01 TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_crd uncore cache TOR Inserts : CRDs issued by iA Cores event=0x35,umask=0xc80fff01 01 TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd uncore cache TOR Inserts : DRds issued by iA Cores event=0x35,umask=0xc817ff01 01 TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt uncore cache TOR Inserts : DRd_Opts issued by iA Cores event=0x35,umask=0xc827ff01 01 TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores event=0x35,umask=0xc8a7ff01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores event=0x35,umask=0xc897ff01 01 TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts : All requests from iA Cores that Hit the LLC event=0x35,umask=0xc001fd01 01 TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts : CRds issued by iA Cores that Hit the LLC event=0x35,umask=0xc80ffd01 01 TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_crd_pref uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC event=0x35,umask=0xc88ffd01 01 TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts : DRds issued by iA Cores that Hit the LLC event=0x35,umask=0xc817fd01 01 TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt uncore cache TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC event=0x35,umask=0xc827fd01 01 TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC event=0x35,umask=0xc8a7fd01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC event=0x35,umask=0xc897fd01 01 TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Hit LLC event=0x35,umask=0xcc47fd01 01 TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC event=0x35,umask=0xcccffd01 01 TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcrd uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE event=0x35,umask=0xcccffd01 11 unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC event=0x35,umask=0xccd7fd01 01 TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefdrd uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA event=0x35,umask=0xccd7fd01 11 unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC event=0x35,umask=0xccc7fd01 01 TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Hit the LLC event=0x35,umask=0xc807fd01 01 TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC event=0x35,umask=0xc887fd01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC event=0x35,umask=0xcc57fd01 01 TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_itom uncore cache TOR Inserts : ItoMs issued by iA Cores event=0x35,umask=0xcc47ff01 01 TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_itomcachenear uncore cache TOR Inserts : ItoMCacheNears issued by iA Cores event=0x35,umask=0xcd47ff01 01 TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores event=0x35,umask=0xcccfff01 01 TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores event=0x35,umask=0xccd7ff01 01 TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores event=0x35,umask=0xccc7ff01 01 TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts : All requests from iA Cores that Missed the LLC event=0x35,umask=0xc001fe01 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts : CRds issued by iA Cores that Missed the LLC event=0x35,umask=0xc80ffe01 01 TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_local uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc80efe01 01 TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc88ffe01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc88efe01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc88f7e01 01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_remote uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc80f7e01 01 TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC event=0x35,umask=0xc817fe01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc816fe01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt uncore cache TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC event=0x35,umask=0xc827fe01 01 TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC event=0x35,umask=0xc8a7fe01 01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc897fe01 01 TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8978601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache TOR Inserts; DRd Pref misses from local IA event=0x35,umask=0xc896fe01 01 TOR Inserts; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8978a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache TOR Inserts; DRd Pref misses from local IA event=0x35,umask=0xc8977e01 01 TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970601 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970a01 01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8177e01 01 TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170601 01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170a01 01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_full_streaming_wr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc867fe01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8678601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR event=0x35,umask=0xc8678601 11 unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8668601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR event=0x35,umask=0xc8668601 11 unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8668a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8678a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8670601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR event=0x35,umask=0xc8670601 11 unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8670a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Missed LLC event=0x35,umask=0xcc47fe01 01 TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC event=0x35,umask=0xcccffe01 01 TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC event=0x35,umask=0xccd7fe01 01 TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC event=0x35,umask=0xccc7fe01 01 TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc8668601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc8668a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc86e8601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc86e8a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_partial_streaming_wr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86ffe01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f8601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR event=0x35,umask=0xc86f8601 11 unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86e8601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR event=0x35,umask=0xc86e8601 11 unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86e8a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f8a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f0601 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR event=0x35,umask=0xc86f0601 11 unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f0a01 01 TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc8670601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory event=0x35,umask=0xc8670a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC event=0x35,umask=0xc807fe01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_local uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc806fe01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc887fe01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc886fe01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8877e01 01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8077e01 01 TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC event=0x35,umask=0xcc57fe01 01 TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_ucrdf uncore cache TOR Inserts : UCRdFs issued by iA Cores that Missed LLC event=0x35,umask=0xc877de01 01 TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores that Missed the LLC event=0x35,umask=0xc86ffe01 01 TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores that Missed the LLC event=0x35,umask=0xc867fe01 01 TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc8678601 01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc8678a01 01 TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc86f8601 01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc86f8a01 01 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wil uncore cache TOR Inserts : WiLs issued by iA Cores that Missed LLC event=0x35,umask=0xc87fde01 01 TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo uncore cache TOR Inserts : RFOs issued by iA Cores event=0x35,umask=0xc807ff01 01 TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores event=0x35,umask=0xc887ff01 01 TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores event=0x35,umask=0xcc57ff01 01 TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbeftoi uncore cache TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc37ff01 01 WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoe uncore cache TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc2fff01 01 WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbstoi uncore cache TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs event=0x35,umask=0xcc67ff01 01 WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores event=0x35,umask=0xc86fff01 01 TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores event=0x35,umask=0xc867ff01 01 TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts : All requests from IO Devices event=0x35,umask=0xc001ff04 01 TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_clflush uncore cache TOR Inserts : CLFlushes issued by IO Devices event=0x35,umask=0xc8c3ff04 01 TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit uncore cache TOR Inserts : All requests from IO Devices that hit the LLC event=0x35,umask=0xc001fd04 01 TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itom uncore cache TOR Inserts : ItoMs issued by IO Devices that Hit the LLC event=0x35,umask=0xcc43fd04 01 TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC event=0x35,umask=0xc8f3fd04 01 TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_rfo uncore cache TOR Inserts : RFOs issued by IO Devices that hit the LLC event=0x35,umask=0xc803fd04 01 TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom uncore cache TOR Inserts : ItoMs issued by IO Devices event=0x35,umask=0xcc43ff04 01 TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices event=0x35,umask=0xcd43ff04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_local uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory event=0x35,umask=0xcd42ff04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_remote uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory event=0x35,umask=0xcd437f04 01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_local uncore cache TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory event=0x35,umask=0xcc42ff04 01 TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_remote uncore cache TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory event=0x35,umask=0xcc437f04 01 TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss uncore cache TOR Inserts : All requests from IO Devices that missed the LLC event=0x35,umask=0xc001fe04 01 TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts : ItoMs issued by IO Devices that missed the LLC event=0x35,umask=0xcc43fe04 01 TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC event=0x35,umask=0xc8f3fe04 01 TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts : RFOs issued by IO Devices that missed the LLC event=0x35,umask=0xc803fe04 01 TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices event=0x35,umask=0xc8f3ff04 01 TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_rfo uncore cache TOR Inserts : RFOs issued by IO Devices event=0x35,umask=0xc803ff04 01 TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by IO Devices event=0x35,umask=0xcc23ff04 01 TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ipq uncore cache TOR Inserts : IPQ event=0x35,umask=0x8 01 TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.irq_ia uncore cache TOR Inserts : IRQ - iA event=0x35,umask=0x1 01 TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core unc_cha_tor_inserts.irq_non_ia uncore cache TOR Inserts : IRQ - Non iA event=0x35,umask=0x10 01 TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.isoc uncore cache TOR Inserts : Just ISOC event=0x35 01 TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.local_tgt uncore cache TOR Inserts : Just Local Targets event=0x35 01 TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.loc_all uncore cache TOR Inserts : All from Local iA and IO event=0x35,umask=0xc000ff05 01 TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests unc_cha_tor_inserts.loc_ia uncore cache TOR Inserts : All from Local iA event=0x35,umask=0xc000ff01 01 TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores unc_cha_tor_inserts.loc_io uncore cache TOR Inserts : All from Local IO event=0x35,umask=0xc000ff04 01 TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic unc_cha_tor_inserts.match_opc uncore cache TOR Inserts : Match the Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.miss uncore cache TOR Inserts : Just Misses event=0x35 01 TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.mmcfg uncore cache TOR Inserts : MMCFG Access event=0x35 01 TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.nearmem uncore cache TOR Inserts : Just NearMem event=0x35 01 TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.noncoh uncore cache TOR Inserts : Just NonCoherent event=0x35 01 TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.not_nearmem uncore cache TOR Inserts : Just NotNearMem event=0x35 01 TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.pmm uncore cache TOR Inserts : PMM Access event=0x35 01 TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.premorph_opc uncore cache TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x35 01 TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.prq_iosf uncore cache TOR Inserts : PRQ - IOSF event=0x35,umask=0x4 01 TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device unc_cha_tor_inserts.prq_non_iosf uncore cache TOR Inserts : PRQ - Non IOSF event=0x35,umask=0x20 01 TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.remote_tgt uncore cache TOR Inserts : Just Remote Targets event=0x35 01 TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.rrq uncore cache TOR Inserts : RRQ event=0x35,umask=0x40 01 TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.wbq uncore cache TOR Inserts : WBQ event=0x35,umask=0x80 01 TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ddr uncore cache TOR Occupancy : DDR4 Access event=0x36 01 TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.evict uncore cache TOR Occupancy : SF/LLC Evictions event=0x36,umask=0x2 01 TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy : Just Hits event=0x36 01 TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia uncore cache TOR Occupancy : All requests from iA Cores event=0x36,umask=0xc001ff01 01 TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy : CRDs issued by iA Cores event=0x36,umask=0xc80fff01 01 TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy : DRds issued by iA Cores event=0x36,umask=0xc817ff01 01 TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk event=0x36,umask=0xc837ff01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy : DRd_Opts issued by iA Cores event=0x36,umask=0xc827ff01 01 TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores event=0x36,umask=0xc8a7ff01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores event=0x36,umask=0xc897ff01 01 TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy : All requests from iA Cores that Hit the LLC event=0x36,umask=0xc001fd01 01 TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Hit the LLC event=0x36,umask=0xc80ffd01 01 TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC event=0x36,umask=0xc88ffd01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Hit the LLC event=0x36,umask=0xc817fd01 01 TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC event=0x36,umask=0xc837fd01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC event=0x36,umask=0xc827fd01 01 TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC event=0x36,umask=0xc8a7fd01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC event=0x36,umask=0xc897fd01 01 TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC event=0x36,umask=0xcccffd01 01 TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC event=0x36,umask=0xccd7fd01 01 TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC event=0x36,umask=0xccc7fd01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Hit the LLC event=0x36,umask=0xc807fd01 01 TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC event=0x36,umask=0xc887fd01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores event=0x36,umask=0xcccfff01 01 TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores event=0x36,umask=0xccd7ff01 01 TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores event=0x36,umask=0xccc7ff01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy : All requests from iA Cores that Missed the LLC event=0x36,umask=0xc001fe01 01 TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Missed the LLC event=0x36,umask=0xc80ffe01 01 TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc88ffe01 01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC event=0x36,umask=0xc817fe01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC event=0x36,umask=0xc837fe01 01 TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601 01 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc816fe01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC event=0x36,umask=0xc827fe01 01 TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC event=0x36,umask=0xc8a7fe01 01 TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01 01 TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc897fe01 01 TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8177e01 01 TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_full_streaming_wr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc867fe01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8678601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_local_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8668601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_local_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8668a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8678a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_remote_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8670601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_remote_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8670a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC event=0x36,umask=0xcccffe01 01 TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC event=0x36,umask=0xccd7fe01 01 TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC event=0x36,umask=0xccc7fe01 01 TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_partial_streaming_wr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86ffe01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f8601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_local_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86e8601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_local_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86e8a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f8a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_remote_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f0601 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_remote_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f0a01 01 TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC event=0x36,umask=0xc807fe01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc806fe01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc887fe01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc886fe01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8877e01 01 TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8077e01 01 TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_specitom uncore cache TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC event=0x36,umask=0xcc57fe01 01 TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores event=0x36,umask=0xc807ff01 01 TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores event=0x36,umask=0xc887ff01 01 TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy : All requests from IO Devices event=0x36,umask=0xc001ff04 01 TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy : All requests from IO Devices that hit the LLC event=0x36,umask=0xc001fd04 01 TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC event=0x36,umask=0xcc43fd04 01 TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC event=0x36,umask=0xc8f3fd04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices that hit the LLC event=0x36,umask=0xc803fd04 01 TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices event=0x36,umask=0xcc43ff04 01 TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices event=0x36,umask=0xcd43ff04 01 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy : All requests from IO Devices that missed the LLC event=0x36,umask=0xc001fe04 01 TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices that missed the LLC event=0x36,umask=0xcc43fe04 01 TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC event=0x36,umask=0xc8f3fe04 01 TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices that missed the LLC event=0x36,umask=0xc803fe04 01 TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices event=0x36,umask=0xc8f3ff04 01 TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices event=0x36,umask=0xc803ff04 01 TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy : IPQ event=0x36,umask=0x8 01 TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.irq_ia uncore cache TOR Occupancy : IRQ - iA event=0x36,umask=0x1 01 TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core unc_cha_tor_occupancy.irq_non_ia uncore cache TOR Occupancy : IRQ - Non iA event=0x36,umask=0x10 01 TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.isoc uncore cache TOR Occupancy : Just ISOC event=0x36 01 TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.local_tgt uncore cache TOR Occupancy : Just Local Targets event=0x36 01 TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy : All from Local iA and IO event=0x36,umask=0xc000ff05 01 TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy : All from Local iA event=0x36,umask=0xc000ff01 01 TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy : All from Local IO event=0x36,umask=0xc000ff04 01 TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic unc_cha_tor_occupancy.match_opc uncore cache TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.miss uncore cache TOR Occupancy : Just Misses event=0x36 01 TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.mmcfg uncore cache TOR Occupancy : MMCFG Access event=0x36 01 TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.nearmem uncore cache TOR Occupancy : Just NearMem event=0x36 01 TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.noncoh uncore cache TOR Occupancy : Just NonCoherent event=0x36 01 TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.not_nearmem uncore cache TOR Occupancy : Just NotNearMem event=0x36 01 TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.pmm uncore cache TOR Occupancy : PMM Access event=0x36 01 TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.premorph_opc uncore cache TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x36 01 TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.prq uncore cache TOR Occupancy : PRQ - IOSF event=0x36,umask=0x4 01 TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device unc_cha_tor_occupancy.prq_non_iosf uncore cache TOR Occupancy : PRQ - Non IOSF event=0x36,umask=0x20 01 TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.remote_tgt uncore cache TOR Occupancy : Just Remote Targets event=0x36 01 TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_txr_horz_ads_used.ad_all uncore cache CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_ads_used.ad_crd uncore cache CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ad_uncrd uncore cache CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=0x1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_all uncore cache CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_ads_used.bl_crd uncore cache CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_uncrd uncore cache CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=0x4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_all uncore cache CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_bypass.ad_crd uncore cache CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_uncrd uncore cache CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=0x1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ak uncore cache CMS Horizontal Bypass Used : AK event=0xa7,umask=0x2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.akc_uncrd uncore cache CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_all uncore cache CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_bypass.bl_crd uncore cache CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_uncrd uncore cache CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=0x4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.iv uncore cache CMS Horizontal Bypass Used : IV event=0xa7,umask=0x8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_cycles_full.ad_all uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_full.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ad_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ak uncore cache Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.akc_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_all uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_full.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.iv uncore cache Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_all uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_ne.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ak uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.akc_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_all uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_ne.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.iv uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_all uncore cache CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_inserts.ad_crd uncore cache CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_uncrd uncore cache CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=0x1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ak uncore cache CMS Horizontal Egress Inserts : AK event=0xa1,umask=0x2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.akc_uncrd uncore cache CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_all uncore cache CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_inserts.bl_crd uncore cache CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_uncrd uncore cache CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=0x4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.iv uncore cache CMS Horizontal Egress Inserts : IV event=0xa1,umask=0x8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_nack.ad_all uncore cache CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_cha_txr_horz_nack.ad_crd uncore cache CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ad_uncrd uncore cache CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=0x1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ak uncore cache CMS Horizontal Egress NACKs : AK event=0xa4,umask=0x2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.akc_uncrd uncore cache CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_all uncore cache CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_cha_txr_horz_nack.bl_crd uncore cache CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_uncrd uncore cache CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=0x4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.iv uncore cache CMS Horizontal Egress NACKs : IV event=0xa4,umask=0x8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_occupancy.ad_all uncore cache CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_occupancy.ad_crd uncore cache CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ad_uncrd uncore cache CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=0x1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ak uncore cache CMS Horizontal Egress Occupancy : AK event=0xa0,umask=0x2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.akc_uncrd uncore cache CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_all uncore cache CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_occupancy.bl_crd uncore cache CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_uncrd uncore cache CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=0x4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.iv uncore cache CMS Horizontal Egress Occupancy : IV event=0xa0,umask=0x8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_starved.ad_all uncore cache CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_cha_txr_horz_starved.ad_uncrd uncore cache CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.ak uncore cache CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=0x2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.akc_uncrd uncore cache CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.bl_all uncore cache CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_cha_txr_horz_starved.bl_uncrd uncore cache CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.iv uncore cache CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=0x8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag0 uncore cache CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag1 uncore cache CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag0 uncore cache CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=0x2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag1 uncore cache CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag0 uncore cache CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag1 uncore cache CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.iv_ag1 uncore cache CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=0x8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass_1.akc_ag0 uncore cache CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=0x1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass_1.akc_ag1 uncore cache CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=0x2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_cycles_full0.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full0.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_full0.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_full0.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_full0.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_full0.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_full0.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_full1.akc_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full1.akc_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne0.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne0.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_cycles_ne0.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne0.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_ne0.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_ne0.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_ne0.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_ne1.akc_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne1.akc_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts0.ad_ag0 uncore cache CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=0x1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts0.ad_ag1 uncore cache CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_inserts0.ak_ag0 uncore cache CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=0x2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts0.ak_ag1 uncore cache CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_inserts0.bl_ag0 uncore cache CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=0x4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_inserts0.bl_ag1 uncore cache CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_inserts0.iv_ag0 uncore cache CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=0x8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_inserts1.akc_ag0 uncore cache CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=0x1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts1.akc_ag1 uncore cache CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=0x2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_nack0.ad_ag0 uncore cache CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=0x1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ad_ag1 uncore cache CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ak_ag0 uncore cache CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=0x2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ak_ag1 uncore cache CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.bl_ag0 uncore cache CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=0x4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.bl_ag1 uncore cache CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.iv_ag0 uncore cache CMS Vertical Egress NACKs : IV event=0x98,umask=0x8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack1.akc_ag0 uncore cache CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=0x1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack1.akc_ag1 uncore cache CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=0x2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_occupancy0.ad_ag0 uncore cache CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=0x1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy0.ad_ag1 uncore cache CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_cha_txr_vert_occupancy0.ak_ag0 uncore cache CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=0x2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_occupancy0.ak_ag1 uncore cache CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_occupancy0.bl_ag0 uncore cache CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=0x4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_occupancy0.bl_ag1 uncore cache CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_occupancy0.iv_ag0 uncore cache CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=0x8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_cha_txr_vert_occupancy1.akc_ag0 uncore cache CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=0x1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy1.akc_ag1 uncore cache CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=0x2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_cha_txr_vert_starved0.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=0x1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=0x2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=0x4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.iv_ag0 uncore cache CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=0x8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.akc_ag0 uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.akc_ag1 uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=0x2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.tgc uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_vert_ring_ad_in_use.dn_even uncore cache Vertical AD Ring In Use : Down and Even event=0xb0,umask=0x4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.dn_odd uncore cache Vertical AD Ring In Use : Down and Odd event=0xb0,umask=0x8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_even uncore cache Vertical AD Ring In Use : Up and Even event=0xb0,umask=0x1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_odd uncore cache Vertical AD Ring In Use : Up and Odd event=0xb0,umask=0x2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.dn_even uncore cache Vertical AKC Ring In Use : Down and Even event=0xb4,umask=0x4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.dn_odd uncore cache Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=0x8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.up_even uncore cache Vertical AKC Ring In Use : Up and Even event=0xb4,umask=0x1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.up_odd uncore cache Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=0x2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_even uncore cache Vertical AK Ring In Use : Down and Even event=0xb1,umask=0x4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_odd uncore cache Vertical AK Ring In Use : Down and Odd event=0xb1,umask=0x8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_even uncore cache Vertical AK Ring In Use : Up and Even event=0xb1,umask=0x1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_odd uncore cache Vertical AK Ring In Use : Up and Odd event=0xb1,umask=0x2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_even uncore cache Vertical BL Ring in Use : Down and Even event=0xb2,umask=0x4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_odd uncore cache Vertical BL Ring in Use : Down and Odd event=0xb2,umask=0x8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_even uncore cache Vertical BL Ring in Use : Up and Even event=0xb2,umask=0x1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_odd uncore cache Vertical BL Ring in Use : Up and Odd event=0xb2,umask=0x2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_iv_in_use.dn uncore cache Vertical IV Ring in Use : Down event=0xb3,umask=0x4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_iv_in_use.up uncore cache Vertical IV Ring in Use : Up event=0xb3,umask=0x1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_tgc_in_use.dn_even uncore cache Vertical TGC Ring In Use : Down and Even event=0xb5,umask=0x4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.dn_odd uncore cache Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=0x8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.up_even uncore cache Vertical TGC Ring In Use : Up and Even event=0xb5,umask=0x1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.up_odd uncore cache Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=0x2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_write_no_credits.mc10 uncore cache CHA iMC CHNx WRITE Credits Empty : MC10 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only unc_cha_write_no_credits.mc11 uncore cache CHA iMC CHNx WRITE Credits Empty : MC11 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only unc_cha_write_no_credits.mc12 uncore cache CHA iMC CHNx WRITE Credits Empty : MC12 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only unc_cha_write_no_credits.mc13 uncore cache CHA iMC CHNx WRITE Credits Empty : MC13 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only unc_cha_write_no_credits.mc6 uncore cache CHA iMC CHNx WRITE Credits Empty : MC6 event=0x5a,umask=0x40 01 CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only unc_cha_write_no_credits.mc7 uncore cache CHA iMC CHNx WRITE Credits Empty : MC7 event=0x5a,umask=0x80 01 CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only unc_cha_write_no_credits.mc8 uncore cache CHA iMC CHNx WRITE Credits Empty : MC8 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only unc_cha_write_no_credits.mc9 uncore cache CHA iMC CHNx WRITE Credits Empty : MC9 event=0x5a 01 CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy : Any Source event=0xf,umask=0x1 01 Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port unc_i_cache_total_occupancy.iv_q uncore interconnect Total Write Cache Occupancy : Snoops event=0xf,umask=0x2 01 Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_clockticks uncore interconnect Clockticks of the IO coherency tracker (IRP) event=0x1 01 unc_i_coherent_ops.clflush uncore interconnect Coherent Ops : CLFlush event=0x10,umask=0x80 01 Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops : WbMtoI event=0x10,umask=0x40 01 Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP unc_i_p2p_inserts uncore interconnect P2P Requests event=0x14 01 P2P Requests : P2P requests from the ITC unc_i_p2p_occupancy uncore interconnect P2P Occupancy event=0x15 01 P2P Occupancy : P2P B & S Queue Occupancy unc_i_p2p_transactions.cmpl uncore interconnect P2P Transactions : P2P completions event=0x13,umask=0x8 01 unc_i_p2p_transactions.loc uncore interconnect P2P Transactions : match if local only event=0x13,umask=0x40 01 unc_i_p2p_transactions.loc_and_tgt_match uncore interconnect P2P Transactions : match if local and target matches event=0x13,umask=0x80 01 unc_i_p2p_transactions.msg uncore interconnect P2P Transactions : P2P Message event=0x13,umask=0x4 01 unc_i_p2p_transactions.rd uncore interconnect P2P Transactions : P2P reads event=0x13,umask=0x1 01 unc_i_p2p_transactions.rem uncore interconnect P2P Transactions : Match if remote only event=0x13,umask=0x10 01 unc_i_p2p_transactions.rem_and_tgt_match uncore interconnect P2P Transactions : match if remote and target matches event=0x13,umask=0x20 01 unc_i_p2p_transactions.wr uncore interconnect P2P Transactions : P2P Writes event=0x13,umask=0x2 01 unc_i_transactions.atomic uncore interconnect Inbound Transaction Count : Atomic event=0x11,umask=0x10 01 Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count : Other event=0x11,umask=0x20 01 Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions unc_i_transactions.writes uncore interconnect Inbound Transaction Count : Writes event=0x11,umask=0x2 01 Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_txr2_ad01_stall_credit_cycles uncore interconnect UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES event=0x1c 01 : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2 unc_m2m_ag0_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=0x8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=0x8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=0x8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=0x8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=0x8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=0x8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=0x8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=0x8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_bypass_m2m_egress.not_taken uncore interconnect M2M to iMC Bypass : Not Taken event=0x22,umask=0x2 01 unc_m2m_bypass_m2m_egress.taken uncore interconnect M2M to iMC Bypass : Taken event=0x22,umask=0x1 01 unc_m2m_bypass_m2m_ingress.not_taken uncore interconnect M2M to iMC Bypass : Not Taken event=0x21,umask=0x2 01 unc_m2m_bypass_m2m_ingress.taken uncore interconnect M2M to iMC Bypass : Taken event=0x21,umask=0x1 01 unc_m2m_clockticks uncore interconnect Clockticks of the mesh to memory (M2M) event=0 01 unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode, which bypasses the CHA, was disabled event=0x24 01 unc_m2m_direct2core_not_taken_notforked uncore interconnect UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED event=0x60 01 unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction was overridden event=0x25 01 unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel UPI transactions were overridden event=0x28 01 unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when Direct2UPI was Disabled event=0x27 01 unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel UPI was overridden event=0x29 01 Clockticks of the mesh to PCI (M2P) unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x2a,umask=0x80 01 unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x2a,umask=0x10 01 unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit : On NonDirty Line in L State event=0x2a,umask=0x40 01 unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x2a,umask=0x20 01 unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x2a,umask=0x8 01 unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x2a,umask=0x1 01 unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit : On Dirty Line in L State event=0x2a,umask=0x4 01 unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x2a,umask=0x2 01 unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory Lookups : Found in any state event=0x2d,umask=0x1 01 unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory Lookups : Found in A state event=0x2d,umask=0x8 01 unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory Lookups : Found in I state event=0x2d,umask=0x2 01 unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory Lookups : Found in S state event=0x2d,umask=0x4 01 unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x2b,umask=0x80 01 unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x2b,umask=0x10 01 unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss : On NonDirty Line in L State event=0x2b,umask=0x40 01 unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x2b,umask=0x20 01 unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x2b,umask=0x8 01 unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x2b,umask=0x1 01 unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss : On Dirty Line in L State event=0x2b,umask=0x4 01 unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x2b,umask=0x2 01 unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode event=0x2e,umask=0x1 01 unc_m2m_distress_asserted.dpt_local uncore interconnect Distress signal asserted : DPT Local event=0xaf,umask=0x4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m2m_distress_asserted.dpt_nonlocal uncore interconnect Distress signal asserted : DPT Remote event=0xaf,umask=0x8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m2m_distress_asserted.dpt_stall_iv uncore interconnect Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m2m_distress_asserted.dpt_stall_nocrd uncore interconnect Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m2m_distress_asserted.horz uncore interconnect Distress signal asserted : Horizontal event=0xaf,umask=0x2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m2m_distress_asserted.pmm_local uncore interconnect Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2m_distress_asserted.pmm_nonlocal uncore interconnect Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2m_distress_asserted.vert uncore interconnect Distress signal asserted : Vertical event=0xaf,umask=0x1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m2m_distress_pmm uncore interconnect UNC_M2M_DISTRESS_PMM event=0xf2 01 unc_m2m_distress_pmm_memmode uncore interconnect UNC_M2M_DISTRESS_PMM_MEMMODE event=0xf1 01 unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x4 01 Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x1 01 Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use : Left and Even event=0xb6,umask=0x1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=0x2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use : Right and Even event=0xb6,umask=0x4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=0x8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xbb,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xbb,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xb7,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xb7,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use : Left and Even event=0xb8,umask=0x1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=0x2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use : Right and Even event=0xb8,umask=0x4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=0x8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use : Left event=0xb9,umask=0x1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use : Right event=0xb9,umask=0x4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_imc_reads.all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - All Channels event=0x37,umask=0x704 01 unc_m2m_imc_reads.ch0_all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - Ch0 event=0x37,umask=0x104 01 unc_m2m_imc_reads.ch0_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch0 event=0x37,umask=0x140 01 unc_m2m_imc_reads.ch0_isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - Ch0 event=0x37,umask=0x102 01 unc_m2m_imc_reads.ch0_normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - Ch0 event=0x37,umask=0x101 01 unc_m2m_imc_reads.ch0_to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - Ch0 event=0x37,umask=0x110 01 unc_m2m_imc_reads.ch0_to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - Ch0 event=0x37,umask=0x108 01 unc_m2m_imc_reads.ch0_to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - Ch0 event=0x37,umask=0x120 01 M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC unc_m2m_imc_reads.ch1_all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - Ch1 event=0x37,umask=0x204 01 unc_m2m_imc_reads.ch1_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch1 event=0x37,umask=0x240 01 unc_m2m_imc_reads.ch1_isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - Ch1 event=0x37,umask=0x202 01 unc_m2m_imc_reads.ch1_normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - Ch1 event=0x37,umask=0x201 01 unc_m2m_imc_reads.ch1_to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - Ch1 event=0x37,umask=0x210 01 unc_m2m_imc_reads.ch1_to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - Ch1 event=0x37,umask=0x208 01 unc_m2m_imc_reads.ch1_to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - Ch1 event=0x37,umask=0x220 01 M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC unc_m2m_imc_reads.ch2_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch2 event=0x37,umask=0x440 01 unc_m2m_imc_reads.from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - All Channels event=0x37,umask=0x740 01 unc_m2m_imc_reads.isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - All Channels event=0x37,umask=0x702 01 unc_m2m_imc_reads.normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - All Channels event=0x37,umask=0x701 01 unc_m2m_imc_reads.to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - All Channels event=0x37,umask=0x710 01 unc_m2m_imc_reads.to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - All Channels event=0x37,umask=0x708 01 unc_m2m_imc_reads.to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - All Channels event=0x37,umask=0x720 01 unc_m2m_imc_writes.all uncore interconnect M2M Writes Issued to iMC : All Writes - All Channels event=0x38,umask=0x1c10 01 unc_m2m_imc_writes.ch0_all uncore interconnect M2M Writes Issued to iMC : All Writes - Ch0 event=0x38,umask=0x410 01 unc_m2m_imc_writes.ch0_from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - Ch0 event=0x38 01 unc_m2m_imc_writes.ch0_full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0 event=0x38,umask=0x401 01 unc_m2m_imc_writes.ch0_full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - Ch0 event=0x38,umask=0x404 01 unc_m2m_imc_writes.ch0_ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - Ch0 event=0x38 01 unc_m2m_imc_writes.ch0_ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0 event=0x38 01 unc_m2m_imc_writes.ch0_partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0 event=0x38,umask=0x402 01 unc_m2m_imc_writes.ch0_partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - Ch0 event=0x38,umask=0x408 01 unc_m2m_imc_writes.ch0_to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - Ch0 event=0x38,umask=0x440 01 unc_m2m_imc_writes.ch0_to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - Ch0 event=0x38,umask=0x420 01 unc_m2m_imc_writes.ch0_to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - Ch0 event=0x38,umask=0x480 01 M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.ch1_all uncore interconnect M2M Writes Issued to iMC : All Writes - Ch1 event=0x38,umask=0x810 01 unc_m2m_imc_writes.ch1_from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - Ch1 event=0x38 01 unc_m2m_imc_writes.ch1_full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1 event=0x38,umask=0x801 01 unc_m2m_imc_writes.ch1_full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - Ch1 event=0x38,umask=0x804 01 unc_m2m_imc_writes.ch1_ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - Ch1 event=0x38 01 unc_m2m_imc_writes.ch1_ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1 event=0x38 01 unc_m2m_imc_writes.ch1_partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1 event=0x38,umask=0x802 01 unc_m2m_imc_writes.ch1_partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - Ch1 event=0x38,umask=0x808 01 unc_m2m_imc_writes.ch1_to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - Ch1 event=0x38,umask=0x840 01 unc_m2m_imc_writes.ch1_to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - Ch1 event=0x38,umask=0x820 01 unc_m2m_imc_writes.ch1_to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - Ch1 event=0x38,umask=0x880 01 M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - All Channels event=0x38 01 unc_m2m_imc_writes.full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels event=0x38,umask=0x1c01 01 unc_m2m_imc_writes.full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - All Channels event=0x38,umask=0x1c04 01 unc_m2m_imc_writes.ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - All Channels event=0x38 01 unc_m2m_imc_writes.ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels event=0x38 01 unc_m2m_imc_writes.partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels event=0x38,umask=0x1c02 01 unc_m2m_imc_writes.partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - All Channels event=0x38,umask=0x1c08 01 unc_m2m_imc_writes.to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - All Channels event=0x38,umask=0x1c40 01 unc_m2m_imc_writes.to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - All Channels event=0x38,umask=0x1c20 01 unc_m2m_imc_writes.to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - All Channels event=0x38,umask=0x1c80 01 unc_m2m_mirr_wrq_inserts uncore interconnect Write Tracker Inserts event=0x64 01 unc_m2m_mirr_wrq_occupancy uncore interconnect Write Tracker Occupancy event=0x65 01 unc_m2m_misc_external.mbe_inst0 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=0x1 01 unc_m2m_misc_external.mbe_inst1 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=0x2 01 unc_m2m_pkt_match.mc uncore interconnect Number Packet Header Matches : MC Match event=0x4c,umask=0x2 01 unc_m2m_pkt_match.mesh uncore interconnect Number Packet Header Matches : Mesh Match event=0x4c,umask=0x1 01 unc_m2m_prefcam_cis_drops uncore interconnect UNC_M2M_PREFCAM_CIS_DROPS event=0x73 01 unc_m2m_prefcam_cycles_full.allch uncore interconnect Prefetch CAM Cycles Full : All Channels event=0x6b,umask=0x7 01 unc_m2m_prefcam_cycles_full.ch0 uncore interconnect Prefetch CAM Cycles Full : Channel 0 event=0x6b,umask=0x1 01 unc_m2m_prefcam_cycles_full.ch1 uncore interconnect Prefetch CAM Cycles Full : Channel 1 event=0x6b,umask=0x2 01 unc_m2m_prefcam_cycles_full.ch2 uncore interconnect Prefetch CAM Cycles Full : Channel 2 event=0x6b,umask=0x4 01 unc_m2m_prefcam_cycles_ne.allch uncore interconnect Prefetch CAM Cycles Not Empty : All Channels event=0x6c,umask=0x7 01 unc_m2m_prefcam_cycles_ne.ch0 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 0 event=0x6c,umask=0x1 01 unc_m2m_prefcam_cycles_ne.ch1 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 1 event=0x6c,umask=0x2 01 unc_m2m_prefcam_cycles_ne.ch2 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 2 event=0x6c,umask=0x4 01 unc_m2m_prefcam_deallocs.ch0_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x1 01 unc_m2m_prefcam_deallocs.ch0_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x2 01 unc_m2m_prefcam_deallocs.ch0_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x4 01 unc_m2m_prefcam_deallocs.ch0_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x8 01 unc_m2m_prefcam_deallocs.ch1_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x10 01 unc_m2m_prefcam_deallocs.ch1_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x20 01 unc_m2m_prefcam_deallocs.ch1_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x40 01 unc_m2m_prefcam_deallocs.ch1_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x80 01 unc_m2m_prefcam_deallocs.ch2_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_deallocs.ch2_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_deallocs.ch2_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_deallocs.ch2_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e 01 unc_m2m_prefcam_demand_drops.ch0_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 0 event=0x6f,umask=0x2 01 unc_m2m_prefcam_demand_drops.ch0_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 0 event=0x6f,umask=0x1 01 unc_m2m_prefcam_demand_drops.ch1_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 1 event=0x6f,umask=0x8 01 unc_m2m_prefcam_demand_drops.ch1_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 1 event=0x6f,umask=0x4 01 unc_m2m_prefcam_demand_drops.ch2_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 2 event=0x6f,umask=0x20 01 unc_m2m_prefcam_demand_drops.ch2_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 2 event=0x6f,umask=0x10 01 unc_m2m_prefcam_demand_drops.upi_allch uncore interconnect Data Prefetches Dropped : UPI - All Channels event=0x6f,umask=0x2a 01 unc_m2m_prefcam_demand_drops.xpt_allch uncore interconnect Data Prefetches Dropped : XPT - All Channels event=0x6f,umask=0x15 01 unc_m2m_prefcam_demand_merge.ch0_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0 event=0x74,umask=0x1 01 Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0 unc_m2m_prefcam_demand_merge.ch1_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1 event=0x74,umask=0x4 01 Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1 unc_m2m_prefcam_demand_merge.ch2_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2 event=0x74,umask=0x10 01 Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2 unc_m2m_prefcam_demand_merge.xptupi_allch uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- All Channels event=0x74,umask=0x15 01 Demands Merged with CAMed Prefetches : XPT & UPI - All Channels unc_m2m_prefcam_demand_no_merge.ch0_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0 event=0x75,umask=0x1 01 Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0 unc_m2m_prefcam_demand_no_merge.ch1_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1 event=0x75,umask=0x4 01 Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1 unc_m2m_prefcam_demand_no_merge.ch2_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2 event=0x75,umask=0x10 01 unc_m2m_prefcam_demand_no_merge.xptupi_allch uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels event=0x75,umask=0x15 01 unc_m2m_prefcam_drop_reasons_ch0.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x10 01 unc_m2m_prefcam_drop_reasons_ch0.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x2 01 unc_m2m_prefcam_drop_reasons_ch0.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x20 01 unc_m2m_prefcam_drop_reasons_ch0.pf_cam_full uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x40 01 unc_m2m_prefcam_drop_reasons_ch0.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x4 01 unc_m2m_prefcam_drop_reasons_ch0.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x1 01 unc_m2m_prefcam_drop_reasons_ch0.rpq_proxy uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70 01 unc_m2m_prefcam_drop_reasons_ch0.stop_b2b uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x8 01 unc_m2m_prefcam_drop_reasons_ch0.upi_thresh uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70 01 unc_m2m_prefcam_drop_reasons_ch0.wpq_proxy uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x80 01 unc_m2m_prefcam_drop_reasons_ch0.xpt_thresh uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70 01 unc_m2m_prefcam_drop_reasons_ch1.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x10 01 unc_m2m_prefcam_drop_reasons_ch1.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x2 01 unc_m2m_prefcam_drop_reasons_ch1.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x20 01 unc_m2m_prefcam_drop_reasons_ch1.pf_cam_full uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x40 01 unc_m2m_prefcam_drop_reasons_ch1.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x4 01 unc_m2m_prefcam_drop_reasons_ch1.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x1 01 unc_m2m_prefcam_drop_reasons_ch1.rpq_proxy uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71 01 unc_m2m_prefcam_drop_reasons_ch1.stop_b2b uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x8 01 unc_m2m_prefcam_drop_reasons_ch1.upi_thresh uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71 01 unc_m2m_prefcam_drop_reasons_ch1.wpq_proxy uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x80 01 unc_m2m_prefcam_drop_reasons_ch1.xpt_thresh uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71 01 unc_m2m_prefcam_drop_reasons_ch2.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x10 01 unc_m2m_prefcam_drop_reasons_ch2.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x2 01 unc_m2m_prefcam_drop_reasons_ch2.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x20 01 unc_m2m_prefcam_drop_reasons_ch2.pf_cam_full uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x40 01 unc_m2m_prefcam_drop_reasons_ch2.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x4 01 unc_m2m_prefcam_drop_reasons_ch2.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x1 01 unc_m2m_prefcam_drop_reasons_ch2.rpq_proxy uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72 01 unc_m2m_prefcam_drop_reasons_ch2.stop_b2b uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x8 01 unc_m2m_prefcam_drop_reasons_ch2.upi_thresh uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72 01 unc_m2m_prefcam_drop_reasons_ch2.wpq_proxy uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x80 01 unc_m2m_prefcam_drop_reasons_ch2.xpt_thresh uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72 01 unc_m2m_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x6d,umask=0x2 01 unc_m2m_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x6d,umask=0x1 01 unc_m2m_prefcam_inserts.ch1_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 1 event=0x6d,umask=0x8 01 unc_m2m_prefcam_inserts.ch1_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 1 event=0x6d,umask=0x4 01 unc_m2m_prefcam_inserts.ch2_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 2 event=0x6d,umask=0x20 01 unc_m2m_prefcam_inserts.ch2_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 2 event=0x6d,umask=0x10 01 unc_m2m_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x6d,umask=0x2a 01 unc_m2m_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT - All Channels event=0x6d,umask=0x15 01 unc_m2m_prefcam_occupancy.allch uncore interconnect Prefetch CAM Occupancy : All Channels event=0x6a,umask=0x7 01 unc_m2m_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x6a,umask=0x1 01 unc_m2m_prefcam_occupancy.ch1 uncore interconnect Prefetch CAM Occupancy : Channel 1 event=0x6a,umask=0x2 01 unc_m2m_prefcam_occupancy.ch2 uncore interconnect Prefetch CAM Occupancy : Channel 2 event=0x6a,umask=0x4 01 unc_m2m_prefcam_resp_miss.allch uncore interconnect : All Channels event=0x76,umask=0x7 01 unc_m2m_prefcam_resp_miss.ch0 uncore interconnect : Channel 0 event=0x76,umask=0x1 01 unc_m2m_prefcam_resp_miss.ch1 uncore interconnect : Channel 1 event=0x76,umask=0x2 01 unc_m2m_prefcam_resp_miss.ch2 uncore interconnect : Channel 2 event=0x76,umask=0x4 01 unc_m2m_prefcam_rxc_cycles_ne uncore interconnect UNC_M2M_PREFCAM_RxC_CYCLES_NE event=0x79 01 unc_m2m_prefcam_rxc_deallocs.1lm_posted uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x7a,umask=0x2 01 unc_m2m_prefcam_rxc_deallocs.cis uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS event=0x7a,umask=0x8 01 unc_m2m_prefcam_rxc_deallocs.pmm_memmode_accept uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT event=0x7a,umask=0x4 01 unc_m2m_prefcam_rxc_deallocs.squashed uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x7a,umask=0x1 01 unc_m2m_prefcam_rxc_inserts uncore interconnect UNC_M2M_PREFCAM_RxC_INSERTS event=0x78 01 unc_m2m_prefcam_rxc_occupancy uncore interconnect UNC_M2M_PREFCAM_RxC_OCCUPANCY event=0x77 01 unc_m2m_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=0x1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=0x2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=0x4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=0x8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=0x1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=0x2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.akc uncore interconnect Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=0x4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=0x8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring : AD event=0xad,umask=0x1 01 unc_m2m_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring : AK event=0xad,umask=0x2 01 unc_m2m_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_m2m_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring : BL event=0xad,umask=0x4 01 unc_m2m_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring : IV event=0xad,umask=0x8 01 unc_m2m_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring : AD event=0xab,umask=0x1 01 unc_m2m_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=0x2 01 unc_m2m_ring_sink_starved_vert.akc uncore interconnect Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_m2m_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=0x4 01 unc_m2m_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=0x8 01 unc_m2m_ring_src_thrtl uncore interconnect Source Throttle event=0xae 01 unc_m2m_rpq_no_reg_crd.ch0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0 event=0x43,umask=0x1 01 unc_m2m_rpq_no_reg_crd.ch1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1 event=0x43,umask=0x2 01 unc_m2m_rpq_no_reg_crd.ch2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2 event=0x43,umask=0x4 01 unc_m2m_rpq_no_reg_crd_pmm.chn0 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0 event=0x4f,umask=0x1 01 unc_m2m_rpq_no_reg_crd_pmm.chn1 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1 event=0x4f,umask=0x2 01 unc_m2m_rpq_no_reg_crd_pmm.chn2 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2 event=0x4f,umask=0x4 01 unc_m2m_rpq_no_spec_crd.ch0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 0 event=0x44,umask=0x1 01 unc_m2m_rpq_no_spec_crd.ch1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 1 event=0x44,umask=0x2 01 unc_m2m_rpq_no_spec_crd.ch2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 2 event=0x44,umask=0x4 01 unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) Allocations event=0x1 01 unc_m2m_rxc_ad_pref_occupancy uncore interconnect AD Ingress (from CMS) Occupancy - Prefetches event=0x77 01 unc_m2m_rxc_ak_wr_cmp uncore interconnect AK Egress (to CMS) Allocations event=0x5c 01 unc_m2m_rxr_busy_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2m_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2m_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2m_rxr_bypass.ad_all uncore interconnect Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2m_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ad_uncrd uncore interconnect Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=0x1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ak uncore interconnect Transgress Ingress Bypass : AK event=0xe2,umask=0x2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.akc_uncrd uncore interconnect Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_all uncore interconnect Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2m_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_uncrd uncore interconnect Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=0x4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.iv uncore interconnect Transgress Ingress Bypass : IV event=0xe2,umask=0x8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m2m_rxr_crd_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2m_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ak uncore interconnect Transgress Injection Starvation : AK event=0xe3,umask=0x2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2m_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.iv uncore interconnect Transgress Injection Starvation : IV event=0xe3,umask=0x8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved_1 uncore interconnect Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_inserts.ad_all uncore interconnect Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ad_uncrd uncore interconnect Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=0x1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ak uncore interconnect Transgress Ingress Allocations : AK event=0xe1,umask=0x2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.akc_uncrd uncore interconnect Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_all uncore interconnect Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_uncrd uncore interconnect Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=0x4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.iv uncore interconnect Transgress Ingress Allocations : IV event=0xe1,umask=0x8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_all uncore interconnect Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_uncrd uncore interconnect Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=0x1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ak uncore interconnect Transgress Ingress Occupancy : AK event=0xe0,umask=0x2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.akc_uncrd uncore interconnect Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_all uncore interconnect Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_uncrd uncore interconnect Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=0x4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.iv uncore interconnect Transgress Ingress Occupancy : IV event=0xe0,umask=0x8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2m_scoreboard_ad_retry_accepts uncore interconnect UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS event=0x33 01 unc_m2m_scoreboard_ad_retry_rejects uncore interconnect UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS event=0x34 01 unc_m2m_scoreboard_bl_retry_accepts uncore interconnect Retry - Mem Mirroring Mode event=0x35 01 unc_m2m_scoreboard_bl_retry_rejects uncore interconnect Retry - Mem Mirroring Mode event=0x36 01 unc_m2m_scoreboard_rd_accepts uncore interconnect Scoreboard Accepts event=0x2f 01 unc_m2m_scoreboard_rd_rejects uncore interconnect Scoreboard Rejects event=0x30 01 unc_m2m_scoreboard_wr_accepts uncore interconnect Scoreboard Accepts event=0x31 01 unc_m2m_scoreboard_wr_rejects uncore interconnect Scoreboard Rejects event=0x32 01 unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=0x8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=0x8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=0x8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=0x8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Tag Hit : Clean NearMem Read Hit event=0x2c,umask=0x1 01 Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Read Hit event=0x2c,umask=0x2 01 Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Tag Hit : Clean NearMem Underfill Hit event=0x2c,umask=0x4 01 Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Underfill Hit event=0x2c,umask=0x8 01 Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write unc_m2m_tag_miss uncore interconnect Tag Miss event=0x61 01 unc_m2m_tracker_full.ch0 uncore interconnect Tracker Cycles Full : Channel 0 event=0x45,umask=0x1 01 unc_m2m_tracker_full.ch1 uncore interconnect Tracker Cycles Full : Channel 1 event=0x45,umask=0x2 01 unc_m2m_tracker_full.ch2 uncore interconnect Tracker Cycles Full : Channel 2 event=0x45,umask=0x4 01 unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x49,umask=0x1 01 unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts : Channel 1 event=0x49,umask=0x2 01 unc_m2m_tracker_inserts.ch2 uncore interconnect Tracker Inserts : Channel 2 event=0x49,umask=0x4 01 unc_m2m_tracker_ne.ch0 uncore interconnect Tracker Cycles Not Empty : Channel 0 event=0x46,umask=0x1 01 unc_m2m_tracker_ne.ch1 uncore interconnect Tracker Cycles Not Empty : Channel 1 event=0x46,umask=0x2 01 unc_m2m_tracker_ne.ch2 uncore interconnect Tracker Cycles Not Empty : Channel 2 event=0x46,umask=0x4 01 unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x47,umask=0x1 01 unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy : Channel 1 event=0x47,umask=0x2 01 unc_m2m_tracker_occupancy.ch2 uncore interconnect Tracker Occupancy : Channel 2 event=0x47,umask=0x4 01 unc_m2m_txc_ak.crd_cbo uncore interconnect Outbound Ring Transactions on AK : CRD Transactions to Cbo event=0x39,umask=0x2 01 unc_m2m_txc_ak.ndr uncore interconnect Outbound Ring Transactions on AK : NDR Transactions event=0x39,umask=0x1 01 unc_m2m_txc_akc_credits uncore interconnect AKC Credits event=0x5f 01 unc_m2m_txc_ak_credits_acquired.cms0 uncore interconnect AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side event=0x1d,umask=0x1 01 unc_m2m_txc_ak_credits_acquired.cms1 uncore interconnect AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side event=0x1d,umask=0x2 01 unc_m2m_txc_ak_cycles_full.all uncore interconnect AK Egress (to CMS) Full : All event=0x14,umask=0x3 01 unc_m2m_txc_ak_cycles_full.cms0 uncore interconnect AK Egress (to CMS) Full : Common Mesh Stop - Near Side event=0x14,umask=0x1 01 unc_m2m_txc_ak_cycles_full.cms1 uncore interconnect AK Egress (to CMS) Full : Common Mesh Stop - Far Side event=0x14,umask=0x2 01 unc_m2m_txc_ak_cycles_full.rdcrd0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x8 01 unc_m2m_txc_ak_cycles_full.rdcrd1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x88 01 unc_m2m_txc_ak_cycles_full.wrcmp0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x20 01 unc_m2m_txc_ak_cycles_full.wrcmp1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0xa0 01 unc_m2m_txc_ak_cycles_full.wrcrd0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x10 01 unc_m2m_txc_ak_cycles_full.wrcrd1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x90 01 unc_m2m_txc_ak_cycles_ne.all uncore interconnect AK Egress (to CMS) Not Empty : All event=0x13,umask=0x3 01 unc_m2m_txc_ak_cycles_ne.cms0 uncore interconnect AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side event=0x13,umask=0x1 01 unc_m2m_txc_ak_cycles_ne.cms1 uncore interconnect AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side event=0x13,umask=0x2 01 unc_m2m_txc_ak_cycles_ne.rdcrd uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=0x8 01 unc_m2m_txc_ak_cycles_ne.wrcmp uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=0x20 01 unc_m2m_txc_ak_cycles_ne.wrcrd uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=0x10 01 unc_m2m_txc_ak_inserts.all uncore interconnect AK Egress (to CMS) Allocations : All event=0x11,umask=0x3 01 unc_m2m_txc_ak_inserts.cms0 uncore interconnect AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side event=0x11,umask=0x1 01 unc_m2m_txc_ak_inserts.cms1 uncore interconnect AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side event=0x11,umask=0x2 01 unc_m2m_txc_ak_inserts.pref_rd_cam_hit uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x40 01 unc_m2m_txc_ak_inserts.rdcrd uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x8 01 unc_m2m_txc_ak_inserts.wrcmp uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x20 01 unc_m2m_txc_ak_inserts.wrcrd uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x10 01 unc_m2m_txc_ak_no_credit_cycles.cms0 uncore interconnect Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1f,umask=0x1 01 unc_m2m_txc_ak_no_credit_cycles.cms1 uncore interconnect Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1f,umask=0x2 01 unc_m2m_txc_ak_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x20,umask=0x1 01 unc_m2m_txc_ak_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x20,umask=0x2 01 unc_m2m_txc_ak_occupancy.all uncore interconnect AK Egress (to CMS) Occupancy : All event=0x12,umask=0x3 01 unc_m2m_txc_ak_occupancy.cms0 uncore interconnect AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side event=0x12,umask=0x1 01 unc_m2m_txc_ak_occupancy.cms1 uncore interconnect AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side event=0x12,umask=0x2 01 unc_m2m_txc_ak_occupancy.rdcrd uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=0x8 01 unc_m2m_txc_ak_occupancy.wrcmp uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=0x20 01 unc_m2m_txc_ak_occupancy.wrcrd uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=0x10 01 unc_m2m_txc_bl.drs_cache uncore interconnect Outbound DRS Ring Transactions to Cache : Data to Cache event=0x40,umask=0x1 01 unc_m2m_txc_bl.drs_core uncore interconnect Outbound DRS Ring Transactions to Cache : Data to Core event=0x40,umask=0x2 01 unc_m2m_txc_bl.drs_upi uncore interconnect Outbound DRS Ring Transactions to Cache : Data to QPI event=0x40,umask=0x4 01 unc_m2m_txc_bl_credits_acquired.cms0 uncore interconnect BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side event=0x19,umask=0x1 01 unc_m2m_txc_bl_credits_acquired.cms1 uncore interconnect BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side event=0x19,umask=0x2 01 unc_m2m_txc_bl_cycles_full.all uncore interconnect BL Egress (to CMS) Full : All event=0x18,umask=0x3 01 unc_m2m_txc_bl_cycles_full.cms0 uncore interconnect BL Egress (to CMS) Full : Common Mesh Stop - Near Side event=0x18,umask=0x1 01 unc_m2m_txc_bl_cycles_full.cms1 uncore interconnect BL Egress (to CMS) Full : Common Mesh Stop - Far Side event=0x18,umask=0x2 01 unc_m2m_txc_bl_cycles_ne.all uncore interconnect BL Egress (to CMS) Not Empty : All event=0x17,umask=0x3 01 unc_m2m_txc_bl_cycles_ne.cms0 uncore interconnect BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side event=0x17,umask=0x1 01 unc_m2m_txc_bl_cycles_ne.cms1 uncore interconnect BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side event=0x17,umask=0x2 01 unc_m2m_txc_bl_inserts.all uncore interconnect BL Egress (to CMS) Allocations : All event=0x15,umask=0x3 01 unc_m2m_txc_bl_inserts.cms0 uncore interconnect BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side event=0x15,umask=0x1 01 unc_m2m_txc_bl_inserts.cms1 uncore interconnect BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side event=0x15,umask=0x2 01 unc_m2m_txc_bl_no_credit_cycles.cms0 uncore interconnect Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1b,umask=0x1 01 unc_m2m_txc_bl_no_credit_cycles.cms1 uncore interconnect Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1b,umask=0x2 01 unc_m2m_txc_bl_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1c,umask=0x1 01 unc_m2m_txc_bl_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1c,umask=0x2 01 unc_m2m_txr_horz_ads_used.ad_all uncore interconnect CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ad_uncrd uncore interconnect CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=0x1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_all uncore interconnect CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_uncrd uncore interconnect CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=0x4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_all uncore interconnect CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_uncrd uncore interconnect CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=0x1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ak uncore interconnect CMS Horizontal Bypass Used : AK event=0xa7,umask=0x2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.akc_uncrd uncore interconnect CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_all uncore interconnect CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_uncrd uncore interconnect CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=0x4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.iv uncore interconnect CMS Horizontal Bypass Used : IV event=0xa7,umask=0x8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_cycles_full.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_all uncore interconnect CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_uncrd uncore interconnect CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=0x1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ak uncore interconnect CMS Horizontal Egress Inserts : AK event=0xa1,umask=0x2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.akc_uncrd uncore interconnect CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_all uncore interconnect CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_uncrd uncore interconnect CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=0x4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.iv uncore interconnect CMS Horizontal Egress Inserts : IV event=0xa1,umask=0x8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_nack.ad_all uncore interconnect CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2m_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ad_uncrd uncore interconnect CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=0x1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ak uncore interconnect CMS Horizontal Egress NACKs : AK event=0xa4,umask=0x2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.akc_uncrd uncore interconnect CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_all uncore interconnect CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2m_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_uncrd uncore interconnect CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=0x4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.iv uncore interconnect CMS Horizontal Egress NACKs : IV event=0xa4,umask=0x8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_occupancy.ad_all uncore interconnect CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ad_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=0x1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ak uncore interconnect CMS Horizontal Egress Occupancy : AK event=0xa0,umask=0x2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.akc_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_all uncore interconnect CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_uncrd uncore interconnect CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=0x4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.iv uncore interconnect CMS Horizontal Egress Occupancy : IV event=0xa0,umask=0x8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_starved.ad_all uncore interconnect CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2m_txr_horz_starved.ad_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.ak uncore interconnect CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=0x2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.akc_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.bl_all uncore interconnect CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2m_txr_horz_starved.bl_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.iv uncore interconnect CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=0x8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=0x2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.iv_ag1 uncore interconnect CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=0x8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass_1.akc_ag0 uncore interconnect CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=0x1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass_1.akc_ag1 uncore interconnect CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=0x2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_cycles_full0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_full0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_full0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_full0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_full0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_full0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_full1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_cycles_ne0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_ne0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_ne0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_ne0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_ne1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts0.ad_ag0 uncore interconnect CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=0x1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts0.ad_ag1 uncore interconnect CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_inserts0.ak_ag0 uncore interconnect CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=0x2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts0.ak_ag1 uncore interconnect CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_inserts0.bl_ag0 uncore interconnect CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=0x4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_inserts0.bl_ag1 uncore interconnect CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_inserts0.iv_ag0 uncore interconnect CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=0x8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_inserts1.akc_ag0 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=0x1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts1.akc_ag1 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=0x2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_nack0.ad_ag0 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=0x1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ad_ag1 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ak_ag0 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=0x2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ak_ag1 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.bl_ag0 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=0x4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.bl_ag1 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.iv_ag0 uncore interconnect CMS Vertical Egress NACKs : IV event=0x98,umask=0x8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack1.akc_ag0 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=0x1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack1.akc_ag1 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=0x2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_occupancy0.ad_ag0 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=0x1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy0.ad_ag1 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2m_txr_vert_occupancy0.ak_ag0 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=0x2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_occupancy0.ak_ag1 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_occupancy0.bl_ag0 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=0x4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_occupancy0.bl_ag1 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_occupancy0.iv_ag0 uncore interconnect CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=0x8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2m_txr_vert_occupancy1.akc_ag0 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=0x1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy1.akc_ag1 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=0x2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2m_txr_vert_starved0.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=0x1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=0x2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=0x4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.iv_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=0x8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.akc_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.akc_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=0x2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.tgc uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use : Down and Even event=0xb0,umask=0x4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use : Down and Odd event=0xb0,umask=0x8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use : Up and Even event=0xb0,umask=0x1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use : Up and Odd event=0xb0,umask=0x2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.dn_even uncore interconnect Vertical AKC Ring In Use : Down and Even event=0xb4,umask=0x4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.dn_odd uncore interconnect Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=0x8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.up_even uncore interconnect Vertical AKC Ring In Use : Up and Even event=0xb4,umask=0x1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.up_odd uncore interconnect Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=0x2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use : Down and Even event=0xb1,umask=0x4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use : Down and Odd event=0xb1,umask=0x8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use : Up and Even event=0xb1,umask=0x1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use : Up and Odd event=0xb1,umask=0x2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use : Down and Even event=0xb2,umask=0x4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use : Down and Odd event=0xb2,umask=0x8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use : Up and Even event=0xb2,umask=0x1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use : Up and Odd event=0xb2,umask=0x2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use : Down event=0xb3,umask=0x4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use : Up event=0xb3,umask=0x1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_tgc_in_use.dn_even uncore interconnect Vertical TGC Ring In Use : Down and Even event=0xb5,umask=0x4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.dn_odd uncore interconnect Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=0x8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.up_even uncore interconnect Vertical TGC Ring In Use : Up and Even event=0xb5,umask=0x1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.up_odd uncore interconnect Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=0x2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_wpq_flush.ch0 uncore interconnect WPQ Flush : Channel 0 event=0x58,umask=0x1 01 unc_m2m_wpq_flush.ch1 uncore interconnect WPQ Flush : Channel 1 event=0x58,umask=0x2 01 unc_m2m_wpq_flush.ch2 uncore interconnect WPQ Flush : Channel 2 event=0x58,umask=0x4 01 unc_m2m_wpq_no_reg_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x4d,umask=0x1 01 unc_m2m_wpq_no_reg_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x4d,umask=0x2 01 unc_m2m_wpq_no_reg_crd.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2 event=0x4d,umask=0x4 01 unc_m2m_wpq_no_reg_crd_pmm.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0 event=0x51,umask=0x1 01 unc_m2m_wpq_no_reg_crd_pmm.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1 event=0x51,umask=0x2 01 unc_m2m_wpq_no_reg_crd_pmm.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2 event=0x51,umask=0x4 01 unc_m2m_wpq_no_spec_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x4e,umask=0x1 01 unc_m2m_wpq_no_spec_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x4e,umask=0x2 01 unc_m2m_wpq_no_spec_crd.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 2 event=0x4e,umask=0x4 01 unc_m2m_wr_tracker_full.ch0 uncore interconnect Write Tracker Cycles Full : Channel 0 event=0x4a,umask=0x1 01 unc_m2m_wr_tracker_full.ch1 uncore interconnect Write Tracker Cycles Full : Channel 1 event=0x4a,umask=0x2 01 unc_m2m_wr_tracker_full.ch2 uncore interconnect Write Tracker Cycles Full : Channel 2 event=0x4a,umask=0x4 01 unc_m2m_wr_tracker_full.mirr uncore interconnect Write Tracker Cycles Full : Mirror event=0x4a,umask=0x8 01 unc_m2m_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x56,umask=0x1 01 unc_m2m_wr_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts : Channel 1 event=0x56,umask=0x2 01 unc_m2m_wr_tracker_inserts.ch2 uncore interconnect Write Tracker Inserts : Channel 2 event=0x56,umask=0x4 01 unc_m2m_wr_tracker_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty : Channel 0 event=0x4b,umask=0x1 01 unc_m2m_wr_tracker_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty : Channel 1 event=0x4b,umask=0x2 01 unc_m2m_wr_tracker_ne.ch2 uncore interconnect Write Tracker Cycles Not Empty : Channel 2 event=0x4b,umask=0x4 01 unc_m2m_wr_tracker_ne.mirr uncore interconnect Write Tracker Cycles Not Empty : Mirror event=0x4b,umask=0x8 01 unc_m2m_wr_tracker_ne.mirr_nontgr uncore interconnect Write Tracker Cycles Not Empty event=0x4b,umask=0x10 01 unc_m2m_wr_tracker_ne.mirr_pwr uncore interconnect Write Tracker Cycles Not Empty event=0x4b,umask=0x20 01 unc_m2m_wr_tracker_nonposted_inserts.ch0 uncore interconnect Write Tracker Non-Posted Inserts : Channel 0 event=0x63,umask=0x1 01 unc_m2m_wr_tracker_nonposted_inserts.ch1 uncore interconnect Write Tracker Non-Posted Inserts : Channel 1 event=0x63,umask=0x2 01 unc_m2m_wr_tracker_nonposted_inserts.ch2 uncore interconnect Write Tracker Non-Posted Inserts : Channel 2 event=0x63,umask=0x4 01 unc_m2m_wr_tracker_nonposted_occupancy.ch0 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 0 event=0x62,umask=0x1 01 unc_m2m_wr_tracker_nonposted_occupancy.ch1 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 1 event=0x62,umask=0x2 01 unc_m2m_wr_tracker_nonposted_occupancy.ch2 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 2 event=0x62,umask=0x4 01 unc_m2m_wr_tracker_occupancy.ch0 uncore interconnect Write Tracker Occupancy : Channel 0 event=0x55,umask=0x1 01 unc_m2m_wr_tracker_occupancy.ch1 uncore interconnect Write Tracker Occupancy : Channel 1 event=0x55,umask=0x2 01 unc_m2m_wr_tracker_occupancy.ch2 uncore interconnect Write Tracker Occupancy : Channel 2 event=0x55,umask=0x4 01 unc_m2m_wr_tracker_occupancy.mirr uncore interconnect Write Tracker Occupancy : Mirror event=0x55,umask=0x8 01 unc_m2m_wr_tracker_occupancy.mirr_nontgr uncore interconnect Write Tracker Occupancy event=0x55,umask=0x10 01 unc_m2m_wr_tracker_occupancy.mirr_pwr uncore interconnect Write Tracker Occupancy event=0x55,umask=0x20 01 unc_m2m_wr_tracker_posted_inserts.ch0 uncore interconnect Write Tracker Posted Inserts : Channel 0 event=0x5e,umask=0x1 01 unc_m2m_wr_tracker_posted_inserts.ch1 uncore interconnect Write Tracker Posted Inserts : Channel 1 event=0x5e,umask=0x2 01 unc_m2m_wr_tracker_posted_inserts.ch2 uncore interconnect Write Tracker Posted Inserts : Channel 2 event=0x5e,umask=0x4 01 unc_m2m_wr_tracker_posted_occupancy.ch0 uncore interconnect Write Tracker Posted Occupancy : Channel 0 event=0x5d,umask=0x1 01 unc_m2m_wr_tracker_posted_occupancy.ch1 uncore interconnect Write Tracker Posted Occupancy : Channel 1 event=0x5d,umask=0x2 01 unc_m2m_wr_tracker_posted_occupancy.ch2 uncore interconnect Write Tracker Posted Occupancy : Channel 2 event=0x5d,umask=0x4 01 unc_m3upi_ag0_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=0x8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=0x8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=0x8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=0x8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=0x8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=0x8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=0x8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=0x8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_clockticks uncore interconnect Clockticks of the mesh to UPI (M3UPI) event=0x1 01 Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m3upi_distress_asserted.dpt_local uncore interconnect Distress signal asserted : DPT Local event=0xaf,umask=0x4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m3upi_distress_asserted.dpt_nonlocal uncore interconnect Distress signal asserted : DPT Remote event=0xaf,umask=0x8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m3upi_distress_asserted.dpt_stall_iv uncore interconnect Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m3upi_distress_asserted.dpt_stall_nocrd uncore interconnect Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m3upi_distress_asserted.horz uncore interconnect Distress signal asserted : Horizontal event=0xaf,umask=0x2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m3upi_distress_asserted.pmm_local uncore interconnect Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m3upi_distress_asserted.pmm_nonlocal uncore interconnect Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m3upi_distress_asserted.vert uncore interconnect Distress signal asserted : Vertical event=0xaf,umask=0x1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m3upi_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use : Left and Even event=0xb6,umask=0x1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=0x2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use : Right and Even event=0xb6,umask=0x4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=0x8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xbb,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xbb,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xb7,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xb7,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use : Left and Even event=0xb8,umask=0x1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=0x2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use : Right and Even event=0xb8,umask=0x4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=0x8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use : Left event=0xb9,umask=0x1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use : Right event=0xb9,umask=0x4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_misc_external.mbe_inst0 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=0x1 01 unc_m3upi_misc_external.mbe_inst1 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=0x2 01 unc_m3upi_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=0x1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=0x2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=0x4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=0x8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=0x1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=0x2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.akc uncore interconnect Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=0x4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=0x8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring : AD event=0xad,umask=0x1 01 unc_m3upi_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring : AK event=0xad,umask=0x2 01 unc_m3upi_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_m3upi_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring : BL event=0xad,umask=0x4 01 unc_m3upi_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring : IV event=0xad,umask=0x8 01 unc_m3upi_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring : AD event=0xab,umask=0x1 01 unc_m3upi_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=0x2 01 unc_m3upi_ring_sink_starved_vert.akc uncore interconnect Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_m3upi_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=0x4 01 unc_m3upi_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=0x8 01 unc_m3upi_ring_src_thrtl uncore interconnect Source Throttle event=0xae 01 unc_m3upi_rxc_cycles_ne_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD event=0x44,umask=0x1 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD event=0x44,umask=0x4 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD event=0x44,umask=0x2 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL event=0x44,umask=0x20 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL event=0x44,umask=0x40 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL event=0x44,umask=0x8 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL event=0x44,umask=0x10 01 VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : REQ on AD event=0x41,umask=0x1 01 VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : RSP on AD event=0x41,umask=0x4 01 VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : SNP on AD event=0x41,umask=0x2 01 VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : NCB on BL event=0x41,umask=0x20 01 VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : NCS on BL event=0x41,umask=0x40 01 VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : RSP on BL event=0x41,umask=0x8 01 VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : WB on BL event=0x41,umask=0x10 01 VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : REQ on AD event=0x42,umask=0x1 01 VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : RSP on AD event=0x42,umask=0x4 01 VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : SNP on AD event=0x42,umask=0x2 01 VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : NCB on BL event=0x42,umask=0x20 01 VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : NCS on BL event=0x42,umask=0x40 01 VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : RSP on BL event=0x42,umask=0x8 01 VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : WB on BL event=0x42,umask=0x10 01 VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD event=0x45,umask=0x1 01 VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD event=0x45,umask=0x4 01 VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD event=0x45,umask=0x2 01 VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL event=0x45,umask=0x20 01 VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL event=0x45,umask=0x40 01 VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL event=0x45,umask=0x8 01 VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : WB on BL event=0x45,umask=0x10 01 VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD event=0x46,umask=0x1 01 VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD event=0x46,umask=0x4 01 VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD event=0x46,umask=0x2 01 VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL event=0x46,umask=0x20 01 VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL event=0x46,umask=0x40 01 VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL event=0x46,umask=0x8 01 VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : WB on BL event=0x46,umask=0x10 01 VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxr_busy_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m3upi_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m3upi_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m3upi_rxr_bypass.ad_all uncore interconnect Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m3upi_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ad_uncrd uncore interconnect Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=0x1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ak uncore interconnect Transgress Ingress Bypass : AK event=0xe2,umask=0x2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.akc_uncrd uncore interconnect Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_all uncore interconnect Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m3upi_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_uncrd uncore interconnect Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=0x4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.iv uncore interconnect Transgress Ingress Bypass : IV event=0xe2,umask=0x8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_crd_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m3upi_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ak uncore interconnect Transgress Injection Starvation : AK event=0xe3,umask=0x2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m3upi_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.iv uncore interconnect Transgress Injection Starvation : IV event=0xe3,umask=0x8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved_1 uncore interconnect Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_inserts.ad_all uncore interconnect Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ad_uncrd uncore interconnect Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=0x1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ak uncore interconnect Transgress Ingress Allocations : AK event=0xe1,umask=0x2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.akc_uncrd uncore interconnect Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_all uncore interconnect Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_uncrd uncore interconnect Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=0x4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.iv uncore interconnect Transgress Ingress Allocations : IV event=0xe1,umask=0x8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_all uncore interconnect Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_uncrd uncore interconnect Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=0x1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ak uncore interconnect Transgress Ingress Occupancy : AK event=0xe0,umask=0x2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.akc_uncrd uncore interconnect Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_all uncore interconnect Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_uncrd uncore interconnect Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=0x4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.iv uncore interconnect Transgress Ingress Occupancy : IV event=0xe0,umask=0x8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=0x8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=0x8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=0x8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=0x8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_txr_horz_ads_used.ad_all uncore interconnect CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ad_uncrd uncore interconnect CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=0x1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_all uncore interconnect CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_uncrd uncore interconnect CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=0x4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_all uncore interconnect CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_uncrd uncore interconnect CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=0x1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ak uncore interconnect CMS Horizontal Bypass Used : AK event=0xa7,umask=0x2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.akc_uncrd uncore interconnect CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_all uncore interconnect CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_uncrd uncore interconnect CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=0x4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.iv uncore interconnect CMS Horizontal Bypass Used : IV event=0xa7,umask=0x8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_cycles_full.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_all uncore interconnect CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_uncrd uncore interconnect CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=0x1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ak uncore interconnect CMS Horizontal Egress Inserts : AK event=0xa1,umask=0x2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.akc_uncrd uncore interconnect CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_all uncore interconnect CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_uncrd uncore interconnect CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=0x4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.iv uncore interconnect CMS Horizontal Egress Inserts : IV event=0xa1,umask=0x8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_nack.ad_all uncore interconnect CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m3upi_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ad_uncrd uncore interconnect CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=0x1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ak uncore interconnect CMS Horizontal Egress NACKs : AK event=0xa4,umask=0x2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.akc_uncrd uncore interconnect CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_all uncore interconnect CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m3upi_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_uncrd uncore interconnect CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=0x4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.iv uncore interconnect CMS Horizontal Egress NACKs : IV event=0xa4,umask=0x8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_occupancy.ad_all uncore interconnect CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ad_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=0x1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ak uncore interconnect CMS Horizontal Egress Occupancy : AK event=0xa0,umask=0x2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.akc_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_all uncore interconnect CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_uncrd uncore interconnect CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=0x4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.iv uncore interconnect CMS Horizontal Egress Occupancy : IV event=0xa0,umask=0x8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_starved.ad_all uncore interconnect CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m3upi_txr_horz_starved.ad_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.ak uncore interconnect CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=0x2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.akc_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.bl_all uncore interconnect CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m3upi_txr_horz_starved.bl_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.iv uncore interconnect CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=0x8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=0x2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.iv_ag1 uncore interconnect CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=0x8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass_1.akc_ag0 uncore interconnect CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=0x1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass_1.akc_ag1 uncore interconnect CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=0x2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_cycles_full0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_full0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_full0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_full0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_full0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_full0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_full1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_ne0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_ne0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_ne0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_ne0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_ne1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts0.ad_ag0 uncore interconnect CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=0x1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts0.ad_ag1 uncore interconnect CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_inserts0.ak_ag0 uncore interconnect CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=0x2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts0.ak_ag1 uncore interconnect CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_inserts0.bl_ag0 uncore interconnect CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=0x4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_inserts0.bl_ag1 uncore interconnect CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_inserts0.iv_ag0 uncore interconnect CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=0x8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_inserts1.akc_ag0 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=0x1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts1.akc_ag1 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=0x2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_nack0.ad_ag0 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=0x1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ad_ag1 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ak_ag0 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=0x2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ak_ag1 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.bl_ag0 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=0x4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.bl_ag1 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.iv_ag0 uncore interconnect CMS Vertical Egress NACKs : IV event=0x98,umask=0x8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack1.akc_ag0 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=0x1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack1.akc_ag1 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=0x2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_occupancy0.ad_ag0 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=0x1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy0.ad_ag1 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m3upi_txr_vert_occupancy0.ak_ag0 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=0x2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_occupancy0.ak_ag1 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_occupancy0.bl_ag0 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=0x4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_occupancy0.bl_ag1 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_occupancy0.iv_ag0 uncore interconnect CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=0x8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m3upi_txr_vert_occupancy1.akc_ag0 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=0x1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy1.akc_ag1 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=0x2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_starved0.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=0x1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=0x2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=0x4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.iv_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=0x8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.akc_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.akc_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=0x2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.tgc uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use : Down and Even event=0xb0,umask=0x4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use : Down and Odd event=0xb0,umask=0x8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use : Up and Even event=0xb0,umask=0x1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use : Up and Odd event=0xb0,umask=0x2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.dn_even uncore interconnect Vertical AKC Ring In Use : Down and Even event=0xb4,umask=0x4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.dn_odd uncore interconnect Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=0x8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.up_even uncore interconnect Vertical AKC Ring In Use : Up and Even event=0xb4,umask=0x1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.up_odd uncore interconnect Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=0x2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use : Down and Even event=0xb1,umask=0x4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use : Down and Odd event=0xb1,umask=0x8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use : Up and Even event=0xb1,umask=0x1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use : Up and Odd event=0xb1,umask=0x2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use : Down and Even event=0xb2,umask=0x4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use : Down and Odd event=0xb2,umask=0x8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use : Up and Even event=0xb2,umask=0x1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use : Up and Odd event=0xb2,umask=0x2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use : Down event=0xb3,umask=0x4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use : Up event=0xb3,umask=0x1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_tgc_in_use.dn_even uncore interconnect Vertical TGC Ring In Use : Down and Even event=0xb5,umask=0x4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.dn_odd uncore interconnect Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=0x8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.up_even uncore interconnect Vertical TGC Ring In Use : Up and Even event=0xb5,umask=0x1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.up_odd uncore interconnect Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=0x2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_xpt_pftch.lost_qfull uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_QFULL event=0x61,umask=0x20 01 : xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full unc_upi_clockticks uncore interconnect Number of kfclks event=0x1 01 Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port : Request event=0x5,umask=0x8 01 Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port : Request, Match Opcode event=0x5,umask=0x108 01 Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port : Response - Conflict event=0x5,umask=0x1aa 01 Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port : Response - Invalid event=0x5,umask=0x12a 01 Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port : Response - Data event=0x5,umask=0xc 01 Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port : Response - Data, Match Opcode event=0x5,umask=0x10c 01 Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port : Response - No Data event=0x5,umask=0xa 01 Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port : Response - No Data, Match Opcode event=0x5,umask=0x10a 01 Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port : Snoop event=0x5,umask=0x9 01 Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port : Snoop, Match Opcode event=0x5,umask=0x109 01 Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port : Writeback event=0x5,umask=0xd 01 Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port : Writeback, Match Opcode event=0x5,umask=0x10d 01 Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=0x8 01 LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs unc_upi_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x38 01 VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_null uncore interconnect Valid Flits Received : Null FLITs received from any slot event=0x3,umask=0x27 01 Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Null FLITs received from any slot event=0x3,umask=0x47 01 Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port : Request event=0x4,umask=0x8 01 Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port : Request, Match Opcode event=0x4,umask=0x108 01 Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port : Response - Conflict event=0x4,umask=0x1aa 01 Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port : Response - Invalid event=0x4,umask=0x12a 01 Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port : Response - Data event=0x4,umask=0xc 01 Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - Data, Match Opcode event=0x4,umask=0x10c 01 Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data event=0x4,umask=0xa 01 Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode event=0x4,umask=0x10a 01 Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port : Snoop event=0x4,umask=0x9 01 Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port : Snoop, Match Opcode event=0x4,umask=0x109 01 Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port : Writeback event=0x4,umask=0xd 01 Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port : Writeback, Match Opcode event=0x4,umask=0x10d 01 Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data event=0x2,umask=0xf 01 Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_null uncore interconnect Valid Flits Sent : Null FLITs transmitted to any slot event=0x2,umask=0x27 01 Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c) unc_u_lock_cycles uncore interconnect IDI Lock/SplitLock Cycles event=0x44 01 IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started unc_iio_clockticks uncore io Clockticks of the integrated IO (IIO) traffic controller event=0x1 01 Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz) unc_iio_clockticks_freerun uncore io Free running counter that increments for IIO clocktick event=0xff,umask=0x10 01 Free running counter that increments for integrated IO (IIO) traffic controller clockticks unc_iio_comp_buf_inserts.cmpd.all uncore io PCIe Completion Buffer Inserts : All Ports event=0xc2,ch_mask=0xFF,fc_mask=0x04,umask=0x3 01 unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-7 event=0xc2,ch_mask=0xff,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 0-7 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=0x01,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=0x02,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=0x04,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=0x08,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIe Completion Buffer Inserts of completions with data: Part 4 event=0xc2,ch_mask=0x10,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIe Completion Buffer Inserts of completions with data: Part 5 event=0xc2,ch_mask=0x20,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIe Completion Buffer Inserts of completions with data: Part 6 event=0xc2,ch_mask=0x40,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIe Completion Buffer Inserts of completions with data: Part 7 event=0xc2,ch_mask=0x80,fc_mask=0x04,umask=0x3 01 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_comp_buf_occupancy.cmpd.all uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0-7 event=0xd5,fc_mask=0x04,umask=0xff 01 PCIe Completion Buffer Occupancy : Part 0-7 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0-7 event=0xd5,fc_mask=0x04,umask=0xff 01 PCIe Completion Buffer Occupancy : Part 0-7 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0 event=0xd5,fc_mask=0x04,umask=0x1 01 PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 1 event=0xd5,fc_mask=0x04,umask=0x2 01 PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 2 event=0xd5,fc_mask=0x04,umask=0x4 01 PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 3 event=0xd5,fc_mask=0x04,umask=0x8 01 PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_occupancy.cmpd.part4 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 4 event=0xd5,fc_mask=0x04,umask=0x10 01 PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_occupancy.cmpd.part5 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 5 event=0xd5,fc_mask=0x04,umask=0x20 01 PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_occupancy.cmpd.part6 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 6 event=0xd5,fc_mask=0x04,umask=0x40 01 PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_occupancy.cmpd.part7 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 7 event=0xd5,fc_mask=0x04,umask=0x80 01 PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.cfg_read.iommu0 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.cfg_read.iommu1 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.cfg_read.part0 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_read.part1 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_read.part2 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_read.part3 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_read.part4 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.cfg_read.part5 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.cfg_read.part6 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.cfg_read.part7 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x40 01 Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.cfg_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.cfg_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.cfg_write.part0 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_write.part1 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_write.part2 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_write.part3 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_write.part4 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.cfg_write.part5 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.cfg_write.part6 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.cfg_write.part7 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x10 01 Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.io_read.iommu0 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.io_read.iommu1 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.io_read.part0 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_read.part1 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_read.part2 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_read.part3 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_read.part4 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.io_read.part5 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.io_read.part6 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.io_read.part7 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x80 01 Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.io_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.io_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.io_write.part0 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_write.part1 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_write.part2 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_write.part3 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_write.part4 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.io_write.part5 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.io_write.part6 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.io_write.part7 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x20 01 Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.mem_read.iommu0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_read.iommu1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part2 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.mem_read.part3 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x4 01 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.mem_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part1 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part2 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.mem_write.part3 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x1 01 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.peer_read.iommu0 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.peer_read.iommu1 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part1 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part2 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.peer_read.part3 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part4 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.peer_read.part5 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.peer_read.part6 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.peer_read.part7 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x8 01 Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.peer_write.iommu0 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x100,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.peer_write.iommu1 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x200,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part1 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part2 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.peer_write.part3 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part4 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.peer_write.part5 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.peer_write.part6 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.peer_write.part7 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x2 01 Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.atomic.iommu0 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x100,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.atomic.iommu1 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x200,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.atomic.part0 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomic.part1 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomic.part2 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomic.part3 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.atomic.part4 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.atomic.part5 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.atomic.part6 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.atomic.part7 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x10 01 Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.cmpd.iommu0 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x100,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.cmpd.iommu1 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x200,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.cmpd.part0 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.cmpd.part1 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.cmpd.part2 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.cmpd.part3 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.cmpd.part4 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.cmpd.part5 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.cmpd.part6 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.cmpd.part7 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x80 01 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.mem_read.iommu0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x100,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.mem_read.iommu1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x200,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_read.part0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_read.part3 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part4 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.mem_read.part5 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.mem_read.part6 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.mem_read.part7 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.mem_write.iommu0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x100,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.mem_write.iommu1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x200,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_write.part0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_write.part3 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part4 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.mem_write.part5 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.mem_write.part6 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.mem_write.part7 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.msg.iommu0 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x100,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.msg.iommu1 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x200,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.msg.part0 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.msg.part1 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.msg.part2 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.msg.part3 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.msg.part4 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.msg.part5 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.msg.part6 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.msg.part7 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x40 01 Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.peer_read.iommu0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x100,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.peer_read.iommu1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x200,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.peer_read.part0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_read.part1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_read.part2 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.peer_read.part3 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_read.part4 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.peer_read.part5 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.peer_read.part6 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.peer_read.part7 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x8 01 Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.peer_write.iommu0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x100,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.peer_write.iommu1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x200,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part2 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.peer_write.part3 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x2 01 Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_inbound_arb_req.data uncore io Incoming arbitration requests : Passing data to be written event=0x86,ch_mask=0xFF,fc_mask=0x07,umask=0x20 01 Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.final_rd_wr uncore io Incoming arbitration requests : Issuing final read or write of line event=0x86,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_hit uncore io Incoming arbitration requests : Processing response from IOMMU event=0x86,ch_mask=0xFF,fc_mask=0x07,umask=0x2 01 Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_req uncore io Incoming arbitration requests : Issuing to IOMMU event=0x86,ch_mask=0xFF,fc_mask=0x07,umask=0x1 01 Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.req_own uncore io Incoming arbitration requests : Request Ownership event=0x86,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.wr uncore io Incoming arbitration requests : Writing line event=0x86,ch_mask=0xFF,fc_mask=0x07,umask=0x10 01 Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.data uncore io Incoming arbitration requests granted : Passing data to be written event=0x87,ch_mask=0xFF,fc_mask=0x07,umask=0x20 01 Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.final_rd_wr uncore io Incoming arbitration requests granted : Issuing final read or write of line event=0x87,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_hit uncore io Incoming arbitration requests granted : Processing response from IOMMU event=0x87,ch_mask=0xFF,fc_mask=0x07,umask=0x2 01 Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_req uncore io Incoming arbitration requests granted : Issuing to IOMMU event=0x87,ch_mask=0xFF,fc_mask=0x07,umask=0x1 01 Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.req_own uncore io Incoming arbitration requests granted : Request Ownership event=0x87,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.wr uncore io Incoming arbitration requests granted : Writing line event=0x87,ch_mask=0xFF,fc_mask=0x07,umask=0x10 01 Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_iommu0.1g_hits uncore io : IOTLB Hits to a 1G Page event=0x40,umask=0x10 01 : IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB unc_iio_iommu0.2m_hits uncore io : IOTLB Hits to a 2M Page event=0x40,umask=0x8 01 : IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB unc_iio_iommu0.4k_hits uncore io : IOTLB Hits to a 4K Page event=0x40,umask=0x4 01 : IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB unc_iio_iommu0.all_lookups uncore io : IOTLB lookups all event=0x40,umask=0x2 01 : IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB unc_iio_iommu0.ctxt_cache_hits uncore io : Context cache hits event=0x40,umask=0x80 01 : Context cache hits : Counts each time a first look up of the transaction hits the RCC unc_iio_iommu0.ctxt_cache_lookups uncore io : Context cache lookups event=0x40,umask=0x40 01 : Context cache lookups : Counts each time a transaction looks up root context cache unc_iio_iommu0.first_lookups uncore io : IOTLB lookups first event=0x40,umask=0x1 01 : IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB unc_iio_iommu0.misses uncore io : IOTLB Fills (same as IOTLB miss) event=0x40,umask=0x20 01 : IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB unc_iio_iommu1.cyc_pwt_full uncore io : Cycles PWT full event=0x41,umask=0x80 01 : Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks unc_iio_iommu1.num_mem_accesses uncore io : IOMMU memory access event=0x41,umask=0x40 01 : IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel unc_iio_iommu1.pwc_1g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=0x8 01 : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu1.pwc_2m_hits uncore io : PWC Hit to a 2M page event=0x41,umask=0x4 01 : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.pwc_4k_hits uncore io : PWC Hit to a 4K page event=0x41,umask=0x2 01 : PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level unc_iio_iommu1.pwc_512g_hits uncore io : PWT Hit to a 256T page event=0x41,umask=0x10 01 : PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level unc_iio_iommu3.int_cache_hits uncore io : Interrupt Entry cache hit event=0x43,umask=0x80 01 : Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC unc_iio_iommu3.int_cache_lookups uncore io : Interrupt Entry cache lookup event=0x43,umask=0x40 01 : Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache unc_iio_iommu3.num_ctxt_cache_inval_device uncore io : Device-selective Context cache invalidation cycles event=0x43,umask=0x20 01 : Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events unc_iio_iommu3.num_ctxt_cache_inval_domain uncore io : Domain-selective Context cache invalidation cycles event=0x43,umask=0x10 01 : Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events unc_iio_iommu3.num_ctxt_cache_inval_gbl uncore io : Context cache global invalidation cycles event=0x43,umask=0x8 01 : Context cache global invalidation cycles : Counts number of Context Cache global invalidation events unc_iio_iommu3.num_inval_domain uncore io : Domain-selective IOTLB invalidation cycles event=0x43,umask=0x2 01 : Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events unc_iio_iommu3.num_inval_gbl uncore io : Global IOTLB invalidation cycles event=0x43,umask=0x1 01 : Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation unc_iio_iommu3.num_inval_page uncore io : Page-selective IOTLB invalidation cycles event=0x43,umask=0x4 01 : Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events unc_iio_mask_match_and.bus0 uncore io AND Mask/match for debug bus : Non-PCIE bus event=0x2,umask=0x1 01 AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and PCIE bus event=0x2,umask=0x8 01 AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_not_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=0x2,umask=0x4 01 AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus1 uncore io AND Mask/match for debug bus : PCIE bus event=0x2,umask=0x2 01 AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=0x2,umask=0x10 01 AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_not_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=0x2,umask=0x20 01 AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_or.bus0 uncore io OR Mask/match for debug bus : Non-PCIE bus event=0x3,umask=0x1 01 OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and PCIE bus event=0x3,umask=0x8 01 OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_not_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=0x3,umask=0x4 01 OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus1 uncore io OR Mask/match for debug bus : PCIE bus event=0x3,umask=0x2 01 OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=0x3,umask=0x10 01 OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_not_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=0x3,umask=0x20 01 OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_nothing uncore io Counting disabled event=0x80 01 unc_iio_num_oustanding_req_from_cpu.to_io uncore io Occupancy of outbound request queue : To device event=0xc5,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing unc_iio_num_outstanding_req_of_cpu.data uncore io : Passing data to be written event=0x88,ch_mask=0xFF,fc_mask=0x07,umask=0x20 01 : Passing data to be written : Only for posted requests unc_iio_num_outstanding_req_of_cpu.final_rd_wr uncore io : Issuing final read or write of line event=0x88,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 unc_iio_num_outstanding_req_of_cpu.iommu_hit uncore io : Processing response from IOMMU event=0x88,ch_mask=0xFF,fc_mask=0x07,umask=0x2 01 unc_iio_num_outstanding_req_of_cpu.iommu_req uncore io : Issuing to IOMMU event=0x88,ch_mask=0xFF,fc_mask=0x07,umask=0x1 01 unc_iio_num_outstanding_req_of_cpu.req_own uncore io : Request Ownership event=0x88,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 : Request Ownership : Only for posted requests unc_iio_num_outstanding_req_of_cpu.wr uncore io : Writing line event=0x88,ch_mask=0xFF,fc_mask=0x07,umask=0x10 01 : Writing line : Only for posted requests unc_iio_num_req_from_cpu.irp uncore io Number requests sent to PCIe from main die : From IRP event=0xc2,ch_mask=0xFF,fc_mask=0x07,umask=0x1 01 Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU unc_iio_num_req_from_cpu.itc uncore io Number requests sent to PCIe from main die : From ITC event=0xc2,ch_mask=0xFF,fc_mask=0x07,umask=0x2 01 Number requests sent to PCIe from main die : From ITC : Confined P2P unc_iio_num_req_from_cpu.prealloc uncore io Number requests sent to PCIe from main die : Completion allocations event=0xc2,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 unc_iio_num_req_of_cpu.all.drop uncore io Number requests PCIe makes of the main die : Drop request event=0x85,ch_mask=0xFF,fc_mask=0x07,umask=0x2 01 Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped unc_iio_num_req_of_cpu.commit.all uncore io Number requests PCIe makes of the main die : All event=0x85,ch_mask=0xFF,fc_mask=0x07,umask=0x1 01 Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU unc_iio_num_req_of_cpu_by_tgt.abort uncore io Num requests sent by PCIe - by target : Abort event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x80 01 unc_iio_num_req_of_cpu_by_tgt.confined_p2p uncore io Num requests sent by PCIe - by target : Confined P2P event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x40 01 unc_iio_num_req_of_cpu_by_tgt.loc_p2p uncore io Num requests sent by PCIe - by target : Local P2P event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x20 01 unc_iio_num_req_of_cpu_by_tgt.mcast uncore io Num requests sent by PCIe - by target : Multi-cast event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x2 01 unc_iio_num_req_of_cpu_by_tgt.mem uncore io Num requests sent by PCIe - by target : Memory event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 unc_iio_num_req_of_cpu_by_tgt.msgb uncore io Num requests sent by PCIe - by target : MsgB event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x1 01 unc_iio_num_req_of_cpu_by_tgt.rem_p2p uncore io Num requests sent by PCIe - by target : Remote P2P event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x10 01 unc_iio_num_req_of_cpu_by_tgt.ubox uncore io Num requests sent by PCIe - by target : Ubox event=0x8e,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 unc_iio_num_tgt_matched_req_of_cpu uncore io ITC address map 1 event=0x8f 01 unc_iio_outbound_cl_reqs_issued.to_io uncore io Outbound cacheline requests issued : 64B requests issued to device event=0xd0,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line unc_iio_outbound_tlp_reqs_issued.to_io uncore io Outbound TLP (transaction layer packet) requests issued : To device event=0xd1,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer unc_iio_pwt_occupancy uncore io PWT occupancy event=0x42 01 PWT occupancy : Indicates how many page walks are outstanding at any point in time unc_iio_req_from_pcie_cl_cmpl.data uncore io PCIe Request - cacheline complete : Passing data to be written event=0x91,ch_mask=0xFF,fc_mask=0x07,umask=0x20 01 PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.final_rd_wr uncore io PCIe Request - cacheline complete : Issuing final read or write of line event=0x91,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line unc_iio_req_from_pcie_cl_cmpl.req_own uncore io PCIe Request - cacheline complete : Request Ownership event=0x91,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.wr uncore io PCIe Request - cacheline complete : Writing line event=0x91,ch_mask=0xFF,fc_mask=0x07,umask=0x10 01 PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cmpl.data uncore io PCIe Request complete : Passing data to be written event=0x92,ch_mask=0xFF,fc_mask=0x07,umask=0x20 01 PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_cmpl.final_rd_wr uncore io PCIe Request complete : Issuing final read or write of line event=0x92,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.iommu_hit uncore io PCIe Request complete : Processing response from IOMMU event=0x92,ch_mask=0xFF,fc_mask=0x07,umask=0x2 01 PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.iommu_req uncore io PCIe Request complete : Issuing to IOMMU event=0x92,ch_mask=0xFF,fc_mask=0x07,umask=0x1 01 PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.req_own uncore io PCIe Request complete : Request Ownership event=0x92,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_cmpl.wr uncore io PCIe Request complete : Writing line event=0x92,ch_mask=0xFF,fc_mask=0x07,umask=0x10 01 PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.data uncore io PCIe Request - pass complete : Passing data to be written event=0x90,ch_mask=0xFF,fc_mask=0x07,umask=0x20 01 PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.final_rd_wr uncore io PCIe Request - pass complete : Issuing final read or write of line event=0x90,ch_mask=0xFF,fc_mask=0x07,umask=0x8 01 PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state unc_iio_req_from_pcie_pass_cmpl.req_own uncore io PCIe Request - pass complete : Request Ownership event=0x90,ch_mask=0xFF,fc_mask=0x07,umask=0x4 01 PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.wr uncore io PCIe Request - pass complete : Writing line event=0x90,ch_mask=0xFF,fc_mask=0x07,umask=0x10 01 PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_symbol_times uncore io Symbol Times on Link event=0x82 01 Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS unc_iio_txn_req_by_cpu.cfg_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x100,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.cfg_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.cfg_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.cfg_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.cfg_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.cfg_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x40 01 Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.cfg_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x100,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.cfg_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.cfg_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.cfg_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.cfg_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.cfg_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x10 01 Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.io_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x100,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.io_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.io_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.io_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.io_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.io_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x80 01 Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.io_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x100,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.io_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.io_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.io_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.io_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.io_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x20 01 Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.mem_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x100,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.mem_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x4 01 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.mem_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x100,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.mem_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x1 01 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.peer_read.iommu0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x100,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.peer_read.iommu1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.peer_read.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_read.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_read.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_read.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_read.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_read.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_read.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_read.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x8 01 Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.peer_write.iommu0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x200,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_write.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_write.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_write.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x2 01 Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.atomic.iommu0 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x100,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.atomic.iommu1 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x200,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.atomic.part0 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomic.part1 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomic.part2 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomic.part3 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.atomic.part4 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.atomic.part5 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.atomic.part6 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.atomic.part7 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x10 01 Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.cmpd.iommu0 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x100,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.cmpd.iommu1 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x200,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.cmpd.part0 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.cmpd.part1 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.cmpd.part2 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.cmpd.part3 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.cmpd.part4 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.cmpd.part5 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.cmpd.part6 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.cmpd.part7 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x80 01 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.mem_read.iommu0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x100,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.mem_read.iommu1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x200,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x4 01 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.mem_write.iommu0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x100,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.mem_write.iommu1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x200,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x1 01 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.msg.iommu0 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x100,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.msg.iommu1 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x200,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.msg.part0 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.msg.part1 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.msg.part2 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.msg.part3 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.msg.part4 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.msg.part5 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.msg.part6 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.msg.part7 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x40 01 Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.peer_read.iommu0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x100,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.peer_read.iommu1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x200,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_read.part4 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.peer_read.part5 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.peer_read.part6 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.peer_read.part7 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x8 01 Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.peer_write.iommu0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x100,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.peer_write.iommu1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x200,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_write.part4 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.peer_write.part5 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.peer_write.part6 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.peer_write.part7 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x2 01 Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_m2p_ag0_ad_crd_acquired0.tgr0 uncore io CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr1 uncore io CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr2 uncore io CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr3 uncore io CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=0x8 01 CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr4 uncore io CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10 01 CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr5 uncore io CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20 01 CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr6 uncore io CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40 01 CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr7 uncore io CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80 01 CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr10 uncore io CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=0x4 01 CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr8 uncore io CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=0x1 01 CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr9 uncore io CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=0x2 01 CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr0 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr1 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr2 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr3 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=0x8 01 CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr4 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10 01 CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr5 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20 01 CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr6 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40 01 CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr7 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80 01 CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr10 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=0x4 01 CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr8 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=0x1 01 CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr9 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=0x2 01 CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr0 uncore io CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr1 uncore io CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr2 uncore io CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr3 uncore io CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=0x8 01 CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr4 uncore io CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10 01 CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr5 uncore io CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20 01 CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr6 uncore io CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40 01 CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr7 uncore io CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80 01 CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr10 uncore io CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=0x4 01 CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr8 uncore io CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=0x1 01 CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr9 uncore io CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=0x2 01 CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr0 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr1 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr2 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr3 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=0x8 01 CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr4 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10 01 CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr5 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20 01 CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr6 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40 01 CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr7 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80 01 CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr10 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=0x4 01 CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr8 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=0x1 01 CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr9 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=0x2 01 CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr0 uncore io CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr1 uncore io CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr2 uncore io CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr3 uncore io CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=0x8 01 CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr4 uncore io CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10 01 CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr5 uncore io CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20 01 CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr6 uncore io CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40 01 CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr7 uncore io CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80 01 CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr10 uncore io CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=0x4 01 CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr8 uncore io CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=0x1 01 CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr9 uncore io CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=0x2 01 CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr0 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr1 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr2 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr3 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=0x8 01 CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr4 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10 01 CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr5 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20 01 CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr6 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40 01 CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr7 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80 01 CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr10 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=0x4 01 CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr8 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=0x1 01 CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr9 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=0x2 01 CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr0 uncore io CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr1 uncore io CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr2 uncore io CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr3 uncore io CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=0x8 01 CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr4 uncore io CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr5 uncore io CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr6 uncore io CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40 01 CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr7 uncore io CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80 01 CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr10 uncore io CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=0x4 01 CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr8 uncore io CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=0x1 01 CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr9 uncore io CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=0x2 01 CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr0 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr1 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr2 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr3 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=0x8 01 CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr4 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10 01 CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr5 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20 01 CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr6 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40 01 CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr7 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80 01 CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr10 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=0x4 01 CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr8 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=0x1 01 CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr9 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=0x2 01 CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_clockticks uncore io Clockticks of the mesh to PCI (M2P) event=0x1 01 Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m2p_distress_asserted.dpt_local uncore io Distress signal asserted : DPT Local event=0xaf,umask=0x4 01 Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m2p_distress_asserted.dpt_nonlocal uncore io Distress signal asserted : DPT Remote event=0xaf,umask=0x8 01 Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m2p_distress_asserted.dpt_stall_iv uncore io Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40 01 Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m2p_distress_asserted.dpt_stall_nocrd uncore io Distress signal asserted : DPT Stalled - No Credit event=0xaf,umask=0x80 01 Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m2p_distress_asserted.horz uncore io Distress signal asserted : Horizontal event=0xaf,umask=0x2 01 Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m2p_distress_asserted.pmm_local uncore io Distress signal asserted : PMM Local event=0xaf,umask=0x10 01 Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2p_distress_asserted.pmm_nonlocal uncore io Distress signal asserted : PMM Remote event=0xaf,umask=0x20 01 Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2p_distress_asserted.vert uncore io Distress signal asserted : Vertical event=0xaf,umask=0x1 01 Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m2p_horz_ring_ad_in_use.left_even uncore io Horizontal AD Ring In Use : Left and Even event=0xb6,umask=0x1 01 Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.left_odd uncore io Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=0x2 01 Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.right_even uncore io Horizontal AD Ring In Use : Right and Even event=0xb6,umask=0x4 01 Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.right_odd uncore io Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=0x8 01 Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.left_even uncore io Horizontal AK Ring In Use : Left and Even event=0xbb,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.left_odd uncore io Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.right_even uncore io Horizontal AK Ring In Use : Right and Even event=0xbb,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.right_odd uncore io Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.left_even uncore io Horizontal AK Ring In Use : Left and Even event=0xb7,umask=0x1 01 Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.left_odd uncore io Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=0x2 01 Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.right_even uncore io Horizontal AK Ring In Use : Right and Even event=0xb7,umask=0x4 01 Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.right_odd uncore io Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=0x8 01 Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.left_even uncore io Horizontal BL Ring in Use : Left and Even event=0xb8,umask=0x1 01 Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.left_odd uncore io Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=0x2 01 Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.right_even uncore io Horizontal BL Ring in Use : Right and Even event=0xb8,umask=0x4 01 Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.right_odd uncore io Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=0x8 01 Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_iv_in_use.left uncore io Horizontal IV Ring in Use : Left event=0xb9,umask=0x1 01 Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_horz_ring_iv_in_use.right uncore io Horizontal IV Ring in Use : Right event=0xb9,umask=0x4 01 Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB event=0x19,umask=0x10 01 unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS event=0x19,umask=0x20 01 unc_m2p_misc_external.mbe_inst0 uncore io Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=0x1 01 unc_m2p_misc_external.mbe_inst1 uncore io Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=0x2 01 unc_m2p_ring_bounces_horz.ad uncore io Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=0x1 01 Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.ak uncore io Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=0x2 01 Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.bl uncore io Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=0x4 01 Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.iv uncore io Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=0x8 01 Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_vert.ad uncore io Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=0x1 01 Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.ak uncore io Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=0x2 01 Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.akc uncore io Messages that bounced on the Vertical Ring event=0xaa,umask=0x10 01 Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.bl uncore io Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=0x4 01 Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.iv uncore io Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=0x8 01 Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_sink_starved_horz.ad uncore io Sink Starvation on Horizontal Ring : AD event=0xad,umask=0x1 01 unc_m2p_ring_sink_starved_horz.ak uncore io Sink Starvation on Horizontal Ring : AK event=0xad,umask=0x2 01 unc_m2p_ring_sink_starved_horz.ak_ag1 uncore io Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20 01 unc_m2p_ring_sink_starved_horz.bl uncore io Sink Starvation on Horizontal Ring : BL event=0xad,umask=0x4 01 unc_m2p_ring_sink_starved_horz.iv uncore io Sink Starvation on Horizontal Ring : IV event=0xad,umask=0x8 01 unc_m2p_ring_sink_starved_vert.ad uncore io Sink Starvation on Vertical Ring : AD event=0xab,umask=0x1 01 unc_m2p_ring_sink_starved_vert.ak uncore io Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=0x2 01 unc_m2p_ring_sink_starved_vert.akc uncore io Sink Starvation on Vertical Ring event=0xab,umask=0x10 01 unc_m2p_ring_sink_starved_vert.bl uncore io Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=0x4 01 unc_m2p_ring_sink_starved_vert.iv uncore io Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=0x8 01 unc_m2p_ring_src_thrtl uncore io Source Throttle event=0xae 01 unc_m2p_rxr_busy_starved.ad_all uncore io Transgress Injection Starvation : AD - All event=0xe5,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2p_rxr_busy_starved.ad_crd uncore io Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.ad_uncrd uncore io Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.bl_all uncore io Transgress Injection Starvation : BL - All event=0xe5,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2p_rxr_busy_starved.bl_crd uncore io Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.bl_uncrd uncore io Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority unc_m2p_rxr_bypass.ad_all uncore io Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11 01 Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2p_rxr_bypass.ad_crd uncore io Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10 01 Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.ad_uncrd uncore io Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=0x1 01 Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.ak uncore io Transgress Ingress Bypass : AK event=0xe2,umask=0x2 01 Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.akc_uncrd uncore io Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80 01 Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.bl_all uncore io Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44 01 Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2p_rxr_bypass.bl_crd uncore io Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40 01 Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.bl_uncrd uncore io Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=0x4 01 Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.iv uncore io Transgress Ingress Bypass : IV event=0xe2,umask=0x8 01 Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m2p_rxr_crd_starved.ad_all uncore io Transgress Injection Starvation : AD - All event=0xe3,umask=0x11 01 Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2p_rxr_crd_starved.ad_crd uncore io Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10 01 Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ad_uncrd uncore io Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=0x1 01 Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ak uncore io Transgress Injection Starvation : AK event=0xe3,umask=0x2 01 Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.bl_all uncore io Transgress Injection Starvation : BL - All event=0xe3,umask=0x44 01 Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2p_rxr_crd_starved.bl_crd uncore io Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40 01 Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.bl_uncrd uncore io Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=0x4 01 Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ifv uncore io Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80 01 Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.iv uncore io Transgress Injection Starvation : IV event=0xe3,umask=0x8 01 Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved_1 uncore io Transgress Injection Starvation event=0xe4 01 Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_inserts.ad_all uncore io Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11 01 Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_inserts.ad_crd uncore io Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10 01 Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.ad_uncrd uncore io Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=0x1 01 Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.ak uncore io Transgress Ingress Allocations : AK event=0xe1,umask=0x2 01 Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.akc_uncrd uncore io Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80 01 Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.bl_all uncore io Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44 01 Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_inserts.bl_crd uncore io Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40 01 Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.bl_uncrd uncore io Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=0x4 01 Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.iv uncore io Transgress Ingress Allocations : IV event=0xe1,umask=0x8 01 Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ad_all uncore io Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11 01 Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_occupancy.ad_crd uncore io Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10 01 Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ad_uncrd uncore io Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=0x1 01 Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ak uncore io Transgress Ingress Occupancy : AK event=0xe0,umask=0x2 01 Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.akc_uncrd uncore io Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80 01 Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.bl_all uncore io Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44 01 Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_occupancy.bl_crd uncore io Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20 01 Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.bl_uncrd uncore io Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=0x4 01 Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.iv uncore io Transgress Ingress Occupancy : IV event=0xe0,umask=0x8 01 Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=0x8 01 Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10 01 Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20 01 Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40 01 Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80 01 Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=0x8 01 Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10 01 Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20 01 Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40 01 Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80 01 Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=0x8 01 Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10 01 Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20 01 Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40 01 Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80 01 Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=0x8 01 Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10 01 Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20 01 Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40 01 Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80 01 Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=0x4 01 Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=0x1 01 Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=0x2 01 Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=0x4 01 Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=0x1 01 Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=0x2 01 Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=0x4 01 Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=0x1 01 Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=0x2 01 Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=0x4 01 Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=0x1 01 Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=0x2 01 Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_txc_cycles_full.ad_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x1 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ad_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x10 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ak_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x2 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ak_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x20 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.bl_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x4 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.bl_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x40 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.pmm_block_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x80 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.pmm_block_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x8 01 Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_ne.ad_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x1 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ad_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x10 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ak_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x2 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ak_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x20 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.bl_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x4 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.bl_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x40 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.pmm_distress_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x80 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.pmm_distress_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x8 01 Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_inserts.ad_0 uncore io Egress (to CMS) Ingress event=0x24,umask=0x1 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ad_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x10 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ak_crd_0 uncore io Egress (to CMS) Ingress event=0x24,umask=0x8 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ak_crd_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x80 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.bl_0 uncore io Egress (to CMS) Ingress event=0x24,umask=0x4 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.bl_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x40 01 Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txr_horz_ads_used.ad_all uncore io CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11 01 CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_ads_used.ad_crd uncore io CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10 01 CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.ad_uncrd uncore io CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=0x1 01 CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.bl_all uncore io CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44 01 CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_ads_used.bl_crd uncore io CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40 01 CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.bl_uncrd uncore io CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=0x4 01 CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ad_all uncore io CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11 01 CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_bypass.ad_crd uncore io CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10 01 CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ad_uncrd uncore io CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=0x1 01 CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ak uncore io CMS Horizontal Bypass Used : AK event=0xa7,umask=0x2 01 CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.akc_uncrd uncore io CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80 01 CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.bl_all uncore io CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44 01 CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_bypass.bl_crd uncore io CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40 01 CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.bl_uncrd uncore io CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=0x4 01 CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.iv uncore io CMS Horizontal Bypass Used : IV event=0xa7,umask=0x8 01 CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_cycles_full.ad_all uncore io Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_full.ad_crd uncore io Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.ad_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.ak uncore io Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.akc_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.bl_all uncore io Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_full.bl_crd uncore io Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.bl_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.iv uncore io Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ad_all uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_ne.ad_crd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ad_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=0x1 01 Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ak uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=0x2 01 Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.akc_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80 01 Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.bl_all uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_ne.bl_crd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.bl_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=0x4 01 Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.iv uncore io Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=0x8 01 Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ad_all uncore io CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11 01 CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_inserts.ad_crd uncore io CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10 01 CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ad_uncrd uncore io CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=0x1 01 CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ak uncore io CMS Horizontal Egress Inserts : AK event=0xa1,umask=0x2 01 CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.akc_uncrd uncore io CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80 01 CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.bl_all uncore io CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44 01 CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_inserts.bl_crd uncore io CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40 01 CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.bl_uncrd uncore io CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=0x4 01 CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.iv uncore io CMS Horizontal Egress Inserts : IV event=0xa1,umask=0x8 01 CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_nack.ad_all uncore io CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11 01 CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2p_txr_horz_nack.ad_crd uncore io CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10 01 CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.ad_uncrd uncore io CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=0x1 01 CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.ak uncore io CMS Horizontal Egress NACKs : AK event=0xa4,umask=0x2 01 CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.akc_uncrd uncore io CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80 01 CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.bl_all uncore io CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44 01 CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2p_txr_horz_nack.bl_crd uncore io CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40 01 CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.bl_uncrd uncore io CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=0x4 01 CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.iv uncore io CMS Horizontal Egress NACKs : IV event=0xa4,umask=0x8 01 CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_occupancy.ad_all uncore io CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11 01 CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_occupancy.ad_crd uncore io CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10 01 CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.ad_uncrd uncore io CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=0x1 01 CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.ak uncore io CMS Horizontal Egress Occupancy : AK event=0xa0,umask=0x2 01 CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.akc_uncrd uncore io CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80 01 CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.bl_all uncore io CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44 01 CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_occupancy.bl_crd uncore io CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40 01 CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.bl_uncrd uncore io CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=0x4 01 CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.iv uncore io CMS Horizontal Egress Occupancy : IV event=0xa0,umask=0x8 01 CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_starved.ad_all uncore io CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2p_txr_horz_starved.ad_uncrd uncore io CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=0x1 01 CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.ak uncore io CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=0x2 01 CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.akc_uncrd uncore io CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80 01 CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.bl_all uncore io CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2p_txr_horz_starved.bl_uncrd uncore io CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=0x4 01 CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.iv uncore io CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=0x8 01 CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_vert_ads_used.ad_ag0 uncore io CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.ad_ag1 uncore io CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.bl_ag0 uncore io CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.bl_ag1 uncore io CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ad_ag0 uncore io CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=0x1 01 CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ad_ag1 uncore io CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10 01 CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ak_ag0 uncore io CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=0x2 01 CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ak_ag1 uncore io CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20 01 CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.bl_ag0 uncore io CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=0x4 01 CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.bl_ag1 uncore io CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40 01 CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.iv_ag1 uncore io CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=0x8 01 CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass_1.akc_ag0 uncore io CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=0x1 01 CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass_1.akc_ag1 uncore io CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=0x2 01 CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_cycles_full0.ad_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_full0.ad_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_cycles_full0.ak_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_full0.ak_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_cycles_full0.bl_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_cycles_full0.bl_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_cycles_full0.iv_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_cycles_full1.akc_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_full1.akc_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_ne0.ad_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_ne0.ad_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10 01 Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_cycles_ne0.ak_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_ne0.ak_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20 01 Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_cycles_ne0.bl_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=0x4 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_cycles_ne0.bl_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40 01 Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_cycles_ne0.iv_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=0x8 01 Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_cycles_ne1.akc_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=0x1 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_ne1.akc_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=0x2 01 Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_inserts0.ad_ag0 uncore io CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=0x1 01 CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_inserts0.ad_ag1 uncore io CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10 01 CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_inserts0.ak_ag0 uncore io CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=0x2 01 CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_inserts0.ak_ag1 uncore io CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20 01 CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_inserts0.bl_ag0 uncore io CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=0x4 01 CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_inserts0.bl_ag1 uncore io CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40 01 CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_inserts0.iv_ag0 uncore io CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=0x8 01 CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_inserts1.akc_ag0 uncore io CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=0x1 01 CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_inserts1.akc_ag1 uncore io CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=0x2 01 CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_nack0.ad_ag0 uncore io CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=0x1 01 CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ad_ag1 uncore io CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10 01 CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ak_ag0 uncore io CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=0x2 01 CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ak_ag1 uncore io CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20 01 CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.bl_ag0 uncore io CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=0x4 01 CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.bl_ag1 uncore io CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40 01 CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.iv_ag0 uncore io CMS Vertical Egress NACKs : IV event=0x98,umask=0x8 01 CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack1.akc_ag0 uncore io CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=0x1 01 CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack1.akc_ag1 uncore io CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=0x2 01 CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_occupancy0.ad_ag0 uncore io CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=0x1 01 CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_occupancy0.ad_ag1 uncore io CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10 01 CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests unc_m2p_txr_vert_occupancy0.ak_ag0 uncore io CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=0x2 01 CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_occupancy0.ak_ag1 uncore io CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20 01 CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_occupancy0.bl_ag0 uncore io CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=0x4 01 CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_occupancy0.bl_ag1 uncore io CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40 01 CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_occupancy0.iv_ag0 uncore io CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=0x8 01 CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores unc_m2p_txr_vert_occupancy1.akc_ag0 uncore io CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=0x1 01 CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_occupancy1.akc_ag1 uncore io CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=0x2 01 CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses unc_m2p_txr_vert_starved0.ad_ag0 uncore io CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=0x1 01 CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ad_ag1 uncore io CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10 01 CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ak_ag0 uncore io CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=0x2 01 CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ak_ag1 uncore io CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20 01 CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.bl_ag0 uncore io CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=0x4 01 CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.bl_ag1 uncore io CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40 01 CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.iv_ag0 uncore io CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=0x8 01 CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.akc_ag0 uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x1 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.akc_ag1 uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=0x2 01 CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.tgc uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=0x4 01 CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_vert_ring_ad_in_use.dn_even uncore io Vertical AD Ring In Use : Down and Even event=0xb0,umask=0x4 01 Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.dn_odd uncore io Vertical AD Ring In Use : Down and Odd event=0xb0,umask=0x8 01 Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.up_even uncore io Vertical AD Ring In Use : Up and Even event=0xb0,umask=0x1 01 Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.up_odd uncore io Vertical AD Ring In Use : Up and Odd event=0xb0,umask=0x2 01 Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.dn_even uncore io Vertical AKC Ring In Use : Down and Even event=0xb4,umask=0x4 01 Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.dn_odd uncore io Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=0x8 01 Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.up_even uncore io Vertical AKC Ring In Use : Up and Even event=0xb4,umask=0x1 01 Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.up_odd uncore io Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=0x2 01 Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.dn_even uncore io Vertical AK Ring In Use : Down and Even event=0xb1,umask=0x4 01 Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.dn_odd uncore io Vertical AK Ring In Use : Down and Odd event=0xb1,umask=0x8 01 Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.up_even uncore io Vertical AK Ring In Use : Up and Even event=0xb1,umask=0x1 01 Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.up_odd uncore io Vertical AK Ring In Use : Up and Odd event=0xb1,umask=0x2 01 Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.dn_even uncore io Vertical BL Ring in Use : Down and Even event=0xb2,umask=0x4 01 Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.dn_odd uncore io Vertical BL Ring in Use : Down and Odd event=0xb2,umask=0x8 01 Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.up_even uncore io Vertical BL Ring in Use : Up and Even event=0xb2,umask=0x1 01 Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.up_odd uncore io Vertical BL Ring in Use : Up and Odd event=0xb2,umask=0x2 01 Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_iv_in_use.dn uncore io Vertical IV Ring in Use : Down event=0xb3,umask=0x4 01 Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_vert_ring_iv_in_use.up uncore io Vertical IV Ring in Use : Up event=0xb3,umask=0x1 01 Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_vert_ring_tgc_in_use.dn_even uncore io Vertical TGC Ring In Use : Down and Even event=0xb5,umask=0x4 01 Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.dn_odd uncore io Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=0x8 01 Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.up_even uncore io Vertical TGC Ring In Use : Up and Even event=0xb5,umask=0x1 01 Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.up_odd uncore io Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=0x2 01 Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m_act_count.all uncore memory DRAM Activate Count : All Activates event=0x1,umask=0xb 01 DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.byp uncore memory DRAM Activate Count : Activate due to Bypass event=0x1,umask=0x8 01 DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory All DRAM CAS commands issued event=0x4,umask=0x3f 01 Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.rd uncore memory All DRAM read CAS commands issued (including underfills) event=0x4,umask=0xf 01 Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills unc_m_cas_count.rd_pre_reg uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre event=0x4,umask=0x2 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with explicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_pre_underfill uncore memory DRAM RD_CAS and WR_CAS Commands event=0x4,umask=0x8 01 DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_reg uncore memory All DRAM read CAS commands issued (does not include underfills) event=0x4,umask=0x1 01 Counts the total number of DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_underfill uncore memory DRAM underfill read CAS commands issued event=0x4,umask=0x4 01 Counts the total of DRAM Read CAS commands issued due to an underfill unc_m_cas_count.wr uncore memory All DRAM write CAS commands issued event=0x4,umask=0x30 01 Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel unc_m_cas_count.wr_nonpre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre event=0x4,umask=0x10 01 DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr_pre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre event=0x4,umask=0x20 01 DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_clockticks_freerun uncore memory Free running counter that increments for the Memory Controller event=0xff,umask=0x10 01 unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=0x44 01 DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent unc_m_dram_refresh.high uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x4 01 Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.opportunistic uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x1 01 Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.panic uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x2 01 Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_hclockticks uncore memory Half clockticks for IMC event=0xff 01 unc_m_parity_errors uncore memory UNC_M_PARITY_ERRORS event=0x2c 01 unc_m_pcls.rd uncore memory UNC_M_PCLS.RD event=0xa0,umask=0x1 01 unc_m_pcls.total uncore memory UNC_M_PCLS.TOTAL event=0xa0,umask=0x4 01 unc_m_pcls.wr uncore memory UNC_M_PCLS.WR event=0xa0,umask=0x2 01 unc_m_pmm_cmd1.all uncore memory PMM Commands : All event=0xea,umask=0x1 01 PMM Commands : All : Counts all commands issued to PMM unc_m_pmm_cmd1.misc uncore memory PMM Commands : Misc Commands (error, flow ACKs) event=0xea,umask=0x80 01 unc_m_pmm_cmd1.misc_gnt uncore memory PMM Commands : Misc GNTs event=0xea,umask=0x40 01 unc_m_pmm_cmd1.rd uncore memory PMM Commands : Reads - RPQ event=0xea,umask=0x2 01 PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ unc_m_pmm_cmd1.rpq_gnts uncore memory PMM Commands : RPQ GNTs event=0xea,umask=0x10 01 unc_m_pmm_cmd1.ufill_rd uncore memory PMM Commands : Underfill reads event=0xea,umask=0x8 01 PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM unc_m_pmm_cmd1.wpq_gnts uncore memory PMM Commands : Underfill GNTs event=0xea,umask=0x20 01 unc_m_pmm_cmd1.wr uncore memory PMM Commands : Writes event=0xea,umask=0x4 01 PMM Commands : Writes : Counts write commands issued to PMM unc_m_pmm_cmd2.nodata_exp uncore memory PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding) event=0xeb,umask=0x2 01 unc_m_pmm_cmd2.nodata_unexp uncore memory PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP) event=0xeb,umask=0x4 01 unc_m_pmm_cmd2.opp_rd uncore memory PMM Commands - Part 2 : Opportunistic Reads event=0xeb,umask=0x1 01 unc_m_pmm_cmd2.pmm_ecc_error uncore memory PMM Commands - Part 2 : ECC Errors event=0xeb,umask=0x20 01 unc_m_pmm_cmd2.pmm_erid_error uncore memory PMM Commands - Part 2 : ERID detectable parity error event=0xeb,umask=0x40 01 unc_m_pmm_cmd2.pmm_erid_starved uncore memory PMM Commands - Part 2 event=0xeb,umask=0x80 01 unc_m_pmm_cmd2.reqs_slot0 uncore memory PMM Commands - Part 2 : Read Requests - Slot 0 event=0xeb,umask=0x8 01 unc_m_pmm_cmd2.reqs_slot1 uncore memory PMM Commands - Part 2 : Read Requests - Slot 1 event=0xeb,umask=0x10 01 unc_m_pmm_rpq_inserts uncore memory PMM Read Queue Inserts event=0xe3 01 PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue. This includes both ISOCH and non-ISOCH requests unc_m_pmm_rpq_occupancy.all uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x1 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x4 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x2 01 PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_wpq_flush uncore memory UNC_M_PMM_WPQ_FLUSH event=0xe8 01 unc_m_pmm_wpq_flush_cyc uncore memory UNC_M_PMM_WPQ_FLUSH_CYC event=0xe9 01 unc_m_pmm_wpq_inserts uncore memory PMM Write Queue Inserts event=0xe7 01 PMM Write Queue Inserts : Counts number of write requests allocated in the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=0x1 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.cas uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=0x2 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.pwr uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=0x4 01 PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_power_throttle_cycles.slot0 uncore memory Throttle Cycles for Rank 0 event=0x46,umask=0x1 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID unc_m_power_throttle_cycles.slot1 uncore memory Throttle Cycles for Rank 0 event=0x46,umask=0x2 01 Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_pre_count.all uncore memory DRAM Precharge commands event=0x2,umask=0x1c 01 DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_miss uncore memory DRAM Precharge commands. : Precharge due to page miss event=0x2,umask=0xc 01 DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests) unc_m_pre_count.pgt uncore memory DRAM Precharge commands. : Precharge due to page table event=0x2,umask=0x10 01 DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table unc_m_pre_count.rd uncore memory DRAM Precharge commands. : Precharge due to read event=0x2,umask=0x4 01 DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.wr uncore memory DRAM Precharge commands. : Precharge due to write event=0x2,umask=0x8 01 DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_m_rdb_full uncore memory Read Data Buffer Full event=0x19 01 unc_m_rdb_inserts uncore memory Read Data Buffer Inserts event=0x17 01 unc_m_rdb_not_empty uncore memory Read Data Buffer Not Empty event=0x18 01 unc_m_rdb_occupancy uncore memory Read Data Buffer Occupancy event=0x1a 01 unc_m_rpq_cycles_full_pch0 uncore memory Read Pending Queue Full Cycles event=0x12 01 Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries unc_m_rpq_cycles_full_pch1 uncore memory Read Pending Queue Full Cycles event=0x15 01 Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries unc_m_rpq_cycles_ne.pch0 uncore memory Read Pending Queue Not Empty event=0x11,umask=0x1 01 Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_rpq_cycles_ne.pch1 uncore memory Read Pending Queue Not Empty event=0x11,umask=0x2 01 Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_sb_accesses.accepts uncore memory Scoreboard Accesses : Scoreboard Accesses Accepted event=0xd2,umask=0x5 01 unc_m_sb_accesses.fmrd_cmps uncore memory This event is deprecated event=0xd2,umask=0x40 11 unc_m_sb_accesses.fmwr_cmps uncore memory This event is deprecated event=0xd2,umask=0x80 11 unc_m_sb_accesses.nmrd_cmps uncore memory This event is deprecated event=0xd2,umask=0x10 11 unc_m_sb_accesses.nmwr_cmps uncore memory This event is deprecated event=0xd2,umask=0x20 11 unc_m_sb_accesses.rejects uncore memory Scoreboard Accesses : Scoreboard Accesses Rejected event=0xd2,umask=0xa 01 unc_m_sb_canary.fmrd_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED event=0xd9,umask=0x20 11 unc_m_sb_canary.fmtgrwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED event=0xd9,umask=0x80 11 unc_m_sb_canary.fmwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED event=0xd9,umask=0x40 11 unc_m_sb_canary.nmrd_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED event=0xd9,umask=0x8 11 unc_m_sb_canary.nmwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED event=0xd9,umask=0x10 11 unc_m_sb_pref_inserts.pmm uncore memory Scoreboard Prefetch Inserts : Persistent Mem event=0xda,umask=0x4 01 unc_m_sb_pref_occupancy.pmem uncore memory This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM event=0xdb,umask=0x4 11 unc_m_sb_pref_occupancy.pmm uncore memory Scoreboard Prefetch Occupancy : Persistent Mem event=0xdb,umask=0x4 01 unc_m_sb_strv_alloc.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD event=0xd7,umask=0x2 11 unc_m_sb_strv_alloc.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR event=0xd7,umask=0x10 11 unc_m_sb_strv_alloc.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR event=0xd7,umask=0x8 11 unc_m_sb_strv_alloc.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD event=0xd7,umask=0x1 11 unc_m_sb_strv_alloc.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR event=0xd7,umask=0x4 11 unc_m_sb_strv_dealloc.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD event=0xde,umask=0x2 11 unc_m_sb_strv_dealloc.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR event=0xde,umask=0x10 11 unc_m_sb_strv_dealloc.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR event=0xde,umask=0x8 11 unc_m_sb_strv_dealloc.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD event=0xde,umask=0x1 11 unc_m_sb_strv_dealloc.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR event=0xde,umask=0x4 11 unc_m_sb_strv_occ.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD event=0xd8,umask=0x2 11 unc_m_sb_strv_occ.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR event=0xd8,umask=0x10 11 unc_m_sb_strv_occ.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR event=0xd8,umask=0x8 11 unc_m_sb_strv_occ.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD event=0xd8,umask=0x1 11 unc_m_sb_strv_occ.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR event=0xd8,umask=0x4 11 unc_m_tagchk.hit uncore memory 2LM Tag Check : Hit in Near Memory Cache event=0xd3,umask=0x1 01 unc_m_tagchk.miss_clean uncore memory 2LM Tag Check : Miss, no data in this line event=0xd3,umask=0x2 01 unc_m_tagchk.miss_dirty uncore memory 2LM Tag Check : Miss, existing data may be evicted to Far Memory event=0xd3,umask=0x4 01 unc_m_tagchk.nm_rd_hit uncore memory 2LM Tag Check : Read Hit in Near Memory Cache event=0xd3,umask=0x8 01 unc_m_tagchk.nm_wr_hit uncore memory 2LM Tag Check : Write Hit in Near Memory Cache event=0xd3,umask=0x10 01 unc_m_wpq_cycles_full_pch0 uncore memory Write Pending Queue Full Cycles event=0x22 01 Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_full_pch1 uncore memory Write Pending Queue Full Cycles event=0x16 01 Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne.pch0 uncore memory Write Pending Queue Not Empty event=0x21,umask=0x1 01 Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_cycles_ne.pch1 uncore memory Write Pending Queue Not Empty event=0x21,umask=0x2 01 Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_read_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x23,umask=0x1 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_read_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x23,umask=0x2 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x24,umask=0x1 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x24,umask=0x2 01 Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_p_clockticks uncore power Clockticks of the power control unit (PCU) event=0 01 Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_pkg_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c 01 Package C State Residency - C3 : Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State : C0 and C1 event=0x80 01 Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State : C3 event=0x80 01 Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State : C6 and C7 event=0x80 01 Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details dtlb_load_misses.walk_completed_1g virtual memory Page walks completed due to a demand data load to a 1G page event=0x8,period=100003,umask=0x8 00 Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walks completed due to a demand data store to a 1G page event=0x49,period=100003,umask=0x8 00 Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=0x1 00 Counts the number of lines brought into the L1 data cache l1d_pend_miss.fb_full cache Cycles a demand request was blocked due to Fill Buffers unavailability event=0x48,cmask=1,period=2000003,umask=0x2 00 Cycles a demand request was blocked due to Fill Buffers unavailability l1d_pend_miss.pending_cycles_any cache Cycles with L1D load Misses outstanding from any thread on physical core event=0x48,any=1,cmask=1,period=2000003,umask=0x1 00 Cycles with L1D load Misses outstanding from any thread on physical core l2_l1d_wb_rqsts.all cache Not rejected writebacks from L1D to L2 cache lines in any state event=0x28,period=200003,umask=0xf 00 l2_l1d_wb_rqsts.hit_e cache Not rejected writebacks from L1D to L2 cache lines in E state event=0x28,period=200003,umask=0x4 00 Not rejected writebacks from L1D to L2 cache lines in E state l2_l1d_wb_rqsts.hit_m cache Not rejected writebacks from L1D to L2 cache lines in M state event=0x28,period=200003,umask=0x8 00 Not rejected writebacks from L1D to L2 cache lines in M state l2_l1d_wb_rqsts.miss cache Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) event=0x28,period=200003,umask=0x1 00 Not rejected writebacks that missed LLC l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=0x7 00 L2 cache lines filling L2 l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=0x1 00 Clean L2 cache lines evicted by demand l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=0x2 00 Dirty L2 cache lines evicted by demand l2_lines_out.dirty_all cache Dirty L2 cache lines filling the L2 event=0xf2,period=100003,umask=0xa 00 Dirty L2 cache lines filling the L2 l2_lines_out.pf_clean cache Clean L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=0x4 00 Clean L2 cache lines evicted by the MLC prefetcher l2_lines_out.pf_dirty cache Dirty L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=0x8 00 Dirty L2 cache lines evicted by the MLC prefetcher l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0x30 00 Counts all L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0x3 00 Counts any demand and L1 HW prefetch data load requests to L2 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xc0 00 Counts all L2 HW prefetcher requests l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xc 00 Counts all L2 store RFO requests l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0x10 00 Number of instruction fetches that hit the L2 cache l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x20 00 Number of instruction fetches that missed the L2 cache l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0x1 00 Demand Data Read requests that hit L2 cache l2_rqsts.pf_hit cache Requests from the L2 hardware prefetchers that hit L2 cache event=0x24,period=200003,umask=0x40 00 Counts all L2 HW prefetcher requests that hit L2 l2_rqsts.pf_miss cache Requests from the L2 hardware prefetchers that miss L2 cache event=0x24,period=200003,umask=0x80 00 Counts all L2 HW prefetcher requests that missed L2 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0x4 00 RFO requests that hit L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x8 00 Counts the number of store RFO requests that miss the L2 cache l2_store_lock_rqsts.all cache RFOs that access cache lines in any state event=0x27,period=200003,umask=0xf 00 RFOs that access cache lines in any state l2_store_lock_rqsts.hit_m cache RFOs that hit cache lines in M state event=0x27,period=200003,umask=0x8 00 RFOs that hit cache lines in M state l2_store_lock_rqsts.miss cache RFOs that miss cache lines event=0x27,period=200003,umask=0x1 00 RFOs that miss cache lines l2_trans.all_pf cache L2 or LLC HW prefetches that access L2 cache event=0xf0,period=200003,umask=0x8 00 Any MLC or LLC HW prefetch accessing L2, including rejects l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=0x1 00 Demand Data Read requests that access L2 cache longest_lat_cache.miss cache Core-originated cacheable demand requests missed LLC event=0x2e,period=100003,umask=0x41 00 This event counts each cache miss condition for references to the last level cache longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to LLC event=0x2e,period=100003,umask=0x4f 00 This event counts requests originating from the core that reference a cache line in the last level cache mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event) event=0xd2,period=20011,umask=0x2 00 mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC (Precise event) event=0xd2,period=20011,umask=0x4 00 mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event) event=0xd2,period=20011,umask=0x1 00 mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required (Precise event) event=0xd2,period=100003,umask=0x8 00 mem_load_uops_llc_miss_retired.local_dram cache Retired load uops which data sources missed LLC but serviced from local dram event=0xd3,period=100007,umask=0x1 00 Retired load uops whose data source was local memory (cross-socket snoop not needed or missed) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event) event=0xd1,period=100003,umask=0x40 00 mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources (Precise event) event=0xd1,period=2000003,umask=0x1 00 mem_load_uops_retired.l1_miss cache Retired load uops which data sources following L1 data-cache miss (Precise event) event=0xd1,period=100003,umask=0x8 00 mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources (Precise event) event=0xd1,period=100003,umask=0x2 00 mem_load_uops_retired.l2_miss cache Retired load uops with L2 cache misses as data sources (Precise event) event=0xd1,period=50021,umask=0x10 00 mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required (Precise event) event=0xd1,period=50021,umask=0x4 00 mem_load_uops_retired.llc_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source (Precise event) event=0xd1,period=100007,umask=0x20 00 mem_uops_retired.all_loads cache All retired load uops. (Precise Event) event=0xd0,period=2000003,umask=0x81 00 mem_uops_retired.all_stores cache All retired store uops. (Precise Event) event=0xd0,period=2000003,umask=0x82 00 mem_uops_retired.lock_loads cache Retired load uops with locked access. (Precise Event) event=0xd0,period=100007,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary. (Precise Event) event=0xd0,period=100003,umask=0x41 00 mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary. (Precise Event) event=0xd0,period=100003,umask=0x42 00 mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB. (Precise Event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB. (Precise Event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=0x1 00 Demand data read requests sent to uncore offcore_requests_buffer.sq_full cache Cases when offcore requests buffer cannot take more entries for core event=0xb2,period=2000003,umask=0x1 00 Cases when offcore requests buffer cannot take more entries for core offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=0x8 00 Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x8 00 Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore offcore_requests_outstanding.cycles_with_demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=0x2 00 Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x1 00 Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=0x4 00 Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=0x2 00 Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=0x1 00 Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=0x1 00 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=0x4 00 Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_response.all_code_rd.llc_hit.any_response cache Counts all demand & prefetch code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0244 00 offcore_response.all_code_rd.llc_hit.no_snoop_needed cache Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0244 00 offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x000105B3 00 offcore_response.all_data_rd.llc_hit.any_response cache Counts all demand & prefetch data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0091 00 offcore_response.all_data_rd.llc_hit.hitm_other_core cache Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0091 00 offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0091 00 offcore_response.all_data_rd.llc_hit.no_snoop_needed cache Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0091 00 offcore_response.all_reads.any_response cache Counts all data/code/rfo references (demand & prefetch) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x000107F7 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010122 00 offcore_response.all_rfo.llc_hit.any_response cache Counts all demand & prefetch RFOs that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0122 00 offcore_response.all_rfo.llc_hit.no_snoop_needed cache Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0122 00 offcore_response.corewb.any_response cache Counts all writebacks from the core to the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10008 00 offcore_response.demand_code_rd.any_response cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010004 00 offcore_response.demand_code_rd.llc_hit.any_response cache Counts all demand code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0004 00 offcore_response.demand_code_rd.llc_hit.no_snoop_needed cache Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0004 00 offcore_response.demand_data_rd.any_response cache Counts all demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010001 00 offcore_response.demand_data_rd.llc_hit.any_response cache Counts all demand data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0001 00 offcore_response.demand_data_rd.llc_hit.hitm_other_core cache Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0001 00 offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0001 00 offcore_response.demand_data_rd.llc_hit.no_snoop_needed cache Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0001 00 offcore_response.demand_rfo.any_response cache Counts all demand rfo's event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010002 00 offcore_response.demand_rfo.llc_hit.any_response cache Counts all demand data writes (RFOs) that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0002 00 offcore_response.demand_rfo.llc_hit.hitm_other_core cache Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0002 00 offcore_response.demand_rfo.llc_hit.no_snoop_needed cache Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0002 00 offcore_response.other.any_response cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000 00 offcore_response.split_lock_uc_lock.any_response cache Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400 00 offcore_response.streaming_stores.any_response cache Counts non-temporal stores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10800 00 fp_comp_ops_exe.sse_packed_double floating point Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle event=0x10,period=2000003,umask=0x10 00 Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle fp_comp_ops_exe.sse_packed_single floating point Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle event=0x10,period=2000003,umask=0x40 00 Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle fp_comp_ops_exe.sse_scalar_double floating point Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle event=0x10,period=2000003,umask=0x80 00 Counts number of SSE* or AVX-128 double precision FP scalar uops executed fp_comp_ops_exe.sse_scalar_single floating point Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle event=0x10,period=2000003,umask=0x20 00 Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle fp_comp_ops_exe.x87 floating point Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s event=0x10,period=2000003,umask=0x1 00 Counts number of X87 uops executed other_assists.avx_store floating point Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations event=0xc1,period=100003,umask=0x8 00 Number of assists associated with 256-bit AVX store operations other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable event=0xc1,period=100003,umask=0x10 00 other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable event=0xc1,period=100003,umask=0x20 00 simd_fp_256.packed_double floating point number of AVX-256 Computational FP double precision uops issued this cycle event=0x11,period=2000003,umask=0x2 00 Counts 256-bit packed double-precision floating-point instructions simd_fp_256.packed_single floating point number of GSSE-256 Computational FP single precision uops issued this cycle event=0x11,period=2000003,umask=0x1 00 Counts 256-bit packed single-precision floating-point instructions dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=0x1 00 Number of DSB to MITE switches dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=0x2 00 Cycles DSB to MITE switches caused delay dsb_fill.exceed_dsb_lines frontend Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines event=0xac,period=2000003,umask=0x8 00 DSB Fill encountered > 3 DSB lines icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=0x1 00 Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches icache.ifetch_stall frontend Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss event=0x80,period=2000003,umask=0x4 00 Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss icache.misses frontend Instruction cache, streaming buffer and victim cache misses event=0x80,period=200003,umask=0x2 00 Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 Counts cycles MITE is delivered at least one uops. Set Cmask = 1 idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=0x8 00 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=0x2 00 Counts cycles the IDQ is empty idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=0x4 00 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10 00 Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10 00 Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=0x1 00 Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=0x1 00 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=0x1 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=0x2 00 mem_trans_retired.load_latency_gt_128 memory Loads with latency value being above 128 (Must be precise) event=0xcd,period=1009,umask=0x1,ldlat=0x80 00 Loads with latency value being above 128 (Must be precise) mem_trans_retired.load_latency_gt_16 memory Loads with latency value being above 16 (Must be precise) event=0xcd,period=20011,umask=0x1,ldlat=0x10 00 Loads with latency value being above 16 (Must be precise) mem_trans_retired.load_latency_gt_256 memory Loads with latency value being above 256 (Must be precise) event=0xcd,period=503,umask=0x1,ldlat=0x100 00 Loads with latency value being above 256 (Must be precise) mem_trans_retired.load_latency_gt_32 memory Loads with latency value being above 32 (Must be precise) event=0xcd,period=100007,umask=0x1,ldlat=0x20 00 Loads with latency value being above 32 (Must be precise) mem_trans_retired.load_latency_gt_4 memory Loads with latency value being above 4 (Must be precise) event=0xcd,period=100003,umask=0x1,ldlat=0x4 00 Loads with latency value being above 4 (Must be precise) mem_trans_retired.load_latency_gt_512 memory Loads with latency value being above 512 (Must be precise) event=0xcd,period=101,umask=0x1,ldlat=0x200 00 Loads with latency value being above 512 (Must be precise) mem_trans_retired.load_latency_gt_64 memory Loads with latency value being above 64 (Must be precise) event=0xcd,period=2003,umask=0x1,ldlat=0x40 00 Loads with latency value being above 64 (Must be precise) mem_trans_retired.load_latency_gt_8 memory Loads with latency value being above 8 (Must be precise) event=0xcd,period=50021,umask=0x1,ldlat=0x8 00 Loads with latency value being above 8 (Must be precise) mem_trans_retired.precise_store memory Sample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise) event=0xcd,period=2000003,umask=0x2 00 misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=0x5,period=2000003,umask=0x2 00 Speculative cache-line split Store-address uops dispatched to L1D offcore_response.all_code_rd.llc_miss.dram memory Counts all demand & prefetch code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400244 00 offcore_response.all_data_rd.llc_miss.dram memory Counts all demand & prefetch data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400091 00 offcore_response.all_reads.llc_miss.dram memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3004003f7 00 offcore_response.data_in_socket.llc_miss.local_dram memory Counts LLC replacements event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004001b3 00 offcore_response.demand_code_rd.llc_miss.dram memory Counts demand code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400004 00 offcore_response.demand_data_rd.llc_miss.dram memory Counts demand data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400001 00 page_walks.llc_miss memory Number of any page walk that had a miss in LLC event=0xbe,period=100003,umask=0x1 00 cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=0x1 00 Number of intervals between processor halts while thread is in ring 0 arith.fpu_div pipeline Divide operations executed event=0x14,cmask=1,edge=1,period=100003,umask=0x4 00 Divide operations executed arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=0x1 00 Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1 00 Speculative and retired macro-conditional branches br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2 00 Speculative and retired macro-unconditional branches excluding calls and indirects br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0 00 Speculative and retired direct near calls br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4 00 Speculative and retired indirect branches excluding calls and returns br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41 00 Not taken macro-conditional branches br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81 00 Taken speculative and retired macro-conditional branches br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82 00 Taken speculative and retired macro-conditional branch instructions excluding calls and indirects br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90 00 Taken speculative and retired direct near calls br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84 00 Taken speculative and retired indirect branches excluding calls and returns br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0 00 Taken speculative and retired indirect calls br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88 00 Taken speculative and retired indirect branches with return mnemonic br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x1 00 br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40 00 Number of far branches retired br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=0x2 00 br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100007,umask=0x2 00 br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=0x8 00 br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20 00 br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1 00 Speculative and retired mispredicted macro conditional branches br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4 00 Mispredicted indirect branches excluding calls and returns br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41 00 Not taken speculative and retired mispredicted macro conditional branches br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81 00 Taken speculative and retired mispredicted macro conditional branches br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84 00 Taken speculative and retired mispredicted indirect branches excluding calls and returns br_misp_exec.taken_indirect_near_call pipeline Taken speculative and retired mispredicted indirect calls event=0x89,period=200003,umask=0xa0 00 Taken speculative and retired mispredicted indirect calls br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88 00 Taken speculative and retired mispredicted indirect branches with return mnemonic br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=0x4 00 br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20 00 cpu_clk_thread_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other is halted event=0x3c,period=2000003,umask=0x2 00 cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=0x1 00 Increments at the frequency of XCLK (100 MHz) when not halted cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=0x1 00 cpu_clk_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=2000003,umask=0x2 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=0x1 00 Reference cycles when the thread is unhalted. (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=0x1 00 cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003 00 cpu_clk_unhalted.thread_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 Core cycles when at least one thread on the physical core is not in halt state cpu_clk_unhalted.thread_p_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003 00 Core cycles when at least one thread on the physical core is not in halt state cycle_activity.cycles_l1d_pending pipeline Cycles with pending L1 cache miss loads event=0xa3,cmask=8,period=2000003,umask=0x8 00 Cycles with pending L1 cache miss loads. Set AnyThread to count per core cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss load* is outstanding event=0xa3,cmask=1,period=2000003,umask=0x1 00 cycle_activity.cycles_l2_pending pipeline Cycles with pending L2 cache miss loads event=0xa3,cmask=1,period=2000003,umask=0x1 00 Cycles with pending L2 miss loads. Set AnyThread to count per core cycle_activity.cycles_ldm_pending pipeline Cycles with pending memory loads event=0xa3,cmask=2,period=2000003,umask=0x2 00 Cycles with pending memory loads. Set AnyThread to count per core cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=0x4 00 Total execution stalls cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss load* is outstanding event=0xa3,cmask=5,period=2000003,umask=0x5 00 cycle_activity.stalls_l2_pending pipeline Execution stalls due to L2 cache misses event=0xa3,cmask=5,period=2000003,umask=0x5 00 Number of loads missed L2 cycle_activity.stalls_ldm_pending pipeline Execution stalls due to memory subsystem event=0xa3,cmask=6,period=2000003,umask=0x6 00 ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=0x1 00 inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event event=0xc0,period=2000003 00 Number of instructions at retirement inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) event=0xc0,period=2000003,umask=0x1 00 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) int_misc.recovery_cycles pipeline Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0xd,cmask=1,period=2000003,umask=0x3 00 int_misc.recovery_stalls_count pipeline Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0xd,cmask=1,edge=1,period=2000003,umask=0x3 00 ld_blocks.no_sr pipeline This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=0x3,period=100003,umask=0x8 00 The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=0x3,period=100003,umask=0x2 00 Loads blocked by overlapping with store buffer that cannot be forwarded ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=0x7,period=100003,umask=0x1 00 False dependencies in MOB due to partial compare on address lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=4,period=2000003,umask=0x1 00 Cycles 4 Uops delivered by the LSD, but didn't come from the decoder lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=0x1 00 Cycles Uops delivered by the LSD, but didn't come from the decoder machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20 00 Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0 machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=0x4 00 Number of self-modifying-code machine clears detected other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x80 00 resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=0x1 00 Cycles Allocation is stalled due to Resource Related reason resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=0x8 00 Cycles stalled due to no store buffers available (not including draining form sync) rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=0x1 00 Cycles the RS is empty for the thread uops_dispatched_port.port_0 pipeline Cycles per thread when uops are dispatched to port 0 event=0xa1,period=2000003,umask=0x1 00 Cycles which a Uop is dispatched on port 0 uops_dispatched_port.port_0_core pipeline Cycles per core when uops are dispatched to port 0 event=0xa1,any=1,period=2000003,umask=0x1 00 Cycles per core when uops are dispatched to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are dispatched to port 1 event=0xa1,period=2000003,umask=0x2 00 Cycles which a Uop is dispatched on port 1 uops_dispatched_port.port_1_core pipeline Cycles per core when uops are dispatched to port 1 event=0xa1,any=1,period=2000003,umask=0x2 00 Cycles per core when uops are dispatched to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when load or STA uops are dispatched to port 2 event=0xa1,period=2000003,umask=0xc 00 Cycles which a Uop is dispatched on port 2 uops_dispatched_port.port_2_core pipeline Uops dispatched to port 2, loads and stores per core (speculative and retired) event=0xa1,any=1,period=2000003,umask=0xc 00 uops_dispatched_port.port_3 pipeline Cycles per thread when load or STA uops are dispatched to port 3 event=0xa1,period=2000003,umask=0x30 00 Cycles which a Uop is dispatched on port 3 uops_dispatched_port.port_3_core pipeline Cycles per core when load or STA uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=0x30 00 Cycles per core when load or STA uops are dispatched to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are dispatched to port 4 event=0xa1,period=2000003,umask=0x40 00 Cycles which a Uop is dispatched on port 4 uops_dispatched_port.port_4_core pipeline Cycles per core when uops are dispatched to port 4 event=0xa1,any=1,period=2000003,umask=0x40 00 Cycles per core when uops are dispatched to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are dispatched to port 5 event=0xa1,period=2000003,umask=0x80 00 Cycles which a Uop is dispatched on port 5 uops_dispatched_port.port_5_core pipeline Cycles per core when uops are dispatched to port 5 event=0xa1,any=1,period=2000003,umask=0x80 00 Cycles per core when uops are dispatched to port 5 uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=0x2 00 Counts total number of uops to be executed per-core each cycle uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=0x2 00 Cycles at least 1 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=0x2 00 Cycles at least 2 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=0x2 00 Cycles at least 3 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=0x2 00 Cycles at least 4 micro-op is executed from any thread on physical core uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,inv=1,period=2000003,umask=0x2 00 Cycles with no micro-ops executed from any thread on physical core uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=0x1 00 uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=0x1 00 Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=0x1 00 Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core uops_issued.core_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads event=0xe,any=1,cmask=1,inv=1,period=2000003,umask=0x1 00 Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads uops_issued.flags_merge pipeline Number of flags-merge uops being allocated event=0xe,period=2000003,umask=0x10 00 Number of flags-merge uops allocated. Such uops adds delay uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20 00 Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=0x1 00 Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread uops_retired.all pipeline Retired uops (Precise event) event=0xc2,period=2000003,umask=0x1 00 uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=0x2 00 uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=10,inv=1,period=2000003,umask=0x1 00 unc_arb_coh_trk_occupancy.all uncore interconnect Cycles weighted by number of requests pending in Coherency Tracker event=0x83,umask=0x1 01 unc_arb_trk_occupancy.all uncore interconnect Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC event=0x80,umask=0x1 01 unc_arb_trk_occupancy.cycles_over_half_full uncore interconnect Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC event=0x80,cmask=10,umask=0x1 01 unc_arb_trk_requests.evictions uncore interconnect Counts the number of LLC evictions allocated event=0x81,umask=0x80 01 unc_arb_trk_requests.writes uncore interconnect Counts the number of allocated write entries, include full, partial, and LLC evictions event=0x81,umask=0x20 01 unc_clock.socket uncore interconnect This 48-bit fixed counter counts the UCLK cycles event=0xff 01 dtlb_load_misses.large_page_walk_completed virtual memory Page walk for a large page completed for Demand load event=0x8,period=100003,umask=0x88 00 dtlb_load_misses.miss_causes_a_walk virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size event=0x8,period=100003,umask=0x81 00 Misses in all TLB levels that cause a page walk of any page size from demand loads dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=0x5f,period=100003,umask=0x4 00 Counts load operations that missed 1st level DTLB but hit the 2nd level dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=0x8,period=100003,umask=0x82 00 Misses in all TLB levels that caused page walk completed of any size by demand loads dtlb_load_misses.walk_duration virtual memory Demand load cycles page miss handler (PMH) is busy with this walk event=0x8,period=2000003,umask=0x84 00 Cycle PMH is busy with a walk due to demand loads dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x10 00 Store operations that miss the first TLB level but hit the second and do not cause page walks dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=0x2 00 Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G) dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=2000003,umask=0x4 00 Cycles PMH is busy with this walk ept.walk_cycles virtual memory Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches event=0x4f,period=2000003,umask=0x10 00 itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=0x1 00 Counts the number of ITLB flushes, includes 4k/2M/4M pages itlb_misses.large_page_walk_completed virtual memory Completed page walks in ITLB due to STLB load misses for large pages event=0x85,period=100003,umask=0x80 00 Completed page walks in ITLB due to STLB load misses for large pages itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=0x1 00 Misses in all ITLB levels that cause page walks itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x10 00 Number of cache load STLB hits. No page walk itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=0x2 00 Misses in all ITLB levels that cause completed page walks itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=2000003,umask=0x4 00 Cycle PMH is busy with a walk tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=0x1 00 DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 Count number of STLB flush attempts mem_load_uops_llc_miss_retired.local_dram cache Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) event=0xd3,period=100007,umask=0x3 00 mem_load_uops_llc_miss_retired.remote_dram cache Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) event=0xd3,period=100007,umask=0xc 00 mem_load_uops_llc_miss_retired.remote_fwd cache Data forwarded from remote cache event=0xd3,period=100007,umask=0x20 00 mem_load_uops_llc_miss_retired.remote_hitm cache Remote cache HITM event=0xd3,period=100007,umask=0x10 00 offcore_response.all_data_rd.llc_hit.snoop_miss cache Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0091 00 offcore_response.all_pf_data_rd.llc_hit.any_response cache Counts all prefetch data reads that hit the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0090 00 offcore_response.all_pf_data_rd.llc_hit.hitm_other_core cache Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0090 00 offcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0090 00 offcore_response.all_pf_data_rd.llc_hit.no_snoop_needed cache Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0090 00 offcore_response.all_pf_data_rd.llc_hit.snoop_miss cache Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0090 00 offcore_response.all_reads.llc_hit.any_response cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c03f7 00 offcore_response.all_reads.llc_hit.hitm_other_core cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c03f7 00 offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c03f7 00 offcore_response.all_reads.llc_hit.no_snoop_needed cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c03f7 00 offcore_response.all_reads.llc_hit.snoop_miss cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c03f7 00 offcore_response.demand_data_rd.llc_hit.snoop_miss cache Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0001 00 offcore_response.other.lru_hints cache Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803c8000 00 offcore_response.other.portio_mmio_uc cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23ffc08000 00 offcore_response.pf_l2_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to L2) code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0040 00 offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to L2) data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0010 00 offcore_response.pf_l2_data_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0010 00 offcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0010 00 offcore_response.pf_l2_data_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0010 00 offcore_response.pf_l2_data_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0010 00 offcore_response.pf_llc_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0200 00 offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0080 00 offcore_response.pf_llc_data_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0080 00 offcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0080 00 offcore_response.pf_llc_data_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0080 00 offcore_response.pf_llc_data_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0080 00 offcore_response.all_code_rd.llc_miss.any_response memory Counts all demand & prefetch code reads that miss the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc00244 00 offcore_response.all_code_rd.llc_miss.remote_dram memory Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800244 00 offcore_response.all_code_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f800244 00 offcore_response.all_data_rd.llc_miss.any_response memory Counts all demand & prefetch data reads that hits the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20091 00 offcore_response.all_reads.llc_miss.any_response memory Counts all data/code/rfo reads (demand & prefetch) that hit the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc203f7 00 offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004003f7 00 offcore_response.all_reads.llc_miss.remote_hitm memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc003f7 00 offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f8203f7 00 offcore_response.demand_code_rd.llc_miss.any_response memory Counts all demand code reads that miss the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20004 00 offcore_response.demand_code_rd.llc_miss.local_dram memory Counts all demand code reads that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400004 00 offcore_response.demand_code_rd.llc_miss.remote_dram memory Counts all demand code reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800004 00 offcore_response.demand_code_rd.llc_miss.remote_hitm memory Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00004 00 offcore_response.demand_code_rd.llc_miss.remote_hit_forward memory Counts all demand code reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820004 00 offcore_response.demand_data_rd.llc_miss.any_dram memory Counts demand data reads that miss the LLC and the data returned from remote & local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67fc00001 00 offcore_response.demand_data_rd.llc_miss.any_response memory Counts demand data reads that miss in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20001 00 offcore_response.demand_data_rd.llc_miss.local_dram memory Counts demand data reads that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400001 00 offcore_response.demand_data_rd.llc_miss.remote_dram memory Counts demand data reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800001 00 offcore_response.demand_data_rd.llc_miss.remote_hitm memory Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00001 00 offcore_response.demand_data_rd.llc_miss.remote_hit_forward memory Counts demand data reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820001 00 offcore_response.demand_rfo.llc_miss.remote_hitm memory Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc20002 00 offcore_response.pf_l2_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20040 00 offcore_response.pf_l2_data_rd.llc_miss.any_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67fc00010 00 offcore_response.pf_l2_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to L2) data reads that miss in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20010 00 offcore_response.pf_l2_data_rd.llc_miss.local_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400010 00 offcore_response.pf_l2_data_rd.llc_miss.remote_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800010 00 offcore_response.pf_l2_data_rd.llc_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00010 00 offcore_response.pf_l2_data_rd.llc_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820010 00 offcore_response.pf_llc_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20200 00 offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) data reads that miss in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20080 00 unc_c_llc_lookup.any uncore cache Cache Lookups; Any Request event=0x34,umask=0x11 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=0x3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions unc_c_llc_lookup.nid uncore cache Cache Lookups; Lookups that Match NID event=0x34,umask=0x41 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=0x9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=0x5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC unc_c_llc_victims.miss uncore cache Lines Victimized event=0x37,umask=0x8 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_llc_victims.s_state uncore cache Lines Victimized; Lines in S State event=0x37,umask=0x4 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_ring_ad_used.ccw uncore cache AD Ring In Use; Counterclockwise event=0x1b,umask=0xc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.cw uncore cache AD Ring In Use; Clockwise event=0x1b,umask=0x3 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_vr0_even uncore cache AD Ring In Use; Down and Even on Vring 0 event=0x1b,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_ad_used.down_vr0_odd uncore cache AD Ring In Use; Down and Odd on Vring 0 event=0x1b,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_ad_used.down_vr1_even uncore cache AD Ring In Use; Down and Even on VRing 1 event=0x1b,umask=0x40 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_ad_used.down_vr1_odd uncore cache AD Ring In Use; Down and Odd on VRing 1 event=0x1b,umask=0x80 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_vr0_even uncore cache AD Ring In Use; Up and Even on Vring 0 event=0x1b,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_ad_used.up_vr0_odd uncore cache AD Ring In Use; Up and Odd on Vring 0 event=0x1b,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_ad_used.up_vr1_even uncore cache AD Ring In Use; Up and Even on VRing 1 event=0x1b,umask=0x10 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_ad_used.up_vr1_odd uncore cache AD Ring In Use; Up and Odd on VRing 1 event=0x1b,umask=0x20 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_ak_used.ccw uncore cache AK Ring In Use; Counterclockwise event=0x1c,umask=0xc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.cw uncore cache AK Ring In Use; Clockwise event=0x1c,umask=0x3 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down uncore cache AK Ring In Use; Down event=0x1c,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_vr0_even uncore cache AK Ring In Use; Down and Even on Vring 0 event=0x1c,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_ak_used.down_vr0_odd uncore cache AK Ring In Use; Down and Odd on Vring 0 event=0x1c,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_ak_used.down_vr1_even uncore cache AK Ring In Use; Down and Even on VRing 1 event=0x1c,umask=0x40 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_ak_used.down_vr1_odd uncore cache AK Ring In Use; Down and Odd on VRing 1 event=0x1c,umask=0x80 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_ak_used.up uncore cache AK Ring In Use; Up event=0x1c,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_vr0_even uncore cache AK Ring In Use; Up and Even on Vring 0 event=0x1c,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_ak_used.up_vr0_odd uncore cache AK Ring In Use; Up and Odd on Vring 0 event=0x1c,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_ak_used.up_vr1_even uncore cache AK Ring In Use; Up and Even on VRing 1 event=0x1c,umask=0x10 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_ak_used.up_vr1_odd uncore cache AK Ring In Use; Up and Odd on VRing 1 event=0x1c,umask=0x20 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_bl_used.ccw uncore cache BL Ring in Use; Counterclockwise event=0x1d,umask=0xc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.cw uncore cache BL Ring in Use; Clockwise event=0x1d,umask=0x3 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down uncore cache BL Ring in Use; Down event=0x1d,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_vr0_even uncore cache BL Ring in Use; Down and Even on Vring 0 event=0x1d,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_bl_used.down_vr0_odd uncore cache BL Ring in Use; Down and Odd on Vring 0 event=0x1d,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_bl_used.down_vr1_even uncore cache BL Ring in Use; Down and Even on VRing 1 event=0x1d,umask=0x40 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_bl_used.down_vr1_odd uncore cache BL Ring in Use; Down and Odd on VRing 1 event=0x1d,umask=0x80 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_bl_used.up uncore cache BL Ring in Use; Up event=0x1d,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_vr0_even uncore cache BL Ring in Use; Up and Even on Vring 0 event=0x1d,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_bl_used.up_vr0_odd uncore cache BL Ring in Use; Up and Odd on Vring 0 event=0x1d,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_bl_used.up_vr1_even uncore cache BL Ring in Use; Up and Even on VRing 1 event=0x1d,umask=0x10 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_bl_used.up_vr1_odd uncore cache BL Ring in Use; Up and Odd on VRing 1 event=0x1d,umask=0x20 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_bounces.ad_irq uncore cache Number of LLC responses that bounced on the Ring event=0x5,umask=0x2 01 unc_c_ring_bounces.ak uncore cache Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=0x5,umask=0x4 01 unc_c_ring_bounces.ak_core uncore cache Number of LLC responses that bounced on the Ring.: Acknowledgements to core event=0x5,umask=0x2 01 unc_c_ring_bounces.bl uncore cache Number of LLC responses that bounced on the Ring.; Data Responses to core event=0x5,umask=0x8 01 unc_c_ring_bounces.bl_core uncore cache Number of LLC responses that bounced on the Ring.: Data Responses to core event=0x5,umask=0x4 01 unc_c_ring_bounces.iv_core uncore cache Number of LLC responses that bounced on the Ring.: Snoops of processor's cache event=0x5,umask=0x8 01 unc_c_ring_iv_used.any uncore cache IV Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity unc_c_ring_iv_used.down uncore cache IV Ring in Use; Down event=0x1e,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache IV Ring in Use; Up event=0x1e,umask=0x33 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Up polarity unc_c_ring_sink_starved.ad_ipq uncore cache event=0x6,umask=0x2 01 unc_c_ring_sink_starved.ad_irq uncore cache event=0x6,umask=0x1 01 unc_c_ring_sink_starved.iv uncore cache event=0x6,umask=0x10 01 unc_c_ring_src_thrtl uncore cache event=0x7 01 unc_c_rxr_ext_starved.prq uncore cache Ingress Arbiter Blocking Cycles event=0x12,umask=0x4 01 IRQ is blocking the ingress queue and causing the starvation unc_c_rxr_inserts.irq_rejected uncore cache Ingress Allocations: IRQ Rejected event=0x13,umask=0x2 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.vfifo uncore cache Ingress Allocations; VFIFO event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue.; Counts the number of allocations into the IRQ Ordering FIFO. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Occupancy Accumulator event, can be used to calculate average lifetime in the FIFO. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ unc_c_rxr_ismq_retry.wb_credits uncore cache ISMQ Retries; No WB Credits event=0x33,umask=0x80 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Retries of writes to local memory due to lack of HT WB credits unc_c_rxr_occupancy.irq_rejected uncore cache IRQ Rejected event=0x11,umask=0x2 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.vfifo uncore cache Ingress Occupancy; VFIFO event=0x11,umask=0x10 01 Counts number of entries in the specified Ingress queue in each cycle.; Accumulates the number of used entries in the IRQ Ordering FIFO in each cycle. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Allocations event, can be used to calculate average lifetime in the FIFO. This event can be used in conjunction with the Not Empty event to calculate average queue occupancy. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ unc_h_bt_bypass uncore cache BT Bypass event=0x52 01 Number of transactions that bypass the BT (fifo) to HT unc_h_bt_cycles_ne.local uncore cache BT Cycles Not Empty: Local event=0x42,umask=0x1 01 Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_cycles_ne.remote uncore cache BT Cycles Not Empty: Remote event=0x42,umask=0x2 01 Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_occupancy.local uncore cache BT Occupancy; Local event=0x43,umask=0x1 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.reads_local uncore cache BT Occupancy; Reads Local event=0x43,umask=0x4 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.reads_remote uncore cache BT Occupancy; Reads Remote event=0x43,umask=0x8 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.remote uncore cache BT Occupancy; Remote event=0x43,umask=0x2 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.writes_local uncore cache BT Occupancy; Writes Local event=0x43,umask=0x10 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.writes_remote uncore cache BT Occupancy; Writes Remote event=0x43,umask=0x20 01 Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_conflict_cycles.ackcnflts uncore cache Conflict Checks; Acknowledge Conflicts event=0xb,umask=0x8 01 Count the number of Ackcnflts unc_h_conflict_cycles.cmp_fwds uncore cache Conflict Checks; Cmp Fwds event=0xb,umask=0x10 01 Count the number of Cmp_Fwd. This will give the number of late conflicts unc_h_conflict_cycles.conflict uncore cache Conflict Checks; Conflict Detected event=0xb,umask=0x2 01 Counts the number of cycles that we are handling conflicts unc_h_conflict_cycles.last uncore cache Conflict Checks; Last in conflict chain event=0xb,umask=0x4 01 Count every last conflictor in conflict chain. Can be used to compute the average conflict chain length as (#Ackcnflts/#LastConflictor)+1. This can be used to give a feel for the conflict chain lengths while analyzing lock kernels unc_h_directory_lookup.any uncore cache Directory Lookups: Any state event=0xc,umask=0x10 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snoop_a uncore cache Directory Lookups: Snoop A event=0xc,umask=0x8 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snoop_s uncore cache Directory Lookups: Snoop S event=0xc,umask=0x2 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_a uncore cache Directory Lookups: A State event=0xc,umask=0x80 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_i uncore cache Directory Lookups: I State event=0xc,umask=0x20 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_s uncore cache Directory Lookups: S State event=0xc,umask=0x40 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_update.a2i uncore cache Directory Updates: A2I event=0xd,umask=0x20 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.a2s uncore cache Directory Updates: A2S event=0xd,umask=0x40 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.i2a uncore cache Directory Updates: I2A event=0xd,umask=0x4 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.i2s uncore cache Directory Updates: I2S event=0xd,umask=0x2 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.s2a uncore cache Directory Updates: S2A event=0xd,umask=0x10 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.s2i uncore cache Directory Updates: S2I event=0xd,umask=0x8 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_igr_ad_qpi2_accumulator uncore cache AD QPI Link 2 Credit Accumulator event=0x59 01 Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer unc_h_igr_bl_qpi2_accumulator uncore cache BL QPI Link 2 Credit Accumulator event=0x5a 01 Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer unc_h_igr_credits_ad_qpi2 uncore cache AD QPI Link 2 Credit Accumulator event=0x59 01 Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer unc_h_igr_credits_bl_qpi2 uncore cache BL QPI Link 2 Credit Accumulator event=0x5a 01 Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer unc_h_iodc_conflicts.any uncore cache IODC Conflicts; Any Conflict event=0x57,umask=0x1 01 unc_h_iodc_conflicts.last uncore cache IODC Conflicts; Last Conflict event=0x57,umask=0x4 01 unc_h_iodc_conflicts.remote_invi2e_same_rtid uncore cache IODC Conflicts: Remote InvItoE - Same RTID event=0x57,umask=0x1 01 unc_h_iodc_conflicts.remote_other_same_addr uncore cache IODC Conflicts: Remote (Other) - Same Addr event=0x57,umask=0x4 01 unc_h_iodc_inserts uncore cache IODC Inserts event=0x56 01 IODC Allocations unc_h_iodc_olen_wbmtoi uncore cache Num IODC 0 Length Writes event=0x58 01 Num IODC 0 Length Writebacks M to I - All of which are dropped unc_h_ring_ad_used.ccw uncore cache HA AD Ring in Use; Counterclockwise event=0x3e,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_vr0_even uncore cache HA AD Ring in Use; Counterclockwise and Even on VRing 0 event=0x3e,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ad_used.ccw_vr0_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd on VRing 0 event=0x3e,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ad_used.ccw_vr1_even uncore cache HA AD Ring in Use; Counterclockwise and Even on VRing 1 event=0x3e,umask=0x40 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ad_used.ccw_vr1_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd on VRing 1 event=0x3e,umask=0x80 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ad_used.cw uncore cache HA AD Ring in Use; Clockwise event=0x3e,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_vr0_even uncore cache HA AD Ring in Use; Clockwise and Even on VRing 0 event=0x3e,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ad_used.cw_vr0_odd uncore cache HA AD Ring in Use; Clockwise and Odd on VRing 0 event=0x3e,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ad_used.cw_vr1_even uncore cache HA AD Ring in Use; Clockwise and Even on VRing 1 event=0x3e,umask=0x10 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ad_used.cw_vr1_odd uncore cache HA AD Ring in Use; Clockwise and Odd on VRing 1 event=0x3e,umask=0x20 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ak_used.ccw uncore cache HA AK Ring in Use; Counterclockwise event=0x3f,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_vr0_even uncore cache HA AK Ring in Use; Counterclockwise and Even on VRing 0 event=0x3f,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ak_used.ccw_vr0_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd on VRing 0 event=0x3f,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ak_used.ccw_vr1_even uncore cache HA AK Ring in Use; Counterclockwise and Even on VRing 1 event=0x3f,umask=0x40 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ak_used.ccw_vr1_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd on VRing 1 event=0x3f,umask=0x80 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ak_used.cw uncore cache HA AK Ring in Use; Clockwise event=0x3f,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_vr0_even uncore cache HA AK Ring in Use; Clockwise and Even on VRing 0 event=0x3f,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ak_used.cw_vr0_odd uncore cache HA AK Ring in Use; Clockwise and Odd on VRing 0 event=0x3f,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ak_used.cw_vr1_even uncore cache HA AK Ring in Use; Clockwise and Even on VRing 1 event=0x3f,umask=0x10 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ak_used.cw_vr1_odd uncore cache HA AK Ring in Use; Clockwise and Odd on VRing 1 event=0x3f,umask=0x20 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_bl_used.ccw uncore cache HA BL Ring in Use; Counterclockwise event=0x40,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_vr0_even uncore cache HA BL Ring in Use; Counterclockwise and Even on VRing 0 event=0x40,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_bl_used.ccw_vr0_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd on VRing 0 event=0x40,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_bl_used.ccw_vr1_even uncore cache HA BL Ring in Use; Counterclockwise and Even on VRing 1 event=0x40,umask=0x40 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_bl_used.ccw_vr1_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd on VRing 1 event=0x40,umask=0x80 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_bl_used.cw uncore cache HA BL Ring in Use; Clockwise event=0x40,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_vr0_even uncore cache HA BL Ring in Use; Clockwise and Even on VRing 0 event=0x40,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_bl_used.cw_vr0_odd uncore cache HA BL Ring in Use; Clockwise and Odd on VRing 0 event=0x40,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_bl_used.cw_vr1_even uncore cache HA BL Ring in Use; Clockwise and Even on VRing 1 event=0x40,umask=0x10 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_bl_used.cw_vr1_odd uncore cache HA BL Ring in Use; Clockwise and Odd on VRing 1 event=0x40,umask=0x20 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_snoop_resp.rspsfwd uncore cache Snoop Responses Received; RspSFwd event=0x21,umask=0x8 01 Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state unc_h_tracker_cycles_ne uncore cache Tracker Cycles Not Empty event=0x3 01 Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_txr_ad_occupancy.sched0 uncore cache AD Egress Occupancy; Scheduler 0 event=0x28,umask=0x1 01 AD Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_ad_occupancy.sched1 uncore cache AD Egress Occupancy; Scheduler 1 event=0x28,umask=0x2 01 AD Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_h_txr_ak.crd_cbo uncore cache Outbound Ring Transactions on AK: CRD Transactions to Cbo event=0xe,umask=0x2 01 unc_h_txr_ak_occupancy.sched0 uncore cache AK Egress Occupancy; Scheduler 0 event=0x30,umask=0x1 01 AK Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_ak_occupancy.sched1 uncore cache AK Egress Occupancy; Scheduler 1 event=0x30,umask=0x2 01 AK Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_h_txr_bl_occupancy.all uncore cache BL Egress Occupancy: All event=0x34,umask=0x3 01 unc_h_txr_bl_occupancy.sched0 uncore cache BL Egress Occupancy; Scheduler 0 event=0x34,umask=0x1 01 BL Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_bl_occupancy.sched1 uncore cache BL Egress Occupancy; Scheduler 1 event=0x34,umask=0x2 01 BL Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_i_address_match.merge_count uncore interconnect Address Match (Conflict) Count; Conflict Merges event=0x17,umask=0x2 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together unc_i_address_match.stall_count uncore interconnect Address Match (Conflict) Count; Conflict Stalls event=0x17,umask=0x1 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs. This is bad for performance unc_i_cache_ack_pending_occupancy.any uncore interconnect Write Ack Pending Occupancy; Any Source event=0x14,umask=0x1 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_cache_ack_pending_occupancy.source uncore interconnect Write Ack Pending Occupancy; Select Source event=0x14,umask=0x2 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port unc_i_cache_own_occupancy.any uncore interconnect Outstanding Write Ownership Occupancy; Any Source event=0x13,umask=0x1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port unc_i_cache_own_occupancy.source uncore interconnect Outstanding Write Ownership Occupancy; Select Source event=0x13,umask=0x2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_cache_read_occupancy.any uncore interconnect Outstanding Read Occupancy; Any Source event=0x10,umask=0x1 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port unc_i_cache_read_occupancy.source uncore interconnect Outstanding Read Occupancy; Select Source event=0x10,umask=0x2 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_cache_write_occupancy.any uncore interconnect Outstanding Write Occupancy; Any Source event=0x11,umask=0x1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port unc_i_cache_write_occupancy.source uncore interconnect Outstanding Write Occupancy; Select Source event=0x11,umask=0x2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time unc_i_rxr_ak_cycles_full uncore interconnect event=0xb 01 Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_ak_occupancy uncore interconnect event=0xc 01 Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_bl_drs_cycles_full uncore interconnect event=0x4 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_occupancy uncore interconnect event=0x7 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_cycles_full uncore interconnect event=0x5 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_occupancy uncore interconnect event=0x8 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_cycles_full uncore interconnect event=0x6 01 Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_occupancy uncore interconnect event=0x9 01 Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes unc_i_tickles.lost_ownership uncore interconnect Tickle Count; Ownership Lost event=0x16,umask=0x1 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle. When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue. This will therefore track the number of requests that lost ownership and not just the number of tickles unc_i_tickles.top_of_queue uncore interconnect Tickle Count; Data Returned event=0x16,umask=0x2 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch. In this case, data is returned rather than releasing ownership unc_i_transactions.pd_prefetches uncore interconnect Inbound Transaction Count: Read Prefetches event=0x15,umask=0x4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.rd_prefetches uncore interconnect Inbound Transaction Count; Read Prefetches event=0x15,umask=0x4 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x15,umask=0x1 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x15,umask=0x2 01 Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_write_ordering_stall_cycles uncore interconnect Write Ordering Stalls event=0x1a 01 Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/8th the GT/s speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed unc_q_match_mask uncore interconnect event=0x38 01 unc_q_message.drs.anydatac uncore interconnect event=0x38 01 unc_q_message.drs.anyresp uncore interconnect event=0x38 01 unc_q_message.drs.anyresp11flits uncore interconnect event=0x38 01 unc_q_message.drs.anyresp9flits uncore interconnect event=0x38 01 unc_q_message.drs.datac_e uncore interconnect event=0x38 01 unc_q_message.drs.datac_e_cmp uncore interconnect event=0x38 01 unc_q_message.drs.datac_e_frcackcnflt uncore interconnect event=0x38 01 unc_q_message.drs.datac_f uncore interconnect event=0x38 01 unc_q_message.drs.datac_f_cmp uncore interconnect event=0x38 01 unc_q_message.drs.datac_f_frcackcnflt uncore interconnect event=0x38 01 unc_q_message.drs.datac_m uncore interconnect event=0x38 01 unc_q_message.drs.wbedata uncore interconnect event=0x38 01 unc_q_message.drs.wbidata uncore interconnect event=0x38 01 unc_q_message.drs.wbsdata uncore interconnect event=0x38 01 unc_q_message.hom.anyreq uncore interconnect event=0x38 01 unc_q_message.hom.anyresp uncore interconnect event=0x38 01 unc_q_message.hom.respfwd uncore interconnect event=0x38 01 unc_q_message.hom.respfwdi uncore interconnect event=0x38 01 unc_q_message.hom.respfwdiwb uncore interconnect event=0x38 01 unc_q_message.hom.respfwds uncore interconnect event=0x38 01 unc_q_message.hom.respfwdswb uncore interconnect event=0x38 01 unc_q_message.hom.respiwb uncore interconnect event=0x38 01 unc_q_message.hom.respswb uncore interconnect event=0x38 01 unc_q_message.ncb.anyint uncore interconnect event=0x38 01 unc_q_message.ncb.anymsg uncore interconnect event=0x38 01 unc_q_message.ncb.anymsg11flits uncore interconnect event=0x38 01 unc_q_message.ncb.anymsg9flits uncore interconnect event=0x38 01 unc_q_message.ncs.anymsg1or2flits uncore interconnect event=0x38 01 unc_q_message.ncs.anymsg3flits uncore interconnect event=0x38 01 unc_q_message.ncs.ncrd uncore interconnect event=0x38 01 unc_q_message.ndr.anycmp uncore interconnect event=0x38 01 unc_q_message.snp.anysnp uncore interconnect event=0x38 01 unc_q_rxl_flits_g0.data uncore interconnect Flits Received - Group 0; Data Tx Flits event=0x1,umask=0x2 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits received over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets unc_q_rxl_flits_g0.non_data uncore interconnect Flits Received - Group 0; Non-Data protocol Tx Flits event=0x1,umask=0x4 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits received across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets unc_q_rxl_inserts_drs uncore interconnect Rx Flit Buffer Allocations - DRS event=0x9 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits unc_q_rxl_inserts_hom uncore interconnect Rx Flit Buffer Allocations - HOM event=0xc 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits unc_q_rxl_inserts_ncb uncore interconnect Rx Flit Buffer Allocations - NCB event=0xa 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits unc_q_rxl_inserts_ncs uncore interconnect Rx Flit Buffer Allocations - NCS event=0xb 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits unc_q_rxl_inserts_ndr uncore interconnect Rx Flit Buffer Allocations - NDR event=0xe 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits unc_q_rxl_inserts_snp uncore interconnect Rx Flit Buffer Allocations - SNP event=0xd 01 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits unc_q_rxl_occupancy_drs uncore interconnect RxQ Occupancy - DRS event=0x15 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only unc_q_rxl_occupancy_hom uncore interconnect RxQ Occupancy - HOM event=0x18 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only unc_q_rxl_occupancy_ncb uncore interconnect RxQ Occupancy - NCB event=0x16 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only unc_q_rxl_occupancy_ncs uncore interconnect RxQ Occupancy - NCS event=0x17 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only unc_q_rxl_occupancy_ndr uncore interconnect RxQ Occupancy - NDR event=0x1a 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only unc_q_rxl_occupancy_snp uncore interconnect RxQ Occupancy - SNP event=0x19 01 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only unc_q_txr_ak_ndr_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN0 event=0x29,umask=0x1 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN1 event=0x29,umask=0x2 01 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN0 event=0x25,umask=0x1 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN1 event=0x25,umask=0x2 01 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress unc_r3_c_hi_ad_credits_empty.cbo10 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x4 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10 unc_r3_c_hi_ad_credits_empty.cbo11 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x8 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11 unc_r3_c_hi_ad_credits_empty.cbo12 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12 unc_r3_c_hi_ad_credits_empty.cbo13 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13 unc_r3_c_hi_ad_credits_empty.cbo14 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16 unc_r3_c_hi_ad_credits_empty.cbo8 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x1 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8 unc_r3_c_hi_ad_credits_empty.cbo9 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x2 01 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9 unc_r3_c_lo_ad_credits_empty.cbo0 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x1 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0 unc_r3_c_lo_ad_credits_empty.cbo1 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x2 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1 unc_r3_c_lo_ad_credits_empty.cbo2 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x4 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2 unc_r3_c_lo_ad_credits_empty.cbo3 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x8 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3 unc_r3_c_lo_ad_credits_empty.cbo4 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x10 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4 unc_r3_c_lo_ad_credits_empty.cbo5 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x20 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5 unc_r3_c_lo_ad_credits_empty.cbo6 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x40 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6 unc_r3_c_lo_ad_credits_empty.cbo7 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x80 01 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7 unc_r3_ha_r2_bl_credits_empty.ha0 uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=0x1 01 No credits available to send to either HA or R2 on the BL Ring; HA0 unc_r3_ha_r2_bl_credits_empty.ha1 uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=0x2 01 No credits available to send to either HA or R2 on the BL Ring; HA1 unc_r3_ha_r2_bl_credits_empty.r2_ncb uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=0x4 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages unc_r3_ha_r2_bl_credits_empty.r2_ncs uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=0x8 01 No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages unc_r3_qpi0_ad_credits_empty.vn0_hom uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x2 01 No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages unc_r3_qpi0_ad_credits_empty.vn0_ndr uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x8 01 No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages unc_r3_qpi0_ad_credits_empty.vn0_snp uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x4 01 No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages unc_r3_qpi0_ad_credits_empty.vn1_hom uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x10 01 No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages unc_r3_qpi0_ad_credits_empty.vn1_ndr uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x40 01 No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages unc_r3_qpi0_ad_credits_empty.vn1_snp uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x20 01 No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages unc_r3_qpi0_ad_credits_empty.vna uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x1 01 No credits available to send to QPI0 on the AD Ring; VNA unc_r3_qpi0_bl_credits_empty.vn0_hom uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x2 01 No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages unc_r3_qpi0_bl_credits_empty.vn0_ndr uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x8 01 No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages unc_r3_qpi0_bl_credits_empty.vn0_snp uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x4 01 No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages unc_r3_qpi0_bl_credits_empty.vn1_hom uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x10 01 No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages unc_r3_qpi0_bl_credits_empty.vn1_ndr uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x40 01 No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages unc_r3_qpi0_bl_credits_empty.vn1_snp uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x20 01 No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages unc_r3_qpi0_bl_credits_empty.vna uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x1 01 No credits available to send to QPI0 on the BL Ring; VNA unc_r3_qpi1_ad_credits_empty.vn0_hom uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x2 01 No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages unc_r3_qpi1_ad_credits_empty.vn0_ndr uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x8 01 No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages unc_r3_qpi1_ad_credits_empty.vn0_snp uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x4 01 No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages unc_r3_qpi1_ad_credits_empty.vn1_hom uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x10 01 No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages unc_r3_qpi1_ad_credits_empty.vn1_ndr uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x40 01 No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages unc_r3_qpi1_ad_credits_empty.vn1_snp uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x20 01 No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages unc_r3_qpi1_ad_credits_empty.vna uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x1 01 No credits available to send to QPI1 on the AD Ring; VNA unc_r3_qpi1_bl_credits_empty.vn0_hom uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x2 01 No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages unc_r3_qpi1_bl_credits_empty.vn0_ndr uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x8 01 No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages unc_r3_qpi1_bl_credits_empty.vn0_snp uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x4 01 No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages unc_r3_qpi1_bl_credits_empty.vn1_hom uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x10 01 No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages unc_r3_qpi1_bl_credits_empty.vn1_ndr uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x40 01 No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages unc_r3_qpi1_bl_credits_empty.vn1_snp uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x20 01 No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages unc_r3_qpi1_bl_credits_empty.vna uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x1 01 No credits available to send to QPI1 on the BL Ring; VNA unc_r3_ring_ad_used.ccw uncore interconnect R3 AD Ring in Use; Counterclockwise event=0x7,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_vr0_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even on VRing 0 event=0x7,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.ccw_vr0_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd on VRing 0 event=0x7,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.cw uncore interconnect R3 AD Ring in Use; Clockwise event=0x7,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_vr0_even uncore interconnect R3 AD Ring in Use; Clockwise and Even on VRing 0 event=0x7,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.cw_vr0_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd on VRing 0 event=0x7,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.ccw uncore interconnect R3 AK Ring in Use; Counterclockwise event=0x8,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_vr0_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even on VRing 0 event=0x8,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.ccw_vr0_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd on VRing 0 event=0x8,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.cw uncore interconnect R3 AK Ring in Use; Clockwise event=0x8,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.cw_vr0_even uncore interconnect R3 AK Ring in Use; Clockwise and Even on VRing 0 event=0x8,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.cw_vr0_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd on VRing 0 event=0x8,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.ccw uncore interconnect R3 BL Ring in Use; Counterclockwise event=0x9,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_vr0_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even on VRing 0 event=0x9,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.ccw_vr0_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd on VRing 0 event=0x9,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.cw uncore interconnect R3 BL Ring in Use; Clockwise event=0x9,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_vr0_even uncore interconnect R3 BL Ring in Use; Clockwise and Even on VRing 0 event=0x9,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.cw_vr0_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd on VRing 0 event=0x9,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_iv_used.any uncore interconnect R2 IV Ring in Use; Any event=0xa,umask=0xff 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity unc_r3_ring_iv_used.ccw uncore interconnect R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity unc_r3_ring_iv_used.cw uncore interconnect R2 IV Ring in Use; Clockwise event=0xa,umask=0x33 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity unc_r3_rxr_ad_bypassed uncore interconnect AD Ingress Bypassed event=0x12 01 Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain unc_r3_rxr_bypassed.ad uncore interconnect Ingress Bypassed event=0x12,umask=0x1 01 Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain unc_r3_rxr_occupancy.drs uncore interconnect Ingress Occupancy Accumulator; DRS event=0x13,umask=0x8 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r3_rxr_occupancy.hom uncore interconnect Ingress Occupancy Accumulator; HOM event=0x13,umask=0x1 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue unc_r3_rxr_occupancy.ncb uncore interconnect Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue unc_r3_rxr_occupancy.ncs uncore interconnect Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue unc_r3_rxr_occupancy.ndr uncore interconnect Ingress Occupancy Accumulator; NDR event=0x13,umask=0x4 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue unc_r3_rxr_occupancy.snp uncore interconnect Ingress Occupancy Accumulator; SNP event=0x13,umask=0x2 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue unc_r3_txr_nack_ccw.ad uncore interconnect Egress NACK; AK CCW event=0x28,umask=0x1 01 BL CounterClockwise Egress Queue unc_r3_txr_nack_ccw.ak uncore interconnect Egress NACK; BL CW event=0x28,umask=0x2 01 AD Clockwise Egress Queue unc_r3_txr_nack_ccw.bl uncore interconnect Egress NACK; BL CCW event=0x28,umask=0x4 01 AD CounterClockwise Egress Queue unc_r3_txr_nack_cw.ad uncore interconnect Egress NACK; AD CW event=0x26,umask=0x1 01 AD Clockwise Egress Queue unc_r3_txr_nack_cw.ak uncore interconnect Egress NACK; AD CCW event=0x26,umask=0x2 01 AD CounterClockwise Egress Queue unc_r3_txr_nack_cw.bl uncore interconnect Egress NACK; AK CW event=0x26,umask=0x4 01 BL Clockwise Egress Queue unc_r3_vna_credits_acquired uncore interconnect VNA credit Acquisitions event=0x33 01 Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event unc_r3_vna_credit_cycles_out uncore interconnect Cycles with no VNA credits available event=0x31 01 Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth unc_r3_vna_credit_cycles_used uncore interconnect Cycles with 1 or more VNA credits in use event=0x32 01 Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits unc_u_clockticks uncore interconnect event=0 01 unc_u_event_msg.int_prio uncore interconnect VLW Received event=0x42,umask=0x10 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.ipi_rcvd uncore interconnect VLW Received event=0x42,umask=0x4 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.msi_rcvd uncore interconnect VLW Received event=0x42,umask=0x2 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.vlw_rcvd uncore interconnect VLW Received event=0x42,umask=0x1 01 Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_racu_requests uncore interconnect RACU Request event=0x46 01 unc_r2_iio_credits_reject.drs uncore io R2PCIe IIO Failed to Acquire a Credit; DRS event=0x34,umask=0x8 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_ring_ad_used.ccw uncore io R2 AD Ring in Use; Counterclockwise event=0x7,umask=0xcc 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_vr0_even uncore io R2 AD Ring in Use; Counterclockwise and Even on VRing 0 event=0x7,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.ccw_vr0_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd on VRing 0 event=0x7,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.ccw_vr1_even uncore io R2 AD Ring in Use; Counterclockwise and Even on VRing 1 event=0x7,umask=0x40 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.ccw_vr1_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd on VRing 1 event=0x7,umask=0x80 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.cw uncore io R2 AD Ring in Use; Clockwise event=0x7,umask=0x33 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_vr0_even uncore io R2 AD Ring in Use; Clockwise and Even on VRing 0 event=0x7,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.cw_vr0_odd uncore io R2 AD Ring in Use; Clockwise and Odd on VRing 0 event=0x7,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.cw_vr1_even uncore io R2 AD Ring in Use; Clockwise and Even on VRing 1 event=0x7,umask=0x10 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.cw_vr1_odd uncore io R2 AD Ring in Use; Clockwise and Odd on VRing 1 event=0x7,umask=0x20 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.ccw uncore io R2 AK Ring in Use; Counterclockwise event=0x8,umask=0xcc 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_vr0_even uncore io R2 AK Ring in Use; Counterclockwise and Even on VRing 0 event=0x8,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.ccw_vr0_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd on VRing 0 event=0x8,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.ccw_vr1_even uncore io R2 AK Ring in Use; Counterclockwise and Even on VRing 1 event=0x8,umask=0x40 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.ccw_vr1_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd on VRing 1 event=0x8,umask=0x80 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.cw uncore io R2 AK Ring in Use; Clockwise event=0x8,umask=0x33 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_vr0_even uncore io R2 AK Ring in Use; Clockwise and Even on VRing 0 event=0x8,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.cw_vr0_odd uncore io R2 AK Ring in Use; Clockwise and Odd on VRing 0 event=0x8,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.cw_vr1_even uncore io R2 AK Ring in Use; Clockwise and Even on VRing 1 event=0x8,umask=0x10 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.cw_vr1_odd uncore io R2 AK Ring in Use; Clockwise and Odd on VRing 1 event=0x8,umask=0x20 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.ccw uncore io R2 BL Ring in Use; Counterclockwise event=0x9,umask=0xcc 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_vr0_even uncore io R2 BL Ring in Use; Counterclockwise and Even on VRing 0 event=0x9,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.ccw_vr0_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd on VRing 0 event=0x9,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.ccw_vr1_even uncore io R2 BL Ring in Use; Counterclockwise and Even on VRing 1 event=0x9,umask=0x40 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.ccw_vr1_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd on VRing 1 event=0x9,umask=0x80 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.cw uncore io R2 BL Ring in Use; Clockwise event=0x9,umask=0x33 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_vr0_even uncore io R2 BL Ring in Use; Clockwise and Even on VRing 0 event=0x9,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.cw_vr0_odd uncore io R2 BL Ring in Use; Clockwise and Odd on VRing 0 event=0x9,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.cw_vr1_even uncore io R2 BL Ring in Use; Clockwise and Even on VRing 1 event=0x9,umask=0x10 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.cw_vr1_odd uncore io R2 BL Ring in Use; Clockwise and Odd on VRing 1 event=0x9,umask=0x20 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xff 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity unc_r2_ring_iv_used.ccw uncore io R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xcc 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity unc_r2_ring_iv_used.cw uncore io R2 IV Ring in Use; Clockwise event=0xa,umask=0x33 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity unc_r2_rxr_ak_bounces uncore io AK Ingress Bounced event=0x12 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_rxr_ak_bounces.ccw uncore io AK Ingress Bounced; Counterclockwise event=0x12,umask=0x2 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_rxr_ak_bounces.cw uncore io AK Ingress Bounced; Clockwise event=0x12,umask=0x1 01 Counts the number of times when a request destined for the AK ingress bounced unc_r2_txr_nack_ccw.ad uncore io Egress CCW NACK; AD CCW event=0x28,umask=0x1 01 AD CounterClockwise Egress Queue unc_r2_txr_nack_ccw.ak uncore io Egress CCW NACK; AK CCW event=0x28,umask=0x2 01 AK CounterClockwise Egress Queue unc_r2_txr_nack_ccw.bl uncore io Egress CCW NACK; BL CCW event=0x28,umask=0x4 01 BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.ad uncore io Egress CW NACK; AD CW event=0x26,umask=0x1 01 AD Clockwise Egress Queue unc_r2_txr_nack_cw.ak uncore io Egress CW NACK; AK CW event=0x26,umask=0x2 01 AK Clockwise Egress Queue unc_r2_txr_nack_cw.bl uncore io Egress CW NACK; BL CW event=0x26,umask=0x4 01 BL Clockwise Egress Queue unc_m_power_pcu_throttling uncore memory event=0x42 01 unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0,umask=0x1 01 unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=0x2 01 unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=0x4 01 unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=0x8 01 unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=0x10 01 unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=0x20 01 unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=0x40 01 unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=0x80 01 unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1,umask=0x1 01 unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=0x2 01 unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=0x4 01 unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=0x8 01 unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=0x10 01 unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=0x20 01 unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=0x40 01 unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=0x80 01 unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2,umask=0x1 01 unc_m_rd_cas_rank2.bank1 uncore memory RD_CAS Access to Rank 2; Bank 1 event=0xb2,umask=0x2 01 unc_m_rd_cas_rank2.bank2 uncore memory RD_CAS Access to Rank 2; Bank 2 event=0xb2,umask=0x4 01 unc_m_rd_cas_rank2.bank3 uncore memory RD_CAS Access to Rank 2; Bank 3 event=0xb2,umask=0x8 01 unc_m_rd_cas_rank2.bank4 uncore memory RD_CAS Access to Rank 2; Bank 4 event=0xb2,umask=0x10 01 unc_m_rd_cas_rank2.bank5 uncore memory RD_CAS Access to Rank 2; Bank 5 event=0xb2,umask=0x20 01 unc_m_rd_cas_rank2.bank6 uncore memory RD_CAS Access to Rank 2; Bank 6 event=0xb2,umask=0x40 01 unc_m_rd_cas_rank2.bank7 uncore memory RD_CAS Access to Rank 2; Bank 7 event=0xb2,umask=0x80 01 unc_m_rd_cas_rank3.bank0 uncore memory RD_CAS Access to Rank 3; Bank 0 event=0xb3,umask=0x1 01 unc_m_rd_cas_rank3.bank1 uncore memory RD_CAS Access to Rank 3; Bank 1 event=0xb3,umask=0x2 01 unc_m_rd_cas_rank3.bank2 uncore memory RD_CAS Access to Rank 3; Bank 2 event=0xb3,umask=0x4 01 unc_m_rd_cas_rank3.bank3 uncore memory RD_CAS Access to Rank 3; Bank 3 event=0xb3,umask=0x8 01 unc_m_rd_cas_rank3.bank4 uncore memory RD_CAS Access to Rank 3; Bank 4 event=0xb3,umask=0x10 01 unc_m_rd_cas_rank3.bank5 uncore memory RD_CAS Access to Rank 3; Bank 5 event=0xb3,umask=0x20 01 unc_m_rd_cas_rank3.bank6 uncore memory RD_CAS Access to Rank 3; Bank 6 event=0xb3,umask=0x40 01 unc_m_rd_cas_rank3.bank7 uncore memory RD_CAS Access to Rank 3; Bank 7 event=0xb3,umask=0x80 01 unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4,umask=0x1 01 unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=0x2 01 unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=0x4 01 unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=0x8 01 unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=0x10 01 unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=0x20 01 unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=0x40 01 unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=0x80 01 unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5,umask=0x1 01 unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=0x2 01 unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=0x4 01 unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=0x8 01 unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=0x10 01 unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=0x20 01 unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=0x40 01 unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=0x80 01 unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6,umask=0x1 01 unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=0x2 01 unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=0x4 01 unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=0x8 01 unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=0x10 01 unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=0x20 01 unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=0x40 01 unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=0x80 01 unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7,umask=0x1 01 unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=0x2 01 unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=0x4 01 unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=0x8 01 unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=0x10 01 unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=0x20 01 unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=0x40 01 unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=0x80 01 unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20 01 Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8,umask=0x1 01 unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=0x2 01 unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=0x4 01 unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=0x8 01 unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=0x10 01 unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=0x20 01 unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=0x40 01 unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=0x80 01 unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9,umask=0x1 01 unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=0x2 01 unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=0x4 01 unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=0x8 01 unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=0x10 01 unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=0x20 01 unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=0x40 01 unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=0x80 01 unc_m_wr_cas_rank2.bank0 uncore memory WR_CAS Access to Rank 2; Bank 0 event=0xba,umask=0x1 01 unc_m_wr_cas_rank2.bank1 uncore memory WR_CAS Access to Rank 2; Bank 1 event=0xba,umask=0x2 01 unc_m_wr_cas_rank2.bank2 uncore memory WR_CAS Access to Rank 2; Bank 2 event=0xba,umask=0x4 01 unc_m_wr_cas_rank2.bank3 uncore memory WR_CAS Access to Rank 2; Bank 3 event=0xba,umask=0x8 01 unc_m_wr_cas_rank2.bank4 uncore memory WR_CAS Access to Rank 2; Bank 4 event=0xba,umask=0x10 01 unc_m_wr_cas_rank2.bank5 uncore memory WR_CAS Access to Rank 2; Bank 5 event=0xba,umask=0x20 01 unc_m_wr_cas_rank2.bank6 uncore memory WR_CAS Access to Rank 2; Bank 6 event=0xba,umask=0x40 01 unc_m_wr_cas_rank2.bank7 uncore memory WR_CAS Access to Rank 2; Bank 7 event=0xba,umask=0x80 01 unc_m_wr_cas_rank3.bank0 uncore memory WR_CAS Access to Rank 3; Bank 0 event=0xbb,umask=0x1 01 unc_m_wr_cas_rank3.bank1 uncore memory WR_CAS Access to Rank 3; Bank 1 event=0xbb,umask=0x2 01 unc_m_wr_cas_rank3.bank2 uncore memory WR_CAS Access to Rank 3; Bank 2 event=0xbb,umask=0x4 01 unc_m_wr_cas_rank3.bank3 uncore memory WR_CAS Access to Rank 3; Bank 3 event=0xbb,umask=0x8 01 unc_m_wr_cas_rank3.bank4 uncore memory WR_CAS Access to Rank 3; Bank 4 event=0xbb,umask=0x10 01 unc_m_wr_cas_rank3.bank5 uncore memory WR_CAS Access to Rank 3; Bank 5 event=0xbb,umask=0x20 01 unc_m_wr_cas_rank3.bank6 uncore memory WR_CAS Access to Rank 3; Bank 6 event=0xbb,umask=0x40 01 unc_m_wr_cas_rank3.bank7 uncore memory WR_CAS Access to Rank 3; Bank 7 event=0xbb,umask=0x80 01 unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc,umask=0x1 01 unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=0x2 01 unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=0x4 01 unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=0x8 01 unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=0x10 01 unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=0x20 01 unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=0x40 01 unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=0x80 01 unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd,umask=0x1 01 unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=0x2 01 unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=0x4 01 unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=0x8 01 unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=0x10 01 unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=0x20 01 unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=0x40 01 unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=0x80 01 unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe,umask=0x1 01 unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=0x2 01 unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=0x4 01 unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=0x8 01 unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=0x10 01 unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=0x20 01 unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=0x40 01 unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=0x80 01 unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf,umask=0x1 01 unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=0x2 01 unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=0x4 01 unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=0x8 01 unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=0x10 01 unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=0x20 01 unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=0x40 01 unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=0x80 01 unc_p_core0_transition_cycles uncore power Core 0 C State Transition Cycles event=0x70 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core10_transition_cycles uncore power Core 10 C State Transition Cycles event=0x7a 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core11_transition_cycles uncore power Core 11 C State Transition Cycles event=0x7b 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core12_transition_cycles uncore power Core 12 C State Transition Cycles event=0x7c 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core13_transition_cycles uncore power Core 13 C State Transition Cycles event=0x7d 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core14_transition_cycles uncore power Core 14 C State Transition Cycles event=0x7e 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core1_transition_cycles uncore power Core 1 C State Transition Cycles event=0x71 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core2_transition_cycles uncore power Core 2 C State Transition Cycles event=0x72 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core3_transition_cycles uncore power Core 3 C State Transition Cycles event=0x73 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core4_transition_cycles uncore power Core 4 C State Transition Cycles event=0x74 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core5_transition_cycles uncore power Core 5 C State Transition Cycles event=0x75 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core6_transition_cycles uncore power Core 6 C State Transition Cycles event=0x76 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core7_transition_cycles uncore power Core 7 C State Transition Cycles event=0x77 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core8_transition_cycles uncore power Core 8 C State Transition Cycles event=0x78 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core9_transition_cycles uncore power Core 9 C State Transition Cycles event=0x79 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_delayed_c_state_abort_core0 uncore power Deep C State Rejection - Core 0 event=0x17 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core1 uncore power Deep C State Rejection - Core 1 event=0x18 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core10 uncore power Deep C State Rejection - Core 10 event=0x21 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core11 uncore power Deep C State Rejection - Core 11 event=0x22 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core12 uncore power Deep C State Rejection - Core 12 event=0x23 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core13 uncore power Deep C State Rejection - Core 13 event=0x24 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core14 uncore power Deep C State Rejection - Core 14 event=0x25 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core2 uncore power Deep C State Rejection - Core 2 event=0x19 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core3 uncore power Deep C State Rejection - Core 3 event=0x1a 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core4 uncore power Deep C State Rejection - Core 4 event=0x1b 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core5 uncore power Deep C State Rejection - Core 5 event=0x1c 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core6 uncore power Deep C State Rejection - Core 6 event=0x1d 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core7 uncore power Deep C State Rejection - Core 7 event=0x1e 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core8 uncore power Deep C State Rejection - Core 8 event=0x1f 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core9 uncore power Deep C State Rejection - Core 9 event=0x20 01 Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_demotions_core0 uncore power Core 0 C State Demotions event=0x1e 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core 1 C State Demotions event=0x1f 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core10 uncore power Core 10 C State Demotions event=0x42 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core11 uncore power Core 11 C State Demotions event=0x43 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core12 uncore power Core 12 C State Demotions event=0x44 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core13 uncore power Core 13 C State Demotions event=0x45 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core14 uncore power Core 14 C State Demotions event=0x46 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core 2 C State Demotions event=0x20 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core 3 C State Demotions event=0x21 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core 4 C State Demotions event=0x22 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core 5 C State Demotions event=0x23 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core 6 C State Demotions event=0x24 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core 7 C State Demotions event=0x25 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core8 uncore power Core 8 C State Demotions event=0x40 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core9 uncore power Core 9 C State Demotions event=0x41 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_max_current_cycles uncore power Current Strongest Upper Limit Cycles event=0x7 01 Counts the number of cycles when current is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x61 01 Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_min_perf_p_cycles uncore power Perf P Limit Strongest Lower Limit Cycles event=0x62 01 Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower. Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down. This is largely to minimize increases in snoop and remote read latencies unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x60 01 Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_pkg_c_exit_latency uncore power Package C State Exit Latency event=0x26 01 Counts the number of cycles that the package is transitioning from package C2 to C3 unc_p_pkg_c_exit_latency_sel uncore power Package C State Exit Latency event=0x26 01 Counts the number of cycles that the package is transitioning from package C2 to C3 unc_p_pkg_c_state_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a 01 Counts the number of cycles that the package is in C0 unc_p_pkg_c_state_residency_c2_cycles uncore power Package C State Residency - C2 event=0x2b 01 Counts the number of cycles that the package is in C2 unc_p_pkg_c_state_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c 01 Counts the number of cycles that the package is in C3 unc_p_pkg_c_state_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d 01 Counts the number of cycles that the package is in C6 unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x63 01 Number of cycles spent performing core C state transitions across all cores unc_p_volt_trans_cycles_change uncore power Cycles Changing Voltage event=0x3 01 Counts the number of cycles when the system is changing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition. This event is calculated by or'ing together the increasing and decreasing events unc_p_volt_trans_cycles_decrease uncore power Cycles Decreasing Voltage event=0x2 01 Counts the number of cycles when the system is decreasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition unc_p_volt_trans_cycles_increase uncore power Cycles Increasing Voltage event=0x1 01 Counts the number of cycles when the system is increasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition unc_p_vr_hot_cycles uncore power VR Hot event=0x32 01 dtlb_load_misses.demand_ld_walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=0x8,period=100003,umask=0x82 00 dtlb_load_misses.demand_ld_walk_duration virtual memory Demand load cycles page miss handler (PMH) is busy with this walk event=0x8,period=2000003,umask=0x84 00 l1d.allocated_in_m cache Allocated L1D data cache lines in M state event=0x51,period=2000003,umask=0x2 00 l1d.all_m_replacement cache Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement event=0x51,period=2000003,umask=0x8 00 l1d.eviction cache L1D data cache lines in M state evicted due to replacement event=0x51,period=2000003,umask=0x4 00 l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=0x1 00 This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier l1d_blocks.bank_conflict_cycles cache Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports event=0xbf,cmask=1,period=100003,umask=0x5 00 l1d_pend_miss.pending cache L1D miss outstanding duration in cycles event=0x48,period=2000003,umask=0x1 00 l2_l1d_wb_rqsts.hit_e cache Not rejected writebacks from L1D to L2 cache lines in E state event=0x28,period=200003,umask=0x4 00 l2_l1d_wb_rqsts.hit_m cache Not rejected writebacks from L1D to L2 cache lines in M state event=0x28,period=200003,umask=0x8 00 l2_l1d_wb_rqsts.hit_s cache Not rejected writebacks from L1D to L2 cache lines in S state event=0x28,period=200003,umask=0x2 00 l2_l1d_wb_rqsts.miss cache Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) event=0x28,period=200003,umask=0x1 00 l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=0x4 00 l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=0x1 00 l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=0x2 00 l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=0x1 00 l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=0x2 00 l2_lines_out.dirty_all cache Dirty L2 cache lines filling the L2 event=0xf2,period=100003,umask=0xa 00 l2_lines_out.pf_clean cache Clean L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=0x4 00 l2_lines_out.pf_dirty cache Dirty L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=0x8 00 l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0x30 00 l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0x3 00 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xc0 00 l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xc 00 l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0x10 00 l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x20 00 l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0x1 00 l2_rqsts.pf_hit cache Requests from the L2 hardware prefetchers that hit L2 cache event=0x24,period=200003,umask=0x40 00 l2_rqsts.pf_miss cache Requests from the L2 hardware prefetchers that miss L2 cache event=0x24,period=200003,umask=0x80 00 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0x4 00 l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x8 00 l2_store_lock_rqsts.all cache RFOs that access cache lines in any state event=0x27,period=200003,umask=0xf 00 l2_store_lock_rqsts.hit_e cache RFOs that hit cache lines in E state event=0x27,period=200003,umask=0x4 00 l2_store_lock_rqsts.hit_m cache RFOs that hit cache lines in M state event=0x27,period=200003,umask=0x8 00 l2_store_lock_rqsts.miss cache RFOs that miss cache lines event=0x27,period=200003,umask=0x1 00 l2_trans.all_pf cache L2 or LLC HW prefetches that access L2 cache event=0xf0,period=200003,umask=0x8 00 l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80 00 l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=0x4 00 l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=0x1 00 l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10 00 l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20 00 l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40 00 l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=0x2 00 lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=0x2 00 longest_lat_cache.miss cache Core-originated cacheable demand requests missed LLC event=0x2e,period=100003,umask=0x41 00 longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to LLC event=0x2e,period=100003,umask=0x4f 00 mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache event=0xd2,period=20011,umask=0x2 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC event=0xd2,period=20011,umask=0x4 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2 mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache event=0xd2,period=20011,umask=0x1 00 mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required event=0xd2,period=100003,umask=0x8 00 mem_load_uops_llc_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI) event=0xd3,period=100007,umask=0x1 00 mem_load_uops_llc_miss_retired.remote_dram cache Data from remote DRAM either Snoop not needed or Snoop Miss (RspI) event=0xd3,period=100007,umask=0x4 00 mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required event=0xd1,period=50021,umask=0x4 00 This event counts retired load uops that hit in the last-level (L3) cache without snoops required mem_load_uops_retired.llc_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source event=0xd1,period=100007,umask=0x20 00 mem_uops_retired.all_loads cache All retired load uops (Precise event) event=0xd0,period=2000003,umask=0x81 00 This event counts the number of load uops retired (Precise event) mem_uops_retired.all_stores cache All retired store uops (Precise event) event=0xd0,period=2000003,umask=0x82 00 This event counts the number of store uops retired (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access (Precise event) event=0xd0,period=100007,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary (Precise event) event=0xd0,period=100003,umask=0x41 00 This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary (Precise event) event=0xd0,period=100003,umask=0x42 00 This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB (Precise event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB (Precise event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=0x8 00 offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=0x2 00 offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=0x1 00 offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=0x4 00 offcore_requests_buffer.sq_full cache Cases when offcore requests buffer cannot take more entries for core event=0xb2,period=2000003,umask=0x1 00 offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=0x8 00 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x8 00 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=0x1 00 offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=0x4 00 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=0x1 00 offcore_requests_outstanding.demand_data_rd_c6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=0x1 00 offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=0x4 00 fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e 00 fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10 00 fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=0x8 00 fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=0x4 00 fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=0x2 00 fp_comp_ops_exe.sse_packed_double floating point Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle event=0x10,period=2000003,umask=0x10 00 fp_comp_ops_exe.sse_packed_single floating point Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle event=0x10,period=2000003,umask=0x40 00 fp_comp_ops_exe.sse_scalar_double floating point Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle event=0x10,period=2000003,umask=0x80 00 fp_comp_ops_exe.sse_scalar_single floating point Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle event=0x10,period=2000003,umask=0x20 00 fp_comp_ops_exe.x87 floating point Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s event=0x10,period=2000003,umask=0x1 00 other_assists.avx_store floating point Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations event=0xc1,period=100003,umask=0x8 00 simd_fp_256.packed_double floating point Number of AVX-256 Computational FP double precision uops issued this cycle event=0x11,period=2000003,umask=0x2 00 simd_fp_256.packed_single floating point Number of GSSE-256 Computational FP single precision uops issued this cycle event=0x11,period=2000003,umask=0x1 00 dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=0x1 00 dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=0x2 00 This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end dsb_fill.all_cancel frontend Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit event=0xac,period=2000003,umask=0xa 00 dsb_fill.exceed_dsb_lines frontend Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines event=0xac,period=2000003,umask=0x8 00 dsb_fill.other_cancel frontend Cases of cancelling valid DSB fill not because of exceeding way limit event=0xac,period=2000003,umask=0x2 00 icache.misses frontend Instruction cache, streaming buffer and victim cache misses event=0x80,period=200003,umask=0x2 00 This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18 00 idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18 00 idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24 00 idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24 00 idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=0x8 00 idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=0x2 00 idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c 00 idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x4 00 idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10 00 idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20 00 idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30 00 idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=0x1 00 This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization idq_uops_not_delivered.cycles_ge_1_uop_deliv.core frontend Cycles when 1 or more uops were delivered to the by the front end event=0x9c,cmask=4,inv=1,period=2000003,umask=0x1 00 machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=0x2 00 This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently mem_trans_retired.load_latency_gt_128 memory Loads with latency value being above 128 (Must be precise) event=0xcd,period=1009,umask=0x1,ldlat=0x80 00 mem_trans_retired.load_latency_gt_16 memory Loads with latency value being above 16 (Must be precise) event=0xcd,period=20011,umask=0x1,ldlat=0x10 00 mem_trans_retired.load_latency_gt_256 memory Loads with latency value being above 256 (Must be precise) event=0xcd,period=503,umask=0x1,ldlat=0x100 00 mem_trans_retired.load_latency_gt_32 memory Loads with latency value being above 32 (Must be precise) event=0xcd,period=100007,umask=0x1,ldlat=0x20 00 mem_trans_retired.load_latency_gt_4 memory Loads with latency value being above 4 (Must be precise) event=0xcd,period=100003,umask=0x1,ldlat=0x4 00 mem_trans_retired.load_latency_gt_512 memory Loads with latency value being above 512 (Must be precise) event=0xcd,period=101,umask=0x1,ldlat=0x200 00 mem_trans_retired.load_latency_gt_64 memory Loads with latency value being above 64 (Must be precise) event=0xcd,period=2003,umask=0x1,ldlat=0x40 00 mem_trans_retired.load_latency_gt_8 memory Loads with latency value being above 8 (Must be precise) event=0xcd,period=50021,umask=0x1,ldlat=0x8 00 mem_trans_retired.precise_store memory Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise) event=0xcd,period=2000003,umask=0x2 00 misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=0x5,period=2000003,umask=0x1 00 misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=0x5,period=2000003,umask=0x2 00 offcore_response.all_demand_mlc_pref_reads.llc_miss.any_response memory This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC20077 00 offcore_response.all_demand_mlc_pref_reads.llc_miss.local_dram memory Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400077 00 offcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forward memory This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x187FC20077 00 offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20080 00 cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=0x1 00 cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=0x1 00 cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=0x2 00 hw_pre_req.dl1_miss other Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for event=0x4e,period=2000003,umask=0x2 00 insts_written_to_iq.insts other Valid instructions written to IQ per cycle event=0x17,period=2000003,umask=0x1 00 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=0x1 00 agu_bypass_cancel.count pipeline This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an event=0xb6,period=100003,umask=0x1 00 arith.fpu_div pipeline Divide operations executed event=0x14,cmask=1,edge=1,period=100003,umask=0x1 00 This event counts the number of the divide operations executed arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=0x1 00 br_inst_exec.all_branches pipeline Speculative and retired branches event=0x88,period=200003,umask=0xff 00 br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009 00 br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc4,period=400009,umask=0x4 00 br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40 00 br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10 00 br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff 00 br_misp_exec.all_direct_near_call pipeline Speculative and retired mispredicted direct near calls event=0x89,period=200003,umask=0xd0 00 br_misp_exec.taken_direct_near_call pipeline Taken speculative and retired mispredicted direct near calls event=0x89,period=200003,umask=0x90 00 br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009 00 br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc5,period=400009,umask=0x4 00 br_misp_retired.near_call pipeline Direct and indirect mispredicted near call instructions retired (Precise event) event=0xc5,period=100007,umask=0x2 00 br_misp_retired.not_taken pipeline Mispredicted not taken branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x10 00 br_misp_retired.taken pipeline Mispredicted taken branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x20 00 cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=0x1 00 cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=0x1 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=0x1 00 cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=0x1 00 cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003 00 cycle_activity.cycles_l1d_pending pipeline Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING event=0xa3,cmask=2,period=2000003,umask=0x2 00 cycle_activity.cycles_l2_pending pipeline Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 event=0xa3,cmask=1,period=2000003,umask=0x1 00 cycle_activity.cycles_no_dispatch pipeline Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event event=0xa3,cmask=4,period=2000003,umask=0x4 00 cycle_activity.stalls_l1d_pending pipeline Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING event=0xa3,cmask=6,period=2000003,umask=0x6 00 cycle_activity.stalls_l2_pending pipeline Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2 event=0xa3,cmask=5,period=2000003,umask=0x5 00 ild_stall.iq_full pipeline Stall cycles because IQ is full event=0x87,period=2000003,umask=0x4 00 inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003 00 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event event=0xc0,period=2000003 00 inst_retired.prec_dist pipeline Instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc0,period=2000003,umask=0x1 00 int_misc.rat_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xd,period=2000003,umask=0x40 00 int_misc.recovery_cycles pipeline Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) event=0xd,cmask=1,period=2000003,umask=0x3 00 int_misc.recovery_stalls_count pipeline Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) event=0xd,cmask=1,edge=1,period=2000003,umask=0x3 00 ld_blocks.all_block pipeline Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss) event=0x3,period=100003,umask=0x10 00 ld_blocks.data_unknown pipeline Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data event=0x3,period=100003,umask=0x1 00 ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=0x3,period=100003,umask=0x2 00 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare event=0x7,period=100003,umask=0x1 00 Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles ld_blocks_partial.all_sta_block pipeline This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type event=0x7,period=100003,umask=0x8 00 load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=0x2 00 load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=0x1 00 other_assists.itlb_miss_retired pipeline Retired instructions experiencing ITLB misses event=0xc1,period=100003,umask=0x2 00 partial_rat_stalls.flags_merge_uop pipeline Increments the number of flags-merge uops in flight each cycle event=0x59,period=2000003,umask=0x20 00 partial_rat_stalls.flags_merge_uop_cycles pipeline Performance sensitive flags-merging uops added by Sandy Bridge u-arch event=0x59,cmask=1,period=2000003,umask=0x20 00 This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual partial_rat_stalls.mul_single_uop pipeline Multiply packed/scalar single precision uops allocated event=0x59,period=2000003,umask=0x80 00 partial_rat_stalls.slow_lea_window pipeline Cycles with at least one slow LEA uop being allocated event=0x59,period=2000003,umask=0x40 00 This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=0x1 00 resource_stalls.lb pipeline Counts the cycles of stall due to lack of load buffers event=0xa2,period=2000003,umask=0x2 00 resource_stalls.lb_sb pipeline Resource stalls due to load or store buffers all being in use event=0xa2,period=2000003,umask=0xa 00 resource_stalls.mem_rs pipeline Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized event=0xa2,period=2000003,umask=0xe 00 resource_stalls.ooo_rsrc pipeline Resource stalls due to Rob being full, FCSW, MXCSR and OTHER event=0xa2,period=2000003,umask=0xf0 00 resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=0x8 00 resource_stalls2.all_fl_empty pipeline Cycles with either free list is empty event=0x5b,period=2000003,umask=0xc 00 resource_stalls2.all_prf_control pipeline Resource stalls2 control structures full for physical registers event=0x5b,period=2000003,umask=0xf 00 resource_stalls2.bob_full pipeline Cycles when Allocator is stalled if BOB is full and new branch needs it event=0x5b,period=2000003,umask=0x40 00 resource_stalls2.ooo_rsrc pipeline Resource stalls out of order resources full event=0x5b,period=2000003,umask=0x4f 00 rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20 00 rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=0x1 00 rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=0x1 00 uops_dispatched.core pipeline Uops dispatched from any thread event=0xb1,period=2000003,umask=0x2 00 uops_dispatched.thread pipeline Uops dispatched per thread event=0xb1,period=2000003,umask=0x1 00 uops_dispatched_port.port_0 pipeline Cycles per thread when uops are dispatched to port 0 event=0xa1,period=2000003,umask=0x1 00 uops_dispatched_port.port_0_core pipeline Cycles per core when uops are dispatched to port 0 event=0xa1,any=1,period=2000003,umask=0x1 00 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are dispatched to port 1 event=0xa1,period=2000003,umask=0x2 00 uops_dispatched_port.port_1_core pipeline Cycles per core when uops are dispatched to port 1 event=0xa1,any=1,period=2000003,umask=0x2 00 uops_dispatched_port.port_2 pipeline Cycles per thread when load or STA uops are dispatched to port 2 event=0xa1,period=2000003,umask=0xc 00 uops_dispatched_port.port_2_core pipeline Cycles per core when load or STA uops are dispatched to port 2 event=0xa1,any=1,period=2000003,umask=0xc 00 uops_dispatched_port.port_3 pipeline Cycles per thread when load or STA uops are dispatched to port 3 event=0xa1,period=2000003,umask=0x30 00 uops_dispatched_port.port_3_core pipeline Cycles per core when load or STA uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=0x30 00 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are dispatched to port 4 event=0xa1,period=2000003,umask=0x40 00 uops_dispatched_port.port_4_core pipeline Cycles per core when uops are dispatched to port 4 event=0xa1,any=1,period=2000003,umask=0x40 00 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are dispatched to port 5 event=0xa1,period=2000003,umask=0x80 00 uops_dispatched_port.port_5_core pipeline Cycles per core when uops are dispatched to port 5 event=0xa1,any=1,period=2000003,umask=0x80 00 uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=0x1 00 This event counts the number of Uops issued by the front-end of the pipeilne to the back-end uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=0x1 00 This event counts the number of micro-ops retired (Precise event) uops_retired.core_stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=0x1 00 uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=0x2 00 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event) unc_c_ismq_drd_miss_occ uncore cache event=0x21 01 unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=0x3 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.nid uncore cache Cache Lookups; RTID event=0x34,umask=0x41 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=0x9 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=0x5 01 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_victims.nid uncore cache Lines Victimized; Victimized Lines that Match NID event=0x37,umask=0x40 01 Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_c_misc.rfo_hit_s uncore cache Cbo Misc; RFO HitS event=0x39,umask=0x8 01 Miscellaneous events in the Cbo unc_c_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=0x1 01 Miscellaneous events in the Cbo unc_c_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=0x2 01 Miscellaneous events in the Cbo unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bounces.ak_core uncore cache Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=0x5,umask=0x2 01 unc_c_ring_bounces.bl_core uncore cache Number of LLC responses that bounced on the Ring.; Data Responses to core event=0x5,umask=0x4 01 unc_c_ring_bounces.iv_core uncore cache Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=0x5,umask=0x8 01 unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in JKT. Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN. To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD unc_c_ring_sink_starved.ad_cache uncore cache event=0x6,umask=0x1 01 unc_c_ring_sink_starved.ak_core uncore cache event=0x6,umask=0x2 01 unc_c_ring_sink_starved.bl_core uncore cache event=0x6,umask=0x4 01 unc_c_ring_sink_starved.iv_core uncore cache event=0x6,umask=0x8 01 unc_c_rxr_ext_starved.ipq uncore cache Ingress Arbiter Blocking Cycles; IRQ event=0x12,umask=0x2 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.irq uncore cache Ingress Arbiter Blocking Cycles; IPQ event=0x12,umask=0x1 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.ismq uncore cache Ingress Arbiter Blocking Cycles; ISMQ event=0x12,umask=0x4 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.ismq_bids uncore cache Ingress Arbiter Blocking Cycles; ISMQ_BID event=0x12,umask=0x8 01 Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_inserts.irq_rejected uncore cache Ingress Allocations; IRQ Rejected event=0x13,umask=0x2 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.vfifo uncore cache Ingress Allocations; VFIFO event=0x13,umask=0x10 01 Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_int_starved.ipq uncore cache Ingress Internal Starvation Cycles; IPQ event=0x14,umask=0x4 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_int_starved.irq uncore cache Ingress Internal Starvation Cycles; IRQ event=0x14,umask=0x1 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_int_starved.ismq uncore cache Ingress Internal Starvation Cycles; ISMQ event=0x14,umask=0x8 01 Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_ipq_retry.addr_conflict uncore cache Probe Queue Retries; Address Conflict event=0x31,umask=0x4 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry.any uncore cache Probe Queue Retries; Any Reject event=0x31,umask=0x1 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry.full uncore cache Probe Queue Retries; No Egress Credits event=0x31,umask=0x2 01 Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries unc_c_rxr_irq_retry.addr_conflict uncore cache Ingress Request Queue Rejects; Address Conflict event=0x32,umask=0x4 01 unc_c_rxr_irq_retry.any uncore cache Ingress Request Queue Rejects; Any Reject event=0x32,umask=0x1 01 unc_c_rxr_irq_retry.full uncore cache Ingress Request Queue Rejects; No Egress Credits event=0x32,umask=0x2 01 unc_c_rxr_irq_retry.qpi_credits uncore cache Ingress Request Queue Rejects; No QPI Credits event=0x32,umask=0x10 01 unc_c_rxr_irq_retry.rtid uncore cache Ingress Request Queue Rejects; No RTIDs event=0x32,umask=0x8 01 unc_c_rxr_ismq_retry.any uncore cache ISMQ Retries; Any Reject event=0x33,umask=0x1 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.full uncore cache ISMQ Retries; No Egress Credits event=0x33,umask=0x2 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.iio_credits uncore cache ISMQ Retries; No IIO Credits event=0x33,umask=0x20 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.rtid uncore cache ISMQ Retries; No RTIDs event=0x33,umask=0x8 01 Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_occupancy.irq_rejected uncore cache Ingress Occupancy; IRQ Rejected event=0x11,umask=0x2 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.vfifo uncore cache Ingress Occupancy; VFIFO event=0x11,umask=0x10 01 Counts number of entries in the specified Ingress queue in each cycle unc_c_tor_inserts.eviction uncore cache TOR Inserts; Evictions event=0x35,umask=0x4 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.miss_all uncore cache TOR Inserts; Miss All event=0x35,umask=0xa 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.miss_opcode uncore cache TOR Inserts; Miss Opcode Match event=0x35,umask=0x3 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_all uncore cache TOR Inserts; NID Matched event=0x35,umask=0x48 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_eviction uncore cache TOR Inserts; NID Matched Evictions event=0x35,umask=0x44 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_miss_all uncore cache TOR Inserts; NID Matched Miss All event=0x35,umask=0x4a 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_miss_opcode uncore cache TOR Inserts; NID and Opcode Matched Miss event=0x35,umask=0x43 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_opcode uncore cache TOR Inserts; NID and Opcode Matched event=0x35,umask=0x41 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.nid_wb uncore cache TOR Inserts; NID Matched Writebacks event=0x35,umask=0x50 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.opcode uncore cache TOR Inserts; Opcode Match event=0x35,umask=0x1 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_inserts.wb uncore cache TOR Inserts; Writebacks event=0x35,umask=0x10 01 Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.all uncore cache TOR Occupancy; Any event=0x36,umask=0x8 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.eviction uncore cache TOR Occupancy; Evictions event=0x36,umask=0x4 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_all uncore cache TOR Occupancy; Miss All event=0x36,umask=0xa 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_opcode uncore cache TOR Occupancy; Miss Opcode Match event=0x36,umask=0x3 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x48 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_eviction uncore cache TOR Occupancy; NID Matched Evictions event=0x36,umask=0x44 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_miss_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x4a 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_miss_opcode uncore cache TOR Occupancy; NID and Opcode Matched Miss event=0x36,umask=0x43 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_opcode uncore cache TOR Occupancy; NID and Opcode Matched event=0x36,umask=0x41 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.opcode uncore cache TOR Occupancy; Opcode Match event=0x36,umask=0x1 01 For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_txr_ads_used uncore cache event=0x4 01 unc_c_txr_inserts.ad_cache uncore cache Egress Allocations; AD - Cachebo event=0x2,umask=0x1 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ad_core uncore cache Egress Allocations; AD - Corebo event=0x2,umask=0x10 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ak_cache uncore cache Egress Allocations; AK - Cachebo event=0x2,umask=0x2 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ak_core uncore cache Egress Allocations; AK - Corebo event=0x2,umask=0x20 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.bl_cache uncore cache Egress Allocations; BL - Cacheno event=0x2,umask=0x4 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.bl_core uncore cache Egress Allocations; BL - Corebo event=0x2,umask=0x40 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.iv_cache uncore cache Egress Allocations; IV - Cachebo event=0x2,umask=0x8 01 Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring unc_c_txr_starved.ak uncore cache Injection Starvation; Onto AK Ring event=0x3,umask=0x2 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_c_txr_starved.bl uncore cache Injection Starvation; Onto BL Ring event=0x3,umask=0x4 01 Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_bypass_imc.not_taken uncore cache HA to iMC Bypass; Not Taken event=0x14,umask=0x2 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not unc_h_bypass_imc.taken uncore cache HA to iMC Bypass; Taken event=0x14,umask=0x1 01 Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not unc_h_conflict_cycles.conflict uncore cache Conflict Checks; Conflict Detected event=0xb,umask=0x2 01 unc_h_conflict_cycles.no_conflict uncore cache Conflict Checks; No Conflict event=0xb,umask=0x1 01 unc_h_directory_lookup.no_snp uncore cache Directory Lookups; Snoop Not Needed event=0xc,umask=0x2 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snp uncore cache Directory Lookups; Snoop Needed event=0xc,umask=0x1 01 Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_update.clear uncore cache Directory Updates; Directory Clear event=0xd,umask=0x2 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_directory_update.set uncore cache Directory Updates; Directory Set event=0xd,umask=0x1 01 Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears unc_h_requests.reads uncore cache Read and Write Requests; Reads event=0x1,umask=0x3 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_h_requests.writes uncore cache Read and Write Requests; Writes event=0x1,umask=0xc 01 Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc) unc_h_ring_ad_used.ccw_even uncore cache HA AD Ring in Use; Counterclockwise and Even event=0x3e,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd event=0x3e,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_even uncore cache HA AD Ring in Use; Clockwise and Even event=0x3e,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_odd uncore cache HA AD Ring in Use; Clockwise and Odd event=0x3e,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_even uncore cache HA AK Ring in Use; Counterclockwise and Even event=0x3f,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd event=0x3f,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_even uncore cache HA AK Ring in Use; Clockwise and Even event=0x3f,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_odd uncore cache HA AK Ring in Use; Clockwise and Odd event=0x3f,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_even uncore cache HA BL Ring in Use; Counterclockwise and Even event=0x40,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd event=0x40,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_even uncore cache HA BL Ring in Use; Clockwise and Even event=0x40,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_odd uncore cache HA BL Ring in Use; Clockwise and Odd event=0x40,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_rpq_cycles_no_reg_credits.chn0 uncore cache iMC RPQ Credits Empty - Regular; Channel 0 event=0x15,umask=0x1 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn1 uncore cache iMC RPQ Credits Empty - Regular; Channel 1 event=0x15,umask=0x2 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn2 uncore cache iMC RPQ Credits Empty - Regular; Channel 2 event=0x15,umask=0x4 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn3 uncore cache iMC RPQ Credits Empty - Regular; Channel 3 event=0x15,umask=0x8 01 Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn0 uncore cache iMC RPQ Credits Empty - Special; Channel 0 event=0x16,umask=0x1 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn1 uncore cache iMC RPQ Credits Empty - Special; Channel 1 event=0x16,umask=0x2 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn2 uncore cache iMC RPQ Credits Empty - Special; Channel 2 event=0x16,umask=0x4 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn3 uncore cache iMC RPQ Credits Empty - Special; Channel 3 event=0x16,umask=0x8 01 Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_tad_requests_g0.region0 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 0 event=0x1b,umask=0x1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region1 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 1 event=0x1b,umask=0x2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region2 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 2 event=0x1b,umask=0x4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region3 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 3 event=0x1b,umask=0x8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region4 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 4 event=0x1b,umask=0x10 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region5 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 5 event=0x1b,umask=0x20 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region6 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 6 event=0x1b,umask=0x40 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region7 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 7 event=0x1b,umask=0x80 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region10 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 10 event=0x1c,umask=0x4 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region11 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 11 event=0x1c,umask=0x8 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region8 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 8 event=0x1c,umask=0x1 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region9 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 9 event=0x1c,umask=0x2 01 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tracker_inserts.all uncore cache Tracker Allocations; All Requests event=0x6,umask=0x3 01 Counts the number of allocations into the local HA tracker pool. This can be used in conjunction with the occupancy accumulation event in order to calculate average latency. One cannot filter between reads and writes. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_txr_ad.ndr uncore cache Outbound NDR Ring Transactions; Non-data Responses event=0xf,umask=0x1 01 Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details unc_h_txr_ad.snp uncore cache Outbound NDR Ring Transactions; Snoops event=0xf,umask=0x2 01 Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details unc_h_txr_ad_cycles_full.all uncore cache AD Egress Full; All event=0x2a,umask=0x3 01 unc_h_txr_ad_cycles_full.sched0 uncore cache AD Egress Full; Scheduler 0 event=0x2a,umask=0x1 01 unc_h_txr_ad_cycles_full.sched1 uncore cache AD Egress Full; Scheduler 1 event=0x2a,umask=0x2 01 unc_h_txr_ad_cycles_ne.all uncore cache AD Egress Not Empty; All event=0x29,umask=0x3 01 unc_h_txr_ad_cycles_ne.sched0 uncore cache AD Egress Not Empty; Scheduler 0 event=0x29,umask=0x1 01 unc_h_txr_ad_cycles_ne.sched1 uncore cache AD Egress Not Empty; Scheduler 1 event=0x29,umask=0x2 01 unc_h_txr_ad_inserts.all uncore cache AD Egress Allocations; All event=0x27,umask=0x3 01 unc_h_txr_ad_inserts.sched0 uncore cache AD Egress Allocations; Scheduler 0 event=0x27,umask=0x1 01 unc_h_txr_ad_inserts.sched1 uncore cache AD Egress Allocations; Scheduler 1 event=0x27,umask=0x2 01 unc_h_txr_ad_occupancy.all uncore cache AD Egress Occupancy; All event=0x28,umask=0x3 01 unc_h_txr_ad_occupancy.sched0 uncore cache AD Egress Occupancy; Scheduler 0 event=0x28,umask=0x1 01 unc_h_txr_ad_occupancy.sched1 uncore cache AD Egress Occupancy; Scheduler 1 event=0x28,umask=0x2 01 unc_h_txr_ak_cycles_full.all uncore cache AK Egress Full; All event=0x32,umask=0x3 01 unc_h_txr_ak_cycles_full.sched0 uncore cache AK Egress Full; Scheduler 0 event=0x32,umask=0x1 01 unc_h_txr_ak_cycles_full.sched1 uncore cache AK Egress Full; Scheduler 1 event=0x32,umask=0x2 01 unc_h_txr_ak_cycles_ne.all uncore cache AK Egress Not Empty; All event=0x31,umask=0x3 01 unc_h_txr_ak_cycles_ne.sched0 uncore cache AK Egress Not Empty; Scheduler 0 event=0x31,umask=0x1 01 unc_h_txr_ak_cycles_ne.sched1 uncore cache AK Egress Not Empty; Scheduler 1 event=0x31,umask=0x2 01 unc_h_txr_ak_inserts.all uncore cache AK Egress Allocations; All event=0x2f,umask=0x3 01 unc_h_txr_ak_inserts.sched0 uncore cache AK Egress Allocations; Scheduler 0 event=0x2f,umask=0x1 01 unc_h_txr_ak_inserts.sched1 uncore cache AK Egress Allocations; Scheduler 1 event=0x2f,umask=0x2 01 unc_h_txr_ak_ndr uncore cache Outbound NDR Ring Transactions event=0xe 01 Counts the number of outbound NDR transactions sent on the AK ring. NDR stands for 'non-data response' and is generally used for completions that do not include data. AK NDR is used for messages to the local socket unc_h_txr_ak_occupancy.all uncore cache AK Egress Occupancy; All event=0x30,umask=0x3 01 unc_h_txr_ak_occupancy.sched0 uncore cache AK Egress Occupancy; Scheduler 0 event=0x30,umask=0x1 01 unc_h_txr_ak_occupancy.sched1 uncore cache AK Egress Occupancy; Scheduler 1 event=0x30,umask=0x2 01 unc_h_txr_bl.drs_cache uncore cache Outbound DRS Ring Transactions to Cache; Data to Cache event=0x10,umask=0x1 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination unc_h_txr_bl.drs_core uncore cache Outbound DRS Ring Transactions to Cache; Data to Core event=0x10,umask=0x2 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination unc_h_txr_bl.drs_qpi uncore cache Outbound DRS Ring Transactions to Cache; Data to QPI event=0x10,umask=0x4 01 Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination unc_h_txr_bl_cycles_full.all uncore cache BL Egress Full; All event=0x36,umask=0x3 01 unc_h_txr_bl_cycles_full.sched0 uncore cache BL Egress Full; Scheduler 0 event=0x36,umask=0x1 01 unc_h_txr_bl_cycles_full.sched1 uncore cache BL Egress Full; Scheduler 1 event=0x36,umask=0x2 01 unc_h_txr_bl_cycles_ne.all uncore cache BL Egress Not Empty; All event=0x35,umask=0x3 01 unc_h_txr_bl_cycles_ne.sched0 uncore cache BL Egress Not Empty; Scheduler 0 event=0x35,umask=0x1 01 unc_h_txr_bl_cycles_ne.sched1 uncore cache BL Egress Not Empty; Scheduler 1 event=0x35,umask=0x2 01 unc_h_txr_bl_inserts.all uncore cache BL Egress Allocations; All event=0x33,umask=0x3 01 unc_h_txr_bl_inserts.sched0 uncore cache BL Egress Allocations; Scheduler 0 event=0x33,umask=0x1 01 unc_h_txr_bl_inserts.sched1 uncore cache BL Egress Allocations; Scheduler 1 event=0x33,umask=0x2 01 unc_h_txr_bl_occupancy.all uncore cache BL Egress Occupancy; All event=0x34,umask=0x3 01 unc_h_txr_bl_occupancy.sched0 uncore cache BL Egress Occupancy; Scheduler 0 event=0x34,umask=0x1 01 unc_h_txr_bl_occupancy.sched1 uncore cache BL Egress Occupancy; Scheduler 1 event=0x34,umask=0x2 01 unc_h_wpq_cycles_no_reg_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0 event=0x18,umask=0x1 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1 event=0x18,umask=0x2 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2 event=0x18,umask=0x4 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3 event=0x18,umask=0x8 01 Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 0 event=0x19,umask=0x1 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 1 event=0x19,umask=0x2 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 2 event=0x19,umask=0x4 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 3 event=0x19,umask=0x8 01 Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the 'special' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time unc_i_address_match.merge_count uncore interconnect Address Match (Conflict) Count; Conflict Merges event=0x17,umask=0x2 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache unc_i_address_match.stall_count uncore interconnect Address Match (Conflict) Count; Conflict Stalls event=0x17,umask=0x1 01 Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache unc_i_cache_ack_pending_occupancy.any uncore interconnect Write Ack Pending Occupancy; Any Source event=0x14,umask=0x1 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements unc_i_cache_ack_pending_occupancy.source uncore interconnect Write Ack Pending Occupancy; Select Source event=0x14,umask=0x2 01 Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements unc_i_cache_own_occupancy.any uncore interconnect Outstanding Write Ownership Occupancy; Any Source event=0x13,umask=0x1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned unc_i_cache_own_occupancy.source uncore interconnect Outstanding Write Ownership Occupancy; Select Source event=0x13,umask=0x2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned unc_i_cache_read_occupancy.any uncore interconnect Outstanding Read Occupancy; Any Source event=0x10,umask=0x1 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned unc_i_cache_read_occupancy.source uncore interconnect Outstanding Read Occupancy; Select Source event=0x10,umask=0x2 01 Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0x12,umask=0x1 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_total_occupancy.source uncore interconnect Total Write Cache Occupancy; Select Source event=0x12,umask=0x2 01 Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_write_occupancy.any uncore interconnect Outstanding Write Occupancy; Any Source event=0x11,umask=0x1 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore unc_i_cache_write_occupancy.source uncore interconnect Outstanding Write Occupancy; Select Source event=0x11,umask=0x2 01 Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore unc_i_tickles.lost_ownership uncore interconnect Tickle Count; Ownership Lost event=0x16,umask=0x1 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles unc_i_tickles.top_of_queue uncore interconnect Tickle Count; Data Returned event=0x16,umask=0x2 01 Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles unc_i_transactions.pd_prefetches uncore interconnect Inbound Transaction Count; Read Prefetches event=0x15,umask=0x4 01 Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x15,umask=0x1 01 Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x15,umask=0x2 01 Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_q_clockticks uncore interconnect Number of qfclks event=0x14 01 Counts the number of clocks in the QPI LL. This clock runs at 1/8th the 'GT/s' speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed unc_q_direct2core.failure_credits uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress Credits event=0x13,umask=0x2 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.failure_credits_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT event=0x13,umask=0x8 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.failure_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Not Set event=0x13,umask=0x4 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.success uncore interconnect Direct 2 Core Spawning; Spawn Success event=0x13,umask=0x1 01 Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_rxl_crc_errors.link_init uncore interconnect CRC Errors Detected; LinkInit event=0x3,umask=0x1 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_q_rxl_crc_errors.normal_op uncore interconnect CRC Errors Detected; Normal Operations event=0x3,umask=0x2 01 Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_q_rxl_credits_consumed_vn0.drs uncore interconnect VN0 Credit Consumed; DRS event=0x1e,umask=0x1 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.hom uncore interconnect VN0 Credit Consumed; HOM event=0x1e,umask=0x8 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ncb uncore interconnect VN0 Credit Consumed; NCB event=0x1e,umask=0x2 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ncs uncore interconnect VN0 Credit Consumed; NCS event=0x1e,umask=0x4 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ndr uncore interconnect VN0 Credit Consumed; NDR event=0x1e,umask=0x20 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.snp uncore interconnect VN0 Credit Consumed; SNP event=0x1e,umask=0x10 01 Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_flits_g0.data uncore interconnect Flits Received - Group 0; Data Tx Flits event=0x1,umask=0x2 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g0.idle uncore interconnect Flits Received - Group 0; Idle and Null Flits event=0x1,umask=0x1 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g0.non_data uncore interconnect Flits Received - Group 0; Non-Data protocol Tx Flits event=0x1,umask=0x4 01 Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g1.drs uncore interconnect Flits Received - Group 1; DRS Flits (both Header and Data) event=0x2,umask=0x18 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.drs_data uncore interconnect Flits Received - Group 1; DRS Data Flits event=0x2,umask=0x8 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.drs_nondata uncore interconnect Flits Received - Group 1; DRS Header Flits event=0x2,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom uncore interconnect Flits Received - Group 1; HOM Flits event=0x2,umask=0x6 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom_nonreq uncore interconnect Flits Received - Group 1; HOM Non-Request Flits event=0x2,umask=0x4 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom_req uncore interconnect Flits Received - Group 1; HOM Request Flits event=0x2,umask=0x2 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.snp uncore interconnect Flits Received - Group 1; SNP Flits event=0x2,umask=0x1 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb uncore interconnect Flits Received - Group 2; Non-Coherent Rx Flits event=0x3,umask=0xc 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb_data uncore interconnect Flits Received - Group 2; Non-Coherent data Rx Flits event=0x3,umask=0x4 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb_nondata uncore interconnect Flits Received - Group 2; Non-Coherent non-data Rx Flits event=0x3,umask=0x8 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncs uncore interconnect Flits Received - Group 2; Non-Coherent standard Rx Flits event=0x3,umask=0x10 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ndr_ad uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AD event=0x3,umask=0x1 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ndr_ak uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AK event=0x3,umask=0x2 01 Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_stalls.bgf_drs uncore interconnect Stalls Sending to R3QPI; BGF Stall - HOM event=0x35,umask=0x1 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_hom uncore interconnect Stalls Sending to R3QPI; BGF Stall - DRS event=0x35,umask=0x8 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ncb uncore interconnect Stalls Sending to R3QPI; BGF Stall - SNP event=0x35,umask=0x2 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ncs uncore interconnect Stalls Sending to R3QPI; BGF Stall - NDR event=0x35,umask=0x4 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ndr uncore interconnect Stalls Sending to R3QPI; BGF Stall - NCS event=0x35,umask=0x20 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_snp uncore interconnect Stalls Sending to R3QPI; BGF Stall - NCB event=0x35,umask=0x10 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.egress_credits uncore interconnect Stalls Sending to R3QPI; Egress Credits event=0x35,umask=0x40 01 Number of stalls trying to send to R3QPI unc_q_rxl_stalls.gv uncore interconnect Stalls Sending to R3QPI; GV event=0x35,umask=0x80 01 Number of stalls trying to send to R3QPI unc_q_txl_crc_no_credits.almost_full uncore interconnect Cycles Stalled with no LLR Credits; LLR is almost full event=0x2,umask=0x2 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall unc_q_txl_crc_no_credits.full uncore interconnect Cycles Stalled with no LLR Credits; LLR is full event=0x2,umask=0x1 01 Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall unc_q_txl_flits_g0.data uncore interconnect Flits Transferred - Group 0; Data Tx Flits event=0,umask=0x2 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g0.idle uncore interconnect Flits Transferred - Group 0; Idle and Null Flits event=0,umask=0x1 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g0.non_data uncore interconnect Flits Transferred - Group 0; Non-Data protocol Tx Flits event=0,umask=0x4 01 Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g1.drs uncore interconnect Flits Transferred - Group 1; DRS Flits (both Header and Data) event=0,umask=0x18 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.drs_data uncore interconnect Flits Transferred - Group 1; DRS Data Flits event=0,umask=0x8 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.drs_nondata uncore interconnect Flits Transferred - Group 1; DRS Header Flits event=0,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom uncore interconnect Flits Transferred - Group 1; HOM Flits event=0,umask=0x6 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom_nonreq uncore interconnect Flits Transferred - Group 1; HOM Non-Request Flits event=0,umask=0x4 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom_req uncore interconnect Flits Transferred - Group 1; HOM Request Flits event=0,umask=0x2 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.snp uncore interconnect Flits Transferred - Group 1; SNP Flits event=0,umask=0x1 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb uncore interconnect Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits event=0x1,umask=0xc 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb_data uncore interconnect Flits Transferred - Group 2; Non-Coherent data Tx Flits event=0x1,umask=0x4 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb_nondata uncore interconnect Flits Transferred - Group 2; Non-Coherent non-data Tx Flits event=0x1,umask=0x8 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncs uncore interconnect Flits Transferred - Group 2; Non-Coherent standard Tx Flits event=0x1,umask=0x10 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ndr_ad uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AD event=0x1,umask=0x1 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ndr_ak uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AK event=0x1,umask=0x2 01 Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_r3_iio_credits_acquired.drs uncore interconnect to IIO BL Credit Acquired event=0x20,umask=0x8 01 Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_acquired.ncb uncore interconnect to IIO BL Credit Acquired event=0x20,umask=0x10 01 Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_acquired.ncs uncore interconnect to IIO BL Credit Acquired event=0x20,umask=0x20 01 Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_reject.drs uncore interconnect to IIO BL Credit Rejected event=0x21,umask=0x8 01 Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_reject.ncb uncore interconnect to IIO BL Credit Rejected event=0x21,umask=0x10 01 Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_reject.ncs uncore interconnect to IIO BL Credit Rejected event=0x21,umask=0x20 01 Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_used.drs uncore interconnect to IIO BL Credit In Use event=0x22,umask=0x8 01 Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_used.ncb uncore interconnect to IIO BL Credit In Use event=0x22,umask=0x10 01 Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_iio_credits_used.ncs uncore interconnect to IIO BL Credit In Use event=0x22,umask=0x20 01 Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time unc_r3_ring_ad_used.ccw_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even event=0x7,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd event=0x7,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_even uncore interconnect R3 AD Ring in Use; Clockwise and Even event=0x7,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd event=0x7,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even event=0x8,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.ccw_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd event=0x8,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.cw_even uncore interconnect R3 AK Ring in Use; Clockwise and Even event=0x8,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.cw_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd event=0x8,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_bl_used.ccw_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even event=0x9,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd event=0x9,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_even uncore interconnect R3 BL Ring in Use; Clockwise and Even event=0x9,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd event=0x9,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_iv_used.any uncore interconnect R3 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time unc_r3_rxr_cycles_ne.drs uncore interconnect Ingress Cycles Not Empty; DRS event=0x10,umask=0x8 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.hom uncore interconnect Ingress Cycles Not Empty; HOM event=0x10,umask=0x1 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ncb uncore interconnect Ingress Cycles Not Empty; NCB event=0x10,umask=0x10 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ncs uncore interconnect Ingress Cycles Not Empty; NCS event=0x10,umask=0x20 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ndr uncore interconnect Ingress Cycles Not Empty; NDR event=0x10,umask=0x4 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.snp uncore interconnect Ingress Cycles Not Empty; SNP event=0x10,umask=0x2 01 Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.drs uncore interconnect Ingress Allocations; DRS event=0x11,umask=0x8 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.hom uncore interconnect Ingress Allocations; HOM event=0x11,umask=0x1 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ncb uncore interconnect Ingress Allocations; NCB event=0x11,umask=0x10 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ncs uncore interconnect Ingress Allocations; NCS event=0x11,umask=0x20 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ndr uncore interconnect Ingress Allocations; NDR event=0x11,umask=0x4 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.snp uncore interconnect Ingress Allocations; SNP event=0x11,umask=0x2 01 Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_occupancy.drs uncore interconnect Ingress Occupancy Accumulator; DRS event=0x13,umask=0x8 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.hom uncore interconnect Ingress Occupancy Accumulator; HOM event=0x13,umask=0x1 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ncb uncore interconnect Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ncs uncore interconnect Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ndr uncore interconnect Ingress Occupancy Accumulator; NDR event=0x13,umask=0x4 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.snp uncore interconnect Ingress Occupancy Accumulator; SNP event=0x13,umask=0x2 01 Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_vn0_credits_reject.drs uncore interconnect VN0 Credit Acquisition Failed on DRS; DRS Message Class event=0x37,umask=0x8 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.hom uncore interconnect VN0 Credit Acquisition Failed on DRS; HOM Message Class event=0x37,umask=0x1 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.ncb uncore interconnect VN0 Credit Acquisition Failed on DRS; NCB Message Class event=0x37,umask=0x10 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.ncs uncore interconnect VN0 Credit Acquisition Failed on DRS; NCS Message Class event=0x37,umask=0x20 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.ndr uncore interconnect VN0 Credit Acquisition Failed on DRS; NDR Message Class event=0x37,umask=0x4 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_reject.snp uncore interconnect VN0 Credit Acquisition Failed on DRS; SNP Message Class event=0x37,umask=0x2 01 Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation unc_r3_vn0_credits_used.drs uncore interconnect VN0 Credit Used; DRS Message Class event=0x36,umask=0x8 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.hom uncore interconnect VN0 Credit Used; HOM Message Class event=0x36,umask=0x1 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; NCB Message Class event=0x36,umask=0x10 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCS Message Class event=0x36,umask=0x20 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ndr uncore interconnect VN0 Credit Used; NDR Message Class event=0x36,umask=0x4 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP Message Class event=0x36,umask=0x2 01 Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vna_credits_reject.drs uncore interconnect VNA Credit Reject; DRS Message Class event=0x34,umask=0x8 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.hom uncore interconnect VNA Credit Reject; HOM Message Class event=0x34,umask=0x1 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ncb uncore interconnect VNA Credit Reject; NCB Message Class event=0x34,umask=0x10 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ncs uncore interconnect VNA Credit Reject; NCS Message Class event=0x34,umask=0x20 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ndr uncore interconnect VNA Credit Reject; NDR Message Class event=0x34,umask=0x4 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.snp uncore interconnect VNA Credit Reject; SNP Message Class event=0x34,umask=0x2 01 Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough unc_u_msg_chnl_size_count.4b uncore interconnect MsgCh Requests by Size; 4B Requests event=0x47,umask=0x1 01 Number of transactions on the message channel filtered by request size. This includes both reads and writes unc_u_msg_chnl_size_count.8b uncore interconnect MsgCh Requests by Size; 8B Requests event=0x47,umask=0x2 01 Number of transactions on the message channel filtered by request size. This includes both reads and writes unc_u_phold_cycles.ack_to_deassert uncore interconnect Cycles PHOLD Assert to Ack; ACK to Deassert event=0x45,umask=0x2 01 PHOLD cycles. Filter from source CoreID unc_u_racu_requests.count uncore interconnect RACU Request event=0x46,umask=0x1 01 unc_u_u2c_events.livelock uncore interconnect Monitor Sent to T0; Livelock event=0x43,umask=0x4 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.lterror uncore interconnect Monitor Sent to T0; LTError event=0x43,umask=0x8 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.monitor_t0 uncore interconnect Monitor Sent to T0; Monitor T0 event=0x43,umask=0x1 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.monitor_t1 uncore interconnect Monitor Sent to T0; Monitor T1 event=0x43,umask=0x2 01 Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.other uncore interconnect Monitor Sent to T0; Other event=0x43,umask=0x80 01 Events coming from Uncore can be sent to one or all cores unc_r2_iio_credits_acquired.drs uncore io R2PCIe IIO Credit Acquired; DRS event=0x33,umask=0x8 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_acquired.ncb uncore io R2PCIe IIO Credit Acquired; NCB event=0x33,umask=0x10 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_acquired.ncs uncore io R2PCIe IIO Credit Acquired; NCS event=0x33,umask=0x20 01 Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.drs uncore io R2PCIe IIO Failed to Acquire a Credit; DRS event=0x34,umask=0x8 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.ncb uncore io R2PCIe IIO Failed to Acquire a Credit; NCB event=0x34,umask=0x10 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.ncs uncore io R2PCIe IIO Failed to Acquire a Credit; NCS event=0x34,umask=0x20 01 Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.drs uncore io R2PCIe IIO Credits in Use; DRS event=0x32,umask=0x8 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.ncb uncore io R2PCIe IIO Credits in Use; NCB event=0x32,umask=0x10 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.ncs uncore io R2PCIe IIO Credits in Use; NCS event=0x32,umask=0x20 01 Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly) unc_r2_ring_ad_used.ccw_even uncore io R2 AD Ring in Use; Counterclockwise and Even event=0x7,umask=0x4 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd event=0x7,umask=0x8 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_even uncore io R2 AD Ring in Use; Clockwise and Even event=0x7,umask=0x1 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_odd uncore io R2 AD Ring in Use; Clockwise and Odd event=0x7,umask=0x2 01 Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_even uncore io R2 AK Ring in Use; Counterclockwise and Even event=0x8,umask=0x4 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd event=0x8,umask=0x8 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_even uncore io R2 AK Ring in Use; Clockwise and Even event=0x8,umask=0x1 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_odd uncore io R2 AK Ring in Use; Clockwise and Odd event=0x8,umask=0x2 01 Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_even uncore io R2 BL Ring in Use; Counterclockwise and Even event=0x9,umask=0x4 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd event=0x9,umask=0x8 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_even uncore io R2 BL Ring in Use; Clockwise and Even event=0x9,umask=0x1 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_odd uncore io R2 BL Ring in Use; Clockwise and Odd event=0x9,umask=0x2 01 Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xf 01 Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time unc_r2_rxr_cycles_ne.drs uncore io Ingress Cycles Not Empty; DRS event=0x10,umask=0x8 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_rxr_cycles_ne.ncb uncore io Ingress Cycles Not Empty; NCB event=0x10,umask=0x10 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_rxr_cycles_ne.ncs uncore io Ingress Cycles Not Empty; NCS event=0x10,umask=0x20 01 Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_txr_cycles_full.ad uncore io Egress Cycles Full; AD event=0x25,umask=0x1 01 Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_full.ak uncore io Egress Cycles Full; AK event=0x25,umask=0x2 01 Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_full.bl uncore io Egress Cycles Full; BL event=0x25,umask=0x4 01 Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_ne.ad uncore io Egress Cycles Not Empty; AD event=0x23,umask=0x1 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_r2_txr_cycles_ne.ak uncore io Egress Cycles Not Empty; AK event=0x23,umask=0x2 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_r2_txr_cycles_ne.bl uncore io Egress Cycles Not Empty; BL event=0x23,umask=0x4 01 Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity unc_r2_txr_nacks.ad uncore io Egress NACK; AD event=0x26,umask=0x1 01 Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_r2_txr_nacks.ak uncore io Egress NACK; AK event=0x26,umask=0x2 01 Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_r2_txr_nacks.bl uncore io Egress NACK; BL event=0x26,umask=0x4 01 Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_m_act_count uncore memory DRAM Activate Count event=0x1 01 Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre) event=0x4,umask=0xf 01 unc_m_cas_count.rd uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills) event=0x4,umask=0x3 01 unc_m_cas_count.rd_reg uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre) event=0x4,umask=0x1 01 unc_m_cas_count.rd_underfill uncore memory DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued event=0x4,umask=0x2 01 unc_m_cas_count.wr uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes) event=0x4,umask=0xc 01 unc_m_cas_count.wr_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=0x4,umask=0x8 01 unc_m_cas_count.wr_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=0x4,umask=0x4 01 unc_m_clockticks uncore memory uclks event=0 01 Uncore Fixed Counter - uclks unc_m_major_modes.isoch uncore memory Cycles in a Major Mode; Isoch Major Mode event=0x7,umask=0x8 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.partial uncore memory Cycles in a Major Mode; Partial Major Mode event=0x7,umask=0x4 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.read uncore memory Cycles in a Major Mode; Read Major Mode event=0x7,umask=0x1 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.write uncore memory Cycles in a Major Mode; Write Major Mode event=0x7,umask=0x2 01 Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_power_throttle_cycles.rank0 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x1 01 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_preemption.rd_preempt_rd uncore memory Read Preemption Count; Read over Read Preemption event=0x8,umask=0x1 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency unc_m_preemption.rd_preempt_wr uncore memory Read Preemption Count; Read over Write Preemption event=0x8,umask=0x2 01 Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency unc_m_pre_count.page_close uncore memory DRAM Precharge commands.; Precharge due to timer expiration event=0x2,umask=0x2 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_miss uncore memory DRAM Precharge commands.; Precharges due to page miss event=0x2,umask=0x1 01 Counts the number of DRAM Precharge commands sent on this channel unc_m_rpq_occupancy uncore memory Read Pending Queue Occupancy event=0x80 01 Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21 01 Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20 01 Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_m_wpq_occupancy uncore memory Write Pending Queue Occupancy event=0x81 01 Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts unc_p_core0_transition_cycles uncore power Core C State Transition Cycles event=0x3 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core1_transition_cycles uncore power Core C State Transition Cycles event=0x4 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core2_transition_cycles uncore power Core C State Transition Cycles event=0x5 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core3_transition_cycles uncore power Core C State Transition Cycles event=0x6 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core4_transition_cycles uncore power Core C State Transition Cycles event=0x7 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core5_transition_cycles uncore power Core C State Transition Cycles event=0x8 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core6_transition_cycles uncore power Core C State Transition Cycles event=0x9 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_core7_transition_cycles uncore power Core C State Transition Cycles event=0xa 01 Number of cycles spent performing core C state transitions. There is one event per core unc_p_demotions_core0 uncore power Core C State Demotions event=0x1e 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core C State Demotions event=0x1f 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core C State Demotions event=0x20 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core C State Demotions event=0x21 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core C State Demotions event=0x22 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core C State Demotions event=0x23 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core C State Demotions event=0x24 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core C State Demotions event=0x25 01 Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x1 01 Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_min_perf_p_cycles uncore power Perf P Limit Strongest Lower Limit Cycles event=0x2 01 Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower. Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down. This is largely to minimize increases in snoop and remote read latencies unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0 01 Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C0 event=0x80 01 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C0 event=0x80 01 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C0 event=0x80 01 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0xb 01 Number of cycles spent performing core C state transitions across all cores dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=0x8,period=100003,umask=0x1 00 dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=0x8,period=100003,umask=0x10 00 This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles dtlb_load_misses.walk_completed virtual memory Load misses at all DTLB levels that cause completed page walks event=0x8,period=100003,umask=0x2 00 dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x8,period=2000003,umask=0x4 00 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=0x1 00 dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x10 00 dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=0x2 00 dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=2000003,umask=0x4 00 itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=0x1 00 itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=0x1 00 itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x10 00 itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=0x2 00 itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=2000003,umask=0x4 00 This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=0x1 00 tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20 00 core_reject_l2q.all cache Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path event=0x31,period=200003 00 fetch_stall.icache_fill_pending_cycles cache This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses event=0x86,period=200003,umask=0x4 00 l2_prefetcher.alloc_xq cache Counts the number of L2HWP allocated into XQ GP event=0x3e,period=100007,umask=0x4 00 l2_requests.miss cache Counts the number of L2 cache misses event=0x2e,period=200003,umask=0x41 00 l2_requests.reference cache Counts the total number of L2 cache references event=0x2e,period=200003,umask=0x4f 00 l2_requests_reject.all cache Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times event=0x30,period=200003 00 mem_uops_retired.all_loads cache Counts all the load micro-ops retired event=0x4,period=200003,umask=0x40 00 This event counts the number of load micro-ops retired mem_uops_retired.all_stores cache Counts all the store micro-ops retired event=0x4,period=200003,umask=0x80 00 This event counts the number of store micro-ops retired mem_uops_retired.hitm cache Counts the loads retired that get the data from the other core in the same tile in M state (Precise Event) Supports address when precise event=0x4,period=200003,umask=0x20 00 This event counts the number of load micro-ops retired that got data from another core's cache. (Precise Event) Supports address when precise mem_uops_retired.l1_miss_loads cache Counts the number of load micro-ops retired that miss in L1 D cache event=0x4,period=200003,umask=0x1 00 This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted mem_uops_retired.l2_hit_loads cache Counts the number of load micro-ops retired that hit in the L2 (Precise Event) Supports address when precise event=0x4,period=200003,umask=0x2 00 This event counts the number of load micro-uops retired that hit in the L2 (Precise Event) Supports address when precise mem_uops_retired.l2_miss_loads cache Counts the number of load micro-ops retired that miss in the L2 (Precise Event) Supports address when precise event=0x4,period=100007,umask=0x4 00 This event counts the number of load micro-ops retired that miss in the L2 (Precise Event) Supports address when precise mem_uops_retired.utlb_miss_loads cache Counts the number of load micro-ops retired that caused micro TLB miss event=0x4,period=200003,umask=0x10 00 offcore_response cache Counts the matrix events specified by MSR_OFFCORE_RESPx event=0xb7,period=100007,umask=0x1 00 offcore_response.any_code_rd.any_response cache Counts Demand code reads and prefetch code read requests that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010044 00 offcore_response.any_code_rd.l2_hit_far_tile cache Counts Demand code reads and prefetch code read requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400044 00 offcore_response.any_code_rd.l2_hit_far_tile_e_f cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400044 00 offcore_response.any_code_rd.l2_hit_far_tile_m cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400044 00 offcore_response.any_code_rd.l2_hit_near_tile cache Counts Demand code reads and prefetch code read requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180044 00 offcore_response.any_code_rd.l2_hit_near_tile_e_f cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080044 00 offcore_response.any_code_rd.l2_hit_near_tile_m cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080044 00 offcore_response.any_code_rd.l2_hit_this_tile_e cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000044 00 offcore_response.any_code_rd.l2_hit_this_tile_f cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000044 00 offcore_response.any_code_rd.l2_hit_this_tile_m cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000044 00 offcore_response.any_code_rd.l2_hit_this_tile_s cache Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000044 00 offcore_response.any_code_rd.outstanding cache Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000044 00 offcore_response.any_data_rd.any_response cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013091 00 offcore_response.any_data_rd.l2_hit_far_tile cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800403091 00 offcore_response.any_data_rd.l2_hit_far_tile_e_f cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800403091 00 offcore_response.any_data_rd.l2_hit_far_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000403091 00 offcore_response.any_data_rd.l2_hit_near_tile cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800183091 00 offcore_response.any_data_rd.l2_hit_near_tile_e_f cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800083091 00 offcore_response.any_data_rd.l2_hit_near_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000083091 00 offcore_response.any_data_rd.l2_hit_this_tile_e cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004003091 00 offcore_response.any_data_rd.l2_hit_this_tile_f cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010003091 00 offcore_response.any_data_rd.l2_hit_this_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002003091 00 offcore_response.any_data_rd.l2_hit_this_tile_s cache Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008003091 00 offcore_response.any_data_rd.outstanding cache Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000003091 00 offcore_response.any_pf_l2.any_response cache Counts any Prefetch requests that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010070 00 offcore_response.any_pf_l2.l2_hit_far_tile cache Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400070 00 offcore_response.any_pf_l2.l2_hit_far_tile_e_f cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400070 00 offcore_response.any_pf_l2.l2_hit_far_tile_m cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400070 00 offcore_response.any_pf_l2.l2_hit_near_tile cache Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180070 00 offcore_response.any_pf_l2.l2_hit_near_tile_e_f cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080070 00 offcore_response.any_pf_l2.l2_hit_near_tile_m cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080070 00 offcore_response.any_pf_l2.l2_hit_this_tile_e cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000070 00 offcore_response.any_pf_l2.l2_hit_this_tile_f cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000070 00 offcore_response.any_pf_l2.l2_hit_this_tile_m cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000070 00 offcore_response.any_pf_l2.outstanding cache Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000070 00 offcore_response.any_read.any_response cache Counts any Read request that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000132f7 00 offcore_response.any_read.l2_hit_far_tile cache Counts any Read request that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x18004032f7 00 offcore_response.any_read.l2_hit_far_tile_e_f cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x08004032f7 00 offcore_response.any_read.l2_hit_far_tile_m cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x10004032f7 00 offcore_response.any_read.l2_hit_near_tile cache Counts any Read request that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x18001832f7 00 offcore_response.any_read.l2_hit_near_tile_e_f cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x08000832f7 00 offcore_response.any_read.l2_hit_near_tile_m cache Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x10000832f7 00 offcore_response.any_read.l2_hit_this_tile_e cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00040032f7 00 offcore_response.any_read.l2_hit_this_tile_f cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00100032f7 00 offcore_response.any_read.l2_hit_this_tile_m cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00020032f7 00 offcore_response.any_read.l2_hit_this_tile_s cache Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00080032f7 00 offcore_response.any_read.outstanding cache Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x40000032f7 00 offcore_response.any_request.any_response cache Counts any request that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018000 00 offcore_response.any_request.l2_hit_far_tile cache Counts any request that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800408000 00 offcore_response.any_request.l2_hit_far_tile_e_f cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800408000 00 offcore_response.any_request.l2_hit_far_tile_m cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000408000 00 offcore_response.any_request.l2_hit_near_tile cache Counts any request that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800188000 00 offcore_response.any_request.l2_hit_near_tile_e_f cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800088000 00 offcore_response.any_request.l2_hit_near_tile_m cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000088000 00 offcore_response.any_request.l2_hit_this_tile_e cache Counts any request that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004008000 00 offcore_response.any_request.l2_hit_this_tile_f cache Counts any request that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010008000 00 offcore_response.any_request.l2_hit_this_tile_m cache Counts any request that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002008000 00 offcore_response.any_request.l2_hit_this_tile_s cache Counts any request that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008008000 00 offcore_response.any_request.l2_miss cache Accounts for responses which miss its own tile's L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x18001981F8 00 offcore_response.any_request.outstanding cache Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000008000 00 offcore_response.any_rfo.any_response cache Counts Demand cacheable data write requests that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010022 00 offcore_response.any_rfo.l2_hit_far_tile cache Counts Demand cacheable data write requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400022 00 offcore_response.any_rfo.l2_hit_far_tile_e_f cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400022 00 offcore_response.any_rfo.l2_hit_far_tile_m cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400022 00 offcore_response.any_rfo.l2_hit_near_tile cache Counts Demand cacheable data write requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180022 00 offcore_response.any_rfo.l2_hit_near_tile_e_f cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080022 00 offcore_response.any_rfo.l2_hit_near_tile_m cache Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080022 00 offcore_response.any_rfo.l2_hit_this_tile_e cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000022 00 offcore_response.any_rfo.l2_hit_this_tile_f cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000022 00 offcore_response.any_rfo.l2_hit_this_tile_m cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000022 00 offcore_response.any_rfo.l2_hit_this_tile_s cache Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000022 00 offcore_response.any_rfo.outstanding cache Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000022 00 offcore_response.bus_locks.any_response cache Counts Bus locks and split lock requests that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010400 00 offcore_response.bus_locks.l2_hit_far_tile cache Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400400 00 offcore_response.bus_locks.l2_hit_far_tile_e_f cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400400 00 offcore_response.bus_locks.l2_hit_far_tile_m cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400400 00 offcore_response.bus_locks.l2_hit_near_tile cache Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180400 00 offcore_response.bus_locks.l2_hit_near_tile_e_f cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080400 00 offcore_response.bus_locks.l2_hit_near_tile_m cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080400 00 offcore_response.bus_locks.l2_hit_this_tile_e cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000400 00 offcore_response.bus_locks.l2_hit_this_tile_f cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000400 00 offcore_response.bus_locks.l2_hit_this_tile_m cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000400 00 offcore_response.bus_locks.l2_hit_this_tile_s cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000400 00 offcore_response.bus_locks.outstanding cache Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000400 00 offcore_response.demand_code_rd.any_response cache Counts demand code reads and prefetch code reads that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010004 00 offcore_response.demand_code_rd.l2_hit_far_tile cache Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400004 00 offcore_response.demand_code_rd.l2_hit_far_tile_e_f cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400004 00 offcore_response.demand_code_rd.l2_hit_far_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400004 00 offcore_response.demand_code_rd.l2_hit_near_tile cache Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180004 00 offcore_response.demand_code_rd.l2_hit_near_tile_e_f cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080004 00 offcore_response.demand_code_rd.l2_hit_near_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080004 00 offcore_response.demand_code_rd.l2_hit_this_tile_e cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000004 00 offcore_response.demand_code_rd.l2_hit_this_tile_f cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000004 00 offcore_response.demand_code_rd.l2_hit_this_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000004 00 offcore_response.demand_code_rd.l2_hit_this_tile_s cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000004 00 offcore_response.demand_code_rd.outstanding cache Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000004 00 offcore_response.demand_data_rd.any_response cache Counts demand cacheable data and L1 prefetch data reads that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010001 00 offcore_response.demand_data_rd.l2_hit_far_tile_e_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400001 00 offcore_response.demand_data_rd.l2_hit_far_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400001 00 offcore_response.demand_data_rd.l2_hit_near_tile_e_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080001 00 offcore_response.demand_data_rd.l2_hit_near_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080001 00 offcore_response.demand_data_rd.l2_hit_this_tile_e cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000001 00 offcore_response.demand_data_rd.l2_hit_this_tile_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000001 00 offcore_response.demand_data_rd.l2_hit_this_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000001 00 offcore_response.demand_data_rd.l2_hit_this_tile_s cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000001 00 offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000001 00 offcore_response.demand_rfo.any_response cache Counts Demand cacheable data writes that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010002 00 offcore_response.demand_rfo.l2_hit_far_tile cache Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400002 00 offcore_response.demand_rfo.l2_hit_far_tile_e_f cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400002 00 offcore_response.demand_rfo.l2_hit_far_tile_m cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400002 00 offcore_response.demand_rfo.l2_hit_near_tile cache Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180002 00 offcore_response.demand_rfo.l2_hit_near_tile_e_f cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080002 00 offcore_response.demand_rfo.l2_hit_near_tile_m cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080002 00 offcore_response.demand_rfo.l2_hit_this_tile_e cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000002 00 offcore_response.demand_rfo.l2_hit_this_tile_f cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000002 00 offcore_response.demand_rfo.l2_hit_this_tile_m cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000002 00 offcore_response.demand_rfo.l2_hit_this_tile_s cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000002 00 offcore_response.demand_rfo.outstanding cache Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000002 00 offcore_response.full_streaming_stores.any_response cache Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010800 00 offcore_response.partial_reads.any_response cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010080 00 offcore_response.partial_reads.l2_hit_far_tile cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400080 00 offcore_response.partial_reads.l2_hit_far_tile_e_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400080 00 offcore_response.partial_reads.l2_hit_far_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400080 00 offcore_response.partial_reads.l2_hit_near_tile cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180080 00 offcore_response.partial_reads.l2_hit_near_tile_e_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080080 00 offcore_response.partial_reads.l2_hit_near_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080080 00 offcore_response.partial_reads.l2_hit_this_tile_e cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000080 00 offcore_response.partial_reads.l2_hit_this_tile_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000080 00 offcore_response.partial_reads.l2_hit_this_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000080 00 offcore_response.partial_reads.l2_hit_this_tile_s cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000080 00 offcore_response.partial_reads.outstanding cache Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000080 00 offcore_response.partial_streaming_stores.any_response cache Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000014000 00 offcore_response.partial_writes.any_response cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010100 00 offcore_response.partial_writes.l2_hit_far_tile cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400100 00 offcore_response.partial_writes.l2_hit_far_tile_e_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400100 00 offcore_response.partial_writes.l2_hit_far_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400100 00 offcore_response.partial_writes.l2_hit_near_tile cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180100 00 offcore_response.partial_writes.l2_hit_near_tile_e_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080100 00 offcore_response.partial_writes.l2_hit_near_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080100 00 offcore_response.partial_writes.l2_hit_this_tile_e cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000100 00 offcore_response.partial_writes.l2_hit_this_tile_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000100 00 offcore_response.partial_writes.l2_hit_this_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000100 00 offcore_response.partial_writes.l2_hit_this_tile_s cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000100 00 offcore_response.pf_l1_data_rd.any_response cache Counts L1 data HW prefetches that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000012000 00 offcore_response.pf_l1_data_rd.l2_hit_far_tile cache Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800402000 00 offcore_response.pf_l1_data_rd.l2_hit_far_tile_e_f cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800402000 00 offcore_response.pf_l1_data_rd.l2_hit_far_tile_m cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000402000 00 offcore_response.pf_l1_data_rd.l2_hit_near_tile cache Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800182000 00 offcore_response.pf_l1_data_rd.l2_hit_near_tile_e_f cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800082000 00 offcore_response.pf_l1_data_rd.l2_hit_near_tile_m cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000082000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_e cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004002000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_f cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010002000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_m cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002002000 00 offcore_response.pf_l1_data_rd.l2_hit_this_tile_s cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008002000 00 offcore_response.pf_l1_data_rd.outstanding cache Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000002000 00 offcore_response.pf_l2_code_rd.any_response cache Counts L2 code HW prefetches that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010040 00 offcore_response.pf_l2_code_rd.l2_hit_far_tile cache Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400040 00 offcore_response.pf_l2_code_rd.l2_hit_far_tile_e_f cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400040 00 offcore_response.pf_l2_code_rd.l2_hit_far_tile_m cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400040 00 offcore_response.pf_l2_code_rd.l2_hit_near_tile cache Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180040 00 offcore_response.pf_l2_code_rd.l2_hit_near_tile_e_f cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080040 00 offcore_response.pf_l2_code_rd.l2_hit_near_tile_m cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080040 00 offcore_response.pf_l2_code_rd.l2_hit_this_tile_e cache Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000040 00 offcore_response.pf_l2_code_rd.l2_hit_this_tile_f cache Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000040 00 offcore_response.pf_l2_code_rd.outstanding cache Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000040 00 offcore_response.pf_l2_rfo.any_response cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010020 00 offcore_response.pf_l2_rfo.l2_hit_far_tile_e_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400020 00 offcore_response.pf_l2_rfo.l2_hit_far_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400020 00 offcore_response.pf_l2_rfo.l2_hit_near_tile cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180020 00 offcore_response.pf_l2_rfo.l2_hit_near_tile_e_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080020 00 offcore_response.pf_l2_rfo.l2_hit_near_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_e cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000020 00 offcore_response.pf_l2_rfo.l2_hit_this_tile_s cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000020 00 offcore_response.pf_software.any_response cache Counts Software Prefetches that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000011000 00 offcore_response.pf_software.l2_hit_far_tile cache Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800401000 00 offcore_response.pf_software.l2_hit_far_tile_e_f cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800401000 00 offcore_response.pf_software.l2_hit_far_tile_m cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000401000 00 offcore_response.pf_software.l2_hit_near_tile cache Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800181000 00 offcore_response.pf_software.l2_hit_near_tile_e_f cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800081000 00 offcore_response.pf_software.l2_hit_near_tile_m cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000081000 00 offcore_response.pf_software.l2_hit_this_tile_e cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004001000 00 offcore_response.pf_software.l2_hit_this_tile_f cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010001000 00 offcore_response.pf_software.l2_hit_this_tile_m cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002001000 00 offcore_response.pf_software.l2_hit_this_tile_s cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008001000 00 offcore_response.pf_software.outstanding cache Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000001000 00 offcore_response.streaming_stores.any_response cache Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000014800 00 offcore_response.uc_code_reads.any_response cache Counts UC code reads (valid only for Outstanding response type) that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010200 00 offcore_response.uc_code_reads.l2_hit_far_tile_e_f cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400200 00 offcore_response.uc_code_reads.l2_hit_far_tile_m cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400200 00 offcore_response.uc_code_reads.l2_hit_near_tile cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180200 00 offcore_response.uc_code_reads.l2_hit_near_tile_e_f cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080200 00 offcore_response.uc_code_reads.l2_hit_near_tile_m cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080200 00 offcore_response.uc_code_reads.l2_hit_this_tile_e cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000200 00 offcore_response.uc_code_reads.l2_hit_this_tile_f cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000200 00 offcore_response.uc_code_reads.l2_hit_this_tile_m cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000200 00 offcore_response.uc_code_reads.l2_hit_this_tile_s cache Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000200 00 offcore_response.uc_code_reads.outstanding cache Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000200 00 machine_clears.fp_assist floating point Counts the number of floating operations retired that required microcode assists event=0xc3,period=200003,umask=0x4 00 This event counts the number of times that the pipeline stalled due to FP operations needing assists uops_retired.packed_simd floating point Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies event=0xc2,period=200003,umask=0x40 00 The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). Mask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1) This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all uops_retired.scalar_simd floating point Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt event=0xc2,period=200003,umask=0x20 00 This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all baclears.all frontend Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=0x1 00 baclears.cond frontend Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=0x10 00 baclears.return frontend Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=0x8 00 icache.accesses frontend Counts all instruction fetches, including uncacheable fetches event=0x80,period=200003,umask=0x3 00 icache.hit frontend Counts all instruction fetches that hit the instruction cache event=0x80,period=200003,umask=0x1 00 icache.misses frontend Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding event=0x80,period=200003,umask=0x2 00 ms_decoded.ms_entry frontend Counts the number of times the MSROM starts a flow of uops event=0xe7,period=200003,umask=0x1 00 machine_clears.memory_ordering memory Counts the number of times the machine clears due to memory ordering hazards event=0xc3,period=200003,umask=0x2 00 offcore_response.any_code_rd.ddr memory Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800044 00 offcore_response.any_code_rd.ddr_far memory Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000044 00 offcore_response.any_code_rd.ddr_near memory Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800044 00 offcore_response.any_code_rd.mcdram memory Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600044 00 offcore_response.any_code_rd.mcdram_far memory Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400044 00 offcore_response.any_code_rd.mcdram_near memory Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200044 00 offcore_response.any_data_rd.ddr memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181803091 00 offcore_response.any_data_rd.ddr_far memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101003091 00 offcore_response.any_data_rd.ddr_near memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080803091 00 offcore_response.any_data_rd.mcdram memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180603091 00 offcore_response.any_data_rd.mcdram_far memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100403091 00 offcore_response.any_data_rd.mcdram_near memory Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080203091 00 offcore_response.any_pf_l2.ddr_far memory Counts any Prefetch requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000070 00 offcore_response.any_pf_l2.ddr_near memory Counts any Prefetch requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800070 00 offcore_response.any_pf_l2.mcdram memory Counts any Prefetch requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600070 00 offcore_response.any_pf_l2.mcdram_far memory Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400070 00 offcore_response.any_pf_l2.mcdram_near memory Counts any Prefetch requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200070 00 offcore_response.any_read.ddr memory Counts any Read request that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01818032f7 00 offcore_response.any_read.ddr_far memory Counts any Read request that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01010032f7 00 offcore_response.any_read.ddr_near memory Counts any Read request that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00808032f7 00 offcore_response.any_read.mcdram memory Counts any Read request that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01806032f7 00 offcore_response.any_read.mcdram_far memory Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01004032f7 00 offcore_response.any_read.mcdram_near memory Counts any Read request that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00802032f7 00 offcore_response.any_request.ddr memory Counts any request that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181808000 00 offcore_response.any_request.ddr_far memory Counts any request that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101008000 00 offcore_response.any_request.ddr_near memory Counts any request that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080808000 00 offcore_response.any_request.mcdram memory Counts any request that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180608000 00 offcore_response.any_request.mcdram_far memory Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100408000 00 offcore_response.any_request.mcdram_near memory Counts any request that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080208000 00 offcore_response.any_rfo.ddr memory Counts Demand cacheable data write requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800022 00 offcore_response.any_rfo.ddr_far memory Counts Demand cacheable data write requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000022 00 offcore_response.any_rfo.ddr_near memory Counts Demand cacheable data write requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800022 00 offcore_response.any_rfo.mcdram memory Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600022 00 offcore_response.any_rfo.mcdram_far memory Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400022 00 offcore_response.any_rfo.mcdram_near memory Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200022 00 offcore_response.bus_locks.ddr memory Counts Bus locks and split lock requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800400 00 offcore_response.bus_locks.ddr_far memory Counts Bus locks and split lock requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000400 00 offcore_response.bus_locks.ddr_near memory Counts Bus locks and split lock requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800400 00 offcore_response.bus_locks.mcdram memory Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600400 00 offcore_response.bus_locks.mcdram_far memory Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400400 00 offcore_response.bus_locks.mcdram_near memory Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200400 00 offcore_response.demand_code_rd.ddr memory Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800004 00 offcore_response.demand_code_rd.ddr_far memory Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000004 00 offcore_response.demand_code_rd.ddr_near memory Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800004 00 offcore_response.demand_code_rd.mcdram memory Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600004 00 offcore_response.demand_code_rd.mcdram_far memory Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400004 00 offcore_response.demand_code_rd.mcdram_near memory Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200004 00 offcore_response.demand_data_rd.ddr memory Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800001 00 offcore_response.demand_data_rd.ddr_far memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000001 00 offcore_response.demand_data_rd.ddr_near memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800001 00 offcore_response.demand_data_rd.mcdram memory Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600001 00 offcore_response.demand_data_rd.mcdram_far memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400001 00 offcore_response.demand_data_rd.mcdram_near memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200001 00 offcore_response.demand_rfo.ddr memory Counts Demand cacheable data writes that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800002 00 offcore_response.demand_rfo.ddr_far memory Counts Demand cacheable data writes that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000002 00 offcore_response.demand_rfo.ddr_near memory Counts Demand cacheable data writes that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800002 00 offcore_response.demand_rfo.mcdram memory Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600002 00 offcore_response.demand_rfo.mcdram_far memory Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400002 00 offcore_response.demand_rfo.mcdram_near memory Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200002 00 offcore_response.partial_reads.ddr memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800080 00 offcore_response.partial_reads.ddr_far memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000080 00 offcore_response.partial_reads.ddr_near memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800080 00 offcore_response.partial_reads.mcdram memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600080 00 offcore_response.partial_reads.mcdram_far memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400080 00 offcore_response.partial_reads.mcdram_near memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200080 00 offcore_response.partial_reads.non_dram memory Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions event=0xb7,period=100007,umask=0x1,offcore_rsp=0x2000020080 00 offcore_response.partial_writes.ddr_far memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000100 00 offcore_response.partial_writes.ddr_near memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800100 00 offcore_response.partial_writes.mcdram memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600100 00 offcore_response.partial_writes.mcdram_far memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400100 00 offcore_response.partial_writes.mcdram_near memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200100 00 offcore_response.pf_l1_data_rd.ddr memory Counts L1 data HW prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181802000 00 offcore_response.pf_l1_data_rd.ddr_far memory Counts L1 data HW prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101002000 00 offcore_response.pf_l1_data_rd.ddr_near memory Counts L1 data HW prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080802000 00 offcore_response.pf_l1_data_rd.mcdram_far memory Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100402000 00 offcore_response.pf_l1_data_rd.mcdram_near memory Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080202000 00 offcore_response.pf_l2_code_rd.ddr memory Counts L2 code HW prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800040 00 offcore_response.pf_l2_code_rd.ddr_far memory Counts L2 code HW prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000040 00 offcore_response.pf_l2_code_rd.ddr_near memory Counts L2 code HW prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800040 00 offcore_response.pf_l2_code_rd.mcdram_far memory Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400040 00 offcore_response.pf_l2_code_rd.mcdram_near memory Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200040 00 offcore_response.pf_l2_rfo.ddr memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800020 00 offcore_response.pf_l2_rfo.ddr_far memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000020 00 offcore_response.pf_l2_rfo.ddr_near memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800020 00 offcore_response.pf_l2_rfo.mcdram memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600020 00 offcore_response.pf_l2_rfo.mcdram_far memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400020 00 offcore_response.pf_l2_rfo.mcdram_near memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200020 00 offcore_response.pf_l2_rfo.non_dram memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions event=0xb7,period=100007,umask=0x1,offcore_rsp=0x2000020020 00 offcore_response.pf_software.ddr memory Counts Software Prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181801000 00 offcore_response.pf_software.ddr_far memory Counts Software Prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101001000 00 offcore_response.pf_software.ddr_near memory Counts Software Prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080801000 00 offcore_response.pf_software.mcdram memory Counts Software Prefetches that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180601000 00 offcore_response.pf_software.mcdram_far memory Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100401000 00 offcore_response.pf_software.mcdram_near memory Counts Software Prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080201000 00 offcore_response.uc_code_reads.ddr memory Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800200 00 offcore_response.uc_code_reads.ddr_far memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000200 00 offcore_response.uc_code_reads.ddr_near memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800200 00 offcore_response.uc_code_reads.mcdram memory Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600200 00 offcore_response.uc_code_reads.mcdram_far memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400200 00 offcore_response.uc_code_reads.mcdram_near memory Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200200 00 br_inst_retired.all_branches pipeline Counts the number of branch instructions retired (Precise Event) event=0xc4,period=200003 00 br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xf9 00 br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xbf 00 br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xfb 00 br_inst_retired.jcc pipeline Counts the number of branch instructions retired that were conditional jumps. (Precise Event) event=0xc4,period=200003,umask=0x7e 00 br_inst_retired.non_return_ind pipeline Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event) event=0xc4,period=200003,umask=0xeb 00 br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xfd 00 br_inst_retired.return pipeline Counts the number of near RET branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xf7 00 br_inst_retired.taken_jcc pipeline Counts the number of branch instructions retired that were conditional jumps and predicted taken. (Precise Event) event=0xc4,period=200003,umask=0xfe 00 br_misp_retired.all_branches pipeline Counts the number of mispredicted branch instructions retired (Precise Event) event=0xc5,period=200003 00 br_misp_retired.call pipeline Counts the number of mispredicted near CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xf9 00 br_misp_retired.far_branch pipeline Counts the number of mispredicted far branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xbf 00 br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xfb 00 br_misp_retired.jcc pipeline Counts the number of mispredicted branch instructions retired that were conditional jumps. (Precise Event) event=0xc5,period=200003,umask=0x7e 00 br_misp_retired.non_return_ind pipeline Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event) event=0xc5,period=200003,umask=0xeb 00 br_misp_retired.rel_call pipeline Counts the number of mispredicted near relative CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xfd 00 br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xf7 00 br_misp_retired.taken_jcc pipeline Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken. (Precise Event) event=0xc5,period=200003,umask=0xfe 00 cpu_clk_unhalted.ref pipeline Counts the number of unhalted reference clock cycles event=0x0,umask=0x03,period=2000003 00 cpu_clk_unhalted.thread pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 cycles_div_busy.all pipeline Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider event=0xcd,period=2000003,umask=0x1 00 This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003 00 This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps inst_retired.any_p pipeline Counts the total number of instructions retired event=0xc0,period=2000003 00 inst_retired.any_ps pipeline Counts the number of instructions retired (Precise Event) event=0xc0,period=2000003 00 machine_clears.all pipeline Counts all machine clears event=0xc3,period=200003,umask=0x8 00 machine_clears.smc pipeline Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page event=0xc3,period=200003,umask=0x1 00 no_alloc_cycles.all pipeline Counts the total number of core cycles when no micro-ops are allocated for any reason event=0xca,period=200003,umask=0x7f 00 no_alloc_cycles.mispredicts pipeline Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire event=0xca,period=200003,umask=0x4 00 This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire no_alloc_cycles.not_delivered pipeline Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation event=0xca,period=200003,umask=0x90 00 This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched no_alloc_cycles.rat_stall pipeline Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted event=0xca,period=200003,umask=0x20 00 no_alloc_cycles.rob_full pipeline Counts the number of core cycles when no micro-ops are allocated and the ROB is full event=0xca,period=200003,umask=0x1 00 recycleq.any_ld pipeline Counts any retired load that was pushed into the recycle queue for any reason event=0x3,period=200003,umask=0x40 00 recycleq.any_st pipeline Counts any retired store that was pushed into the recycle queue for any reason event=0x3,period=200003,umask=0x80 00 recycleq.ld_block_std_notready pipeline Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready event=0x3,period=200003,umask=0x2 00 recycleq.ld_block_st_forward pipeline Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store (Precise Event) Supports address when precise event=0x3,period=200003,umask=0x1 00 This event counts the number of retired loads that were prohibited from receiving forwarded data from a previous store because of address mismatch Supports address when precise recycleq.ld_splits pipeline Counts the number of occurrences a retired load was pushed into the rehab queue because it sees a cache line split. Each split should be counted only once. (Precise Event) Supports address when precise event=0x3,period=200003,umask=0x8 00 This event counts the number of retired loads which was pushed into the recycled queue that experienced cache line boundary splits (Precise event). Not that each split should be counted only once Supports address when precise recycleq.lock pipeline Counts all the retired locked loads. It does not include stores because we would double count if we count stores event=0x3,period=200003,umask=0x10 00 recycleq.sta_full pipeline Counts the store micro-ops retired that were pushed in the rehab queue because the store address buffer is full event=0x3,period=200003,umask=0x20 00 recycleq.st_splits pipeline Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once event=0x3,period=200003,umask=0x4 00 This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once rs_full_stall.all pipeline Counts the total number of core cycles allocation pipeline is stalled when any one of the reservation stations is full event=0xcb,period=200003,umask=0x1f 00 rs_full_stall.mec pipeline Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry event=0xcb,period=200003,umask=0x1 00 uops_retired.all pipeline Counts the number of micro-ops retired event=0xc2,period=2000003,umask=0x10 00 This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists uops_retired.ms pipeline Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS) event=0xc2,period=2000003,umask=0x1 00 This event counts the number of micro-ops retired that were supplied from MSROM unc_c_tor_inserts.ipq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ event=0x35,umask=0x18 01 unc_c_tor_inserts.ipq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ event=0x35,umask=0x28 01 unc_c_tor_inserts.irq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ event=0x35,umask=0x11 01 unc_c_tor_inserts.irq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ event=0x35,umask=0x21 01 unc_c_tor_inserts.loc_all uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ event=0x35,umask=0x37 01 unc_c_tor_inserts.prq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ event=0x35,umask=0x14 01 unc_c_tor_inserts.prq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ event=0x35,umask=0x24 01 unc_h_ag0_ad_crd_acquired.tgr0 uncore cache CMS Agent0 AD Credits Acquired For Transgress 0 event=0x80,umask=0x1 01 unc_h_ag0_ad_crd_acquired.tgr1 uncore cache CMS Agent0 AD Credits Acquired For Transgress 1 event=0x80,umask=0x2 01 unc_h_ag0_ad_crd_acquired.tgr2 uncore cache CMS Agent0 AD Credits Acquired For Transgress 2 event=0x80,umask=0x4 01 unc_h_ag0_ad_crd_acquired.tgr3 uncore cache CMS Agent0 AD Credits Acquired For Transgress 3 event=0x80,umask=0x8 01 unc_h_ag0_ad_crd_acquired.tgr4 uncore cache CMS Agent0 AD Credits Acquired For Transgress 4 event=0x80,umask=0x10 01 unc_h_ag0_ad_crd_acquired.tgr5 uncore cache CMS Agent0 AD Credits Acquired For Transgress 5 event=0x80,umask=0x20 01 unc_h_ag0_ad_crd_acquired.tgr6 uncore cache CMS Agent0 AD Credits Acquired For Transgress 6 event=0x80,umask=0x40 01 unc_h_ag0_ad_crd_acquired.tgr7 uncore cache CMS Agent0 AD Credits Acquired For Transgress 7 event=0x80,umask=0x80 01 unc_h_ag0_ad_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 AD Credits Acquired For Transgress 0-7 event=0x81,umask=0x2 01 unc_h_ag0_ad_crd_acquired_ext.tgr8 uncore cache CMS Agent0 AD Credits Acquired For Transgress 8 event=0x81,umask=0x1 01 unc_h_ag0_ad_crd_occupancy.tgr0 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 0 event=0x82,umask=0x1 01 unc_h_ag0_ad_crd_occupancy.tgr1 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 1 event=0x82,umask=0x2 01 unc_h_ag0_ad_crd_occupancy.tgr2 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 2 event=0x82,umask=0x4 01 unc_h_ag0_ad_crd_occupancy.tgr3 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 3 event=0x82,umask=0x8 01 unc_h_ag0_ad_crd_occupancy.tgr4 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 4 event=0x82,umask=0x10 01 unc_h_ag0_ad_crd_occupancy.tgr5 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 5 event=0x82,umask=0x20 01 unc_h_ag0_ad_crd_occupancy.tgr6 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 6 event=0x82,umask=0x40 01 unc_h_ag0_ad_crd_occupancy.tgr7 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 7 event=0x82,umask=0x80 01 unc_h_ag0_ad_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 0-7 event=0x83,umask=0x2 01 unc_h_ag0_ad_crd_occupancy_ext.tgr8 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 8 event=0x83,umask=0x1 01 unc_h_ag0_bl_crd_acquired.tgr0 uncore cache CMS Agent0 BL Credits Acquired For Transgress 0 event=0x88,umask=0x1 01 unc_h_ag0_bl_crd_acquired.tgr1 uncore cache CMS Agent0 BL Credits Acquired For Transgress 1 event=0x88,umask=0x2 01 unc_h_ag0_bl_crd_acquired.tgr2 uncore cache CMS Agent0 BL Credits Acquired For Transgress 2 event=0x88,umask=0x4 01 unc_h_ag0_bl_crd_acquired.tgr3 uncore cache CMS Agent0 BL Credits Acquired For Transgress 3 event=0x88,umask=0x8 01 unc_h_ag0_bl_crd_acquired.tgr4 uncore cache CMS Agent0 BL Credits Acquired For Transgress 4 event=0x88,umask=0x10 01 unc_h_ag0_bl_crd_acquired.tgr5 uncore cache CMS Agent0 BL Credits Acquired For Transgress 5 event=0x88,umask=0x20 01 unc_h_ag0_bl_crd_acquired.tgr6 uncore cache CMS Agent0 BL Credits Acquired For Transgress 6 event=0x88,umask=0x40 01 unc_h_ag0_bl_crd_acquired.tgr7 uncore cache CMS Agent0 BL Credits Acquired For Transgress 7 event=0x88,umask=0x80 01 unc_h_ag0_bl_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 BL Credits Acquired For Transgress 0-7 event=0x89,umask=0x2 01 unc_h_ag0_bl_crd_acquired_ext.tgr8 uncore cache CMS Agent0 BL Credits Acquired For Transgress 8 event=0x89,umask=0x1 01 unc_h_ag0_bl_crd_occupancy.tgr0 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 0 event=0x8a,umask=0x1 01 unc_h_ag0_bl_crd_occupancy.tgr1 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 1 event=0x8a,umask=0x2 01 unc_h_ag0_bl_crd_occupancy.tgr2 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 2 event=0x8a,umask=0x4 01 unc_h_ag0_bl_crd_occupancy.tgr3 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 3 event=0x8a,umask=0x8 01 unc_h_ag0_bl_crd_occupancy.tgr4 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 4 event=0x8a,umask=0x10 01 unc_h_ag0_bl_crd_occupancy.tgr5 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 5 event=0x8a,umask=0x20 01 unc_h_ag0_bl_crd_occupancy.tgr6 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 6 event=0x8a,umask=0x40 01 unc_h_ag0_bl_crd_occupancy.tgr7 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 7 event=0x8a,umask=0x80 01 unc_h_ag0_bl_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 0-7 event=0x8b,umask=0x2 01 unc_h_ag0_bl_crd_occupancy_ext.tgr8 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 8 event=0x8b,umask=0x1 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd0,umask=0x1 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd0,umask=0x2 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd0,umask=0x4 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd0,umask=0x8 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd0,umask=0x10 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd0,umask=0x20 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd0,umask=0x40 01 unc_h_ag0_stall_no_crd_egress_horz_ad.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd0,umask=0x80 01 unc_h_ag0_stall_no_crd_egress_horz_ad_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd1,umask=0x2 01 unc_h_ag0_stall_no_crd_egress_horz_ad_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd1,umask=0x1 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd4,umask=0x1 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd4,umask=0x2 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd4,umask=0x4 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd4,umask=0x8 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd4,umask=0x10 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd4,umask=0x20 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd4,umask=0x40 01 unc_h_ag0_stall_no_crd_egress_horz_bl.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd4,umask=0x80 01 unc_h_ag0_stall_no_crd_egress_horz_bl_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd5,umask=0x2 01 unc_h_ag0_stall_no_crd_egress_horz_bl_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd5,umask=0x1 01 unc_h_ag1_ad_crd_acquired.tgr0 uncore cache CMS Agent1 AD Credits Acquired For Transgress 0 event=0x84,umask=0x1 01 unc_h_ag1_ad_crd_acquired.tgr1 uncore cache CMS Agent1 AD Credits Acquired For Transgress 1 event=0x84,umask=0x2 01 unc_h_ag1_ad_crd_acquired.tgr2 uncore cache CMS Agent1 AD Credits Acquired For Transgress 2 event=0x84,umask=0x4 01 unc_h_ag1_ad_crd_acquired.tgr3 uncore cache CMS Agent1 AD Credits Acquired For Transgress 3 event=0x84,umask=0x8 01 unc_h_ag1_ad_crd_acquired.tgr4 uncore cache CMS Agent1 AD Credits Acquired For Transgress 4 event=0x84,umask=0x10 01 unc_h_ag1_ad_crd_acquired.tgr5 uncore cache CMS Agent1 AD Credits Acquired For Transgress 5 event=0x84,umask=0x20 01 unc_h_ag1_ad_crd_acquired.tgr6 uncore cache CMS Agent1 AD Credits Acquired For Transgress 6 event=0x84,umask=0x40 01 unc_h_ag1_ad_crd_acquired.tgr7 uncore cache CMS Agent1 AD Credits Acquired For Transgress 7 event=0x84,umask=0x80 01 unc_h_ag1_ad_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 AD Credits Acquired For Transgress 0-7 event=0x85,umask=0x2 01 unc_h_ag1_ad_crd_acquired_ext.tgr8 uncore cache CMS Agent1 AD Credits Acquired For Transgress 8 event=0x85,umask=0x1 01 unc_h_ag1_ad_crd_occupancy.tgr0 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 0 event=0x86,umask=0x1 01 unc_h_ag1_ad_crd_occupancy.tgr1 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 1 event=0x86,umask=0x2 01 unc_h_ag1_ad_crd_occupancy.tgr2 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 2 event=0x86,umask=0x4 01 unc_h_ag1_ad_crd_occupancy.tgr3 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 3 event=0x86,umask=0x8 01 unc_h_ag1_ad_crd_occupancy.tgr4 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 4 event=0x86,umask=0x10 01 unc_h_ag1_ad_crd_occupancy.tgr5 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 5 event=0x86,umask=0x20 01 unc_h_ag1_ad_crd_occupancy.tgr6 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 6 event=0x86,umask=0x40 01 unc_h_ag1_ad_crd_occupancy.tgr7 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 7 event=0x86,umask=0x80 01 unc_h_ag1_ad_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 0-7 event=0x87,umask=0x2 01 unc_h_ag1_ad_crd_occupancy_ext.tgr8 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 8 event=0x87,umask=0x1 01 unc_h_ag1_bl_crd_acquired.tgr0 uncore cache CMS Agent1 BL Credits Acquired For Transgress 0 event=0x8c,umask=0x1 01 unc_h_ag1_bl_crd_acquired.tgr1 uncore cache CMS Agent1 BL Credits Acquired For Transgress 1 event=0x8c,umask=0x2 01 unc_h_ag1_bl_crd_acquired.tgr2 uncore cache CMS Agent1 BL Credits Acquired For Transgress 2 event=0x8c,umask=0x4 01 unc_h_ag1_bl_crd_acquired.tgr3 uncore cache CMS Agent1 BL Credits Acquired For Transgress 3 event=0x8c,umask=0x8 01 unc_h_ag1_bl_crd_acquired.tgr4 uncore cache CMS Agent1 BL Credits Acquired For Transgress 4 event=0x8c,umask=0x10 01 unc_h_ag1_bl_crd_acquired.tgr5 uncore cache CMS Agent1 BL Credits Acquired For Transgress 5 event=0x8c,umask=0x20 01 unc_h_ag1_bl_crd_acquired.tgr6 uncore cache CMS Agent1 BL Credits Acquired For Transgress 6 event=0x8c,umask=0x40 01 unc_h_ag1_bl_crd_acquired.tgr7 uncore cache CMS Agent1 BL Credits Acquired For Transgress 7 event=0x8c,umask=0x80 01 unc_h_ag1_bl_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 BL Credits Acquired For Transgress 0-7 event=0x8d,umask=0x2 01 unc_h_ag1_bl_crd_acquired_ext.tgr8 uncore cache CMS Agent1 BL Credits Acquired For Transgress 8 event=0x8d,umask=0x1 01 unc_h_ag1_bl_crd_occupancy.tgr0 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 0 event=0x8e,umask=0x1 01 unc_h_ag1_bl_crd_occupancy.tgr1 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 1 event=0x8e,umask=0x2 01 unc_h_ag1_bl_crd_occupancy.tgr2 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 2 event=0x8e,umask=0x4 01 unc_h_ag1_bl_crd_occupancy.tgr3 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 3 event=0x8e,umask=0x8 01 unc_h_ag1_bl_crd_occupancy.tgr4 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 4 event=0x8e,umask=0x10 01 unc_h_ag1_bl_crd_occupancy.tgr5 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 5 event=0x8e,umask=0x20 01 unc_h_ag1_bl_crd_occupancy.tgr6 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 6 event=0x8e,umask=0x40 01 unc_h_ag1_bl_crd_occupancy.tgr7 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 7 event=0x8e,umask=0x80 01 unc_h_ag1_bl_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 0-7 event=0x8f,umask=0x2 01 unc_h_ag1_bl_crd_occupancy_ext.tgr8 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 8 event=0x8f,umask=0x1 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd2,umask=0x1 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd2,umask=0x2 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd2,umask=0x4 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd2,umask=0x8 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd2,umask=0x10 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd2,umask=0x20 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd2,umask=0x40 01 unc_h_ag1_stall_no_crd_egress_horz_ad.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd2,umask=0x80 01 unc_h_ag1_stall_no_crd_egress_horz_ad_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd3,umask=0x2 01 unc_h_ag1_stall_no_crd_egress_horz_ad_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd3,umask=0x1 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd6,umask=0x1 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd6,umask=0x2 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd6,umask=0x4 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd6,umask=0x8 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd6,umask=0x10 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd6,umask=0x20 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd6,umask=0x40 01 unc_h_ag1_stall_no_crd_egress_horz_bl.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd6,umask=0x80 01 unc_h_ag1_stall_no_crd_egress_horz_bl_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd7,umask=0x2 01 unc_h_ag1_stall_no_crd_egress_horz_bl_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd7,umask=0x1 01 unc_h_cache_lines_victimized.e_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC event=0x37,umask=0x2 01 unc_h_cache_lines_victimized.f_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ event=0x37,umask=0x8 01 unc_h_cache_lines_victimized.local uncore cache Lines Victimized that Match NID event=0x37,umask=0x20 01 unc_h_cache_lines_victimized.m_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Read transactions event=0x37,umask=0x1 01 unc_h_cache_lines_victimized.remote uncore cache Lines Victimized that Does Not Match NID event=0x37,umask=0x80 01 unc_h_cache_lines_victimized.s_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ event=0x37,umask=0x4 01 unc_h_clock uncore cache Uncore Clocks event=0xc0 01 unc_h_egress_horz_ads_used.ad uncore cache CMS Horizontal ADS Used event=0x9d,umask=0x1 01 unc_h_egress_horz_ads_used.ak uncore cache CMS Horizontal ADS Used event=0x9d,umask=0x2 01 unc_h_egress_horz_ads_used.bl uncore cache CMS Horizontal ADS Used event=0x9d,umask=0x4 01 unc_h_egress_horz_bypass.ad uncore cache CMS Horizontal Egress Bypass. AD ring event=0x9f,umask=0x1 01 unc_h_egress_horz_bypass.ak uncore cache CMS Horizontal Egress Bypass. AK ring event=0x9f,umask=0x2 01 unc_h_egress_horz_bypass.bl uncore cache CMS Horizontal Egress Bypass. BL ring event=0x9f,umask=0x4 01 unc_h_egress_horz_bypass.iv uncore cache CMS Horizontal Egress Bypass. IV ring event=0x9f,umask=0x8 01 unc_h_egress_horz_cycles_full.ad uncore cache Cycles CMS Horizontal Egress Queue is Full AD event=0x96,umask=0x1 01 unc_h_egress_horz_cycles_full.ak uncore cache Cycles CMS Horizontal Egress Queue is Full AK event=0x96,umask=0x2 01 unc_h_egress_horz_cycles_full.bl uncore cache Cycles CMS Horizontal Egress Queue is Full BL event=0x96,umask=0x4 01 unc_h_egress_horz_cycles_full.iv uncore cache Cycles CMS Horizontal Egress Queue is Full IV event=0x96,umask=0x8 01 unc_h_egress_horz_cycles_ne.ad uncore cache Cycles CMS Horizontal Egress Queue is Not Empty AD event=0x97,umask=0x1 01 unc_h_egress_horz_cycles_ne.ak uncore cache Cycles CMS Horizontal Egress Queue is Not Empty AK event=0x97,umask=0x2 01 unc_h_egress_horz_cycles_ne.bl uncore cache Cycles CMS Horizontal Egress Queue is Not Empty BL event=0x97,umask=0x4 01 unc_h_egress_horz_cycles_ne.iv uncore cache Cycles CMS Horizontal Egress Queue is Not Empty IV event=0x97,umask=0x8 01 unc_h_egress_horz_inserts.ad uncore cache CMS Horizontal Egress Inserts AD event=0x95,umask=0x1 01 unc_h_egress_horz_inserts.ak uncore cache CMS Horizontal Egress Inserts AK event=0x95,umask=0x2 01 unc_h_egress_horz_inserts.bl uncore cache CMS Horizontal Egress Inserts BL event=0x95,umask=0x4 01 unc_h_egress_horz_inserts.iv uncore cache CMS Horizontal Egress Inserts IV event=0x95,umask=0x8 01 unc_h_egress_horz_nack.ad uncore cache CMS Horizontal Egress NACKs event=0x99,umask=0x1 01 unc_h_egress_horz_nack.ak uncore cache CMS Horizontal Egress NACKs event=0x99,umask=0x2 01 unc_h_egress_horz_nack.bl uncore cache CMS Horizontal Egress NACKs event=0x99,umask=0x4 01 unc_h_egress_horz_nack.iv uncore cache CMS Horizontal Egress NACKs event=0x99,umask=0x8 01 unc_h_egress_horz_occupancy.ad uncore cache CMS Horizontal Egress Occupancy AD event=0x94,umask=0x1 01 unc_h_egress_horz_occupancy.ak uncore cache CMS Horizontal Egress Occupancy AK event=0x94,umask=0x2 01 unc_h_egress_horz_occupancy.bl uncore cache CMS Horizontal Egress Occupancy BL event=0x94,umask=0x4 01 unc_h_egress_horz_occupancy.iv uncore cache CMS Horizontal Egress Occupancy IV event=0x94,umask=0x8 01 unc_h_egress_horz_starved.ad uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=0x1 01 unc_h_egress_horz_starved.ak uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=0x2 01 unc_h_egress_horz_starved.bl uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=0x4 01 unc_h_egress_horz_starved.iv uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=0x8 01 unc_h_egress_ordering.iv_snp_go_dn uncore cache Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements event=0xae,umask=0x4 01 unc_h_egress_ordering.iv_snp_go_up uncore cache Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements event=0xae,umask=0x1 01 unc_h_egress_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x1 01 unc_h_egress_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x10 01 unc_h_egress_vert_ads_used.ak_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x2 01 unc_h_egress_vert_ads_used.ak_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x20 01 unc_h_egress_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x4 01 unc_h_egress_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x40 01 unc_h_egress_vert_bypass.ad_ag0 uncore cache CMS Vertical Egress Bypass. AD ring agent 0 event=0x9e,umask=0x1 01 unc_h_egress_vert_bypass.ad_ag1 uncore cache CMS Vertical Egress Bypass. AD ring agent 1 event=0x9e,umask=0x10 01 unc_h_egress_vert_bypass.ak_ag0 uncore cache CMS Vertical Egress Bypass. AK ring agent 0 event=0x9e,umask=0x2 01 unc_h_egress_vert_bypass.ak_ag1 uncore cache CMS Vertical Egress Bypass. AK ring agent 1 event=0x9e,umask=0x20 01 unc_h_egress_vert_bypass.bl_ag0 uncore cache CMS Vertical Egress Bypass. BL ring agent 0 event=0x9e,umask=0x4 01 unc_h_egress_vert_bypass.bl_ag1 uncore cache CMS Vertical Egress Bypass. BL ring agent 1 event=0x9e,umask=0x40 01 unc_h_egress_vert_bypass.iv uncore cache CMS Vertical Egress Bypass. IV ring agent 0 event=0x9e,umask=0x8 01 unc_h_egress_vert_cycles_full.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full AD - Agent 0 event=0x92,umask=0x1 01 unc_h_egress_vert_cycles_full.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full AD - Agent 1 event=0x92,umask=0x10 01 unc_h_egress_vert_cycles_full.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full AK - Agent 0 event=0x92,umask=0x2 01 unc_h_egress_vert_cycles_full.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full AK - Agent 1 event=0x92,umask=0x20 01 unc_h_egress_vert_cycles_full.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full BL - Agent 0 event=0x92,umask=0x4 01 unc_h_egress_vert_cycles_full.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full BL - Agent 1 event=0x92,umask=0x40 01 unc_h_egress_vert_cycles_full.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full IV - Agent 0 event=0x92,umask=0x8 01 unc_h_egress_vert_cycles_ne.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0 event=0x93,umask=0x1 01 unc_h_egress_vert_cycles_ne.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1 event=0x93,umask=0x10 01 unc_h_egress_vert_cycles_ne.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0 event=0x93,umask=0x2 01 unc_h_egress_vert_cycles_ne.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1 event=0x93,umask=0x20 01 unc_h_egress_vert_cycles_ne.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0 event=0x93,umask=0x4 01 unc_h_egress_vert_cycles_ne.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1 event=0x93,umask=0x40 01 unc_h_egress_vert_cycles_ne.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0 event=0x93,umask=0x8 01 unc_h_egress_vert_inserts.ad_ag0 uncore cache CMS Vert Egress Allocations AD - Agent 0 event=0x91,umask=0x1 01 unc_h_egress_vert_inserts.ad_ag1 uncore cache CMS Vert Egress Allocations AD - Agent 1 event=0x91,umask=0x10 01 unc_h_egress_vert_inserts.ak_ag0 uncore cache CMS Vert Egress Allocations AK - Agent 0 event=0x91,umask=0x2 01 unc_h_egress_vert_inserts.ak_ag1 uncore cache CMS Vert Egress Allocations AK - Agent 1 event=0x91,umask=0x20 01 unc_h_egress_vert_inserts.bl_ag0 uncore cache CMS Vert Egress Allocations BL - Agent 0 event=0x91,umask=0x4 01 unc_h_egress_vert_inserts.bl_ag1 uncore cache CMS Vert Egress Allocations BL - Agent 1 event=0x91,umask=0x40 01 unc_h_egress_vert_inserts.iv_ag0 uncore cache CMS Vert Egress Allocations IV - Agent 0 event=0x91,umask=0x8 01 unc_h_egress_vert_nack.ad_ag0 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x1 01 unc_h_egress_vert_nack.ad_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x10 01 unc_h_egress_vert_nack.ak_ag0 uncore cache CMS Vertical Egress NACKs Onto AK Ring event=0x98,umask=0x2 01 unc_h_egress_vert_nack.ak_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x20 01 unc_h_egress_vert_nack.bl_ag0 uncore cache CMS Vertical Egress NACKs Onto BL Ring event=0x98,umask=0x4 01 unc_h_egress_vert_nack.bl_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x40 01 unc_h_egress_vert_nack.iv_ag0 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x8 01 unc_h_egress_vert_occupancy.ad_ag0 uncore cache CMS Vert Egress Occupancy AD - Agent 0 event=0x90,umask=0x1 01 unc_h_egress_vert_occupancy.ad_ag1 uncore cache CMS Vert Egress Occupancy AD - Agent 1 event=0x90,umask=0x10 01 unc_h_egress_vert_occupancy.ak_ag0 uncore cache CMS Vert Egress Occupancy AK - Agent 0 event=0x90,umask=0x2 01 unc_h_egress_vert_occupancy.ak_ag1 uncore cache CMS Vert Egress Occupancy AK - Agent 1 event=0x90,umask=0x20 01 unc_h_egress_vert_occupancy.bl_ag0 uncore cache CMS Vert Egress Occupancy BL - Agent 0 event=0x90,umask=0x4 01 unc_h_egress_vert_occupancy.bl_ag1 uncore cache CMS Vert Egress Occupancy BL - Agent 1 event=0x90,umask=0x40 01 unc_h_egress_vert_occupancy.iv_ag0 uncore cache CMS Vert Egress Occupancy IV - Agent 0 event=0x90,umask=0x8 01 unc_h_egress_vert_starved.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x1 01 unc_h_egress_vert_starved.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x10 01 unc_h_egress_vert_starved.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation Onto AK Ring event=0x9a,umask=0x2 01 unc_h_egress_vert_starved.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x20 01 unc_h_egress_vert_starved.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation Onto BL Ring event=0x9a,umask=0x4 01 unc_h_egress_vert_starved.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x40 01 unc_h_egress_vert_starved.iv_ag0 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x8 01 unc_h_fast_asserted.horz uncore cache Counts cycles source throttling is asserted - horizontal event=0xa5,umask=0x1 01 unc_h_fast_asserted.vert uncore cache Counts cycles source throttling is asserted - vertical event=0xa5 01 unc_h_horz_ring_ad_in_use.left_even uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even event=0xa7,umask=0x1 01 unc_h_horz_ring_ad_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd event=0xa7,umask=0x2 01 unc_h_horz_ring_ad_in_use.right_even uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even event=0xa7,umask=0x4 01 unc_h_horz_ring_ad_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd event=0xa7,umask=0x8 01 unc_h_horz_ring_ak_in_use.left_even uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even event=0xa9,umask=0x1 01 unc_h_horz_ring_ak_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd event=0xa9,umask=0x2 01 unc_h_horz_ring_ak_in_use.right_even uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even event=0xa9,umask=0x4 01 unc_h_horz_ring_ak_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd event=0xa9,umask=0x8 01 unc_h_horz_ring_bl_in_use.left_even uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even event=0xab,umask=0x1 01 unc_h_horz_ring_bl_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd event=0xab,umask=0x2 01 unc_h_horz_ring_bl_in_use.right_even uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even event=0xab,umask=0x4 01 unc_h_horz_ring_bl_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd event=0xab,umask=0x8 01 unc_h_horz_ring_iv_in_use.left uncore cache Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left event=0xad,umask=0x1 01 unc_h_horz_ring_iv_in_use.right uncore cache Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right event=0xad,umask=0x4 01 unc_h_ingress_inserts.ipq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ event=0x13,umask=0x4 01 unc_h_ingress_inserts.irq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ event=0x13,umask=0x1 01 unc_h_ingress_inserts.irq_rej uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected event=0x13,umask=0x2 01 unc_h_ingress_inserts.prq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ event=0x13,umask=0x10 01 unc_h_ingress_inserts.prq_rej uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected event=0x13,umask=0x20 01 unc_h_ingress_int_starved.ipq uncore cache Cycles with the IPQ in Internal Starvation event=0x14,umask=0x4 01 unc_h_ingress_int_starved.irq uncore cache Cycles with the IRQ in Internal Starvation event=0x14,umask=0x1 01 unc_h_ingress_int_starved.ismq uncore cache Cycles with the ISMQ in Internal Starvation event=0x14,umask=0x8 01 unc_h_ingress_int_starved.prq uncore cache Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue event=0x14,umask=0x10 01 unc_h_ingress_occupancy.ipq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IPQ event=0x11,umask=0x4 01 unc_h_ingress_occupancy.irq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ event=0x11,umask=0x1 01 unc_h_ingress_occupancy.irq_rej uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ Rejected event=0x11,umask=0x2 01 unc_h_ingress_occupancy.prq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ event=0x11,umask=0x10 01 unc_h_ingress_occupancy.prq_rej uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ Rejected event=0x11,umask=0x20 01 unc_h_ingress_retry_ipq0_reject.ad_req_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x1 01 unc_h_ingress_retry_ipq0_reject.ad_rsp_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x2 01 unc_h_ingress_retry_ipq0_reject.ak_non_upi uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x40 01 unc_h_ingress_retry_ipq0_reject.bl_ncb_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x10 01 unc_h_ingress_retry_ipq0_reject.bl_ncs_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x20 01 unc_h_ingress_retry_ipq0_reject.bl_rsp_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x4 01 unc_h_ingress_retry_ipq0_reject.bl_wb_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x8 01 unc_h_ingress_retry_ipq0_reject.iv_non_upi uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x80 01 unc_h_ingress_retry_ipq1_reject.allow_snp uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x40 01 unc_h_ingress_retry_ipq1_reject.any_reject_ipq0 uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x1 01 unc_h_ingress_retry_ipq1_reject.pa_match uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x80 01 unc_h_ingress_retry_ipq1_reject.sf_victim uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x8 01 unc_h_ingress_retry_ipq1_reject.sf_way uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x20 01 unc_h_ingress_retry_irq0_reject.ad_req_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x1 01 unc_h_ingress_retry_irq0_reject.ad_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x2 01 unc_h_ingress_retry_irq0_reject.ak_non_upi uncore cache Ingress Request Queue Rejects event=0x18,umask=0x40 01 unc_h_ingress_retry_irq0_reject.bl_ncb_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x10 01 unc_h_ingress_retry_irq0_reject.bl_ncs_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x20 01 unc_h_ingress_retry_irq0_reject.bl_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x4 01 unc_h_ingress_retry_irq0_reject.bl_wb_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x8 01 unc_h_ingress_retry_irq0_reject.iv_non_upi uncore cache Ingress Request Queue Rejects event=0x18,umask=0x80 01 unc_h_ingress_retry_irq1_reject.allow_snp uncore cache Ingress Request Queue Rejects event=0x19,umask=0x40 01 unc_h_ingress_retry_irq1_reject.any_reject_irq0 uncore cache Ingress Request Queue Rejects event=0x19,umask=0x1 01 unc_h_ingress_retry_irq1_reject.pa_match uncore cache Ingress Request Queue Rejects event=0x19,umask=0x80 01 unc_h_ingress_retry_irq1_reject.sf_victim uncore cache Ingress Request Queue Rejects event=0x19,umask=0x8 01 unc_h_ingress_retry_irq1_reject.sf_way uncore cache Ingress Request Queue Rejects event=0x19,umask=0x20 01 unc_h_ingress_retry_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x1 01 unc_h_ingress_retry_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x2 01 unc_h_ingress_retry_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects event=0x24,umask=0x40 01 unc_h_ingress_retry_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x10 01 unc_h_ingress_retry_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x20 01 unc_h_ingress_retry_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x4 01 unc_h_ingress_retry_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x8 01 unc_h_ingress_retry_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects event=0x24,umask=0x80 01 unc_h_ingress_retry_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x1 01 unc_h_ingress_retry_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x2 01 unc_h_ingress_retry_ismq0_retry.ak_non_upi uncore cache ISMQ Retries event=0x2c,umask=0x40 01 unc_h_ingress_retry_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x10 01 unc_h_ingress_retry_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x20 01 unc_h_ingress_retry_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x4 01 unc_h_ingress_retry_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x8 01 unc_h_ingress_retry_ismq0_retry.iv_non_upi uncore cache ISMQ Retries event=0x2c,umask=0x80 01 unc_h_ingress_retry_other0_retry.ad_req_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x1 01 unc_h_ingress_retry_other0_retry.ad_rsp_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x2 01 unc_h_ingress_retry_other0_retry.ak_non_upi uncore cache Other Queue Retries event=0x2e,umask=0x40 01 unc_h_ingress_retry_other0_retry.bl_ncb_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x10 01 unc_h_ingress_retry_other0_retry.bl_ncs_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x20 01 unc_h_ingress_retry_other0_retry.bl_rsp_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x4 01 unc_h_ingress_retry_other0_retry.bl_wb_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x8 01 unc_h_ingress_retry_other0_retry.iv_non_upi uncore cache Other Queue Retries event=0x2e,umask=0x80 01 unc_h_ingress_retry_other1_retry.allow_snp uncore cache Other Queue Retries event=0x2f,umask=0x40 01 unc_h_ingress_retry_other1_retry.any_reject_irq0 uncore cache Other Queue Retries event=0x2f,umask=0x1 01 unc_h_ingress_retry_other1_retry.pa_match uncore cache Other Queue Retries event=0x2f,umask=0x80 01 unc_h_ingress_retry_other1_retry.sf_victim uncore cache Other Queue Retries event=0x2f,umask=0x8 01 unc_h_ingress_retry_other1_retry.sf_way uncore cache Other Queue Retries event=0x2f,umask=0x20 01 unc_h_ingress_retry_prq0_reject.ad_req_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x1 01 unc_h_ingress_retry_prq0_reject.ad_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x2 01 unc_h_ingress_retry_prq0_reject.ak_non_upi uncore cache Ingress Request Queue Rejects event=0x20,umask=0x40 01 unc_h_ingress_retry_prq0_reject.bl_ncb_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x10 01 unc_h_ingress_retry_prq0_reject.bl_ncs_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x20 01 unc_h_ingress_retry_prq0_reject.bl_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x4 01 unc_h_ingress_retry_prq0_reject.bl_wb_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x8 01 unc_h_ingress_retry_prq0_reject.iv_non_upi uncore cache Ingress Request Queue Rejects event=0x20,umask=0x80 01 unc_h_ingress_retry_prq1_reject.allow_snp uncore cache Ingress Request Queue Rejects event=0x21,umask=0x40 01 unc_h_ingress_retry_prq1_reject.any_reject_irq0 uncore cache Ingress Request Queue Rejects event=0x21,umask=0x1 01 unc_h_ingress_retry_prq1_reject.pa_match uncore cache Ingress Request Queue Rejects event=0x21,umask=0x80 01 unc_h_ingress_retry_prq1_reject.sf_victim uncore cache Ingress Request Queue Rejects event=0x21,umask=0x8 01 unc_h_ingress_retry_prq1_reject.sf_way uncore cache Ingress Request Queue Rejects event=0x21,umask=0x20 01 unc_h_ingress_retry_req_q0_retry.ad_req_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x1 01 unc_h_ingress_retry_req_q0_retry.ad_rsp_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x2 01 unc_h_ingress_retry_req_q0_retry.ak_non_upi uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x40 01 unc_h_ingress_retry_req_q0_retry.bl_ncb_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x10 01 unc_h_ingress_retry_req_q0_retry.bl_ncs_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x20 01 unc_h_ingress_retry_req_q0_retry.bl_rsp_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x4 01 unc_h_ingress_retry_req_q0_retry.bl_wb_vn0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x8 01 unc_h_ingress_retry_req_q0_retry.iv_non_upi uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x80 01 unc_h_ingress_retry_req_q1_retry.allow_snp uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x40 01 unc_h_ingress_retry_req_q1_retry.any_reject_irq0 uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x1 01 unc_h_ingress_retry_req_q1_retry.pa_match uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x80 01 unc_h_ingress_retry_req_q1_retry.sf_victim uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x8 01 unc_h_ingress_retry_req_q1_retry.sf_way uncore cache REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x20 01 unc_h_misc.cv0_pref_miss uncore cache Miscellaneous events in the Cbo. CV0 Prefetch Miss event=0x39,umask=0x20 01 unc_h_misc.cv0_pref_vic uncore cache Miscellaneous events in the Cbo. CV0 Prefetch Victim event=0x39,umask=0x10 01 unc_h_misc.rfo_hit_s uncore cache Miscellaneous events in the Cbo. RFO HitS event=0x39,umask=0x8 01 unc_h_misc.rspi_was_fse uncore cache Miscellaneous events in the Cbo. Silent Snoop Eviction event=0x39,umask=0x1 01 unc_h_misc.wc_aliasing uncore cache Miscellaneous events in the Cbo. Write Combining Aliasing event=0x39,umask=0x2 01 unc_h_ring_bounces_horz.ad uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type event=0xa1,umask=0x1 01 unc_h_ring_bounces_horz.ak uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core event=0xa1,umask=0x2 01 unc_h_ring_bounces_horz.bl uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core event=0xa1,umask=0x4 01 unc_h_ring_bounces_horz.iv uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache event=0xa1,umask=0x8 01 unc_h_ring_bounces_vert.ad uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type event=0xa0,umask=0x1 01 unc_h_ring_bounces_vert.ak uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core event=0xa0,umask=0x2 01 unc_h_ring_bounces_vert.bl uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core event=0xa0,umask=0x4 01 unc_h_ring_bounces_vert.iv uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache event=0xa0,umask=0x8 01 unc_h_ring_sink_starved_horz.ad uncore cache Horizontal ring sink starvation count - AD ring event=0xa3,umask=0x1 01 unc_h_ring_sink_starved_horz.ak uncore cache Horizontal ring sink starvation count - AK ring event=0xa3,umask=0x2 01 unc_h_ring_sink_starved_horz.bl uncore cache Horizontal ring sink starvation count - BL ring event=0xa3,umask=0x4 01 unc_h_ring_sink_starved_horz.iv uncore cache Horizontal ring sink starvation count - IV ring event=0xa3,umask=0x8 01 unc_h_ring_sink_starved_vert.ad uncore cache Vertical ring sink starvation count - AD ring event=0xa2,umask=0x1 01 unc_h_ring_sink_starved_vert.ak uncore cache Vertical ring sink starvation count - AK ring event=0xa2,umask=0x2 01 unc_h_ring_sink_starved_vert.bl uncore cache Vertical ring sink starvation count - BL ring event=0xa2,umask=0x4 01 unc_h_ring_sink_starved_vert.iv uncore cache Vertical ring sink starvation count - IV ring event=0xa2,umask=0x8 01 unc_h_ring_src_thrtl uncore cache Counts cycles in throttle mode event=0xa4 01 unc_h_sf_lookup.any uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ event=0x34,umask=0x11 01 unc_h_sf_lookup.data_read uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Read transactions event=0x34,umask=0x3 01 unc_h_sf_lookup.remote_snoop uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ event=0x34,umask=0x9 01 unc_h_sf_lookup.write uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC event=0x34,umask=0x5 01 unc_h_tg_ingress_busy_starved.ad_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=0x1 01 unc_h_tg_ingress_busy_starved.ad_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=0x10 01 unc_h_tg_ingress_busy_starved.bl_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=0x4 01 unc_h_tg_ingress_busy_starved.bl_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority event=0xb4,umask=0x40 01 unc_h_tg_ingress_bypass.ad_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x1 01 unc_h_tg_ingress_bypass.ad_crd uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x10 01 unc_h_tg_ingress_bypass.ak_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x2 01 unc_h_tg_ingress_bypass.bl_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x4 01 unc_h_tg_ingress_bypass.bl_crd uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x40 01 unc_h_tg_ingress_bypass.iv_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress event=0xb2,umask=0x8 01 unc_h_tg_ingress_crd_starved.ad_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x1 01 unc_h_tg_ingress_crd_starved.ad_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x10 01 unc_h_tg_ingress_crd_starved.ak_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x2 01 unc_h_tg_ingress_crd_starved.bl_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x4 01 unc_h_tg_ingress_crd_starved.bl_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x40 01 unc_h_tg_ingress_crd_starved.ifv uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x80 01 unc_h_tg_ingress_crd_starved.iv_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x8 01 unc_h_tg_ingress_inserts.ad_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x1 01 unc_h_tg_ingress_inserts.ad_crd uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x10 01 unc_h_tg_ingress_inserts.ak_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x2 01 unc_h_tg_ingress_inserts.bl_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x4 01 unc_h_tg_ingress_inserts.bl_crd uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x40 01 unc_h_tg_ingress_inserts.iv_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x8 01 unc_h_tg_ingress_occupancy.ad_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x1 01 unc_h_tg_ingress_occupancy.ad_crd uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x10 01 unc_h_tg_ingress_occupancy.ak_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x2 01 unc_h_tg_ingress_occupancy.bl_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x4 01 unc_h_tg_ingress_occupancy.bl_crd uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x40 01 unc_h_tg_ingress_occupancy.iv_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x8 01 unc_h_tor_inserts.evict uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions event=0x35,umask=0x32 01 unc_h_tor_inserts.hit uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss) event=0x35,umask=0x1f 01 unc_h_tor_inserts.ipq uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ event=0x35,umask=0x38 01 unc_h_tor_inserts.irq uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ event=0x35,umask=0x31 01 unc_h_tor_inserts.miss uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss event=0x35,umask=0x2f 01 unc_h_tor_inserts.prq uncore cache Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ event=0x35,umask=0x34 01 unc_h_tor_occupancy.evict uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -SF/LLC Evictions event=0x36,umask=0x32 01 unc_h_tor_occupancy.hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Hit (Not a Miss) event=0x36,umask=0x1f 01 unc_h_tor_occupancy.ipq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ event=0x36,umask=0x38 01 unc_h_tor_occupancy.ipq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ hit event=0x36,umask=0x18 01 unc_h_tor_occupancy.ipq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ miss event=0x36,umask=0x28 01 unc_h_tor_occupancy.irq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ event=0x36,umask=0x31 01 unc_h_tor_occupancy.irq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ hit event=0x36,umask=0x11 01 unc_h_tor_occupancy.irq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ miss event=0x36,umask=0x21 01 unc_h_tor_occupancy.miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Miss event=0x36,umask=0x2f 01 unc_h_tor_occupancy.prq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ event=0x36,umask=0x34 01 unc_h_tor_occupancy.prq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ hit event=0x36,umask=0x14 01 unc_h_tor_occupancy.prq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ miss event=0x36,umask=0x24 01 unc_h_u_clockticks uncore cache Uncore Clocks event=0 01 unc_h_vert_ring_ad_in_use.dn_even uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even event=0xa6,umask=0x4 01 unc_h_vert_ring_ad_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd event=0xa6,umask=0x8 01 unc_h_vert_ring_ad_in_use.up_even uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even event=0xa6,umask=0x1 01 unc_h_vert_ring_ad_in_use.up_odd uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd event=0xa6,umask=0x2 01 unc_h_vert_ring_ak_in_use.dn_even uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even event=0xa8,umask=0x4 01 unc_h_vert_ring_ak_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd event=0xa8,umask=0x8 01 unc_h_vert_ring_ak_in_use.up_even uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even event=0xa8,umask=0x1 01 unc_h_vert_ring_ak_in_use.up_odd uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd event=0xa8,umask=0x2 01 unc_h_vert_ring_bl_in_use.dn_even uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even event=0xaa,umask=0x4 01 unc_h_vert_ring_bl_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd event=0xaa,umask=0x8 01 unc_h_vert_ring_bl_in_use.up_even uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even event=0xaa,umask=0x1 01 unc_h_vert_ring_bl_in_use.up_odd uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd event=0xaa,umask=0x2 01 unc_h_vert_ring_iv_in_use.dn uncore cache Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down event=0xac,umask=0x4 01 unc_h_vert_ring_iv_in_use.up uncore cache Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up event=0xac,umask=0x1 01 unc_m2p_egress_cycles_full.ad_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0 event=0x25,umask=0x1 01 unc_m2p_egress_cycles_full.ad_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1 event=0x25,umask=0x8 01 unc_m2p_egress_cycles_full.ak_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0 event=0x25,umask=0x2 01 unc_m2p_egress_cycles_full.ak_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1 event=0x25,umask=0x10 01 unc_m2p_egress_cycles_full.bl_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0 event=0x25,umask=0x4 01 unc_m2p_egress_cycles_full.bl_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1 event=0x25,umask=0x20 01 unc_m2p_egress_cycles_ne.ad_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0 event=0x23,umask=0x1 01 unc_m2p_egress_cycles_ne.ad_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1 event=0x23,umask=0x8 01 unc_m2p_egress_cycles_ne.ak_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0 event=0x23,umask=0x2 01 unc_m2p_egress_cycles_ne.ak_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1 event=0x23,umask=0x10 01 unc_m2p_egress_cycles_ne.bl_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0 event=0x23,umask=0x4 01 unc_m2p_egress_cycles_ne.bl_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1 event=0x23,umask=0x20 01 unc_m2p_egress_inserts.ad_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0 event=0x24,umask=0x1 01 unc_m2p_egress_inserts.ad_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1 event=0x24,umask=0x10 01 unc_m2p_egress_inserts.ak_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0 event=0x24,umask=0x2 01 unc_m2p_egress_inserts.ak_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1 event=0x24,umask=0x20 01 unc_m2p_egress_inserts.ak_crd_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0 event=0x24,umask=0x8 01 unc_m2p_egress_inserts.ak_crd_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1 event=0x24,umask=0x80 01 unc_m2p_egress_inserts.bl_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0 event=0x24,umask=0x4 01 unc_m2p_egress_inserts.bl_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1 event=0x24,umask=0x40 01 unc_m2p_ingress_cycles_ne.all uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL event=0x10,umask=0x80 01 unc_m2p_ingress_cycles_ne.cbo_idi uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI event=0x10,umask=0x1 01 unc_m2p_ingress_cycles_ne.cbo_ncb uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB event=0x10,umask=0x2 01 unc_m2p_ingress_cycles_ne.cbo_ncs uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS event=0x10,umask=0x4 01 uncore_edc_uclk unc_e_edc_access.hit_clean uncore memory Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode event=0x2,umask=0x1 01 unc_e_edc_access.hit_dirty uncore memory Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode event=0x2,umask=0x2 01 unc_e_edc_access.miss_clean uncore memory Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode event=0x2,umask=0x4 01 unc_e_edc_access.miss_dirty uncore memory Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode event=0x2,umask=0x8 01 unc_e_edc_access.miss_invalid uncore memory Number of EDC Hits or Misses. Miss I event=0x2,umask=0x10 01 uncore_edc_eclk unc_e_e_clockticks uncore memory ECLK count event=0 01 unc_e_rpq_inserts uncore memory Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache event=0x1,umask=0x1 01 unc_e_u_clockticks uncore memory UCLK count event=0 01 unc_e_wpq_inserts uncore memory Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache event=0x2,umask=0x1 01 uncore_imc_dclk unc_m_cas_count.all uncore memory CAS All event=0x3,umask=0x3 01 unc_m_cas_count.rd uncore memory CAS Reads event=0x3,umask=0x1 01 unc_m_cas_count.wr uncore memory CAS Writes event=0x3,umask=0x2 01 unc_m_d_clockticks uncore memory DCLK count event=0 01 uncore_imc_uclk unc_m_u_clockticks uncore memory UCLK count event=0 01 mem_uops_retired.dtlb_miss_loads virtual memory Counts the number of load micro-ops retired that cause a DTLB miss (Precise Event) Supports address when precise event=0x4,period=200003,umask=0x8 00 page_walks.cycles virtual memory Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included event=0x5,period=200003,umask=0x3 00 This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress page_walks.d_side_cycles virtual memory Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included event=0x5,period=200003,umask=0x1 00 page_walks.d_side_walks virtual memory Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted event=0x5,edge=1,period=100003,umask=0x1 00 page_walks.i_side_cycles virtual memory Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included event=0x5,period=200003,umask=0x2 00 This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress page_walks.i_side_walks virtual memory Counts the total I-side page walks that are completed event=0x5,edge=1,period=100003,umask=0x2 00 page_walks.walks virtual memory Counts the total page walks that are completed (I-side and D-side) event=0x5,edge=1,period=100003,umask=0x3 00 l2_request.all cache Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event event=0x24,period=1000003,umask=0x7 00 Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only longest_lat_cache.reference cache Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis event=0x2e,period=1000003,umask=0x4f 00 Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis mem_uops_retired.all_loads cache Counts the number of load uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x81 00 mem_uops_retired.all_stores cache Counts the number of store uops retired Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x82 00 idq_bubbles.core frontend This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations event=0x9c,period=1000003,umask=0x1 00 This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method mem_trans_retired.load_latency_gt_1024 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles Supports address when precise (Must be precise) event=0xcd,period=53,umask=0x1,ldlat=0x400 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_2048 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles Supports address when precise (Must be precise) event=0xcd,period=23,umask=0x1,ldlat=0x800 00 Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) ocr.demand_data_rd.l3_miss memory Counts cacheable demand data reads were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 00 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002 00 ocr.demand_data_rd.any_response other Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 00 ocr.demand_data_rd.dram other Counts cacheable demand data reads were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 00 ocr.demand_rfo.any_response other Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 00 cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=1000003,umask=0x3 00 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=0x3 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_tsc_p pipeline Reference cycles when the core is not in halt state event=0x3c,period=2000003,umask=0x1 00 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case ld_blocks.store_forward pipeline Counts the number of occurrences a retired load gets blocked because its address partially overlaps with an older store (size mismatch) - unknown_sta/bad_forward (Precise event) event=0x3,period=1000003,umask=0x2 00 topdown.backend_bound_slots pipeline This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions event=0xa4,period=10000003,umask=0x2 00 This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method topdown.slots pipeline TMA slots available for an unhalted logical processor. Fixed counter - architectural event event=0,period=10000003,umask=0x4 00 Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3) topdown.slots_p pipeline TMA slots available for an unhalted logical processor. General counter - architectural event event=0xa4,period=10000003,umask=0x1 00 Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method topdown_bad_speculation.all pipeline Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0,period=1000003,umask=0x5 00 Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the IQ. Also, includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_be_bound.all pipeline Counts the number of retirement slots not consumed due to backend stalls event=0xa4,period=1000003,umask=0x2 00 topdown_fe_bound.all pipeline Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls event=0,period=1000003,umask=0x6 00 topdown_retiring.all pipeline Fixed Counter: Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL (Precise event) event=0,period=1000003,umask=0x7 00 itlb_misses.walk_completed virtual memory Counts the number of page walks completed due to instruction fetch misses to any page size event=0x85,period=2000003,umask=0xe 00 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault l2_lines_out.non_silent cache Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0x26,period=200003,umask=0x2 00 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 l2_request.hit cache All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT] event=0x24,period=200003,umask=0xdf 00 Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT] l2_request.miss cache Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] l2_rqsts.hit cache All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT] event=0x24,period=200003,umask=0xdf 00 Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT] l2_rqsts.miss cache Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS] event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0x23,period=200003,umask=0x40 00 Counts L2 writebacks that access L2 cache lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x42,period=2000003,umask=0x2 00 This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) mem_bound_stalls_ifetch.all cache Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss event=0x35,period=1000003,umask=0x6f 00 mem_bound_stalls_ifetch.l2_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache event=0x35,period=1000003,umask=0x1 00 Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache mem_bound_stalls_ifetch.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC event=0x35,period=1000003,umask=0x6 00 mem_bound_stalls_ifetch.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches event=0x35,period=1000003,umask=0x68 00 mem_bound_stalls_load.all cache Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss event=0x34,period=1000003,umask=0x6f 00 mem_bound_stalls_load.l2_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=1000003,umask=0x1 00 Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache mem_bound_stalls_load.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC event=0x34,period=1000003,umask=0x6 00 mem_bound_stalls_load.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches event=0x34,period=1000003,umask=0x68 00 mem_inst_retired.stlb_hit_loads cache Retired load instructions that hit the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x9 00 Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB) Supports address when precise (Precise event) mem_inst_retired.stlb_hit_stores cache Retired store instructions that hit the STLB Supports address when precise (Precise event) event=0xd0,period=100003,umask=0xa 00 Number of retired store instructions that hit in the 2nd-level TLB (STLB) Supports address when precise (Precise event) mem_load_uops_misc_retired.local_dram cache Counts the number of load ops retired that miss the L3 cache and hit in DRAM (Precise event) event=0xd4,period=1000003,umask=0x2 00 mem_load_uops_retired.l1_hit cache Counts the number of load ops retired that hit the L1 data cache (Precise event) event=0xd1,period=200003,umask=0x1 00 mem_load_uops_retired.l1_miss cache Counts the number of load ops retired that miss in the L1 data cache (Precise event) event=0xd1,period=200003,umask=0x40 00 mem_load_uops_retired.l2_hit cache Counts the number of load ops retired that hit in the L2 cache (Precise event) event=0xd1,period=200003,umask=0x2 00 mem_load_uops_retired.l2_miss cache Counts the number of load ops retired that miss in the L2 cache (Precise event) event=0xd1,period=200003,umask=0x80 00 mem_load_uops_retired.l3_hit cache Counts the number of load ops retired that hit in the L3 cache (Precise event) event=0xd1,period=200003,umask=0x1c 00 mem_load_uops_retired.wcb_hit cache Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate (Precise event) event=0xd1,period=200003,umask=0x20 00 offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0x21,period=100003,umask=0x80 00 Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. offcore_requests.demand_code_rd cache Cacheable and Non-Cacheable code read requests event=0x21,period=100003,umask=0x2 00 Counts both cacheable and Non-Cacheable code read requests offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0x21,period=100003,umask=0x4 00 Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=0x8 00 Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=0x2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=0x4 00 Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_code_rd cache Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle event=0x20,period=1000003,umask=0x2 00 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x20,cmask=6,period=2000003,umask=0x1 00 offcore_requests_outstanding.demand_rfo cache Store Read transactions pending for off-core. Highly correlated event=0x20,period=1000003,umask=0x4 00 Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion topdown_fe_bound.icache cache Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss event=0x71,period=1000003,umask=0x20 00 arith.fpdiv_active floating point This event counts the cycles the floating point divider is busy event=0xb0,cmask=1,period=1000003,umask=0x1 00 uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt) (Precise event) event=0xc2,period=2000003,umask=0x8 00 dsb_fill.fb_stall_ot frontend DSB_FILL.FB_STALL_OT event=0x62,period=1000003,umask=0x10 00 frontend_retired.any_ant frontend Retired ANT branches (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x9 00 Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted) (Precise event) frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x1 00 Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x11 00 Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss (Precise event) frontend_retired.itlb_miss frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss (Precise event) event=0xc6,period=1000003,umask=0x10 00 frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x14 00 Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x12 00 Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event) frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x13 00 Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event) frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x600106 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x608006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x601006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x600206 00 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x610006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x100206 00 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x602006 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x600406 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x620006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x604006 00 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x600806 00 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.misp_ant frontend Mispredicted Retired ANT branches (Precise event) event=0xc6,period=100007,umask=0x2,frontend=0x9 00 ANT retired branches that got just mispredicted (Precise event) frontend_retired.ms_flows frontend FRONTEND_RETIRED.MS_FLOWS (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x8 00 frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x15 00 Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) frontend_retired.unknown_branch frontend FRONTEND_RETIRED.UNKNOWN_BRANCH (Precise event) event=0xc6,period=100007,umask=0x3,frontend=0x17 00 icache_data.stall_periods frontend ICACHE_DATA.STALL_PERIODS event=0x80,cmask=1,edge=1,period=500009,umask=0x4 00 icache_tag.hit frontend Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=0x1 00 Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses idq.ms_uops frontend Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=1000003,umask=0x20 00 Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ memory_ordering.md_nuke memory MEMORY_ORDERING.MD_NUKE event=0x9,period=100003,umask=0x1 00 memory_ordering.mrn_nuke memory Counts the number of memory ordering machine clears due to memory renaming event=0x9,period=100003,umask=0x2 00 misalign_mem_ref.load_page_split memory Counts misaligned loads that are 4K page splits (Precise event) event=0x13,period=200003,umask=0x2 00 misalign_mem_ref.store_page_split memory Counts misaligned stores that are 4K page splits (Precise event) event=0x13,period=200003,umask=0x4 00 offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles where data return is pending for a Demand Data Read request who miss L3 cache event=0x20,cmask=1,period=1000003,umask=0x10 00 Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 memory Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache event=0x20,cmask=6,period=2000003,umask=0x10 00 Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache rs.empty_resource other RS.EMPTY_RESOURCE event=0xa5,period=1000003,umask=0x1 00 serialization.c01_ms_scb other Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state) event=0x75,period=200003,umask=0x4 00 br_misp_retired.all_branches_cost pipeline All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x44 00 br_misp_retired.cond_cost pipeline Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x51 00 br_misp_retired.cond_ntaken_cost pipeline Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x50 00 br_misp_retired.cond_taken_cost pipeline Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x41 00 br_misp_retired.indirect_call_cost pipeline Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x42 00 br_misp_retired.indirect_cost pipeline Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=100003,umask=0xc0 00 br_misp_retired.near_taken_cost pipeline Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=400009,umask=0x60 00 br_misp_retired.ret_cost pipeline Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch (Precise event) event=0xc5,period=100007,umask=0x48 00 inst_retired.nop pipeline Retired NOP instructions event=0xc0,period=2000003,umask=0x2 00 Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions int_misc.all_recovery_cycles pipeline Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall event=0xad,cmask=1,period=2000003,umask=0x3 00 Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall int_misc.rat_stalls pipeline Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xad,period=1000003,umask=0x8 00 This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread topdown_bad_speculation.fastnuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes event=0x73,period=1000003,umask=0x2 00 topdown_bad_speculation.mispredict pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict event=0x73,period=1000003,umask=0x4 00 topdown_be_bound.alloc_restrictions pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions event=0x74,period=1000003,umask=0x1 00 topdown_be_bound.mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block event=0x74,period=1000003,umask=0x2 00 topdown_be_bound.non_mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. ) event=0x74,period=1000003,umask=0x8 00 topdown_be_bound.register pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST) event=0x74,period=1000003,umask=0x20 00 topdown_be_bound.reorder_buffer pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full event=0x74,period=1000003,umask=0x40 00 topdown_be_bound.serialization pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb event=0x74,period=1000003,umask=0x10 00 topdown_fe_bound.branch_detect pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear event=0x71,period=1000003,umask=0x2 00 topdown_fe_bound.branch_resteer pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear event=0x71,period=1000003,umask=0x40 00 topdown_fe_bound.cisc pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to ms event=0x71,period=1000003,umask=0x1 00 topdown_fe_bound.decode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall event=0x71,period=1000003,umask=0x8 00 topdown_fe_bound.frontend_latency pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses event=0x71,period=1000003,umask=0x72 00 topdown_fe_bound.itlb pipeline This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS] event=0x71,period=1000003,umask=0x10 10 topdown_fe_bound.itlb_miss pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB] event=0x71,period=1000003,umask=0x10 00 topdown_fe_bound.other pipeline Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall event=0x71,period=1000003,umask=0x80 00 topdown_fe_bound.predecode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong event=0x71,period=1000003,umask=0x4 00 uops_decoded.dec0_uops pipeline Number of non dec-by-all uops decoded by decoder event=0x76,period=1000003,umask=0x1 00 This event counts the number of not dec-by-all uops decoded by decoder 0 uops_issued.any pipeline Counts the number of uops issued by the front end every cycle event=0xe,period=1000003 00 Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued uops_issued.cycles pipeline UOPS_ISSUED.CYCLES event=0xae,cmask=1,period=2000003,umask=0x1 00 uops_issued.stalls pipeline Cycles when RAT does not issue Uops to RS for the thread event=0xae,cmask=1,inv=1,period=1000003,umask=0x1 00 Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_retired.ms pipeline Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows (Precise event) event=0xc2,period=2000003,umask=0x1 00 uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in ms flows (Precise event) event=0xc2,period=2000003,umask=0x2 00 uncore_hac_cbo unc_hac_cbo_tor_allocation.all uncore cache Number of all entries allocated. Includes also retries event=0x35,umask=0x8 01 unc_hac_cbo_tor_allocation.drd uncore cache Asserted on coherent DRD + DRdPref allocations into the queue. Cacheable only event=0x35,umask=0x1 01 uncore_hac_arb unc_hac_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches event=0x81,umask=0x2 01 unc_hac_arb_transactions.all uncore interconnect Number of all CMI transactions event=0x8a,umask=0x1 01 unc_hac_arb_transactions.reads uncore interconnect Number of all CMI reads event=0x8a,umask=0x2 01 unc_hac_arb_transactions.writes uncore interconnect Number of all CMI writes not including Mflush event=0x8a,umask=0x4 01 unc_hac_arb_trk_requests.all uncore interconnect Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=0x1 01 unc_mc0_rdcas_count_freerun uncore memory Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc0_total_reqcount_freerun uncore memory Counts every read and write request entering the Memory Controller 0 event=0xff,umask=0x10 01 Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW unc_mc0_wrcas_count_freerun uncore memory Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x30 01 Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc1_rdcas_count_freerun uncore memory Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x20 01 Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc1_total_reqcount_freerun uncore memory Counts every read and write request entering the Memory Controller 1 event=0xff,umask=0x10 01 Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW unc_mc1_wrcas_count_freerun uncore memory Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x30 01 Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_m_rd_data uncore memory Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data event=0x3a 01 unc_m_total_data uncore memory Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data event=0x3c 01 unc_m_wr_data uncore memory Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data event=0x3b 01 dtlb_load_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB event=0x8,period=200003,umask=0x20 00 dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses event=0x8,period=200003,umask=0xe 00 dtlb_load_misses.walk_pending virtual memory Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle event=0x8,period=200003,umask=0x10 00 Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x20 00 dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x49,period=2000003,umask=0xe 00 dtlb_store_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle event=0x49,period=200003,umask=0x10 00 Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals itlb_misses.walk_pending virtual memory Counts the number of page walks outstanding for iside in PMH every cycle event=0x85,period=200003,umask=0x10 00 Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks cache_lock_cycles.l1d cache Cycles L1D locked event=0x63,period=2000000,umask=0x2 00 cache_lock_cycles.l1d_l2 cache Cycles L1D and L2 locked event=0x63,period=2000000,umask=0x1 00 l1d.m_evict cache L1D cache lines replaced in M state event=0x51,period=2000000,umask=0x4 00 l1d.m_repl cache L1D cache lines allocated in the M state event=0x51,period=2000000,umask=0x2 00 l1d.m_snoop_evict cache L1D snoop eviction of cache lines in M state event=0x51,period=2000000,umask=0x8 00 l1d.repl cache L1 data cache lines allocated event=0x51,period=2000000,umask=0x1 00 l1d_all_ref.any cache All references to the L1 data cache event=0x43,period=2000000,umask=0x1 00 l1d_all_ref.cacheable cache L1 data cacheable reads and writes event=0x43,period=2000000,umask=0x2 00 l1d_cache_ld.e_state cache L1 data cache read in E state event=0x40,period=2000000,umask=0x4 00 l1d_cache_ld.i_state cache L1 data cache read in I state (misses) event=0x40,period=2000000,umask=0x1 00 l1d_cache_ld.mesi cache L1 data cache reads event=0x40,period=2000000,umask=0xf 00 l1d_cache_ld.m_state cache L1 data cache read in M state event=0x40,period=2000000,umask=0x8 00 l1d_cache_ld.s_state cache L1 data cache read in S state event=0x40,period=2000000,umask=0x2 00 l1d_cache_lock.e_state cache L1 data cache load locks in E state event=0x42,period=2000000,umask=0x4 00 l1d_cache_lock.hit cache L1 data cache load lock hits event=0x42,period=2000000,umask=0x1 00 l1d_cache_lock.m_state cache L1 data cache load locks in M state event=0x42,period=2000000,umask=0x8 00 l1d_cache_lock.s_state cache L1 data cache load locks in S state event=0x42,period=2000000,umask=0x2 00 l1d_cache_lock_fb_hit cache L1D load lock accepted in fill buffer event=0x53,period=2000000,umask=0x1 00 l1d_cache_prefetch_lock_fb_hit cache L1D prefetch load lock accepted in fill buffer event=0x52,period=2000000,umask=0x1 00 l1d_cache_st.e_state cache L1 data cache stores in E state event=0x41,period=2000000,umask=0x4 00 l1d_cache_st.m_state cache L1 data cache stores in M state event=0x41,period=2000000,umask=0x8 00 l1d_cache_st.s_state cache L1 data cache stores in S state event=0x41,period=2000000,umask=0x2 00 l1d_prefetch.miss cache L1D hardware prefetch misses event=0x4e,period=200000,umask=0x2 00 l1d_prefetch.requests cache L1D hardware prefetch requests event=0x4e,period=200000,umask=0x1 00 l1d_prefetch.triggers cache L1D hardware prefetch requests triggered event=0x4e,period=200000,umask=0x4 00 l1d_wb_l2.e_state cache L1 writebacks to L2 in E state event=0x28,period=100000,umask=0x4 00 l1d_wb_l2.i_state cache L1 writebacks to L2 in I state (misses) event=0x28,period=100000,umask=0x1 00 l1d_wb_l2.mesi cache All L1 writebacks to L2 event=0x28,period=100000,umask=0xf 00 l1d_wb_l2.m_state cache L1 writebacks to L2 in M state event=0x28,period=100000,umask=0x8 00 l1d_wb_l2.s_state cache L1 writebacks to L2 in S state event=0x28,period=100000,umask=0x2 00 l2_data_rqsts.any cache All L2 data requests event=0x26,period=200000,umask=0xff 00 l2_data_rqsts.demand.e_state cache L2 data demand loads in E state event=0x26,period=200000,umask=0x4 00 l2_data_rqsts.demand.i_state cache L2 data demand loads in I state (misses) event=0x26,period=200000,umask=0x1 00 l2_data_rqsts.demand.mesi cache L2 data demand requests event=0x26,period=200000,umask=0xf 00 l2_data_rqsts.demand.m_state cache L2 data demand loads in M state event=0x26,period=200000,umask=0x8 00 l2_data_rqsts.demand.s_state cache L2 data demand loads in S state event=0x26,period=200000,umask=0x2 00 l2_data_rqsts.prefetch.e_state cache L2 data prefetches in E state event=0x26,period=200000,umask=0x40 00 l2_data_rqsts.prefetch.i_state cache L2 data prefetches in the I state (misses) event=0x26,period=200000,umask=0x10 00 l2_data_rqsts.prefetch.mesi cache All L2 data prefetches event=0x26,period=200000,umask=0xf0 00 l2_data_rqsts.prefetch.m_state cache L2 data prefetches in M state event=0x26,period=200000,umask=0x80 00 l2_data_rqsts.prefetch.s_state cache L2 data prefetches in the S state event=0x26,period=200000,umask=0x20 00 l2_lines_in.any cache L2 lines allocated event=0xf1,period=100000,umask=0x7 00 l2_lines_in.e_state cache L2 lines allocated in the E state event=0xf1,period=100000,umask=0x4 00 l2_lines_in.s_state cache L2 lines allocated in the S state event=0xf1,period=100000,umask=0x2 00 l2_lines_out.any cache L2 lines evicted event=0xf2,period=100000,umask=0xf 00 l2_lines_out.demand_clean cache L2 lines evicted by a demand request event=0xf2,period=100000,umask=0x1 00 l2_lines_out.demand_dirty cache L2 modified lines evicted by a demand request event=0xf2,period=100000,umask=0x2 00 l2_lines_out.prefetch_clean cache L2 lines evicted by a prefetch request event=0xf2,period=100000,umask=0x4 00 l2_lines_out.prefetch_dirty cache L2 modified lines evicted by a prefetch request event=0xf2,period=100000,umask=0x8 00 l2_rqsts.ifetches cache L2 instruction fetches event=0x24,period=200000,umask=0x30 00 l2_rqsts.ifetch_hit cache L2 instruction fetch hits event=0x24,period=200000,umask=0x10 00 l2_rqsts.ifetch_miss cache L2 instruction fetch misses event=0x24,period=200000,umask=0x20 00 l2_rqsts.ld_hit cache L2 load hits event=0x24,period=200000,umask=0x1 00 l2_rqsts.ld_miss cache L2 load misses event=0x24,period=200000,umask=0x2 00 l2_rqsts.loads cache L2 requests event=0x24,period=200000,umask=0x3 00 l2_rqsts.miss cache All L2 misses event=0x24,period=200000,umask=0xaa 00 l2_rqsts.prefetches cache All L2 prefetches event=0x24,period=200000,umask=0xc0 00 l2_rqsts.prefetch_hit cache L2 prefetch hits event=0x24,period=200000,umask=0x40 00 l2_rqsts.prefetch_miss cache L2 prefetch misses event=0x24,period=200000,umask=0x80 00 l2_rqsts.references cache All L2 requests event=0x24,period=200000,umask=0xff 00 l2_rqsts.rfos cache L2 RFO requests event=0x24,period=200000,umask=0xc 00 l2_rqsts.rfo_hit cache L2 RFO hits event=0x24,period=200000,umask=0x4 00 l2_rqsts.rfo_miss cache L2 RFO misses event=0x24,period=200000,umask=0x8 00 l2_transactions.any cache All L2 transactions event=0xf0,period=200000,umask=0x80 00 l2_transactions.fill cache L2 fill transactions event=0xf0,period=200000,umask=0x20 00 l2_transactions.ifetch cache L2 instruction fetch transactions event=0xf0,period=200000,umask=0x4 00 l2_transactions.l1d_wb cache L1D writeback to L2 transactions event=0xf0,period=200000,umask=0x10 00 l2_transactions.load cache L2 Load transactions event=0xf0,period=200000,umask=0x1 00 l2_transactions.prefetch cache L2 prefetch transactions event=0xf0,period=200000,umask=0x8 00 l2_transactions.rfo cache L2 RFO transactions event=0xf0,period=200000,umask=0x2 00 l2_transactions.wb cache L2 writeback to LLC transactions event=0xf0,period=200000,umask=0x40 00 l2_write.lock.e_state cache L2 demand lock RFOs in E state event=0x27,period=100000,umask=0x40 00 l2_write.lock.hit cache All demand L2 lock RFOs that hit the cache event=0x27,period=100000,umask=0xe0 00 l2_write.lock.i_state cache L2 demand lock RFOs in I state (misses) event=0x27,period=100000,umask=0x10 00 l2_write.lock.mesi cache All demand L2 lock RFOs event=0x27,period=100000,umask=0xf0 00 l2_write.lock.m_state cache L2 demand lock RFOs in M state event=0x27,period=100000,umask=0x80 00 l2_write.lock.s_state cache L2 demand lock RFOs in S state event=0x27,period=100000,umask=0x20 00 l2_write.rfo.hit cache All L2 demand store RFOs that hit the cache event=0x27,period=100000,umask=0xe 00 l2_write.rfo.i_state cache L2 demand store RFOs in I state (misses) event=0x27,period=100000,umask=0x1 00 l2_write.rfo.mesi cache All L2 demand store RFOs event=0x27,period=100000,umask=0xf 00 l2_write.rfo.m_state cache L2 demand store RFOs in M state event=0x27,period=100000,umask=0x8 00 l2_write.rfo.s_state cache L2 demand store RFOs in S state event=0x27,period=100000,umask=0x2 00 longest_lat_cache.miss cache Longest latency cache miss event=0x2e,period=100000,umask=0x41 00 longest_lat_cache.reference cache Longest latency cache reference event=0x2e,period=200000,umask=0x4f 00 mem_inst_retired.latency_above_threshold_0 cache Memory instructions retired above 0 clocks (Precise Event) event=0xb,period=2000000,umask=0x10,ldlat=None 00 mem_inst_retired.latency_above_threshold_1024 cache Memory instructions retired above 1024 clocks (Precise Event) event=0xb,period=100,umask=0x10,ldlat=0x400 00 mem_inst_retired.latency_above_threshold_128 cache Memory instructions retired above 128 clocks (Precise Event) event=0xb,period=1000,umask=0x10,ldlat=0x80 00 mem_inst_retired.latency_above_threshold_16 cache Memory instructions retired above 16 clocks (Precise Event) event=0xb,period=10000,umask=0x10,ldlat=0x10 00 mem_inst_retired.latency_above_threshold_16384 cache Memory instructions retired above 16384 clocks (Precise Event) event=0xb,period=5,umask=0x10,ldlat=0x4000 00 mem_inst_retired.latency_above_threshold_2048 cache Memory instructions retired above 2048 clocks (Precise Event) event=0xb,period=50,umask=0x10,ldlat=0x800 00 mem_inst_retired.latency_above_threshold_256 cache Memory instructions retired above 256 clocks (Precise Event) event=0xb,period=500,umask=0x10,ldlat=0x100 00 mem_inst_retired.latency_above_threshold_32 cache Memory instructions retired above 32 clocks (Precise Event) event=0xb,period=5000,umask=0x10,ldlat=0x20 00 mem_inst_retired.latency_above_threshold_32768 cache Memory instructions retired above 32768 clocks (Precise Event) event=0xb,period=3,umask=0x10,ldlat=0x8000 00 mem_inst_retired.latency_above_threshold_4 cache Memory instructions retired above 4 clocks (Precise Event) event=0xb,period=50000,umask=0x10,ldlat=0x4 00 mem_inst_retired.latency_above_threshold_4096 cache Memory instructions retired above 4096 clocks (Precise Event) event=0xb,period=20,umask=0x10,ldlat=0x1000 00 mem_inst_retired.latency_above_threshold_512 cache Memory instructions retired above 512 clocks (Precise Event) event=0xb,period=200,umask=0x10,ldlat=0x200 00 mem_inst_retired.latency_above_threshold_64 cache Memory instructions retired above 64 clocks (Precise Event) event=0xb,period=2000,umask=0x10,ldlat=0x40 00 mem_inst_retired.latency_above_threshold_8 cache Memory instructions retired above 8 clocks (Precise Event) event=0xb,period=20000,umask=0x10,ldlat=0x8 00 mem_inst_retired.latency_above_threshold_8192 cache Memory instructions retired above 8192 clocks (Precise Event) event=0xb,period=10,umask=0x10,ldlat=0x2000 00 mem_inst_retired.loads cache Instructions retired which contains a load (Precise Event) event=0xb,period=2000000,umask=0x1 00 mem_inst_retired.stores cache Instructions retired which contains a store (Precise Event) event=0xb,period=2000000,umask=0x2 00 mem_load_retired.hit_lfb cache Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) event=0xcb,period=200000,umask=0x40 00 mem_load_retired.l1d_hit cache Retired loads that hit the L1 data cache (Precise Event) event=0xcb,period=2000000,umask=0x1 00 mem_load_retired.l2_hit cache Retired loads that hit the L2 cache (Precise Event) event=0xcb,period=200000,umask=0x2 00 mem_load_retired.llc_miss cache Retired loads that miss the LLC cache (Precise Event) event=0xcb,period=10000,umask=0x10 00 mem_load_retired.llc_unshared_hit cache Retired loads that hit valid versions in the LLC cache (Precise Event) event=0xcb,period=40000,umask=0x4 00 mem_load_retired.other_core_l2_hit_hitm cache Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) event=0xcb,period=40000,umask=0x8 00 mem_uncore_retired.local_dram cache Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) event=0xf,period=10000,umask=0x20 00 mem_uncore_retired.other_core_l2_hitm cache Load instructions retired that HIT modified data in sibling core (Precise Event) event=0xf,period=40000,umask=0x2 00 mem_uncore_retired.remote_cache_local_home_hit cache Load instructions retired remote cache HIT data source (Precise Event) event=0xf,period=20000,umask=0x8 00 mem_uncore_retired.remote_dram cache Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) event=0xf,period=10000,umask=0x10 00 mem_uncore_retired.uncacheable cache Load instructions retired IO (Precise Event) event=0xf,period=4000,umask=0x80 00 offcore_requests.l1d_writeback cache Offcore L1 data cache writebacks event=0xb0,period=100000,umask=0x40 00 offcore_requests_sq_full cache Offcore requests blocked due to Super Queue full event=0xb2,period=100000,umask=0x1 00 offcore_response.any_data.any_cache_dram cache Offcore data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F11 00 offcore_response.any_data.any_location cache All offcore data reads event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF11 00 offcore_response.any_data.io_csr_mmio cache Offcore data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8011 00 offcore_response.any_data.llc_hit_no_other_core cache Offcore data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x111 00 offcore_response.any_data.llc_hit_other_core_hit cache Offcore data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x211 00 offcore_response.any_data.llc_hit_other_core_hitm cache Offcore data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x411 00 offcore_response.any_data.local_cache cache Offcore data reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x711 00 offcore_response.any_data.local_cache_dram cache Offcore data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4711 00 offcore_response.any_data.remote_cache cache Offcore data reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1811 00 offcore_response.any_data.remote_cache_dram cache Offcore data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3811 00 offcore_response.any_data.remote_cache_hit cache Offcore data reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1011 00 offcore_response.any_data.remote_cache_hitm cache Offcore data reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x811 00 offcore_response.any_ifetch.any_cache_dram cache Offcore code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F44 00 offcore_response.any_ifetch.any_location cache All offcore code reads event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF44 00 offcore_response.any_ifetch.io_csr_mmio cache Offcore code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8044 00 offcore_response.any_ifetch.llc_hit_no_other_core cache Offcore code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x144 00 offcore_response.any_ifetch.llc_hit_other_core_hit cache Offcore code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x244 00 offcore_response.any_ifetch.llc_hit_other_core_hitm cache Offcore code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x444 00 offcore_response.any_ifetch.local_cache cache Offcore code reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x744 00 offcore_response.any_ifetch.local_cache_dram cache Offcore code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4744 00 offcore_response.any_ifetch.remote_cache cache Offcore code reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1844 00 offcore_response.any_ifetch.remote_cache_dram cache Offcore code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3844 00 offcore_response.any_ifetch.remote_cache_hit cache Offcore code reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1044 00 offcore_response.any_ifetch.remote_cache_hitm cache Offcore code reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x844 00 offcore_response.any_request.any_cache_dram cache Offcore requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7FFF 00 offcore_response.any_request.any_location cache All offcore requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFFFF 00 offcore_response.any_request.io_csr_mmio cache Offcore requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x80FF 00 offcore_response.any_request.llc_hit_no_other_core cache Offcore requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1FF 00 offcore_response.any_request.llc_hit_other_core_hit cache Offcore requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2FF 00 offcore_response.any_request.llc_hit_other_core_hitm cache Offcore requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4FF 00 offcore_response.any_request.local_cache cache Offcore requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7FF 00 offcore_response.any_request.local_cache_dram cache Offcore requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x47FF 00 offcore_response.any_request.remote_cache cache Offcore requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x18FF 00 offcore_response.any_request.remote_cache_dram cache Offcore requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x38FF 00 offcore_response.any_request.remote_cache_hit cache Offcore requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x10FF 00 offcore_response.any_request.remote_cache_hitm cache Offcore requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8FF 00 offcore_response.any_rfo.any_cache_dram cache Offcore RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F22 00 offcore_response.any_rfo.any_location cache All offcore RFO requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF22 00 offcore_response.any_rfo.io_csr_mmio cache Offcore RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8022 00 offcore_response.any_rfo.llc_hit_no_other_core cache Offcore RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x122 00 offcore_response.any_rfo.llc_hit_other_core_hit cache Offcore RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x222 00 offcore_response.any_rfo.llc_hit_other_core_hitm cache Offcore RFO requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x422 00 offcore_response.any_rfo.local_cache cache Offcore RFO requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x722 00 offcore_response.any_rfo.local_cache_dram cache Offcore RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4722 00 offcore_response.any_rfo.remote_cache cache Offcore RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1822 00 offcore_response.any_rfo.remote_cache_dram cache Offcore RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3822 00 offcore_response.any_rfo.remote_cache_hit cache Offcore RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1022 00 offcore_response.any_rfo.remote_cache_hitm cache Offcore RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x822 00 offcore_response.corewb.any_cache_dram cache Offcore writebacks to any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F08 00 offcore_response.corewb.any_location cache All offcore writebacks event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF08 00 offcore_response.corewb.io_csr_mmio cache Offcore writebacks to the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8008 00 offcore_response.corewb.llc_hit_no_other_core cache Offcore writebacks to the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x108 00 offcore_response.corewb.llc_hit_other_core_hitm cache Offcore writebacks to the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x408 00 offcore_response.corewb.local_cache cache Offcore writebacks to the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x708 00 offcore_response.corewb.local_cache_dram cache Offcore writebacks to the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4708 00 offcore_response.corewb.remote_cache cache Offcore writebacks to a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1808 00 offcore_response.corewb.remote_cache_dram cache Offcore writebacks to a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3808 00 offcore_response.corewb.remote_cache_hit cache Offcore writebacks that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1008 00 offcore_response.corewb.remote_cache_hitm cache Offcore writebacks that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x808 00 offcore_response.data_ifetch.any_cache_dram cache Offcore code or data read requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F77 00 offcore_response.data_ifetch.any_location cache All offcore code or data read requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF77 00 offcore_response.data_ifetch.io_csr_mmio cache Offcore code or data read requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8077 00 offcore_response.data_ifetch.llc_hit_no_other_core cache Offcore code or data read requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x177 00 offcore_response.data_ifetch.llc_hit_other_core_hit cache Offcore code or data read requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x277 00 offcore_response.data_ifetch.llc_hit_other_core_hitm cache Offcore code or data read requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x477 00 offcore_response.data_ifetch.local_cache cache Offcore code or data read requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x777 00 offcore_response.data_ifetch.local_cache_dram cache Offcore code or data read requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4777 00 offcore_response.data_ifetch.remote_cache cache Offcore code or data read requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1877 00 offcore_response.data_ifetch.remote_cache_dram cache Offcore code or data read requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3877 00 offcore_response.data_ifetch.remote_cache_hit cache Offcore code or data read requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1077 00 offcore_response.data_ifetch.remote_cache_hitm cache Offcore code or data read requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x877 00 offcore_response.data_in.any_cache_dram cache Offcore request = all data, response = any cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F33 00 offcore_response.data_in.any_location cache Offcore request = all data, response = any location event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF33 00 offcore_response.data_in.io_csr_mmio cache Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8033 00 offcore_response.data_in.llc_hit_no_other_core cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x133 00 offcore_response.data_in.llc_hit_other_core_hit cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x233 00 offcore_response.data_in.llc_hit_other_core_hitm cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x433 00 offcore_response.data_in.local_cache cache Offcore request = all data, response = local cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x733 00 offcore_response.data_in.local_cache_dram cache Offcore request = all data, response = local cache or dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4733 00 offcore_response.data_in.remote_cache cache Offcore request = all data, response = remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1833 00 offcore_response.data_in.remote_cache_dram cache Offcore request = all data, response = remote cache or dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3833 00 offcore_response.data_in.remote_cache_hit cache Offcore data reads, RFOs, and prefetches that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1033 00 offcore_response.data_in.remote_cache_hitm cache Offcore data reads, RFOs, and prefetches that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x833 00 offcore_response.demand_data.any_cache_dram cache Offcore demand data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F03 00 offcore_response.demand_data.any_location cache All offcore demand data requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF03 00 offcore_response.demand_data.io_csr_mmio cache Offcore demand data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8003 00 offcore_response.demand_data.llc_hit_no_other_core cache Offcore demand data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x103 00 offcore_response.demand_data.llc_hit_other_core_hit cache Offcore demand data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x203 00 offcore_response.demand_data.llc_hit_other_core_hitm cache Offcore demand data requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x403 00 offcore_response.demand_data.local_cache cache Offcore demand data requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x703 00 offcore_response.demand_data.local_cache_dram cache Offcore demand data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4703 00 offcore_response.demand_data.remote_cache cache Offcore demand data requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1803 00 offcore_response.demand_data.remote_cache_dram cache Offcore demand data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3803 00 offcore_response.demand_data.remote_cache_hit cache Offcore demand data requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1003 00 offcore_response.demand_data.remote_cache_hitm cache Offcore demand data requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x803 00 offcore_response.demand_data_rd.any_cache_dram cache Offcore demand data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F01 00 offcore_response.demand_data_rd.any_location cache All offcore demand data reads event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF01 00 offcore_response.demand_data_rd.io_csr_mmio cache Offcore demand data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8001 00 offcore_response.demand_data_rd.llc_hit_no_other_core cache Offcore demand data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x101 00 offcore_response.demand_data_rd.llc_hit_other_core_hit cache Offcore demand data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x201 00 offcore_response.demand_data_rd.llc_hit_other_core_hitm cache Offcore demand data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x401 00 offcore_response.demand_data_rd.local_cache cache Offcore demand data reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x701 00 offcore_response.demand_data_rd.local_cache_dram cache Offcore demand data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4701 00 offcore_response.demand_data_rd.remote_cache cache Offcore demand data reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1801 00 offcore_response.demand_data_rd.remote_cache_dram cache Offcore demand data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3801 00 offcore_response.demand_data_rd.remote_cache_hit cache Offcore demand data reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1001 00 offcore_response.demand_data_rd.remote_cache_hitm cache Offcore demand data reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x801 00 offcore_response.demand_ifetch.any_cache_dram cache Offcore demand code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F04 00 offcore_response.demand_ifetch.any_location cache All offcore demand code reads event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF04 00 offcore_response.demand_ifetch.io_csr_mmio cache Offcore demand code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8004 00 offcore_response.demand_ifetch.llc_hit_no_other_core cache Offcore demand code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x104 00 offcore_response.demand_ifetch.llc_hit_other_core_hit cache Offcore demand code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x204 00 offcore_response.demand_ifetch.llc_hit_other_core_hitm cache Offcore demand code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x404 00 offcore_response.demand_ifetch.local_cache cache Offcore demand code reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x704 00 offcore_response.demand_ifetch.local_cache_dram cache Offcore demand code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4704 00 offcore_response.demand_ifetch.remote_cache cache Offcore demand code reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1804 00 offcore_response.demand_ifetch.remote_cache_dram cache Offcore demand code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3804 00 offcore_response.demand_ifetch.remote_cache_hit cache Offcore demand code reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1004 00 offcore_response.demand_ifetch.remote_cache_hitm cache Offcore demand code reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x804 00 offcore_response.demand_rfo.any_cache_dram cache Offcore demand RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F02 00 offcore_response.demand_rfo.any_location cache All offcore demand RFO requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF02 00 offcore_response.demand_rfo.io_csr_mmio cache Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8002 00 offcore_response.demand_rfo.llc_hit_no_other_core cache Offcore demand RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x102 00 offcore_response.demand_rfo.llc_hit_other_core_hit cache Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x202 00 offcore_response.demand_rfo.llc_hit_other_core_hitm cache Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x402 00 offcore_response.demand_rfo.local_cache cache Offcore demand RFO requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x702 00 offcore_response.demand_rfo.local_cache_dram cache Offcore demand RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4702 00 offcore_response.demand_rfo.remote_cache cache Offcore demand RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1802 00 offcore_response.demand_rfo.remote_cache_dram cache Offcore demand RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3802 00 offcore_response.demand_rfo.remote_cache_hit cache Offcore demand RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1002 00 offcore_response.demand_rfo.remote_cache_hitm cache Offcore demand RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x802 00 offcore_response.other.any_cache_dram cache Offcore other requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F80 00 offcore_response.other.any_location cache All offcore other requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF80 00 offcore_response.other.io_csr_mmio cache Offcore other requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8080 00 offcore_response.other.llc_hit_no_other_core cache Offcore other requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x180 00 offcore_response.other.llc_hit_other_core_hit cache Offcore other requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x280 00 offcore_response.other.llc_hit_other_core_hitm cache Offcore other requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x480 00 offcore_response.other.local_cache cache Offcore other requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x780 00 offcore_response.other.local_cache_dram cache Offcore other requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4780 00 offcore_response.other.remote_cache cache Offcore other requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1880 00 offcore_response.other.remote_cache_dram cache Offcore other requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3880 00 offcore_response.other.remote_cache_hit cache Offcore other requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1080 00 offcore_response.other.remote_cache_hitm cache Offcore other requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x880 00 offcore_response.pf_data.any_cache_dram cache Offcore prefetch data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F30 00 offcore_response.pf_data.any_location cache All offcore prefetch data requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF30 00 offcore_response.pf_data.io_csr_mmio cache Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8030 00 offcore_response.pf_data.llc_hit_no_other_core cache Offcore prefetch data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x130 00 offcore_response.pf_data.llc_hit_other_core_hit cache Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x230 00 offcore_response.pf_data.llc_hit_other_core_hitm cache Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x430 00 offcore_response.pf_data.local_cache cache Offcore prefetch data requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x730 00 offcore_response.pf_data.local_cache_dram cache Offcore prefetch data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4730 00 offcore_response.pf_data.remote_cache cache Offcore prefetch data requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1830 00 offcore_response.pf_data.remote_cache_dram cache Offcore prefetch data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3830 00 offcore_response.pf_data.remote_cache_hit cache Offcore prefetch data requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1030 00 offcore_response.pf_data.remote_cache_hitm cache Offcore prefetch data requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x830 00 offcore_response.pf_data_rd.any_cache_dram cache Offcore prefetch data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F10 00 offcore_response.pf_data_rd.any_location cache All offcore prefetch data reads event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF10 00 offcore_response.pf_data_rd.io_csr_mmio cache Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8010 00 offcore_response.pf_data_rd.llc_hit_no_other_core cache Offcore prefetch data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x110 00 offcore_response.pf_data_rd.llc_hit_other_core_hit cache Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x210 00 offcore_response.pf_data_rd.llc_hit_other_core_hitm cache Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x410 00 offcore_response.pf_data_rd.local_cache cache Offcore prefetch data reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x710 00 offcore_response.pf_data_rd.local_cache_dram cache Offcore prefetch data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4710 00 offcore_response.pf_data_rd.remote_cache cache Offcore prefetch data reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1810 00 offcore_response.pf_data_rd.remote_cache_dram cache Offcore prefetch data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3810 00 offcore_response.pf_data_rd.remote_cache_hit cache Offcore prefetch data reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1010 00 offcore_response.pf_data_rd.remote_cache_hitm cache Offcore prefetch data reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x810 00 offcore_response.pf_ifetch.any_cache_dram cache Offcore prefetch code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F40 00 offcore_response.pf_ifetch.any_location cache All offcore prefetch code reads event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF40 00 offcore_response.pf_ifetch.io_csr_mmio cache Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8040 00 offcore_response.pf_ifetch.llc_hit_no_other_core cache Offcore prefetch code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x140 00 offcore_response.pf_ifetch.llc_hit_other_core_hit cache Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x240 00 offcore_response.pf_ifetch.llc_hit_other_core_hitm cache Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x440 00 offcore_response.pf_ifetch.local_cache cache Offcore prefetch code reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x740 00 offcore_response.pf_ifetch.local_cache_dram cache Offcore prefetch code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4740 00 offcore_response.pf_ifetch.remote_cache cache Offcore prefetch code reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1840 00 offcore_response.pf_ifetch.remote_cache_dram cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3840 00 offcore_response.pf_ifetch.remote_cache_hit cache Offcore prefetch code reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1040 00 offcore_response.pf_ifetch.remote_cache_hitm cache Offcore prefetch code reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x840 00 offcore_response.pf_rfo.any_cache_dram cache Offcore prefetch RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F20 00 offcore_response.pf_rfo.any_location cache All offcore prefetch RFO requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF20 00 offcore_response.pf_rfo.io_csr_mmio cache Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8020 00 offcore_response.pf_rfo.llc_hit_no_other_core cache Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x120 00 offcore_response.pf_rfo.llc_hit_other_core_hit cache Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x220 00 offcore_response.pf_rfo.llc_hit_other_core_hitm cache Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x420 00 offcore_response.pf_rfo.local_cache cache Offcore prefetch RFO requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x720 00 offcore_response.pf_rfo.local_cache_dram cache Offcore prefetch RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4720 00 offcore_response.pf_rfo.remote_cache cache Offcore prefetch RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1820 00 offcore_response.pf_rfo.remote_cache_dram cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3820 00 offcore_response.pf_rfo.remote_cache_hit cache Offcore prefetch RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1020 00 offcore_response.pf_rfo.remote_cache_hitm cache Offcore prefetch RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x820 00 offcore_response.prefetch.any_cache_dram cache Offcore prefetch requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F70 00 offcore_response.prefetch.any_location cache All offcore prefetch requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF70 00 offcore_response.prefetch.io_csr_mmio cache Offcore prefetch requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8070 00 offcore_response.prefetch.llc_hit_no_other_core cache Offcore prefetch requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x170 00 offcore_response.prefetch.llc_hit_other_core_hit cache Offcore prefetch requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x270 00 offcore_response.prefetch.llc_hit_other_core_hitm cache Offcore prefetch requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x470 00 offcore_response.prefetch.local_cache cache Offcore prefetch requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x770 00 offcore_response.prefetch.local_cache_dram cache Offcore prefetch requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4770 00 offcore_response.prefetch.remote_cache cache Offcore prefetch requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1870 00 offcore_response.prefetch.remote_cache_dram cache Offcore prefetch requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3870 00 offcore_response.prefetch.remote_cache_hit cache Offcore prefetch requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1070 00 offcore_response.prefetch.remote_cache_hitm cache Offcore prefetch requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x870 00 sq_misc.split_lock cache Super Queue lock splits across a cache line event=0xf4,period=2000000,umask=0x10 00 store_blocks.at_ret cache Loads delayed with at-Retirement block code event=0x6,period=200000,umask=0x4 00 store_blocks.l1d_block cache Cacheable loads delayed with L1D block code event=0x6,period=200000,umask=0x8 00 fp_assist.all floating point X87 Floating point assists (Precise Event) event=0xf7,period=20000,umask=0x1 00 fp_assist.input floating point X87 Floating point assists for invalid input value (Precise Event) event=0xf7,period=20000,umask=0x4 00 fp_assist.output floating point X87 Floating point assists for invalid output value (Precise Event) event=0xf7,period=20000,umask=0x2 00 fp_comp_ops_exe.mmx floating point MMX Uops event=0x10,period=2000000,umask=0x2 00 fp_comp_ops_exe.sse2_integer floating point SSE2 integer Uops event=0x10,period=2000000,umask=0x8 00 fp_comp_ops_exe.sse_double_precision floating point SSE* FP double precision Uops event=0x10,period=2000000,umask=0x80 00 fp_comp_ops_exe.sse_fp floating point SSE and SSE2 FP Uops event=0x10,period=2000000,umask=0x4 00 fp_comp_ops_exe.sse_fp_packed floating point SSE FP packed Uops event=0x10,period=2000000,umask=0x10 00 fp_comp_ops_exe.sse_fp_scalar floating point SSE FP scalar Uops event=0x10,period=2000000,umask=0x20 00 fp_comp_ops_exe.sse_single_precision floating point SSE* FP single precision Uops event=0x10,period=2000000,umask=0x40 00 fp_comp_ops_exe.x87 floating point Computational floating-point operations executed event=0x10,period=2000000,umask=0x1 00 fp_mmx_trans.any floating point All Floating Point to and from MMX transitions event=0xcc,period=2000000,umask=0x3 00 fp_mmx_trans.to_fp floating point Transitions from MMX to Floating Point instructions event=0xcc,period=2000000,umask=0x1 00 fp_mmx_trans.to_mmx floating point Transitions from Floating Point to MMX instructions event=0xcc,period=2000000,umask=0x2 00 simd_int_128.pack floating point 128 bit SIMD integer pack operations event=0x12,period=200000,umask=0x4 00 simd_int_128.packed_arith floating point 128 bit SIMD integer arithmetic operations event=0x12,period=200000,umask=0x20 00 simd_int_128.packed_logical floating point 128 bit SIMD integer logical operations event=0x12,period=200000,umask=0x10 00 simd_int_128.packed_mpy floating point 128 bit SIMD integer multiply operations event=0x12,period=200000,umask=0x1 00 simd_int_128.packed_shift floating point 128 bit SIMD integer shift operations event=0x12,period=200000,umask=0x2 00 simd_int_128.shuffle_move floating point 128 bit SIMD integer shuffle/move operations event=0x12,period=200000,umask=0x40 00 simd_int_128.unpack floating point 128 bit SIMD integer unpack operations event=0x12,period=200000,umask=0x8 00 simd_int_64.pack floating point SIMD integer 64 bit pack operations event=0xfd,period=200000,umask=0x4 00 simd_int_64.packed_arith floating point SIMD integer 64 bit arithmetic operations event=0xfd,period=200000,umask=0x20 00 simd_int_64.packed_logical floating point SIMD integer 64 bit logical operations event=0xfd,period=200000,umask=0x10 00 simd_int_64.packed_mpy floating point SIMD integer 64 bit packed multiply operations event=0xfd,period=200000,umask=0x1 00 simd_int_64.packed_shift floating point SIMD integer 64 bit shift operations event=0xfd,period=200000,umask=0x2 00 simd_int_64.shuffle_move floating point SIMD integer 64 bit shuffle/move operations event=0xfd,period=200000,umask=0x40 00 simd_int_64.unpack floating point SIMD integer 64 bit unpack operations event=0xfd,period=200000,umask=0x8 00 macro_insts.decoded frontend Instructions decoded event=0xd0,period=2000000,umask=0x1 00 macro_insts.fusions_decoded frontend Macro-fused instructions decoded event=0xa6,period=2000000,umask=0x1 00 two_uop_insts_decoded frontend Two Uop instructions decoded event=0x19,period=2000000,umask=0x1 00 offcore_response.any_data.any_dram memory Offcore data reads satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6011 00 offcore_response.any_data.any_llc_miss memory Offcore data reads that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF811 00 offcore_response.any_data.local_dram memory Offcore data reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4011 00 offcore_response.any_data.remote_dram memory Offcore data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2011 00 offcore_response.any_ifetch.any_dram memory Offcore code reads satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6044 00 offcore_response.any_ifetch.any_llc_miss memory Offcore code reads that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF844 00 offcore_response.any_ifetch.local_dram memory Offcore code reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4044 00 offcore_response.any_ifetch.remote_dram memory Offcore code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2044 00 offcore_response.any_request.any_dram memory Offcore requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x60FF 00 offcore_response.any_request.any_llc_miss memory Offcore requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF8FF 00 offcore_response.any_request.local_dram memory Offcore requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x40FF 00 offcore_response.any_request.remote_dram memory Offcore requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x20FF 00 offcore_response.any_rfo.any_dram memory Offcore RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6022 00 offcore_response.any_rfo.any_llc_miss memory Offcore RFO requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF822 00 offcore_response.any_rfo.local_dram memory Offcore RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4022 00 offcore_response.any_rfo.remote_dram memory Offcore RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2022 00 offcore_response.corewb.any_dram memory Offcore writebacks to any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6008 00 offcore_response.corewb.any_llc_miss memory Offcore writebacks that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF808 00 offcore_response.corewb.local_dram memory Offcore writebacks to the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4008 00 offcore_response.corewb.remote_dram memory Offcore writebacks to a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2008 00 offcore_response.data_ifetch.any_dram memory Offcore code or data read requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6077 00 offcore_response.data_ifetch.any_llc_miss memory Offcore code or data read requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF877 00 offcore_response.data_ifetch.local_dram memory Offcore code or data read requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4077 00 offcore_response.data_ifetch.remote_dram memory Offcore code or data read requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2077 00 offcore_response.data_in.any_dram memory Offcore request = all data, response = any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6033 00 offcore_response.data_in.any_llc_miss memory Offcore request = all data, response = any LLC miss event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF833 00 offcore_response.data_in.local_dram memory Offcore data reads, RFOs, and prefetches satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4033 00 offcore_response.data_in.remote_dram memory Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2033 00 offcore_response.demand_data.any_dram memory Offcore demand data requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6003 00 offcore_response.demand_data.any_llc_miss memory Offcore demand data requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF803 00 offcore_response.demand_data.local_dram memory Offcore demand data requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4003 00 offcore_response.demand_data.remote_dram memory Offcore demand data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2003 00 offcore_response.demand_data_rd.any_dram memory Offcore demand data reads satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6001 00 offcore_response.demand_data_rd.any_llc_miss memory Offcore demand data reads that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF801 00 offcore_response.demand_data_rd.local_dram memory Offcore demand data reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4001 00 offcore_response.demand_data_rd.remote_dram memory Offcore demand data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2001 00 offcore_response.demand_ifetch.any_dram memory Offcore demand code reads satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6004 00 offcore_response.demand_ifetch.any_llc_miss memory Offcore demand code reads that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF804 00 offcore_response.demand_ifetch.local_dram memory Offcore demand code reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4004 00 offcore_response.demand_ifetch.remote_dram memory Offcore demand code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2004 00 offcore_response.demand_rfo.any_dram memory Offcore demand RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6002 00 offcore_response.demand_rfo.any_llc_miss memory Offcore demand RFO requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF802 00 offcore_response.demand_rfo.local_dram memory Offcore demand RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4002 00 offcore_response.demand_rfo.remote_dram memory Offcore demand RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2002 00 offcore_response.other.any_dram memory Offcore other requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6080 00 offcore_response.other.any_llc_miss memory Offcore other requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF880 00 offcore_response.other.remote_dram memory Offcore other requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2080 00 offcore_response.pf_data.any_dram memory Offcore prefetch data requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6030 00 offcore_response.pf_data.any_llc_miss memory Offcore prefetch data requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF830 00 offcore_response.pf_data.local_dram memory Offcore prefetch data requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4030 00 offcore_response.pf_data.remote_dram memory Offcore prefetch data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2030 00 offcore_response.pf_data_rd.any_dram memory Offcore prefetch data reads satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6010 00 offcore_response.pf_data_rd.any_llc_miss memory Offcore prefetch data reads that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF810 00 offcore_response.pf_data_rd.local_dram memory Offcore prefetch data reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4010 00 offcore_response.pf_data_rd.remote_dram memory Offcore prefetch data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2010 00 offcore_response.pf_ifetch.any_dram memory Offcore prefetch code reads satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6040 00 offcore_response.pf_ifetch.any_llc_miss memory Offcore prefetch code reads that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF840 00 offcore_response.pf_ifetch.local_dram memory Offcore prefetch code reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4040 00 offcore_response.pf_ifetch.remote_dram memory Offcore prefetch code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2040 00 offcore_response.pf_rfo.any_dram memory Offcore prefetch RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6020 00 offcore_response.pf_rfo.any_llc_miss memory Offcore prefetch RFO requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF820 00 offcore_response.pf_rfo.local_dram memory Offcore prefetch RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4020 00 offcore_response.pf_rfo.remote_dram memory Offcore prefetch RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2020 00 offcore_response.prefetch.any_dram memory Offcore prefetch requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6070 00 offcore_response.prefetch.any_llc_miss memory Offcore prefetch requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF870 00 offcore_response.prefetch.local_dram memory Offcore prefetch requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4070 00 offcore_response.prefetch.remote_dram memory Offcore prefetch requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2070 00 es_reg_renames other ES segment renames event=0xd5,period=2000000,umask=0x1 00 io_transactions other I/O transactions event=0x6c,period=2000000,umask=0x1 00 l1i.cycles_stalled other L1I instruction fetch stall cycles event=0x80,period=2000000,umask=0x4 00 l1i.hits other L1I instruction fetch hits event=0x80,period=2000000,umask=0x1 00 l1i.misses other L1I instruction fetch misses event=0x80,period=2000000,umask=0x2 00 l1i.reads other L1I Instruction fetches event=0x80,period=2000000,umask=0x3 00 large_itlb.hit other Large ITLB hit event=0x82,period=200000,umask=0x1 00 load_dispatch.any other All loads dispatched event=0x13,period=2000000,umask=0x7 00 load_dispatch.mob other Loads dispatched from the MOB event=0x13,period=2000000,umask=0x4 00 load_dispatch.rs other Loads dispatched that bypass the MOB event=0x13,period=2000000,umask=0x1 00 load_dispatch.rs_delayed other Loads dispatched from stage 305 event=0x13,period=2000000,umask=0x2 00 partial_address_alias other False dependencies due to partial address aliasing event=0x7,period=200000,umask=0x1 00 sb_drain.any other All Store buffer stall cycles event=0x4,period=200000,umask=0x7 00 seg_rename_stalls other Segment rename stall cycles event=0xd4,period=2000000,umask=0x1 00 snoop_response.hit other Thread responded HIT to snoop event=0xb8,period=100000,umask=0x1 00 snoop_response.hite other Thread responded HITE to snoop event=0xb8,period=100000,umask=0x2 00 snoop_response.hitm other Thread responded HITM to snoop event=0xb8,period=100000,umask=0x4 00 sq_full_stall_cycles other Super Queue full stall cycles event=0xf6,period=2000000,umask=0x1 00 arith.cycles_div_busy pipeline Cycles the divider is busy event=0x14,period=2000000,umask=0x1 00 arith.div pipeline Divide Operations executed event=0x14,cmask=1,edge=1,inv=1,period=2000000,umask=0x1 00 arith.mul pipeline Multiply operations executed event=0x14,period=2000000,umask=0x2 00 baclear.bad_target pipeline BACLEAR asserted with bad target address event=0xe6,period=2000000,umask=0x2 00 baclear.clear pipeline BACLEAR asserted, regardless of cause event=0xe6,period=2000000,umask=0x1 00 baclear_force_iq pipeline Instruction queue forced BACLEAR event=0xa7,period=2000000,umask=0x1 00 bpu_clears.early pipeline Early Branch Prediciton Unit clears event=0xe8,period=2000000,umask=0x1 00 bpu_clears.late pipeline Late Branch Prediction Unit clears event=0xe8,period=2000000,umask=0x2 00 bpu_missed_call_ret pipeline Branch prediction unit missed call or return event=0xe5,period=2000000,umask=0x1 00 br_inst_exec.any pipeline Branch instructions executed event=0x88,period=200000,umask=0x7f 00 br_inst_exec.cond pipeline Conditional branch instructions executed event=0x88,period=200000,umask=0x1 00 br_inst_exec.direct pipeline Unconditional branches executed event=0x88,period=200000,umask=0x2 00 br_inst_exec.direct_near_call pipeline Unconditional call branches executed event=0x88,period=20000,umask=0x10 00 br_inst_exec.indirect_near_call pipeline Indirect call branches executed event=0x88,period=20000,umask=0x20 00 br_inst_exec.indirect_non_call pipeline Indirect non call branches executed event=0x88,period=20000,umask=0x4 00 br_inst_exec.near_calls pipeline Call branches executed event=0x88,period=20000,umask=0x30 00 br_inst_exec.non_calls pipeline All non call branches executed event=0x88,period=200000,umask=0x7 00 br_inst_exec.return_near pipeline Indirect return branches executed event=0x88,period=20000,umask=0x8 00 br_inst_exec.taken pipeline Taken branches executed event=0x88,period=200000,umask=0x40 00 br_inst_retired.all_branches pipeline Retired branch instructions (Precise Event) event=0xc4,period=200000,umask=0x4 00 br_inst_retired.conditional pipeline Retired conditional branch instructions (Precise Event) event=0xc4,period=200000,umask=0x1 00 br_inst_retired.near_call pipeline Retired near call instructions (Precise Event) event=0xc4,period=20000,umask=0x2 00 br_misp_exec.any pipeline Mispredicted branches executed event=0x89,period=20000,umask=0x7f 00 br_misp_exec.cond pipeline Mispredicted conditional branches executed event=0x89,period=20000,umask=0x1 00 br_misp_exec.direct pipeline Mispredicted unconditional branches executed event=0x89,period=20000,umask=0x2 00 br_misp_exec.direct_near_call pipeline Mispredicted non call branches executed event=0x89,period=2000,umask=0x10 00 br_misp_exec.indirect_near_call pipeline Mispredicted indirect call branches executed event=0x89,period=2000,umask=0x20 00 br_misp_exec.indirect_non_call pipeline Mispredicted indirect non call branches executed event=0x89,period=2000,umask=0x4 00 br_misp_exec.near_calls pipeline Mispredicted call branches executed event=0x89,period=2000,umask=0x30 00 br_misp_exec.non_calls pipeline Mispredicted non call branches executed event=0x89,period=20000,umask=0x7 00 br_misp_exec.return_near pipeline Mispredicted return branches executed event=0x89,period=2000,umask=0x8 00 br_misp_exec.taken pipeline Mispredicted taken branches executed event=0x89,period=20000,umask=0x40 00 br_misp_retired.near_call pipeline Mispredicted near retired calls (Precise Event) event=0xc5,period=2000,umask=0x2 00 cpu_clk_unhalted.ref pipeline Reference cycles when thread is not halted (fixed counter) event=0x0,umask=0x03,period=2000003 00 cpu_clk_unhalted.ref_p pipeline Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) event=0x3c,period=100000,umask=0x1 00 cpu_clk_unhalted.thread pipeline Cycles when thread is not halted (fixed counter) event=0x3c,period=2000003 00 cpu_clk_unhalted.thread_p pipeline Cycles when thread is not halted (programmable counter) event=0x3c,period=2000000 00 cpu_clk_unhalted.total_cycles pipeline Total CPU cycles event=0x3c,cmask=2,inv=1,period=2000000 00 ild_stall.any pipeline Any Instruction Length Decoder stall cycles event=0x87,period=2000000,umask=0xf 00 ild_stall.iq_full pipeline Instruction Queue full stall cycles event=0x87,period=2000000,umask=0x4 00 ild_stall.lcp pipeline Length Change Prefix stall cycles event=0x87,period=2000000,umask=0x1 00 ild_stall.mru pipeline Stall cycles due to BPU MRU bypass event=0x87,period=2000000,umask=0x2 00 ild_stall.regen pipeline Regen stall cycles event=0x87,period=2000000,umask=0x8 00 inst_decoded.dec0 pipeline Instructions that must be decoded by decoder 0 event=0x18,period=2000000,umask=0x1 00 inst_queue_writes pipeline Instructions written to instruction queue event=0x17,period=2000000,umask=0x1 00 inst_queue_write_cycles pipeline Cycles instructions are written to the instruction queue event=0x1e,period=2000000,umask=0x1 00 inst_retired.any pipeline Instructions retired (fixed counter) event=0xc0,period=2000003 00 inst_retired.any_p pipeline Instructions retired (Programmable counter and Precise Event) (Precise event) event=0xc0,period=2000003 00 inst_retired.mmx pipeline Retired MMX instructions (Precise Event) event=0xc0,period=2000000,umask=0x4 00 inst_retired.total_cycles pipeline Total cycles (Precise Event) event=0xc0,cmask=16,inv=1,period=2000000,umask=0x1 00 inst_retired.total_cycles_ps pipeline Total cycles (Precise Event) event=0xc0,cmask=16,inv=1,period=2000000,umask=0x1 00 inst_retired.x87 pipeline Retired floating-point operations (Precise Event) event=0xc0,period=2000000,umask=0x2 00 load_hit_pre pipeline Load operations conflicting with software prefetches event=0x4c,period=200000,umask=0x1 00 lsd.active pipeline Cycles when uops were delivered by the LSD event=0xa8,cmask=1,period=2000000,umask=0x1 00 lsd.inactive pipeline Cycles no uops were delivered by the LSD event=0xa8,cmask=1,inv=1,period=2000000,umask=0x1 00 lsd_overflow pipeline Loops that can't stream from the instruction queue event=0x20,period=2000000,umask=0x1 00 machine_clears.cycles pipeline Cycles machine clear asserted event=0xc3,period=20000,umask=0x1 00 machine_clears.mem_order pipeline Execution pipeline restart due to Memory ordering conflicts event=0xc3,period=20000,umask=0x2 00 machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=20000,umask=0x4 00 rat_stalls.any pipeline All RAT stall cycles event=0xd2,period=2000000,umask=0xf 00 rat_stalls.flags pipeline Flag stall cycles event=0xd2,period=2000000,umask=0x1 00 rat_stalls.registers pipeline Partial register stall cycles event=0xd2,period=2000000,umask=0x2 00 rat_stalls.rob_read_port pipeline ROB read port stalls cycles event=0xd2,period=2000000,umask=0x4 00 rat_stalls.scoreboard pipeline Scoreboard stall cycles event=0xd2,period=2000000,umask=0x8 00 resource_stalls.any pipeline Resource related stall cycles event=0xa2,period=2000000,umask=0x1 00 resource_stalls.fpcw pipeline FPU control word write stall cycles event=0xa2,period=2000000,umask=0x20 00 resource_stalls.load pipeline Load buffer stall cycles event=0xa2,period=2000000,umask=0x2 00 resource_stalls.mxcsr pipeline MXCSR rename stall cycles event=0xa2,period=2000000,umask=0x40 00 resource_stalls.other pipeline Other Resource related stall cycles event=0xa2,period=2000000,umask=0x80 00 resource_stalls.rob_full pipeline ROB full stall cycles event=0xa2,period=2000000,umask=0x10 00 resource_stalls.rs_full pipeline Reservation Station full stall cycles event=0xa2,period=2000000,umask=0x4 00 resource_stalls.store pipeline Store buffer stall cycles event=0xa2,period=2000000,umask=0x8 00 ssex_uops_retired.packed_double pipeline SIMD Packed-Double Uops retired (Precise Event) event=0xc7,period=200000,umask=0x4 00 ssex_uops_retired.packed_single pipeline SIMD Packed-Single Uops retired (Precise Event) event=0xc7,period=200000,umask=0x1 00 ssex_uops_retired.scalar_double pipeline SIMD Scalar-Double Uops retired (Precise Event) event=0xc7,period=200000,umask=0x8 00 ssex_uops_retired.scalar_single pipeline SIMD Scalar-Single Uops retired (Precise Event) event=0xc7,period=200000,umask=0x2 00 ssex_uops_retired.vector_integer pipeline SIMD Vector Integer Uops retired (Precise Event) event=0xc7,period=200000,umask=0x10 00 uops_decoded.esp_folding pipeline Stack pointer instructions decoded event=0xd1,period=2000000,umask=0x4 00 uops_decoded.esp_sync pipeline Stack pointer sync operations event=0xd1,period=2000000,umask=0x8 00 uops_decoded.ms_cycles_active pipeline Uops decoded by Microcode Sequencer event=0xd1,cmask=1,period=2000000,umask=0x2 00 uops_decoded.stall_cycles pipeline Cycles no Uops are decoded event=0xd1,cmask=1,inv=1,period=2000000,umask=0x1 00 uops_executed.core_active_cycles pipeline Cycles Uops executed on any port (core count) event=0xb1,any=1,cmask=1,period=2000000,umask=0x3f 00 uops_executed.core_active_cycles_no_port5 pipeline Cycles Uops executed on ports 0-4 (core count) event=0xb1,any=1,cmask=1,period=2000000,umask=0x1f 00 uops_executed.core_stall_count pipeline Uops executed on any port (core count) event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f 00 uops_executed.core_stall_count_no_port5 pipeline Uops executed on ports 0-4 (core count) event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f 00 uops_executed.core_stall_cycles pipeline Cycles no Uops issued on any port (core count) event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x3f 00 uops_executed.core_stall_cycles_no_port5 pipeline Cycles no Uops issued on ports 0-4 (core count) event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x1f 00 uops_executed.port0 pipeline Uops executed on port 0 event=0xb1,period=2000000,umask=0x1 00 uops_executed.port015 pipeline Uops issued on ports 0, 1 or 5 event=0xb1,period=2000000,umask=0x40 00 uops_executed.port015_stall_cycles pipeline Cycles no Uops issued on ports 0, 1 or 5 event=0xb1,cmask=1,inv=1,period=2000000,umask=0x40 00 uops_executed.port1 pipeline Uops executed on port 1 event=0xb1,period=2000000,umask=0x2 00 uops_executed.port234_core pipeline Uops issued on ports 2, 3 or 4 event=0xb1,any=1,period=2000000,umask=0x80 00 uops_executed.port2_core pipeline Uops executed on port 2 (core count) event=0xb1,any=1,period=2000000,umask=0x4 00 uops_executed.port3_core pipeline Uops executed on port 3 (core count) event=0xb1,any=1,period=2000000,umask=0x8 00 uops_executed.port4_core pipeline Uops executed on port 4 (core count) event=0xb1,any=1,period=2000000,umask=0x10 00 uops_executed.port5 pipeline Uops executed on port 5 event=0xb1,period=2000000,umask=0x20 00 uops_issued.any pipeline Uops issued event=0xe,period=2000000,umask=0x1 00 uops_issued.core_stall_cycles pipeline Cycles no Uops were issued on any thread event=0xe,any=1,cmask=1,inv=1,period=2000000,umask=0x1 00 uops_issued.cycles_all_threads pipeline Cycles Uops were issued on either thread event=0xe,any=1,cmask=1,period=2000000,umask=0x1 00 uops_issued.fused pipeline Fused Uops issued event=0xe,period=2000000,umask=0x2 00 uops_issued.stall_cycles pipeline Cycles no Uops were issued event=0xe,cmask=1,inv=1,period=2000000,umask=0x1 00 uops_retired.active_cycles pipeline Cycles Uops are being retired (Precise event) event=0xc2,cmask=1,period=2000000,umask=0x1 00 uops_retired.any pipeline Uops retired (Precise Event) event=0xc2,period=2000000,umask=0x1 00 uops_retired.macro_fused pipeline Macro-fused Uops retired (Precise Event) event=0xc2,period=2000000,umask=0x4 00 uops_retired.retire_slots pipeline Retirement slots used (Precise Event) event=0xc2,period=2000000,umask=0x2 00 uops_retired.stall_cycles pipeline Cycles Uops are not retiring (Precise Event) event=0xc2,cmask=1,inv=1,period=2000000,umask=0x1 00 uops_retired.total_cycles pipeline Total cycles using precise uop retired event (Precise Event) event=0xc2,cmask=16,inv=1,period=2000000,umask=0x1 00 uop_unfusion pipeline Uop unfusions due to FP exceptions event=0xdb,period=2000000,umask=0x1 00 dtlb_load_misses.any virtual memory DTLB load misses event=0x8,period=200000,umask=0x1 00 dtlb_load_misses.pde_miss virtual memory DTLB load miss caused by low part of address event=0x8,period=200000,umask=0x20 00 dtlb_load_misses.stlb_hit virtual memory DTLB second level hit event=0x8,period=2000000,umask=0x10 00 dtlb_load_misses.walk_completed virtual memory DTLB load miss page walks complete event=0x8,period=200000,umask=0x2 00 dtlb_misses.any virtual memory DTLB misses event=0x49,period=200000,umask=0x1 00 dtlb_misses.stlb_hit virtual memory DTLB first level misses but second level hit event=0x49,period=200000,umask=0x10 00 dtlb_misses.walk_completed virtual memory DTLB miss page walks event=0x49,period=200000,umask=0x2 00 itlb_flush virtual memory ITLB flushes event=0xae,period=2000000,umask=0x1 00 itlb_misses.any virtual memory ITLB miss event=0x85,period=200000,umask=0x1 00 itlb_misses.walk_completed virtual memory ITLB miss page walks event=0x85,period=200000,umask=0x2 00 itlb_miss_retired virtual memory Retired instructions that missed the ITLB (Precise Event) event=0xc8,period=200000,umask=0x20 00 mem_load_retired.dtlb_miss virtual memory Retired loads that miss the DTLB (Precise Event) event=0xcb,period=200000,umask=0x80 00 mem_store_retired.dtlb_miss virtual memory Retired stores that miss the DTLB (Precise Event) event=0xc,period=200000,umask=0x1 00 l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f 00 Counts all requests that miss L2 cache l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff 00 Counts all L2 requests mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=0x2 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event) mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=0x4 00 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event) mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=0x1 00 mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) event=0xd2,period=100003,umask=0x8 00 mem_load_uops_misc_retired.llc_miss cache Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event) event=0xd4,period=100007,umask=0x2 00 This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event) event=0xd1,period=100003,umask=0x40 00 mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event) event=0xd1,period=2000003,umask=0x1 00 mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event) event=0xd1,period=100003,umask=0x2 00 mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) event=0xd1,period=50021,umask=0x4 00 This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event) mem_uops_retired.all_loads cache All retired load uops. (Precise Event - PEBS) (Precise event) event=0xd0,period=2000003,umask=0x81 00 This event counts the number of load uops retired (Precise Event) (Precise event) mem_uops_retired.all_stores cache All retired store uops. (Precise Event - PEBS) (Precise event) event=0xd0,period=2000003,umask=0x82 00 This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access. (Precise Event - PEBS) (Precise event) event=0xd0,period=100007,umask=0x21 00 mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x41 00 This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x42 00 This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x11 00 mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x12 00 offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0xb0,period=100003,umask=0x2 00 offcore_response.all_code_rd.llc_hit.hitm_other_core cache Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0244 00 offcore_response.all_code_rd.llc_hit.snoop_miss cache Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0244 00 offcore_response.all_data_rd.llc_hit.snoop_miss cache Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0091 00 offcore_response.all_pf_code_rd.llc_hit.any_response cache Counts all prefetch code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0240 00 offcore_response.all_pf_code_rd.llc_hit.hitm_other_core cache Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0240 00 offcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0240 00 offcore_response.all_pf_code_rd.llc_hit.no_snoop_needed cache Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0240 00 offcore_response.all_pf_code_rd.llc_hit.snoop_miss cache Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0240 00 offcore_response.all_pf_data_rd.llc_hit.any_response cache Counts all prefetch data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0090 00 offcore_response.all_pf_data_rd.llc_hit.snoop_miss cache Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0090 00 offcore_response.all_pf_rfo.llc_hit.any_response cache Counts all prefetch RFOs that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0120 00 offcore_response.all_pf_rfo.llc_hit.hitm_other_core cache Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0120 00 offcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0120 00 offcore_response.all_pf_rfo.llc_hit.no_snoop_needed cache Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0120 00 offcore_response.all_pf_rfo.llc_hit.snoop_miss cache Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0120 00 offcore_response.all_reads.any_response cache Counts all data/code/rfo references (demand & prefetch) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x000107F7 00 offcore_response.all_reads.llc_hit.hitm_other_core cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c03f7 00 offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c03f7 00 offcore_response.all_reads.llc_hit.no_snoop_needed cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c03f7 00 offcore_response.all_reads.llc_hit.snoop_miss cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c03f7 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010122 00 offcore_response.all_rfo.llc_hit.hitm_other_core cache Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0122 00 offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd cache Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0122 00 offcore_response.all_rfo.llc_hit.snoop_miss cache Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0122 00 offcore_response.corewb.any_response cache OFFCORE_RESPONSE.COREWB.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10008 00 offcore_response.data_in.any_response cache REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10433 00 offcore_response.demand_code_rd.llc_hit.hitm_other_core cache Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0004 00 offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd cache Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0004 00 offcore_response.demand_code_rd.llc_hit.snoop_miss cache Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0004 00 offcore_response.demand_data_rd.any_response cache Counts all demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010001 00 offcore_response.demand_data_rd.llc_hit.snoop_miss cache Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0001 00 offcore_response.demand_rfo.any_response cache Counts all demand rfo's event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010002 00 offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd cache Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0002 00 offcore_response.demand_rfo.llc_hit.snoop_miss cache Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0002 00 offcore_response.demand_rfo.llc_hit_m.hitm cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040002 00 offcore_response.other.portio_mmio_uc cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2380408000 00 offcore_response.pf_ifetch.any_response cache REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040 00 offcore_response.pf_l2_code_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0040 00 offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0040 00 offcore_response.pf_l2_code_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0040 00 offcore_response.pf_l2_code_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0040 00 offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to L2) data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0010 00 offcore_response.pf_l2_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0020 00 offcore_response.pf_l2_rfo.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0020 00 offcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0020 00 offcore_response.pf_l2_rfo.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0020 00 offcore_response.pf_l2_rfo.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0020 00 offcore_response.pf_llc_code_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0200 00 offcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0200 00 offcore_response.pf_llc_code_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0200 00 offcore_response.pf_llc_code_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0200 00 offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0080 00 offcore_response.pf_llc_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0100 00 offcore_response.pf_llc_rfo.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0100 00 offcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0100 00 offcore_response.pf_llc_rfo.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0100 00 offcore_response.pf_llc_rfo.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0100 00 offcore_response.pf_l_data_rd.any_response cache REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10080 00 offcore_response.pf_l_ifetch.any_response cache REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10200 00 idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30 00 This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more information offcore_response.all_pf_code_rd.llc_miss.dram memory Counts all prefetch code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400240 00 offcore_response.all_pf_data_rd.llc_miss.dram memory Counts all prefetch data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400090 00 offcore_response.all_pf_rfo.llc_miss.dram memory Counts all prefetch RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400120 00 offcore_response.all_rfo.llc_miss.dram memory Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400122 00 offcore_response.any_request.llc_miss_local.dram memory REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80408fff 00 This event counts any requests that miss the LLC where the data was returned from local DRAM offcore_response.data_in_socket.llc_miss.local_dram memory Counts LLC replacements event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004001b3 00 This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM offcore_response.data_in_socket.llc_miss_local.any_llc_hit memory REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT event=0xb7,period=100003,umask=0x1,offcore_rsp=0x17004001b3 00 offcore_response.demand_ifetch.llc_miss_local.dram memory REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400004 00 offcore_response.demand_rfo.llc_miss.dram memory Counts demand data writes (RFOs) that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400002 00 offcore_response.pf_data_rd.llc_miss_local.dram memory REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400010 00 offcore_response.pf_ifetch.llc_miss_local.dram memory REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400040 00 offcore_response.pf_l2_code_rd.llc_miss.dram memory Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400040 00 offcore_response.pf_l2_data_rd.llc_miss.dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400010 00 offcore_response.pf_l2_rfo.llc_miss.dram memory Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400020 00 offcore_response.pf_llc_code_rd.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400200 00 offcore_response.pf_llc_data_rd.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400080 00 offcore_response.pf_llc_rfo.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400100 00 offcore_response.pf_l_data_rd.llc_miss_local.dram memory REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400080 00 offcore_response.pf_l_ifetch.llc_miss_local.dram memory REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400200 00 page_walks.llc_miss memory Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND event=0xbe,period=100003,umask=0x1 00 br_inst_retired.conditional pipeline Conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=400009,umask=0x1 00 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=0x2 00 br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=0x2 00 br_inst_retired.near_return pipeline Return instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=0x8 00 br_inst_retired.near_taken pipeline Taken branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=400009,umask=0x20 00 br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=0x1 00 br_misp_retired.near_call pipeline Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=100007,umask=0x2 00 br_misp_retired.not_taken pipeline Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=0x10 00 br_misp_retired.taken pipeline Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=0x20 00 ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=0x3,period=100003,umask=0x2 00 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued partial_rat_stalls.flags_merge_uop_cycles pipeline Performance sensitive flags-merging uops added by Sandy Bridge u-arch event=0x59,cmask=1,period=2000003,umask=0x20 00 This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual partial_rat_stalls.slow_lea_window pipeline Cycles with at least one slow LEA uop being allocated event=0x59,period=2000003,umask=0x40 00 This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions uops_retired.all pipeline Actually retired uops. (Precise Event - PEBS) (Precise event) event=0xc2,period=2000003,umask=0x1 00 This event counts the number of micro-ops retired. (Precise Event) (Precise event) uops_retired.retire_slots pipeline Retirement slots used. (Precise Event - PEBS) (Precise event) event=0xc2,period=2000003,umask=0x2 00 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event) mem_load_l3_miss_retired.remote_pmm cache Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches event=0xd3,period=100007,umask=0x10 00 Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 mem_load_retired.local_pmm cache Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) event=0xd1,period=1000003,umask=0x80 00 Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 Supports address when precise (Precise event) ocr.demand_data_rd.local_socket_pmm other Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=0x1,offcore_rsp=0x700C00001 00 ocr.demand_data_rd.pmm other Counts demand data reads that were supplied by PMM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x703C00001 00 ocr.demand_data_rd.remote_pmm other Counts demand data reads that were supplied by PMM attached to another socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x703000001 00 ocr.reads_to_core.local_socket_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=0x1,offcore_rsp=0x700C04477 00 ocr.reads_to_core.remote_pmm other Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket event=0x2a,period=100003,umask=0x1,offcore_rsp=0x703004477 00 amx_ops_retired.bf16 pipeline AMX retired arithmetic BF16 operations event=0xce,period=1000003,umask=0x2 00 Number of AMX-based retired arithmetic bfloat16 (BF16) floating-point operations. Counts TDPBF16PS FP instructions. SW to use operation multiplier of 4 amx_ops_retired.int8 pipeline AMX retired arithmetic integer 8-bit operations event=0xce,period=1000003,umask=0x1 00 Number of AMX-based retired arithmetic integer operations of 8-bit width source operands. Counts TDPB[SS,UU,US,SU]D instructions. SW should use operation multiplier of 8 unc_iio_bandwidth_out.part0_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x30 01 unc_iio_bandwidth_out.part1_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x31 01 unc_iio_bandwidth_out.part2_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x32 01 unc_iio_bandwidth_out.part3_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x33 01 unc_iio_bandwidth_out.part4_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x34 01 unc_iio_bandwidth_out.part5_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x35 01 unc_iio_bandwidth_out.part6_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x36 01 unc_iio_bandwidth_out.part7_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x37 01 core_reject_l2q.all cache Counts the number of request that were not accepted into the L2Q because the L2Q is FULL event=0x31,period=200003 00 Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) fetch_stall.icache_fill_pending_cycles cache Cycles code-fetch stalled due to an outstanding ICache miss event=0x86,period=200003,umask=0x4 00 Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy. Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events l2_reject_xq.all cache Counts the number of request from the L2 that were not accepted into the XQ event=0x30,period=200003 00 This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims) longest_lat_cache.miss cache L2 cache request misses event=0x2e,period=200003,umask=0x41 00 This event counts the total number of L2 cache references and the number of L2 cache misses respectively longest_lat_cache.reference cache L2 cache requests from this core event=0x2e,period=200003,umask=0x4f 00 This event counts requests originating from the core that references a cache line in the L2 cache mem_uops_retired.all_loads cache All Loads event=0x4,period=200003,umask=0x40 00 This event counts the number of load ops retired mem_uops_retired.all_stores cache All Stores event=0x4,period=200003,umask=0x80 00 This event counts the number of store ops retired mem_uops_retired.hitm cache Cross core or cross module hitm (Precise event) event=0x4,period=200003,umask=0x20 00 This event counts the number of load ops retired that got data from the other core or from the other module (Precise event) mem_uops_retired.l1_miss_loads cache Loads missed L1 event=0x4,period=200003,umask=0x1 00 This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted mem_uops_retired.l2_hit_loads cache Loads hit L2 (Precise event) event=0x4,period=200003,umask=0x2 00 This event counts the number of load ops retired that hit in the L2 (Precise event) mem_uops_retired.l2_miss_loads cache Loads missed L2 (Precise event) event=0x4,period=100007,umask=0x4 00 This event counts the number of load ops retired that miss in the L2 (Precise event) mem_uops_retired.utlb_miss cache Loads missed UTLB event=0x4,period=200003,umask=0x10 00 This event counts the number of load ops retired that had UTLB miss offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100007,umask=0x1 00 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction offcore_response.any_code_rd.any_response cache Counts any code reads (demand & prefetch) that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010044 00 offcore_response.any_code_rd.l2_miss.any cache Counts any code reads (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000044 00 offcore_response.any_code_rd.l2_miss.hitm_other_core cache Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000044 00 offcore_response.any_code_rd.l2_miss.hit_other_core_no_fwd cache Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000044 00 offcore_response.any_code_rd.l2_miss.snoop_miss cache Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000044 00 offcore_response.any_data_rd.any_response cache Counts any data read (demand & prefetch) that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013091 00 offcore_response.any_data_rd.l2_miss.any cache Counts any data read (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680003091 00 offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003091 00 offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd cache Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400003091 00 offcore_response.any_data_rd.l2_miss.snoop_miss cache Counts any data read (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003091 00 offcore_response.any_request.any_response cache Counts any request that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018008 00 offcore_response.any_request.l2_miss.hitm_other_core cache Counts any request that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000008008 00 offcore_response.any_request.l2_miss.hit_other_core_no_fwd cache Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400008008 00 offcore_response.any_request.l2_miss.snoop_miss cache Counts any request that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200008008 00 offcore_response.any_rfo.any_response cache Counts any rfo reads (demand & prefetch) that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010022 00 offcore_response.any_rfo.l2_miss.any cache Counts any rfo reads (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000022 00 offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000022 00 offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd cache Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000022 00 offcore_response.any_rfo.l2_miss.snoop_miss cache Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000022 00 offcore_response.corewb.l2_miss.any cache Counts writeback (modified to exclusive) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000008 00 offcore_response.corewb.l2_miss.no_snoop_needed cache Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080000008 00 offcore_response.demand_code_rd.any_response cache Counts demand and DCU prefetch instruction cacheline that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010004 00 offcore_response.demand_code_rd.l2_miss.any cache Counts demand and DCU prefetch instruction cacheline that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000004 00 offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000004 00 offcore_response.demand_code_rd.l2_miss.snoop_miss cache Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000004 00 offcore_response.demand_code_rd.outstanding cache Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000004 00 offcore_response.demand_data_rd.any_response cache Counts demand and DCU prefetch data read that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010001 00 offcore_response.demand_data_rd.l2_miss.any cache Counts demand and DCU prefetch data read that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000001 00 offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000001 00 offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000001 00 offcore_response.demand_data_rd.l2_miss.snoop_miss cache Counts demand and DCU prefetch data read that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000001 00 offcore_response.demand_data_rd.outstanding cache Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000001 00 offcore_response.demand_rfo.l2_miss.any cache Counts demand and DCU prefetch RFOs that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000002 00 offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000002 00 offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000002 00 offcore_response.demand_rfo.l2_miss.snoop_miss cache Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000002 00 offcore_response.demand_rfo.outstanding cache Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000002 00 offcore_response.partial_reads.l2_miss.any cache Counts demand reads of partial cache lines (including UC and WC) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000080 00 offcore_response.partial_writes.l2_miss.any cache Countsof demand RFO requests to write to partial cache lines that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000100 00 offcore_response.pf_l1_data_rd.any_response cache Counts DCU hardware prefetcher data read that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000012000 00 offcore_response.pf_l1_data_rd.l2_miss.any cache Counts DCU hardware prefetcher data read that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680002000 00 offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000002000 00 offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd cache Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400002000 00 offcore_response.pf_l1_data_rd.l2_miss.snoop_miss cache Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200002000 00 offcore_response.pf_l2_code_rd.l2_miss.any cache Counts code reads generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000040 00 offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwd cache Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000040 00 offcore_response.pf_l2_code_rd.l2_miss.snoop_miss cache Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000040 00 offcore_response.pf_l2_data_rd.l2_miss.any cache Counts data cacheline reads generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000010 00 offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000010 00 offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000010 00 offcore_response.pf_l2_data_rd.l2_miss.snoop_miss cache Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000010 00 offcore_response.pf_l2_rfo.l2_miss.any cache Counts RFO requests generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000020 00 offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000020 00 offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd cache Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000020 00 offcore_response.pf_l2_rfo.l2_miss.snoop_miss cache Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000020 00 offcore_response.streaming_stores.l2_miss.any cache Counts streaming store that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680004800 00 rehabq.any_ld cache Any reissued load uops event=0x3,period=200003,umask=0x40 00 This event counts the number of load uops reissued from Rehabq rehabq.any_st cache Any reissued store uops event=0x3,period=200003,umask=0x80 00 This event counts the number of store uops reissued from Rehabq rehabq.ld_block_std_notready cache Loads blocked due to store data not ready event=0x3,period=200003,umask=0x2 00 This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time rehabq.ld_block_st_forward cache Loads blocked due to store forward restriction (Precise event) event=0x3,period=200003,umask=0x1 00 This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event) rehabq.ld_splits cache Load uops that split cache line boundary (Precise event) event=0x3,period=200003,umask=0x8 00 This event counts the number of retire loads that experienced cache line boundary splits (Precise event) rehabq.lock cache Uops with lock semantics event=0x3,period=200003,umask=0x10 00 This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0) rehabq.sta_full cache Store address buffer full event=0x3,period=200003,umask=0x20 00 This event counts the number of retired stores that are delayed because there is not a store address buffer available rehabq.st_splits cache Store uops that split cache line boundary event=0x3,period=200003,umask=0x4 00 This event counts the number of retire stores that experienced cache line boundary splits machine_clears.fp_assist floating point Stalls due to FP assists event=0xc3,period=200003,umask=0x4 00 This event counts the number of times that pipeline stalled due to FP operations needing assists baclears.all frontend Counts the number of baclears event=0xe6,period=200003,umask=0x1 00 The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch baclears.cond frontend Counts the number of JCC baclears event=0xe6,period=200003,umask=0x10 00 The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Conditional Code) baclears baclears.return frontend Counts the number of RETURN baclears event=0xe6,period=200003,umask=0x8 00 The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears decode_restriction.predecode_wrong frontend Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction event=0xe9,period=200003,umask=0x1 00 Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction icache.accesses frontend Instruction fetches event=0x80,period=200003,umask=0x3 00 This event counts all instruction fetches, not including most uncacheable fetches icache.hit frontend Instruction fetches from Icache event=0x80,period=200003,umask=0x1 00 This event counts all instruction fetches from the instruction cache icache.misses frontend Icache miss event=0x80,period=200003,umask=0x2 00 This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding ms_decoded.ms_entry frontend Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count event=0xe7,period=200003,umask=0x1 00 Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions machine_clears.memory_ordering memory Stalls due to Memory ordering event=0xc3,period=200003,umask=0x2 00 This event counts the number of times that pipeline was cleared due to memory ordering issues fetch_stall.all other Cycles code-fetch stalled due to any reason event=0x86,period=200003,umask=0x3f 00 Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events fetch_stall.itlb_fill_pending_cycles other Cycles code-fetch stalled due to an outstanding ITLB miss event=0x86,period=200003,umask=0x2 00 Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation br_inst_retired.all_branches pipeline Counts the number of branch instructions retired.. (Precise event) event=0xc4,period=200003 00 ALL_BRANCHES counts the number of any branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.all_taken_branches pipeline Counts the number of taken branch instructions retired (Must be precise) event=0xc4,period=200003,umask=0x80 00 ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise) br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9 00 CALL counts the number of near CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xbf 00 FAR counts the number of far branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb 00 IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.jcc pipeline Counts the number of JCC branch instructions retired (Precise event) event=0xc4,period=200003,umask=0x7e 00 JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.non_return_ind pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb 00 NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfd 00 REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7 00 RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.taken_jcc pipeline Counts the number of taken JCC branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe 00 TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_misp_retired.all_branches pipeline Counts the number of mispredicted branch instructions retired (Precise event) event=0xc5,period=200003 00 ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb 00 IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.jcc pipeline Counts the number of mispredicted JCC branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e 00 JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.non_return_ind pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb 00 NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xf7 00 RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.taken_jcc pipeline Counts the number of mispredicted taken JCC branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe 00 TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) cpu_clk_unhalted.core pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003 00 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000003 00 This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003 00 This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=2000003,umask=0x3 00 Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF cycles_div_busy.all pipeline Cycles the divider is busy. Does not imply a stall waiting for the divider event=0xcd,period=2000003,umask=0x1 00 Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003 00 This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P inst_retired.any_p pipeline Instructions retired event=0xc0,period=2000003 00 This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers machine_clears.all pipeline Counts all machine clears event=0xc3,period=200003,umask=0x8 00 Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions "older" than this one will be allowed to finish. This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200003,umask=0x1 00 This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors no_alloc_cycles.all pipeline Counts the number of cycles when no uops are allocated for any reason event=0xca,period=200003,umask=0x3f 00 The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle no_alloc_cycles.mispredicts pipeline Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted event=0xca,period=200003,umask=0x4 00 Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted no_alloc_cycles.not_delivered pipeline Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation event=0xca,period=200003,umask=0x50 00 The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth no_alloc_cycles.rat_stall pipeline Counts the number of cycles when no uops are allocated and a RATstall is asserted event=0xca,period=200003,umask=0x20 00 no_alloc_cycles.rob_full pipeline Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) event=0xca,period=200003,umask=0x1 00 Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) rs_full_stall.all pipeline Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts event=0xcb,period=200003,umask=0x1f 00 rs_full_stall.mec pipeline Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M event=0xcb,period=200003,umask=0x1 00 Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M uops_retired.all pipeline Micro-ops retired event=0xc2,period=2000003,umask=0x10 00 This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops uops_retired.ms pipeline MSROM micro-ops retired event=0xc2,period=2000003,umask=0x1 00 This event counts the number of micro-ops retired that were supplied from MSROM mem_uops_retired.dtlb_miss_loads virtual memory Loads missed DTLB (Precise event) event=0x4,period=200003,umask=0x8 00 This event counts the number of load ops retired that had DTLB miss (Precise event) page_walks.cycles virtual memory Total cycles for all the page walks. (I-side and D-side) event=0x5,period=200003,umask=0x3 00 This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event page_walks.d_side_cycles virtual memory Duration of D-side page-walks in core cycles event=0x5,period=200003,umask=0x1 00 This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks page_walks.d_side_walks virtual memory D-side page-walks event=0x5,edge=1,period=100003,umask=0x1 00 This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks page_walks.i_side_cycles virtual memory Duration of I-side page-walks in core cycles event=0x5,period=200003,umask=0x2 00 This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks page_walks.i_side_walks virtual memory I-side page-walks event=0x5,edge=1,period=100003,umask=0x2 00 This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks page_walks.walks virtual memory Total page walks that are completed (I-side and D-side) event=0x5,edge=1,period=100003,umask=0x3 00 This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks l2_lines_out.non_silent cache Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 event=0xf2,period=200003,umask=0x2 00 l2_lines_out.silent cache Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event event=0xf2,period=200003,umask=0x1 00 offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100003,umask=0x1 00 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0004 00 offcore_response.demand_code_rd.l3_hit.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0004 00 offcore_response.demand_code_rd.l3_hit_e.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080004 00 offcore_response.demand_code_rd.l3_hit_e.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080004 00 offcore_response.demand_code_rd.l3_hit_m.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040004 00 offcore_response.demand_code_rd.l3_hit_m.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040004 00 offcore_response.demand_code_rd.l3_hit_s.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100004 00 offcore_response.demand_code_rd.l3_hit_s.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100004 00 offcore_response.demand_code_rd.l4_hit_local_l4.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400004 00 offcore_response.demand_code_rd.l4_hit_local_l4.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400004 00 offcore_response.demand_code_rd.supplier_none.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020004 00 offcore_response.demand_code_rd.supplier_none.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020004 00 offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0001 00 offcore_response.demand_data_rd.l3_hit.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0001 00 offcore_response.demand_data_rd.l3_hit_e.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080001 00 offcore_response.demand_data_rd.l3_hit_e.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080001 00 offcore_response.demand_data_rd.l3_hit_m.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040001 00 offcore_response.demand_data_rd.l3_hit_m.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040001 00 offcore_response.demand_data_rd.l3_hit_s.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100001 00 offcore_response.demand_data_rd.l3_hit_s.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100001 00 offcore_response.demand_data_rd.l4_hit_local_l4.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400001 00 offcore_response.demand_data_rd.l4_hit_local_l4.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400001 00 offcore_response.demand_data_rd.supplier_none.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020001 00 offcore_response.demand_data_rd.supplier_none.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020001 00 offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0002 00 offcore_response.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0002 00 offcore_response.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0002 00 offcore_response.demand_rfo.l3_hit.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0002 00 offcore_response.demand_rfo.l3_hit.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0002 00 offcore_response.demand_rfo.l3_hit_e.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080002 00 offcore_response.demand_rfo.l3_hit_e.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080002 00 offcore_response.demand_rfo.l3_hit_e.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080002 00 offcore_response.demand_rfo.l3_hit_m.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040002 00 offcore_response.demand_rfo.l3_hit_m.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040002 00 offcore_response.demand_rfo.l3_hit_m.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040002 00 offcore_response.demand_rfo.l3_hit_s.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100002 00 offcore_response.demand_rfo.l3_hit_s.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100002 00 offcore_response.demand_rfo.l3_hit_s.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100002 00 offcore_response.demand_rfo.l4_hit_local_l4.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400002 00 offcore_response.demand_rfo.l4_hit_local_l4.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400002 00 offcore_response.demand_rfo.supplier_none.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020002 00 offcore_response.demand_rfo.supplier_none.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020002 00 offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020002 00 offcore_response.demand_rfo.supplier_none.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020002 00 offcore_response.demand_rfo.supplier_none.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020002 00 offcore_response.demand_rfo.supplier_none.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020002 00 offcore_response.demand_rfo.supplier_none.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020002 00 offcore_response.other.l3_hit.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C8000 00 offcore_response.other.l3_hit.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C8000 00 offcore_response.other.l3_hit.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C8000 00 offcore_response.other.l3_hit.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C8000 00 offcore_response.other.l3_hit.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C8000 00 offcore_response.other.l3_hit.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C8000 00 offcore_response.other.l3_hit.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C8000 00 offcore_response.other.l3_hit_e.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0088000 00 offcore_response.other.l3_hit_e.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000088000 00 offcore_response.other.l3_hit_e.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400088000 00 offcore_response.other.l3_hit_e.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200088000 00 offcore_response.other.l3_hit_e.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80088000 00 offcore_response.other.l3_hit_e.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100088000 00 offcore_response.other.l3_hit_e.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40088000 00 offcore_response.other.l3_hit_m.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0048000 00 offcore_response.other.l3_hit_m.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000048000 00 offcore_response.other.l3_hit_m.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400048000 00 offcore_response.other.l3_hit_m.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200048000 00 offcore_response.other.l3_hit_m.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80048000 00 offcore_response.other.l3_hit_m.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100048000 00 offcore_response.other.l3_hit_m.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40048000 00 offcore_response.other.l3_hit_s.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0108000 00 offcore_response.other.l3_hit_s.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000108000 00 offcore_response.other.l3_hit_s.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400108000 00 offcore_response.other.l3_hit_s.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200108000 00 offcore_response.other.l3_hit_s.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80108000 00 offcore_response.other.l3_hit_s.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100108000 00 offcore_response.other.l3_hit_s.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40108000 00 offcore_response.other.l4_hit_local_l4.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0408000 00 offcore_response.other.l4_hit_local_l4.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000408000 00 offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400408000 00 offcore_response.other.l4_hit_local_l4.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200408000 00 offcore_response.other.l4_hit_local_l4.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80408000 00 offcore_response.other.l4_hit_local_l4.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100408000 00 offcore_response.other.l4_hit_local_l4.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40408000 00 offcore_response.other.supplier_none.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0028000 00 offcore_response.other.supplier_none.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40028000 00 offcore_response.demand_code_rd.l3_hit.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0004 00 offcore_response.demand_code_rd.l3_hit_e.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080004 00 offcore_response.demand_code_rd.l3_hit_m.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040004 00 offcore_response.demand_code_rd.l3_hit_s.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100004 00 offcore_response.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400004 00 offcore_response.demand_code_rd.l3_miss.snoop_hitm memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400004 00 offcore_response.demand_code_rd.l3_miss.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400004 00 offcore_response.demand_code_rd.l3_miss.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400004 00 offcore_response.demand_code_rd.l3_miss.spl_hit memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400004 00 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000004 00 offcore_response.demand_code_rd.l3_miss_local_dram.spl_hit memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000004 00 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400004 00 offcore_response.demand_data_rd.l3_hit.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0001 00 offcore_response.demand_data_rd.l3_hit_e.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080001 00 offcore_response.demand_data_rd.l3_hit_m.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040001 00 offcore_response.demand_data_rd.l3_hit_s.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100001 00 offcore_response.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400001 00 offcore_response.demand_data_rd.l3_miss.snoop_hitm memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400001 00 offcore_response.demand_data_rd.l3_miss.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400001 00 offcore_response.demand_data_rd.l3_miss.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400001 00 offcore_response.demand_data_rd.l3_miss.spl_hit memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400001 00 offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000001 00 offcore_response.demand_data_rd.l3_miss_local_dram.spl_hit memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000001 00 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400001 00 offcore_response.demand_rfo.l3_hit.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0002 00 offcore_response.demand_rfo.l3_hit_e.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080002 00 offcore_response.demand_rfo.l3_hit_m.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040002 00 offcore_response.demand_rfo.l3_hit_s.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100002 00 offcore_response.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400002 00 offcore_response.demand_rfo.l3_miss.snoop_hitm memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400002 00 offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400002 00 offcore_response.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400002 00 offcore_response.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400002 00 offcore_response.demand_rfo.l3_miss.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400002 00 offcore_response.demand_rfo.l3_miss.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400002 00 offcore_response.demand_rfo.l3_miss.spl_hit memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400002 00 offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitm memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000002 00 offcore_response.demand_rfo.l3_miss_local_dram.spl_hit memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000002 00 offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400002 00 offcore_response.demand_rfo.supplier_none.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020002 00 offcore_response.other.l3_hit.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C8000 00 offcore_response.other.l3_hit_e.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000088000 00 offcore_response.other.l3_hit_m.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000048000 00 offcore_response.other.l3_hit_s.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000108000 00 offcore_response.other.l3_miss.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC408000 00 offcore_response.other.l3_miss.snoop_hitm memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C408000 00 offcore_response.other.l3_miss.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C408000 00 offcore_response.other.l3_miss.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C408000 00 offcore_response.other.l3_miss.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC408000 00 offcore_response.other.l3_miss.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C408000 00 offcore_response.other.l3_miss.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C408000 00 offcore_response.other.l3_miss.spl_hit memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C408000 00 offcore_response.other.l3_miss_local_dram.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4008000 00 offcore_response.other.l3_miss_local_dram.spl_hit memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44008000 00 offcore_response.other.l4_hit_local_l4.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000408000 00 memory_disambiguation.history_reset other MEMORY_DISAMBIGUATION.HISTORY_RESET event=0x9,period=2000003,umask=0x1 00 unc_arb_trk_occupancy.all uncore interconnect Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic event=0x80,umask=0x1 01 unc_arb_trk_occupancy.data_read uncore interconnect Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk event=0x80,umask=0x2 01 unc_arb_trk_requests.all uncore interconnect UNC_ARB_TRK_REQUESTS.ALL event=0x81,umask=0x1 01 unc_arb_trk_requests.data_read uncore interconnect Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent event=0x81,umask=0x2 01 unc_arb_trk_requests.drd_direct uncore interconnect Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent event=0x81,umask=0x2 01 offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10491 00 offcore_response.all_data_rd.l3_hit.any_snoop cache Counts all demand & prefetch data reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0491 00 offcore_response.all_data_rd.l3_hit.hitm_other_core cache Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0491 00 offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0491 00 offcore_response.all_data_rd.l3_hit.no_snoop_needed cache Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0491 00 offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0491 00 offcore_response.all_pf_data_rd.any_response cache Counts all prefetch data reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10490 00 offcore_response.all_pf_data_rd.l3_hit.any_snoop cache Counts all prefetch data reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0490 00 offcore_response.all_pf_data_rd.l3_hit.hitm_other_core cache Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0490 00 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0490 00 offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0490 00 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0490 00 offcore_response.all_pf_rfo.any_response cache Counts prefetch RFOs that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10120 00 offcore_response.all_pf_rfo.l3_hit.any_snoop cache Counts prefetch RFOs that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0120 00 offcore_response.all_pf_rfo.l3_hit.hitm_other_core cache Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0120 00 offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0120 00 offcore_response.all_pf_rfo.l3_hit.no_snoop_needed cache Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0120 00 offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0120 00 offcore_response.all_rfo.any_response cache Counts all demand & prefetch RFOs that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10122 00 offcore_response.all_rfo.l3_hit.any_snoop cache Counts all demand & prefetch RFOs that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0122 00 offcore_response.all_rfo.l3_hit.hitm_other_core cache Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122 00 offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122 00 offcore_response.all_rfo.l3_hit.no_snoop_needed cache Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0122 00 offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0122 00 offcore_response.demand_code_rd.any_response cache Counts all demand code reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10004 00 offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 00 offcore_response.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 00 offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 00 offcore_response.demand_code_rd.l3_hit.no_snoop_needed cache Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004 00 offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0004 00 offcore_response.demand_data_rd.any_response cache Counts demand data reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 00 offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 00 offcore_response.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 00 offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 00 offcore_response.demand_data_rd.l3_hit.no_snoop_needed cache Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 00 offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 offcore_response.demand_rfo.any_response cache Counts all demand data writes (RFOs) that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 00 offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 00 offcore_response.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 00 offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 00 offcore_response.demand_rfo.l3_hit.no_snoop_needed cache Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002 00 offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0002 00 offcore_response.pf_l1d_and_sw.any_response cache Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400 00 offcore_response.pf_l1d_and_sw.l3_hit.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0400 00 offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0400 00 offcore_response.pf_l2_data_rd.any_response cache Counts prefetch (that bring data to L2) data reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010 00 offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010 00 offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010 00 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0010 00 offcore_response.pf_l2_rfo.any_response cache Counts all prefetch (that bring data to L2) RFOs that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020 00 offcore_response.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020 00 offcore_response.pf_l2_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020 00 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020 00 offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020 00 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0020 00 offcore_response.pf_l3_data_rd.any_response cache Counts all prefetch (that bring data to LLC only) data reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10080 00 offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080 00 offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0080 00 offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0080 00 offcore_response.pf_l3_rfo.any_response cache Counts all prefetch (that bring data to LLC only) RFOs that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100 00 offcore_response.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100 00 offcore_response.pf_l3_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0100 00 offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0100 00 offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0100 00 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0100 00 fp_arith_inst_retired.512b_packed_double floating point Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x40 00 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x80 00 Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events offcore_response.all_data_rd.l3_miss.any_snoop memory Counts all demand & prefetch data reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000491 00 offcore_response.all_data_rd.l3_miss.remote_hitm memory Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00491 00 offcore_response.all_data_rd.l3_miss.remote_hit_forward memory Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00491 00 offcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00491 00 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000491 00 offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800491 00 offcore_response.all_pf_data_rd.l3_miss.any_snoop memory Counts all prefetch data reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000490 00 offcore_response.all_pf_data_rd.l3_miss.remote_hitm memory Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00490 00 offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00490 00 offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00490 00 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000490 00 offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800490 00 offcore_response.all_pf_rfo.l3_miss.any_snoop memory Counts prefetch RFOs that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000120 00 offcore_response.all_pf_rfo.l3_miss.remote_hitm memory Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00120 00 offcore_response.all_pf_rfo.l3_miss.remote_hit_forward memory Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00120 00 offcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00120 00 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000120 00 offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800120 00 offcore_response.all_rfo.l3_miss.any_snoop memory Counts all demand & prefetch RFOs that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000122 00 offcore_response.all_rfo.l3_miss.remote_hitm memory Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00122 00 offcore_response.all_rfo.l3_miss.remote_hit_forward memory Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00122 00 offcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00122 00 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000122 00 offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800122 00 offcore_response.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000004 00 offcore_response.demand_code_rd.l3_miss.remote_hitm memory Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00004 00 offcore_response.demand_code_rd.l3_miss.remote_hit_forward memory Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00004 00 offcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00004 00 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000004 00 offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800004 00 offcore_response.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000001 00 offcore_response.demand_data_rd.l3_miss.remote_hitm memory Counts demand data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00001 00 offcore_response.demand_data_rd.l3_miss.remote_hit_forward memory Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00001 00 offcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00001 00 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000001 00 offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800001 00 offcore_response.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000002 00 offcore_response.demand_rfo.l3_miss.remote_hitm memory Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00002 00 offcore_response.demand_rfo.l3_miss.remote_hit_forward memory Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00002 00 offcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00002 00 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000002 00 offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800002 00 offcore_response.pf_l1d_and_sw.l3_miss.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000400 00 offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00400 00 offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00400 00 offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00400 00 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000400 00 offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800400 00 offcore_response.pf_l2_data_rd.l3_miss.any_snoop memory Counts prefetch (that bring data to L2) data reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000010 00 offcore_response.pf_l2_data_rd.l3_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00010 00 offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00010 00 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00010 00 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000010 00 offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800010 00 offcore_response.pf_l2_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to L2) RFOs that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000020 00 offcore_response.pf_l2_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00020 00 offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00020 00 offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00020 00 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000020 00 offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800020 00 offcore_response.pf_l3_data_rd.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000080 00 offcore_response.pf_l3_data_rd.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00080 00 offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00080 00 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00080 00 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000080 00 offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800080 00 offcore_response.pf_l3_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000100 00 offcore_response.pf_l3_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00100 00 offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00100 00 offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00100 00 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000100 00 offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800100 00 unc_cha_clockticks uncore cache Clockticks of the uncore caching & home agent (CHA) event=0 01 Counts clockticks of the clock controlling the uncore caching and home agent (CHA) unc_upi_rxl_crc_errors uncore interconnect CRC Errors Detected event=0xb 01 Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=0x8 01 Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs unc_iio_clockticks uncore io Clockticks of the IIO Traffic Controller event=0x1 01 Counts clockticks of the 1GHz trafiic controller clock in the IIO unit unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode event=0x85 01 Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of llc_misses.mmio_read uncore cache MMIO reads. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0xc001fe01,config1=0x40040e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_misses.mmio_write uncore cache MMIO writes. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0xc001fe01,config1=0x40041e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_misses.uncacheable uncore cache LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0xc001fe01,config1=0x40e33 01 TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_references.streaming_full uncore cache Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0xc001fe01,config1=0x41833 0164Bytes TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts llc_references.streaming_partial uncore cache Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0xc001fe01,config1=0x41a33 0164Bytes TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_clockticks uncore cache Uncore cache clock ticks event=0 01 unc_cha_llc_lookup.data_read_all uncore cache This event is deprecated event=0x34,umask=0x1fc1ff 11 unc_cha_llc_lookup.write_local uncore cache This event is deprecated event=0x34,umask=0x842ff 11 unc_i_coherent_ops.clflush uncore interconnect Coherent Ops : CLFlush event=0x10,umask=0x80 01 Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops : WbMtoI event=0x10,umask=0x40 01 Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP unc_i_transactions.writes uncore interconnect Inbound Transaction Count : Writes event=0x11,umask=0x2 01 Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry unc_m2m_prefcam_demand_merge.ch0_xpt uncore interconnect Demands Merged with CAMed Prefetches : XPT - Ch 0 event=0x74,umask=0x1 01 unc_m2m_prefcam_demand_merge.ch1_xpt uncore interconnect Demands Merged with CAMed Prefetches : XPT - Ch 1 event=0x74,umask=0x4 01 unc_m2m_prefcam_demand_merge.xpt_allch uncore interconnect Demands Merged with CAMed Prefetches : XPT - All Channels event=0x74,umask=0x15 01 unc_m2m_prefcam_demand_no_merge.ch0_xpt uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - Ch 0 event=0x75,umask=0x1 01 unc_m2m_prefcam_demand_no_merge.ch1_xpt uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - Ch 1 event=0x75,umask=0x4 01 unc_m2m_prefcam_demand_no_merge.xpt_allch uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - All Channels event=0x75,umask=0x15 01 llc_misses.pcie_read uncore io PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x4,ch_mask=0x1f 014Bytes Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 llc_misses.pcie_write uncore io PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x1,ch_mask=0x1f 014Bytes Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_clockticks uncore io Clockticks of the integrated IO (IIO) traffic controller event=0x1 01 unc_iio_data_req_of_cpu.mem_read.part0 uncore io PCI Express bandwidth reading at IIO, part 0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io PCI Express bandwidth reading at IIO, part 1 event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io PCI Express bandwidth reading at IIO, part 2 event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_read.part3 uncore io PCI Express bandwidth reading at IIO, part 3 event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x4 01 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part0 uncore io PCI Express bandwidth writing at IIO, part 0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io PCI Express bandwidth writing at IIO, part 1 event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io PCI Express bandwidth writing at IIO, part 2 event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_write.part3 uncore io PCI Express bandwidth writing at IIO, part 3 event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x1 01 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_m2p_clockticks uncore io Clockticks of the mesh to PCI (M2P) event=0x1 01 llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=0x4,umask=0xf 0164Bytes Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=0x4,umask=0x30 0164Bytes Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel unc_m_clockticks uncore memory Memory controller clock ticks event=0 01 Clockticks of the integrated memory controller (IMC) unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode event=0x85 01 Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_self_refresh uncore memory Cycles Memory is in self refresh power mode event=0x43 01 Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.page_miss uncore memory Pre-charges due to page misses event=0x2,umask=0xc 01 DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests) unc_m_pre_count.rd uncore memory Pre-charge for reads event=0x2,umask=0x4 01 DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.wr uncore memory Pre-charge for writes event=0x2,umask=0x8 01 DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_p_clockticks uncore power Clockticks of the power control unit (PCU) event=0 01 l2_rqsts.miss cache Read requests with true-miss in L2 cache event=0x24,period=200003,umask=0x3f 00 Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses l2_rqsts.references cache All accesses to L2 cache event=0x24,period=200003,umask=0xff 00 Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses mem_load_l3_hit_retired.xsnp_fwd cache Snoop hit a modified(HITM) or clean line(HIT_W_FWD) in another on-pkg core which forwarded the data back due to a retired load instruction Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x4 00 Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD) Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_no_fwd cache Snoop hit without forwarding in another on-pkg core due to a retired load instruction, data was supplied by the L3 Supports address when precise (Precise event) event=0xd2,period=20011,umask=0x2 00 Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD) Supports address when precise (Precise event) mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) event=0xd4,period=100007,umask=0x4 00 Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access Supports address when precise (Precise event) ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 00 offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=1000003,umask=0x8 00 Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=1000003,umask=0x8 00 Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=1000003,umask=0x4 00 Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache Demand Data Read transactions pending for off-core. Highly correlated event=0x60,period=1000003,umask=0x1 00 Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core sq_misc.sq_full cache Cycles the superQ cannot take any more entries event=0xf4,period=100003,umask=0x4 00 Counts the cycles for which the thread is active and the superQ cannot take any more entries exe_activity.bound_on_loads pipeline Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle event=0xa6,cmask=5,period=2000003,umask=0x21 00 Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle inst_retired.nop pipeline Retired NOP instructions (Precise event) event=0xc0,period=2000003,umask=0x2 00 Counts all retired NOP or ENDBR32/64 instructions (Precise event) ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=0x7,period=100003,umask=0x1 00 Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=100003,umask=0x2 00 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide unc_arb_coh_trk_requests.all uncore interconnect UNC_ARB_COH_TRK_REQUESTS.ALL event=0x84,umask=0x1 01 unc_arb_dat_requests.rd uncore interconnect This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD event=0x81,umask=0x2 01 unc_arb_ifa_occupancy.all uncore interconnect This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL event=0x85,umask=0x1 01 unc_arb_trk_occupancy.all uncore interconnect Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=0x1 01 unc_mc0_rdcas_count_freerun uncore memory Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x20 01 unc_mc0_total_reqcount_freerun uncore memory Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x10 01 unc_mc0_wrcas_count_freerun uncore memory Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x30 01 unc_mc1_rdcas_count_freerun uncore memory Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x20 01 unc_mc1_total_reqcount_freerun uncore memory Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x10 01 unc_mc1_wrcas_count_freerun uncore memory Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x30 01 dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=0x4 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x49,period=100003,umask=0x2 00 Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault offcore_requests.any cache All offcore requests event=0xb0,period=100000,umask=0x80 00 offcore_requests.any.read cache Offcore read requests event=0xb0,period=100000,umask=0x8 00 offcore_requests.any.rfo cache Offcore RFO requests event=0xb0,period=100000,umask=0x10 00 offcore_requests.demand.read_code cache Offcore demand code read requests event=0xb0,period=100000,umask=0x2 00 offcore_requests.demand.read_data cache Offcore demand data read requests event=0xb0,period=100000,umask=0x1 00 offcore_requests.demand.rfo cache Offcore demand RFO requests event=0xb0,period=100000,umask=0x4 00 offcore_requests_outstanding.any.read cache Outstanding offcore reads event=0x60,period=2000000,umask=0x8 00 offcore_requests_outstanding.any.read_not_empty cache Cycles offcore reads busy event=0x60,cmask=1,period=2000000,umask=0x8 00 offcore_requests_outstanding.demand.read_code cache Outstanding offcore demand code reads event=0x60,period=2000000,umask=0x2 00 offcore_requests_outstanding.demand.read_code_not_empty cache Cycles offcore demand code read busy event=0x60,cmask=1,period=2000000,umask=0x2 00 offcore_requests_outstanding.demand.read_data cache Outstanding offcore demand data reads event=0x60,period=2000000,umask=0x1 00 offcore_requests_outstanding.demand.read_data_not_empty cache Cycles offcore demand data read busy event=0x60,cmask=1,period=2000000,umask=0x1 00 offcore_requests_outstanding.demand.rfo cache Outstanding offcore demand RFOs event=0x60,period=2000000,umask=0x4 00 offcore_requests_outstanding.demand.rfo_not_empty cache Cycles offcore demand RFOs busy event=0x60,cmask=1,period=2000000,umask=0x4 00 offcore_response.any_data.all_local_dram_and_remote_cache_hit cache REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5011 00 offcore_response.any_data.any_cache_dram cache REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f11 00 offcore_response.any_data.any_location cache REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff11 00 offcore_response.any_data.io_csr_mmio cache REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8011 00 offcore_response.any_data.llc_hit_no_other_core cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x111 00 offcore_response.any_data.llc_hit_other_core_hit cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x211 00 offcore_response.any_data.llc_hit_other_core_hitm cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x411 00 offcore_response.any_data.local_cache cache REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x711 00 offcore_response.any_data.local_dram_and_remote_cache_hit cache REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1011 00 offcore_response.any_data.remote_cache_hitm cache REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x811 00 offcore_response.any_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5044 00 offcore_response.any_ifetch.any_cache_dram cache REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f44 00 offcore_response.any_ifetch.any_location cache REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff44 00 offcore_response.any_ifetch.io_csr_mmio cache REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8044 00 offcore_response.any_ifetch.llc_hit_no_other_core cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x144 00 offcore_response.any_ifetch.llc_hit_other_core_hit cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x244 00 offcore_response.any_ifetch.llc_hit_other_core_hitm cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x444 00 offcore_response.any_ifetch.local_cache cache REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x744 00 offcore_response.any_ifetch.local_dram_and_remote_cache_hit cache REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1044 00 offcore_response.any_ifetch.remote_cache_hitm cache REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x844 00 offcore_response.any_request.all_local_dram_and_remote_cache_hit cache REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x50ff 00 offcore_response.any_request.any_cache_dram cache REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7fff 00 offcore_response.any_request.any_location cache REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xffff 00 offcore_response.any_request.io_csr_mmio cache REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x80ff 00 offcore_response.any_request.llc_hit_no_other_core cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1ff 00 offcore_response.any_request.llc_hit_other_core_hit cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2ff 00 offcore_response.any_request.llc_hit_other_core_hitm cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4ff 00 offcore_response.any_request.local_cache cache REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7ff 00 offcore_response.any_request.local_dram_and_remote_cache_hit cache REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x10ff 00 offcore_response.any_request.remote_cache_hitm cache REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8ff 00 offcore_response.any_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5022 00 offcore_response.any_rfo.any_cache_dram cache REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f22 00 offcore_response.any_rfo.any_location cache REQUEST = ANY RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff22 00 offcore_response.any_rfo.io_csr_mmio cache REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8022 00 offcore_response.any_rfo.llc_hit_no_other_core cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x122 00 offcore_response.any_rfo.llc_hit_other_core_hit cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x222 00 offcore_response.any_rfo.llc_hit_other_core_hitm cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x422 00 offcore_response.any_rfo.local_cache cache REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x722 00 offcore_response.any_rfo.local_dram_and_remote_cache_hit cache REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1022 00 offcore_response.any_rfo.remote_cache_hitm cache REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x822 00 offcore_response.corewb.all_local_dram_and_remote_cache_hit cache REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5008 00 offcore_response.corewb.any_cache_dram cache REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f08 00 offcore_response.corewb.any_location cache REQUEST = CORE_WB and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff08 00 offcore_response.corewb.io_csr_mmio cache REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8008 00 offcore_response.corewb.llc_hit_no_other_core cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x108 00 offcore_response.corewb.llc_hit_other_core_hit cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x208 00 offcore_response.corewb.llc_hit_other_core_hitm cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x408 00 offcore_response.corewb.local_cache cache REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x708 00 offcore_response.corewb.local_dram_and_remote_cache_hit cache REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1008 00 offcore_response.corewb.remote_cache_hitm cache REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x808 00 offcore_response.data_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5077 00 offcore_response.data_ifetch.any_cache_dram cache REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f77 00 offcore_response.data_ifetch.any_location cache REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff77 00 offcore_response.data_ifetch.io_csr_mmio cache REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8077 00 offcore_response.data_ifetch.llc_hit_no_other_core cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x177 00 offcore_response.data_ifetch.llc_hit_other_core_hit cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x277 00 offcore_response.data_ifetch.llc_hit_other_core_hitm cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x477 00 offcore_response.data_ifetch.local_cache cache REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x777 00 offcore_response.data_ifetch.local_dram_and_remote_cache_hit cache REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1077 00 offcore_response.data_ifetch.remote_cache_hitm cache REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x877 00 offcore_response.data_in.all_local_dram_and_remote_cache_hit cache REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5033 00 offcore_response.data_in.any_cache_dram cache REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f33 00 offcore_response.data_in.any_location cache REQUEST = DATA_IN and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff33 00 offcore_response.data_in.io_csr_mmio cache REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8033 00 offcore_response.data_in.llc_hit_no_other_core cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x133 00 offcore_response.data_in.llc_hit_other_core_hit cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x233 00 offcore_response.data_in.llc_hit_other_core_hitm cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x433 00 offcore_response.data_in.local_cache cache REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x733 00 offcore_response.data_in.local_dram_and_remote_cache_hit cache REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1033 00 offcore_response.data_in.remote_cache_hitm cache REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x833 00 offcore_response.demand_data.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5003 00 offcore_response.demand_data.any_cache_dram cache REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f03 00 offcore_response.demand_data.any_location cache REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff03 00 offcore_response.demand_data.io_csr_mmio cache REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8003 00 offcore_response.demand_data.llc_hit_no_other_core cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x103 00 offcore_response.demand_data.llc_hit_other_core_hit cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x203 00 offcore_response.demand_data.llc_hit_other_core_hitm cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x403 00 offcore_response.demand_data.local_cache cache REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x703 00 offcore_response.demand_data.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1003 00 offcore_response.demand_data.remote_cache_hitm cache REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x803 00 offcore_response.demand_data_rd.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5001 00 offcore_response.demand_data_rd.any_cache_dram cache REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f01 00 offcore_response.demand_data_rd.any_location cache REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff01 00 offcore_response.demand_data_rd.io_csr_mmio cache REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8001 00 offcore_response.demand_data_rd.llc_hit_no_other_core cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x101 00 offcore_response.demand_data_rd.llc_hit_other_core_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x201 00 offcore_response.demand_data_rd.llc_hit_other_core_hitm cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x401 00 offcore_response.demand_data_rd.local_cache cache REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x701 00 offcore_response.demand_data_rd.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1001 00 offcore_response.demand_data_rd.remote_cache_hitm cache REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x801 00 offcore_response.demand_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5004 00 offcore_response.demand_ifetch.any_cache_dram cache REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f04 00 offcore_response.demand_ifetch.any_location cache REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff04 00 offcore_response.demand_ifetch.io_csr_mmio cache REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8004 00 offcore_response.demand_ifetch.llc_hit_no_other_core cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x104 00 offcore_response.demand_ifetch.llc_hit_other_core_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x204 00 offcore_response.demand_ifetch.llc_hit_other_core_hitm cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x404 00 offcore_response.demand_ifetch.local_cache cache REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x704 00 offcore_response.demand_ifetch.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1004 00 offcore_response.demand_ifetch.remote_cache_hitm cache REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x804 00 offcore_response.demand_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5002 00 offcore_response.demand_rfo.any_cache_dram cache REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f02 00 offcore_response.demand_rfo.any_location cache REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff02 00 offcore_response.demand_rfo.io_csr_mmio cache REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8002 00 offcore_response.demand_rfo.llc_hit_no_other_core cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x102 00 offcore_response.demand_rfo.llc_hit_other_core_hit cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x202 00 offcore_response.demand_rfo.llc_hit_other_core_hitm cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x402 00 offcore_response.demand_rfo.local_cache cache REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x702 00 offcore_response.demand_rfo.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1002 00 offcore_response.demand_rfo.remote_cache_hitm cache REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x802 00 offcore_response.other.all_local_dram_and_remote_cache_hit cache REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5080 00 offcore_response.other.any_cache_dram cache REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f80 00 offcore_response.other.any_location cache REQUEST = OTHER and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff80 00 offcore_response.other.io_csr_mmio cache REQUEST = OTHER and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8080 00 offcore_response.other.llc_hit_no_other_core cache REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x180 00 offcore_response.other.llc_hit_other_core_hit cache REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x280 00 offcore_response.other.llc_hit_other_core_hitm cache REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x480 00 offcore_response.other.local_cache cache REQUEST = OTHER and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x780 00 offcore_response.other.local_dram_and_remote_cache_hit cache REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1080 00 offcore_response.other.remote_cache_hitm cache REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x880 00 offcore_response.pf_data.all_local_dram_and_remote_cache_hit cache REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5050 00 offcore_response.pf_data.any_cache_dram cache REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f50 00 offcore_response.pf_data.any_location cache REQUEST = PF_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff50 00 offcore_response.pf_data.io_csr_mmio cache REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8050 00 offcore_response.pf_data.llc_hit_no_other_core cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x150 00 offcore_response.pf_data.llc_hit_other_core_hit cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x250 00 offcore_response.pf_data.llc_hit_other_core_hitm cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x450 00 offcore_response.pf_data.local_cache cache REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x750 00 offcore_response.pf_data.local_dram_and_remote_cache_hit cache REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1050 00 offcore_response.pf_data.remote_cache_hitm cache REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x850 00 offcore_response.pf_data_rd.all_local_dram_and_remote_cache_hit cache REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5010 00 offcore_response.pf_data_rd.any_cache_dram cache REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f10 00 offcore_response.pf_data_rd.any_location cache REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff10 00 offcore_response.pf_data_rd.io_csr_mmio cache REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8010 00 offcore_response.pf_data_rd.llc_hit_no_other_core cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x110 00 offcore_response.pf_data_rd.llc_hit_other_core_hit cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x210 00 offcore_response.pf_data_rd.llc_hit_other_core_hitm cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x410 00 offcore_response.pf_data_rd.local_cache cache REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x710 00 offcore_response.pf_data_rd.local_dram_and_remote_cache_hit cache REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1010 00 offcore_response.pf_data_rd.remote_cache_hitm cache REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x810 00 offcore_response.pf_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5040 00 offcore_response.pf_ifetch.any_cache_dram cache REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f40 00 offcore_response.pf_ifetch.any_location cache REQUEST = PF_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff40 00 offcore_response.pf_ifetch.io_csr_mmio cache REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8040 00 offcore_response.pf_ifetch.llc_hit_no_other_core cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x140 00 offcore_response.pf_ifetch.llc_hit_other_core_hit cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x240 00 offcore_response.pf_ifetch.llc_hit_other_core_hitm cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x440 00 offcore_response.pf_ifetch.local_cache cache REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x740 00 offcore_response.pf_ifetch.local_dram_and_remote_cache_hit cache REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1040 00 offcore_response.pf_ifetch.remote_cache_hitm cache REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x840 00 offcore_response.pf_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5020 00 offcore_response.pf_rfo.any_cache_dram cache REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f20 00 offcore_response.pf_rfo.any_location cache REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff20 00 offcore_response.pf_rfo.io_csr_mmio cache REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8020 00 offcore_response.pf_rfo.llc_hit_no_other_core cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x120 00 offcore_response.pf_rfo.llc_hit_other_core_hit cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x220 00 offcore_response.pf_rfo.llc_hit_other_core_hitm cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x420 00 offcore_response.pf_rfo.local_cache cache REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x720 00 offcore_response.pf_rfo.local_dram_and_remote_cache_hit cache REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1020 00 offcore_response.pf_rfo.remote_cache_hitm cache REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x820 00 offcore_response.prefetch.all_local_dram_and_remote_cache_hit cache REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5070 00 offcore_response.prefetch.any_cache_dram cache REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f70 00 offcore_response.prefetch.any_location cache REQUEST = PREFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff70 00 offcore_response.prefetch.io_csr_mmio cache REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8070 00 offcore_response.prefetch.llc_hit_no_other_core cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x170 00 offcore_response.prefetch.llc_hit_other_core_hit cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x270 00 offcore_response.prefetch.llc_hit_other_core_hitm cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x470 00 offcore_response.prefetch.local_cache cache REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x770 00 offcore_response.prefetch.local_dram_and_remote_cache_hit cache REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1070 00 offcore_response.prefetch.remote_cache_hitm cache REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x870 00 sq_misc.lru_hints cache Super Queue LRU hints sent to LLC event=0xf4,period=2000000,umask=0x4 00 misalign_mem_ref.store memory Misaligned store references event=0x5,period=200000,umask=0x2 00 offcore_response.any_data.any_dram_and_remote_fwd memory REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3011 00 offcore_response.any_data.any_llc_miss memory REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf811 00 offcore_response.any_data.other_local_dram memory REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4011 00 offcore_response.any_data.remote_dram memory REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2011 00 offcore_response.any_ifetch.any_dram_and_remote_fwd memory REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3044 00 offcore_response.any_ifetch.any_llc_miss memory REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf844 00 offcore_response.any_ifetch.other_local_dram memory REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4044 00 offcore_response.any_ifetch.remote_dram memory REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2044 00 offcore_response.any_request.any_dram_and_remote_fwd memory REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x30ff 00 offcore_response.any_request.any_llc_miss memory REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf8ff 00 offcore_response.any_request.other_local_dram memory REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x40ff 00 offcore_response.any_request.remote_dram memory REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x20ff 00 offcore_response.any_rfo.any_dram_and_remote_fwd memory REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3022 00 offcore_response.any_rfo.any_llc_miss memory REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf822 00 offcore_response.any_rfo.other_local_dram memory REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4022 00 offcore_response.any_rfo.remote_dram memory REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2022 00 offcore_response.corewb.any_dram_and_remote_fwd memory REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3008 00 offcore_response.corewb.any_llc_miss memory REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf808 00 offcore_response.corewb.other_local_dram memory REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4008 00 offcore_response.corewb.remote_dram memory REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2008 00 offcore_response.data_ifetch.any_dram_and_remote_fwd memory REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3077 00 offcore_response.data_ifetch.any_llc_miss memory REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf877 00 offcore_response.data_ifetch.other_local_dram memory REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4077 00 offcore_response.data_ifetch.remote_dram memory REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2077 00 offcore_response.data_in.any_dram_and_remote_fwd memory REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3033 00 offcore_response.data_in.any_llc_miss memory REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf833 00 offcore_response.data_in.other_local_dram memory REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4033 00 offcore_response.data_in.remote_dram memory REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2033 00 offcore_response.demand_data.any_dram_and_remote_fwd memory REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3003 00 offcore_response.demand_data.any_llc_miss memory REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf803 00 offcore_response.demand_data.other_local_dram memory REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4003 00 offcore_response.demand_data.remote_dram memory REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2003 00 offcore_response.demand_data_rd.any_dram_and_remote_fwd memory REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3001 00 offcore_response.demand_data_rd.any_llc_miss memory REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf801 00 offcore_response.demand_data_rd.other_local_dram memory REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4001 00 offcore_response.demand_data_rd.remote_dram memory REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2001 00 offcore_response.demand_ifetch.any_dram_and_remote_fwd memory REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3004 00 offcore_response.demand_ifetch.any_llc_miss memory REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf804 00 offcore_response.demand_ifetch.other_local_dram memory REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4004 00 offcore_response.demand_ifetch.remote_dram memory REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2004 00 offcore_response.demand_rfo.any_dram_and_remote_fwd memory REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3002 00 offcore_response.demand_rfo.any_llc_miss memory REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf802 00 offcore_response.demand_rfo.other_local_dram memory REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4002 00 offcore_response.demand_rfo.remote_dram memory REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2002 00 offcore_response.other.any_dram_and_remote_fwd memory REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3080 00 offcore_response.other.any_llc_miss memory REQUEST = OTHER and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf880 00 offcore_response.other.other_local_dram memory REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4080 00 offcore_response.other.remote_dram memory REQUEST = OTHER and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2080 00 offcore_response.pf_data.any_dram_and_remote_fwd memory REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3050 00 offcore_response.pf_data.any_llc_miss memory REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf850 00 offcore_response.pf_data.other_local_dram memory REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4050 00 offcore_response.pf_data.remote_dram memory REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2050 00 offcore_response.pf_data_rd.any_dram_and_remote_fwd memory REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3010 00 offcore_response.pf_data_rd.any_llc_miss memory REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf810 00 offcore_response.pf_data_rd.other_local_dram memory REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4010 00 offcore_response.pf_data_rd.remote_dram memory REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2010 00 offcore_response.pf_ifetch.any_dram_and_remote_fwd memory REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3040 00 offcore_response.pf_ifetch.any_llc_miss memory REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf840 00 offcore_response.pf_ifetch.other_local_dram memory REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4040 00 offcore_response.pf_ifetch.remote_dram memory REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2040 00 offcore_response.pf_rfo.any_dram_and_remote_fwd memory REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3020 00 offcore_response.pf_rfo.any_llc_miss memory REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf820 00 offcore_response.pf_rfo.other_local_dram memory REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4020 00 offcore_response.pf_rfo.remote_dram memory REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2020 00 offcore_response.prefetch.any_dram_and_remote_fwd memory REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3070 00 offcore_response.prefetch.any_llc_miss memory REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf870 00 offcore_response.prefetch.other_local_dram memory REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4070 00 offcore_response.prefetch.remote_dram memory REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2070 00 load_block.overlap_store other Loads that partially overlap an earlier store event=0x3,period=200000,umask=0x2 00 snoopq_requests.code other Snoop code requests event=0xb4,period=100000,umask=0x4 00 snoopq_requests.data other Snoop data requests event=0xb4,period=100000,umask=0x1 00 snoopq_requests.invalidate other Snoop invalidate requests event=0xb4,period=100000,umask=0x2 00 snoopq_requests_outstanding.code other Outstanding snoop code requests event=0xb3,period=2000000,umask=0x4 00 snoopq_requests_outstanding.code_not_empty other Cycles snoop code requests queued event=0xb3,cmask=1,period=2000000,umask=0x4 00 snoopq_requests_outstanding.data other Outstanding snoop data requests event=0xb3,period=2000000,umask=0x1 00 snoopq_requests_outstanding.data_not_empty other Cycles snoop data requests queued event=0xb3,cmask=1,period=2000000,umask=0x1 00 snoopq_requests_outstanding.invalidate other Outstanding snoop invalidate requests event=0xb3,period=2000000,umask=0x2 00 snoopq_requests_outstanding.invalidate_not_empty other Cycles snoop invalidate requests queued event=0xb3,cmask=1,period=2000000,umask=0x2 00 br_misp_retired.all_branches pipeline Mispredicted retired branch instructions (Precise Event) event=0xc5,period=20000,umask=0x4 00 br_misp_retired.conditional pipeline Mispredicted conditional retired branches (Precise Event) event=0xc5,period=20000,umask=0x1 00 dtlb_load_misses.large_walk_completed virtual memory DTLB load miss large page walks event=0x8,period=200000,umask=0x80 00 dtlb_load_misses.walk_cycles virtual memory DTLB load miss page walk cycles event=0x8,period=200000,umask=0x4 00 dtlb_misses.large_walk_completed virtual memory DTLB miss large page walks event=0x49,period=200000,umask=0x80 00 dtlb_misses.pde_miss virtual memory DTLB misses caused by low part of address event=0x49,period=200000,umask=0x20 00 dtlb_misses.walk_cycles virtual memory DTLB miss page walk cycles event=0x49,period=2000000,umask=0x4 00 ept.walk_cycles virtual memory Extended Page Table walk cycles event=0x4f,period=2000000,umask=0x10 00 itlb_misses.large_walk_completed virtual memory ITLB miss large page walks event=0x85,period=200000,umask=0x80 00 itlb_misses.walk_cycles virtual memory ITLB miss page walk cycles event=0x85,period=2000000,umask=0x4 00 mem_uncore_retired.local_dram cache Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) event=0xf,period=10000,umask=0x10 00 mem_uncore_retired.remote_dram cache Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) event=0xf,period=10000,umask=0x20 00 offcore_requests.uncached_mem cache Offcore uncached memory accesses event=0xb0,period=100000,umask=0x20 00 offcore_response.any_data.local_cache_dram cache Offcore data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2711 00 offcore_response.any_data.remote_cache_dram cache Offcore data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5811 00 offcore_response.any_ifetch.local_cache_dram cache Offcore code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2744 00 offcore_response.any_ifetch.remote_cache_dram cache Offcore code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5844 00 offcore_response.any_request.local_cache_dram cache Offcore requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x27FF 00 offcore_response.any_request.remote_cache_dram cache Offcore requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x58FF 00 offcore_response.any_rfo.local_cache_dram cache Offcore RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2722 00 offcore_response.any_rfo.remote_cache_dram cache Offcore RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5822 00 offcore_response.corewb.local_cache_dram cache Offcore writebacks to the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2708 00 offcore_response.corewb.remote_cache_dram cache Offcore writebacks to a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5808 00 offcore_response.data_ifetch.local_cache_dram cache Offcore code or data read requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2777 00 offcore_response.data_ifetch.remote_cache_dram cache Offcore code or data read requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5877 00 offcore_response.data_in.local_cache_dram cache Offcore request = all data, response = local cache or dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2733 00 offcore_response.data_in.remote_cache_dram cache Offcore request = all data, response = remote cache or dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5833 00 offcore_response.demand_data.local_cache_dram cache Offcore demand data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2703 00 offcore_response.demand_data.remote_cache_dram cache Offcore demand data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5803 00 offcore_response.demand_data_rd.local_cache_dram cache Offcore demand data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2701 00 offcore_response.demand_data_rd.remote_cache_dram cache Offcore demand data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5801 00 offcore_response.demand_ifetch.local_cache_dram cache Offcore demand code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2704 00 offcore_response.demand_ifetch.remote_cache_dram cache Offcore demand code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5804 00 offcore_response.demand_rfo.local_cache_dram cache Offcore demand RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2702 00 offcore_response.demand_rfo.remote_cache_dram cache Offcore demand RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5802 00 offcore_response.other.local_cache_dram cache Offcore other requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2780 00 offcore_response.other.remote_cache_dram cache Offcore other requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5880 00 offcore_response.pf_data.any_cache_dram cache Offcore prefetch data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F50 00 offcore_response.pf_data.any_location cache All offcore prefetch data requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF50 00 offcore_response.pf_data.io_csr_mmio cache Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8050 00 offcore_response.pf_data.llc_hit_no_other_core cache Offcore prefetch data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x150 00 offcore_response.pf_data.llc_hit_other_core_hit cache Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x250 00 offcore_response.pf_data.llc_hit_other_core_hitm cache Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x450 00 offcore_response.pf_data.local_cache cache Offcore prefetch data requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x750 00 offcore_response.pf_data.local_cache_dram cache Offcore prefetch data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2750 00 offcore_response.pf_data.remote_cache cache Offcore prefetch data requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1850 00 offcore_response.pf_data.remote_cache_dram cache Offcore prefetch data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5850 00 offcore_response.pf_data.remote_cache_hit cache Offcore prefetch data requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1050 00 offcore_response.pf_data.remote_cache_hitm cache Offcore prefetch data requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x850 00 offcore_response.pf_data_rd.local_cache_dram cache Offcore prefetch data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2710 00 offcore_response.pf_data_rd.remote_cache_dram cache Offcore prefetch data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5810 00 offcore_response.pf_ifetch.local_cache_dram cache Offcore prefetch code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2740 00 offcore_response.pf_ifetch.remote_cache_dram cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5840 00 offcore_response.pf_rfo.local_cache_dram cache Offcore prefetch RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2720 00 offcore_response.pf_rfo.remote_cache_dram cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5820 00 offcore_response.prefetch.local_cache_dram cache Offcore prefetch requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2770 00 offcore_response.prefetch.remote_cache_dram cache Offcore prefetch requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5870 00 offcore_response.any_data.local_dram memory Offcore data reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2011 00 offcore_response.any_data.remote_dram memory Offcore data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4011 00 offcore_response.any_ifetch.local_dram memory Offcore code reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2044 00 offcore_response.any_ifetch.remote_dram memory Offcore code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4044 00 offcore_response.any_request.local_dram memory Offcore requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x20FF 00 offcore_response.any_request.remote_dram memory Offcore requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x40FF 00 offcore_response.any_rfo.local_dram memory Offcore RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2022 00 offcore_response.any_rfo.remote_dram memory Offcore RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4022 00 offcore_response.corewb.local_dram memory Offcore writebacks to the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2008 00 offcore_response.corewb.remote_dram memory Offcore writebacks to a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4008 00 offcore_response.data_ifetch.local_dram memory Offcore code or data read requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2077 00 offcore_response.data_ifetch.remote_dram memory Offcore code or data read requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4077 00 offcore_response.data_in.local_dram memory Offcore data reads, RFOs, and prefetches satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2033 00 offcore_response.data_in.remote_dram memory Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4033 00 offcore_response.demand_data.local_dram memory Offcore demand data requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2003 00 offcore_response.demand_data.remote_dram memory Offcore demand data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4003 00 offcore_response.demand_data_rd.local_dram memory Offcore demand data reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2001 00 offcore_response.demand_data_rd.remote_dram memory Offcore demand data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4001 00 offcore_response.demand_ifetch.local_dram memory Offcore demand code reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2004 00 offcore_response.demand_ifetch.remote_dram memory Offcore demand code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4004 00 offcore_response.demand_rfo.local_dram memory Offcore demand RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2002 00 offcore_response.demand_rfo.remote_dram memory Offcore demand RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4002 00 offcore_response.other.remote_dram memory Offcore other requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4080 00 offcore_response.pf_data.any_dram memory Offcore prefetch data requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6050 00 offcore_response.pf_data.any_llc_miss memory Offcore prefetch data requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF850 00 offcore_response.pf_data.local_dram memory Offcore prefetch data requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2050 00 offcore_response.pf_data.remote_dram memory Offcore prefetch data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4050 00 offcore_response.pf_data_rd.local_dram memory Offcore prefetch data reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2010 00 offcore_response.pf_data_rd.remote_dram memory Offcore prefetch data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4010 00 offcore_response.pf_ifetch.local_dram memory Offcore prefetch code reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2040 00 offcore_response.pf_ifetch.remote_dram memory Offcore prefetch code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4040 00 offcore_response.pf_rfo.local_dram memory Offcore prefetch RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2020 00 offcore_response.pf_rfo.remote_dram memory Offcore prefetch RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4020 00 offcore_response.prefetch.local_dram memory Offcore prefetch requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2070 00 offcore_response.prefetch.remote_dram memory Offcore prefetch requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4070 00 mem_uncore_retired.local_dram_and_remote_cache_hit cache Load instructions retired local dram and remote cache HIT data sources (Precise Event) event=0xf,period=20000,umask=0x8 00 mem_uncore_retired.local_hitm cache Load instructions retired that HIT modified data in sibling core (Precise Event) event=0xf,period=40000,umask=0x2 00 mem_uncore_retired.remote_hitm cache Retired loads that hit remote socket in modified state (Precise Event) event=0xf,period=40000,umask=0x4 00 bpu_clears.early pipeline Early Branch Prediction Unit clears event=0xe8,period=2000000,umask=0x1 00 uops_executed.core_stall_count pipeline Uops executed on any port (core count) event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f 00 uops_executed.core_stall_count_no_port5 pipeline Uops executed on ports 0-4 (core count) event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f 00 dtlb_misses.pde_miss virtual memory DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE event=0x49,period=200000,umask=0x20 00 CPI 1 / IPC 00IPC group1 inst_retired.any / cpu_clk_unhalted.thread 00Frontend_Bound_SMT idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk))) 00dcache_miss_cpi l1d\-loads\-misses / inst_retired.any 00icache_miss_cycles l1i\-loads\-misses / inst_retired.any 00cache_miss_cycles group1 dcache_miss_cpi + icache_miss_cycles 00DCache_L2_All_Hits l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit 00DCache_L2_All_Miss max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss 00DCache_L2_All DCache_L2_All_Hits + DCache_L2_All_Miss 00DCache_L2_Hits d_ratio(DCache_L2_All_Hits, DCache_L2_All) 00DCache_L2_Misses d_ratio(DCache_L2_All_Miss, DCache_L2_All) 00M1 ipc + M2 00M2 ipc + M1 00M3 1 / M3 00L1D_Cache_Fill_BW 64 * l1d.replacement / 1e9 / duration_time 00C10_Pkg_Residency Power cstate_pkg@c10\-residency@ / TSC C10 residency percent per package 100% 00C1_Core_Residency Power cstate_core@c1\-residency@ / TSC C1 residency percent per core 100% 00C2_Pkg_Residency Power cstate_pkg@c2\-residency@ / TSC C2 residency percent per package 100% 00C3_Pkg_Residency Power cstate_pkg@c3\-residency@ / TSC C3 residency percent per package 100% 00C6_Core_Residency Power cstate_core@c6\-residency@ / TSC C6 residency percent per core 100% 00C6_Pkg_Residency Power cstate_pkg@c6\-residency@ / TSC C6 residency percent per package 100% 00C7_Core_Residency Power cstate_core@c7\-residency@ / TSC C7 residency percent per core 100% 00C7_Pkg_Residency Power cstate_pkg@c7\-residency@ / TSC C7 residency percent per package 100% 00C8_Pkg_Residency Power cstate_pkg@c8\-residency@ / TSC C8 residency percent per package 100% 00C9_Pkg_Residency Power cstate_pkg@c9\-residency@ / TSC C9 residency percent per package 100% 00smi_cycles smi ((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0) smi_cycles > 0.1 Percentage of cycles spent in System Management Interrupts 100% 00smi_num smi msr@smi@ Number of SMI interrupts 1SMI# 00tsx_aborted_cycles transaction (max(cycles\-t - cycles\-ct, 0) / cycles if has_event(cycles\-t) else 0) Percentage of cycles in aborted transactions 100% 00tsx_cycles_per_elision transaction (cycles\-t / el\-start if has_event(el\-start) else 0) Number of cycles within a transaction divided by the number of elisions 1cycles / elision 00tsx_cycles_per_transaction transaction (cycles\-t / tx\-start if has_event(cycles\-t) else 0) Number of cycles within a transaction divided by the number of transactions 1cycles / transaction 00tsx_transactional_cycles transaction (cycles\-t / cycles if has_event(cycles\-t) else 0) Percentage of cycles within a transaction region 100% 00cpu_atom tma_alloc_restriction TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / tma_info_core_slots tma_alloc_restriction > 0.1 Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions 100% 00tma_backend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_BE_BOUND.ALL@ / tma_info_core_slots tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based 100% TopdownL1;Default TopdownL1 00tma_backend_bound_aux Default;TopdownL1;tma_L1_group tma_backend_bound tma_backend_bound_aux > 0.2 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation 100% TopdownL1;Default TopdownL1 00tma_bad_speculation Default;TopdownL1;tma_L1_group (tma_info_core_slots - (cpu_atom@TOPDOWN_FE_BOUND.ALL@ + cpu_atom@TOPDOWN_BE_BOUND.ALL@ + cpu_atom@TOPDOWN_RETIRING.ALL@)) / tma_info_core_slots tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100% TopdownL1;Default TopdownL1 00tma_base TopdownL2;tma_L2_group;tma_retiring_group (cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RETIRED.MS@) / tma_info_core_slots tma_base > 0.6 Counts the number of uops that are not from the microsequencer 100% TopdownL2 00tma_branch_detect TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / tma_info_core_slots tma_branch_detect > 0.05 Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100% 00tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / tma_info_core_slots tma_branch_mispredicts > 0.05 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts 100% TopdownL2 00tma_branch_resteer TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / tma_info_core_slots tma_branch_resteer > 0.05 Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch 100% 00tma_cisc TopdownL3;tma_L3_group;tma_fetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.CISC@ / tma_info_core_slots tma_cisc > 0.05 Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS) 100% 00tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group max(0, tma_backend_bound - tma_memory_bound) tma_core_bound > 0.1 Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls 100% TopdownL2 00tma_decode TopdownL3;tma_L3_group;tma_fetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / tma_info_core_slots tma_decode > 0.05 Counts the number of issue slots that were not delivered by the frontend due to decode stalls 100% 00tma_disambiguation TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / cpu_atom@MACHINE_CLEARS.SLOW@) tma_disambiguation > 0.02 Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation 100% 00tma_dram_bound TopdownL3;tma_L3_group;tma_memory_bound_group cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@ tma_dram_bound > 0.1 Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM) 100% 00tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / tma_info_core_slots tma_fast_nuke > 0.05 Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming 100% 00tma_fetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / tma_info_core_slots tma_fetch_bandwidth > 0.1 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations 100% TopdownL2 00tma_fetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / tma_info_core_slots tma_fetch_latency > 0.15 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations 100% TopdownL2 00tma_fp_assist TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cpu_atom@MACHINE_CLEARS.SLOW@) tma_fp_assist > 0.02 Counts the number of machine clears relative to the number of nuke slots due to FP assists 100% 00tma_fpdiv_uops TopdownL3;tma_L3_group;tma_base_group cpu_atom@UOPS_RETIRED.FPDIV@ / tma_info_core_slots tma_fpdiv_uops > 0.2 Counts the number of floating point divide operations per uop 100% 00tma_frontend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_FE_BOUND.ALL@ / tma_info_core_slots tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls 100% TopdownL1;Default TopdownL1 00tma_icache_misses TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / tma_info_core_slots tma_icache_misses > 0.05 Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses 100% 00tma_info_core_clks cpu_atom@CPU_CLK_UNHALTED.CORE@ 00tma_info_core_clks_p cpu_atom@CPU_CLK_UNHALTED.CORE_P@ 00tma_info_core_cpi tma_info_core_clks / INST_RETIRED.ANY Cycles Per Instruction 00tma_info_core_ipc cpu_atom@INST_RETIRED.ANY@ / tma_info_core_clks Instructions Per Cycle 00tma_info_core_slots 5 * tma_info_core_clks 00tma_info_core_upi cpu_atom@UOPS_RETIRED.ALL@ / INST_RETIRED.ANY Uops Per Instruction 00tma_info_frontend_inst_miss_cost_dramhit_percent 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@ Percent of instruction miss cost that hit in DRAM 00tma_info_frontend_inst_miss_cost_l2hit_percent 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_L2_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@ Percent of instruction miss cost that hit in the L2 00tma_info_frontend_inst_miss_cost_l3hit_percent 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@ Percent of instruction miss cost that hit in the L3 00tma_info_inst_mix_branch_mispredict_ratio cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BR_INST_RETIRED.ALL_BRANCHES Ratio of all branches which mispredict 00tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BACLEARS.ANY Ratio between Mispredicted branches and unknown branches 00tma_info_inst_mix_fpdiv_uop_ratio 100 * cpu_atom@UOPS_RETIRED.FPDIV@ / UOPS_RETIRED.ALL Percentage of all uops which are FPDiv uops 00tma_info_inst_mix_idiv_uop_ratio 100 * cpu_atom@UOPS_RETIRED.IDIV@ / UOPS_RETIRED.ALL Percentage of all uops which are IDiv uops 00tma_info_inst_mix_ipbranch cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.ALL_BRANCHES Instructions per Branch (lower number means higher occurrence rate) 00tma_info_inst_mix_ipcall cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.CALL Instruction per (near) call (lower number means higher occurrence rate) 00tma_info_inst_mix_ipfarbranch cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_INST_RETIRED.FAR_BRANCH@ / 2) Instructions per Far Branch 00tma_info_inst_mix_ipload cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_LOADS Instructions per Load 00tma_info_inst_mix_ipmisp_cond_ntaken cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETIRED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@) Instructions per retired conditional Branch Misprediction where the branch was not taken 00tma_info_inst_mix_ipmisp_cond_taken cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_TAKEN Instructions per retired conditional Branch Misprediction where the branch was taken 00tma_info_inst_mix_ipmisp_indirect cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.INDIRECT Instructions per retired indirect call or jump Branch Misprediction 00tma_info_inst_mix_ipmisp_ret cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.RETURN Instructions per retired return Branch Misprediction 00tma_info_inst_mix_ipmispredict cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.ALL_BRANCHES Instructions per retired Branch Misprediction 00tma_info_inst_mix_ipstore cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_STORES Instructions per Store 00tma_info_inst_mix_microcode_uop_ratio 100 * cpu_atom@UOPS_RETIRED.MS@ / UOPS_RETIRED.ALL Percentage of all uops which are ucode ops 00tma_info_inst_mix_x87_uop_ratio 100 * cpu_atom@UOPS_RETIRED.X87@ / UOPS_RETIRED.ALL Percentage of all uops which are x87 uops 00tma_info_l1_bound_address_alias_blocks 100 * cpu_atom@LD_BLOCKS.4K_ALIAS@ / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with a address aliasing block 00tma_info_l1_bound_load_splits 100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads that are splits 00tma_info_l1_bound_store_fwd_blocks 100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with a store forward or unknown store address block 00tma_info_memory_cycles_per_demand_load_dram_hit cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / MEM_LOAD_UOPS_RETIRED.DRAM_HIT Cycle cost per DRAM hit 00tma_info_memory_cycles_per_demand_load_l2_hit cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / MEM_LOAD_UOPS_RETIRED.L2_HIT Cycle cost per L2 hit 00tma_info_memory_cycles_per_demand_load_l3_hit cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / MEM_LOAD_UOPS_RETIRED.L3_HIT Cycle cost per LLC hit 00tma_info_memory_memloadpki 1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / INST_RETIRED.ANY load ops retired per 1000 instruction 00tma_info_system_cpu_utilization cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC Average CPU Utilization 00tma_info_system_kernel_utilization Summary cpu_atom@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE Fraction of cycles spent in Kernel mode 00tma_info_system_turbo_utilization Power tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC Average Frequency Utilization relative nominal frequency 00tma_itlb_misses TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ITLB@ / tma_info_core_slots tma_itlb_misses > 0.05 Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses 100% 00tma_l1_bound TopdownL3;tma_L3_group;tma_memory_bound_group cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / tma_info_core_clks tma_l1_bound > 0.1 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block 100% 00tma_l2_bound TopdownL3;tma_L3_group;tma_memory_bound_group cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@ tma_l2_bound > 0.1 Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache 100% 00tma_l3_bound TopdownL3;tma_L3_group;tma_memory_bound_group cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@ tma_l3_bound > 0.1 Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M 100% 00tma_ld_buffer TopdownL4;tma_L4_group;tma_mem_scheduler_group tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / MEM_SCHEDULER_BLOCK.ALL tma_ld_buffer > 0.05 Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full 100% 00tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / tma_info_core_slots tma_machine_clears > 0.05 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation 100% TopdownL2 00tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / tma_info_core_slots tma_mem_scheduler > 0.1 Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops 100% 00tma_memory_bound TopdownL2;tma_L2_group;tma_backend_bound_group min(tma_backend_bound, cpu_atom@LD_HEAD.ANY_AT_RET@ / tma_info_core_clks + tma_store_bound) tma_memory_bound > 0.2 Counts the number of cycles the core is stalled due to stores or loads 100% TopdownL2 00tma_memory_ordering TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_atom@MACHINE_CLEARS.SLOW@) tma_memory_ordering > 0.02 Counts the number of machine clears relative to the number of nuke slots due to memory ordering 100% 00tma_ms_uops TopdownL2;tma_L2_group;tma_retiring_group cpu_atom@UOPS_RETIRED.MS@ / tma_info_core_slots tma_ms_uops > 0.05 Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS) Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows 100% TopdownL2 00tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / tma_info_core_slots tma_non_mem_scheduler > 0.1 Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops 100% 00tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / tma_info_core_slots tma_nuke > 0.05 Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke) 100% 00tma_other_fb TopdownL3;tma_L3_group;tma_fetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / tma_info_core_slots tma_other_fb > 0.05 Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized 100% 00tma_other_l1 TopdownL4;tma_L4_group;tma_l1_bound_group cpu_atom@LD_HEAD.OTHER_AT_RET@ / tma_info_core_clks tma_other_l1 > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks 100% 00tma_other_load_store TopdownL3;tma_L3_group;tma_memory_bound_group max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound)) tma_other_load_store > 0.1 Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer 100% 00tma_other_ret TopdownL3;tma_L3_group;tma_base_group (cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RETIRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / tma_info_core_slots tma_other_ret > 0.3 Counts the number of uops retired excluding ms and fp div uops 100% 00tma_page_fault TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / cpu_atom@MACHINE_CLEARS.SLOW@) tma_page_fault > 0.02 Counts the number of machine clears relative to the number of nuke slots due to page faults 100% 00tma_predecode TopdownL3;tma_L3_group;tma_fetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / tma_info_core_slots tma_predecode > 0.05 Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes 100% 00tma_register TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / tma_info_core_slots tma_register > 0.1 Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) 100% 00tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / tma_info_core_slots tma_reorder_buffer > 0.1 Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls) 100% 00tma_resource_bound TopdownL2;tma_L2_group;tma_backend_bound_aux_group tma_backend_bound tma_resource_bound > 0.2 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100% TopdownL2 00tma_retiring Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_RETIRING.ALL@ / tma_info_core_slots tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots 100% TopdownL1;Default TopdownL1 00tma_rsv TopdownL4;tma_L4_group;tma_mem_scheduler_group tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / MEM_SCHEDULER_BLOCK.ALL tma_rsv > 0.05 Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative 100% 00tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / tma_info_core_slots tma_serialization > 0.1 Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) 100% 00tma_smc TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom@MACHINE_CLEARS.SLOW@) tma_smc > 0.02 Counts the number of machine clears relative to the number of nuke slots due to SMC 100% 00tma_st_buffer TopdownL4;tma_L4_group;tma_mem_scheduler_group tma_store_bound tma_st_buffer > 0.05 Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full 100% 00tma_stlb_hit TopdownL4;tma_L4_group;tma_l1_bound_group cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / tma_info_core_clks tma_stlb_hit > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss 100% 00tma_stlb_miss TopdownL4;tma_L4_group;tma_l1_bound_group cpu_atom@LD_HEAD.PGWALK_AT_RET@ / tma_info_core_clks tma_stlb_miss > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk 100% 00tma_store_bound TopdownL3;tma_L3_group;tma_memory_bound_group tma_mem_scheduler * (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@) tma_store_bound > 0.1 Counts the number of cycles the core is stalled due to store buffer full 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / tma_info_core_clks tma_store_fwd_blk > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block 100% 00cpu_core UNCORE_FREQ SoC tma_info_system_socket_clks / #num_dies / duration_time / 1e9 Uncore frequency per die [GHZ] 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.PORT_0@ + cpu_core@UOPS_DISPATCHED.PORT_1@ + cpu_core@UOPS_DISPATCHED.PORT_5_11@ + cpu_core@UOPS_DISPATCHED.PORT_6@) / (5 * tma_info_core_core_clks) tma_alu_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_assists TopdownL4;tma_L4_group;tma_microcode_sequencer_group 100 * cpu_core@ASSISTS.ANY\,umask\=0x1B@ / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_avx_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_slots tma_avx_assists > 0.1 This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists 100% 00tma_backend_bound Default;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-be\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1;Default TopdownL1 00tma_bad_speculation Default;TmaL1;TopdownL1;tma_L1_group max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0) tma_bad_speculation > 0.15 This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example 100% TopdownL1;Default TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM cpu_core@topdown\-br\-mispredict@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2 00tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks + tma_unknown_branches tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100% 00tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS 100% 00tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - tma_branch_mispredicts / tma_bad_speculation) * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (25 * tma_info_system_average_frequency * (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) + 24 * tma_info_system_average_frequency * cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_core_bound Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group max(0, tma_backend_bound - tma_memory_bound) tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100% TopdownL2 00tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 24 * tma_info_system_average_frequency * (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@ + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu_core@INST_DECODED.DECODERS\,cmask\=1@ - cpu_core@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35)) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100% 00tma_divider TopdownL3;tma_L3_group;tma_core_bound_group cpu_core@ARITH.DIV_ACTIVE@ / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@ / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 00tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.DSB_CYCLES_ANY@ - cpu_core@IDQ.DSB_CYCLES_OK@) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100% 00tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@, max(cpu_core@CYCLE_ACTIVITY.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 100% 00tma_dtlb_store MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs 100% 00tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 28 * tma_info_system_average_frequency * cpu_core@OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM@ / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group cpu_core@L1D_PEND_MISS.FB_FULL@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 00tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_core@topdown\-fetch\-lat@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2 00tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 max(0, tma_heavy_operations - tma_microcode_sequencer) tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100% 00tma_fp_arith HPC;TopdownL3;tma_L3_group;tma_light_operations_group tma_x87_use + tma_fp_scalar + tma_fp_vector tma_fp_arith > 0.2 & tma_light_operations > 0.6 This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired) This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of "Uops" CountDomain and FMA double-counting 100% 00tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 30 * cpu_core@ASSISTS.FP@ / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100% 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@ / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_frontend_bound Default;PGO;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-fe\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100% TopdownL1;Default TopdownL1 00tma_fused_instructions Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * cpu_core@INST_RETIRED.MACRO_FUSED@ / (tma_retiring * tma_info_thread_slots) tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples 100% 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group cpu_core@topdown\-heavy\-ops@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY 100% TopdownL2 00tma_icache_misses BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@ICACHE_DATA.STALLS@ / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_thread_slots / BR_MISP_RETIRED.ALL_BRANCHES Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 00tma_info_bad_spec_ipmisp_cond_ntaken Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_NTAKEN tma_info_bad_spec_ipmisp_cond_ntaken < 200 Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_cond_taken Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_TAKEN tma_info_bad_spec_ipmisp_cond_taken < 200 Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts cpu_core@BR_MISP_RETIRED.INDIRECT_CALL\,umask\=0x80@ / BR_MISP_RETIRED.INDIRECT tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_ret Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.RET tma_info_bad_spec_ipmisp_ret < 500 Instructions per retired mispredicts for return branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmispredict Bad;BadSpec;BrMispredicts cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.ALL_BRANCHES tma_info_bad_spec_ipmispredict < 200 Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate) 00tma_info_botlnk_l0_core_bound_likely Cor;SMT (100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0) tma_info_botlnk_l0_core_bound_likely > 0.5 Probability of Core Bound bottleneck hidden by SMT-profiling artifacts 00tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 00tma_info_botlnk_l2_ic_misses Fed;FetchLat;IcMiss;tma_issueFL 100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_botlnk_l2_ic_misses > 5 Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: 00tma_info_bottleneck_big_code BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC 100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) tma_info_bottleneck_big_code > 20 Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses) Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_bottleneck_branching_overhead 00tma_info_bottleneck_branching_overhead Ret;tma_issueBC 100 * ((cpu_core@BR_INST_RETIRED.COND@ + 3 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + (cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR_INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@)) / tma_info_thread_slots) tma_info_bottleneck_branching_overhead > 10 Total pipeline cost of branch related instructions (used for program control-flow including function calls) Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_bottleneck_big_code 00tma_info_bottleneck_instruction_fetch_bw Fed;FetchBW;Frontend 100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code tma_info_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks 00tma_info_bottleneck_memory_bandwidth Mem;MemoryBW;Offcore;tma_issueBW 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) tma_info_bottleneck_memory_bandwidth > 20 Total pipeline cost of (external) Memory Bandwidth related bottlenecks Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 00tma_info_bottleneck_memory_data_tlbs Mem;MemoryTLB;Offcore;tma_issueTLB 100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store 00tma_info_bottleneck_memory_latency Mem;MemoryLat;Offcore;tma_issueLat 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) tma_info_bottleneck_memory_latency > 20 Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches) Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_bottleneck_mispredictions Bad;BadSpec;BrMispredicts;tma_issueBM 100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_bottleneck_mispredictions > 20 Total pipeline cost of Branch Misprediction related bottlenecks Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 00tma_info_branches_callret Bad;Branches (cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_INST_RETIRED.NEAR_RETURN@) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are CALL or RET 00tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_NTAKEN@ / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are non-taken conditionals 00tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_TAKEN@ / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are taken conditionals 00tma_info_branches_jump Bad;Branches (cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR_INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are unconditional (direct or indirect) jumps 00tma_info_branches_other_branches Bad;Branches 1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_callret + tma_info_branches_jump) Fraction of branches of other types (not individually covered by other metrics in Info.Branches group) 00tma_info_core_core_clks SMT cpu_core@CPU_CLK_UNHALTED.DISTRIBUTED@ Core actual clocks when any Logical Processor is active on the Physical Core 00tma_info_core_coreipc Ret;SMT;TmaL1;tma_L1_group cpu_core@INST_RETIRED.ANY@ / tma_info_core_core_clks Instructions Per Cycle across hyper-threads (per physical core) 00tma_info_core_flopc Flops;Ret (cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@) + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_core_fp_arith_utilization Cor;Flops;HPC (cpu_core@FP_ARITH_DISPATCHED.PORT_0@ + cpu_core@FP_ARITH_DISPATCHED.PORT_1@ + cpu_core@FP_ARITH_DISPATCHED.PORT_5@) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil cpu_core@UOPS_EXECUTED.THREAD@ / (cpu_core@UOPS_EXECUTED.CORE_CYCLES_GE_1@ / 2 if #SMT_on else cpu_core@UOPS_EXECUTED.CORE_CYCLES_GE_1@) Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB cpu_core@IDQ.DSB_UOPS@ / cpu_core@UOPS_ISSUED.ANY@ tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_dsb_switch_cost DSBmiss cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES\,cmask\=1\,edge@ Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details 00tma_info_frontend_fetch_upc Fed;FetchBW cpu_core@UOPS_ISSUED.ANY@ / cpu_core@UOPS_ISSUED.ANY\,cmask\=1@ Average number of Uops issued by front-end when it issued something 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss cpu_core@ICACHE_DATA.STALLS@ / cpu_core@ICACHE_DATA.STALLS\,cmask\=1\,edge@ Average Latency for L1 instruction cache misses 00tma_info_frontend_ipdsb_miss_ret DSBmiss;Fed cpu_core@INST_RETIRED.ANY@ / FRONTEND_RETIRED.ANY_DSB_MISS tma_info_frontend_ipdsb_miss_ret < 50 Instructions per non-speculative DSB miss (lower number means higher occurrence rate) 00tma_info_frontend_ipunknown_branch Fed tma_info_inst_mix_instructions / BACLEARS.ANY Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate) 00tma_info_frontend_l2mpki_code IcMiss 1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / INST_RETIRED.ANY L2 cache true code cacheline misses per kilo instruction 00tma_info_frontend_l2mpki_code_all IcMiss 1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / INST_RETIRED.ANY L2 cache speculative code cacheline misses per kilo instruction 00tma_info_frontend_lsd_coverage Fed;LSD cpu_core@LSD.UOPS@ / cpu_core@UOPS_ISSUED.ANY@ Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache) 00tma_info_inst_mix_bptkbranch Branches;Fed;PGO cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ / BR_INST_RETIRED.NEAR_TAKEN Branch instructions per taken branch 00tma_info_inst_mix_instructions Summary;TmaL1;tma_L1_group cpu_core@INST_RETIRED.ANY@ Total number of retired Instructions Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST 00tma_info_inst_mix_iparith Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW 00tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_scalar_dp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE tma_info_inst_mix_iparith_scalar_dp < 10 Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_scalar_sp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / FP_ARITH_INST_RETIRED.SCALAR_SINGLE tma_info_inst_mix_iparith_scalar_sp < 10 Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_ipbranch Branches;Fed;InsType cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.ALL_BRANCHES tma_info_inst_mix_ipbranch < 8 Instructions per Branch (lower number means higher occurrence rate) 00tma_info_inst_mix_ipcall Branches;Fed;PGO cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_CALL tma_info_inst_mix_ipcall < 200 Instructions per (near) call (lower number means higher occurrence rate) 00tma_info_inst_mix_ipflop Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@) + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_ipload InsType cpu_core@INST_RETIRED.ANY@ / MEM_INST_RETIRED.ALL_LOADS tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate) 00tma_info_inst_mix_ipstore InsType cpu_core@INST_RETIRED.ANY@ / MEM_INST_RETIRED.ALL_STORES tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate) 00tma_info_inst_mix_ipswpf Prefetches cpu_core@INST_RETIRED.ANY@ / cpu_core@SW_PREFETCH_ACCESS.T0\,umask\=0xF@ tma_info_inst_mix_ipswpf < 100 Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 13 Instruction per taken branch Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_core_l1d_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L1D.REPLACEMENT@ / 1e9 / duration_time Average per-core data fill bandwidth to the L1 data cache [GB / sec] 00tma_info_memory_core_l2_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L2_LINES_IN.ALL@ / 1e9 / duration_time Average per-core data fill bandwidth to the L2 cache [GB / sec] 00tma_info_memory_core_l3_cache_access_bw Mem;MemoryBW;Offcore 64 * cpu_core@OFFCORE_REQUESTS.ALL_REQUESTS@ / 1e9 / duration_time Average per-core data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_core_l3_cache_fill_bw Mem;MemoryBW 64 * cpu_core@LONGEST_LAT_CACHE.MISS@ / 1e9 / duration_time Average per-core data fill bandwidth to the L3 cache [GB / sec] 00tma_info_memory_fb_hpki CacheMisses;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / INST_RETIRED.ANY Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries) 00tma_info_memory_l1mpki CacheMisses;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / INST_RETIRED.ANY L1 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l1mpki_load CacheMisses;Mem 1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / INST_RETIRED.ANY L1 cache true misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2hpki_all CacheMisses;Mem 1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_RQSTS.MISS@) / INST_RETIRED.ANY L2 cache hits per kilo instruction for all request types (including speculative) 00tma_info_memory_l2hpki_load CacheMisses;Mem 1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / INST_RETIRED.ANY L2 cache hits per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki Backend;CacheMisses;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / INST_RETIRED.ANY L2 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l2mpki_all CacheMisses;Mem;Offcore 1e3 * cpu_core@L2_RQSTS.MISS@ / INST_RETIRED.ANY L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative) 00tma_info_memory_l2mpki_load CacheMisses;Mem 1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / INST_RETIRED.ANY L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l3mpki CacheMisses;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / INST_RETIRED.ANY L3 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat cpu_core@L1D_PEND_MISS.PENDING@ / MEM_LOAD_COMPLETED.L1_MISS_ANY Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 00tma_info_memory_mlp Mem;MemoryBW;MemoryBound cpu_core@L1D_PEND_MISS.PENDING@ / L1D_PEND_MISS.PENDING_CYCLES Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) 00tma_info_memory_oro_data_l2_mlp Memory_BW;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD@ / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Average Parallel L2 cache miss data reads 00tma_info_memory_oro_load_l2_miss_latency Memory_Lat;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / OFFCORE_REQUESTS.DEMAND_DATA_RD Average Latency for L2 cache miss demand Loads 00tma_info_memory_oro_load_l2_mlp Memory_BW;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,cmask\=1@ Average Parallel L2 cache miss demand Loads 00tma_info_memory_oro_load_l3_miss_latency Memory_Lat;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Average Latency for L3 cache miss demand Loads 00tma_info_memory_thread_l1d_cache_fill_bw_1t Mem;MemoryBW tma_info_memory_core_l1d_cache_fill_bw Average per-thread data fill bandwidth to the L1 data cache [GB / sec] 00tma_info_memory_thread_l2_cache_fill_bw_1t Mem;MemoryBW tma_info_memory_core_l2_cache_fill_bw Average per-thread data fill bandwidth to the L2 cache [GB / sec] 00tma_info_memory_thread_l3_cache_access_bw_1t Mem;MemoryBW;Offcore tma_info_memory_core_l3_cache_access_bw Average per-thread data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_thread_l3_cache_fill_bw_1t Mem;MemoryBW tma_info_memory_core_l3_cache_fill_bw Average per-thread data fill bandwidth to the L3 cache [GB / sec] 00tma_info_memory_tlb_code_stlb_mpki Fed;MemoryTLB 1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / INST_RETIRED.ANY STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_load_stlb_mpki Mem;MemoryTLB 1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / INST_RETIRED.ANY STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (cpu_core@ITLB_MISSES.WALK_PENDING@ + cpu_core@DTLB_LOAD_MISSES.WALK_PENDING@ + cpu_core@DTLB_STORE_MISSES.WALK_PENDING@) / (4 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_memory_tlb_store_stlb_mpki Mem;MemoryTLB 1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / INST_RETIRED.ANY STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT cpu_core@UOPS_EXECUTED.THREAD@ / cpu_core@UOPS_EXECUTED.THREAD\,cmask\=1@ Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread 00tma_info_pipeline_ipassist Pipeline;Ret;Retire cpu_core@INST_RETIRED.ANY@ / cpu_core@ASSISTS.ANY\,umask\=0x1B@ tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate) 00tma_info_pipeline_retire Pipeline;Ret tma_retiring * tma_info_thread_slots / cpu_core@UOPS_RETIRED.SLOTS\,cmask\=1@ Average number of Uops retired in cycles where at least one uop has retired 00tma_info_pipeline_strings_cycles Pipeline;Ret cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.SLOTS\,cmask\=1@ tma_info_pipeline_strings_cycles > 0.1 Estimated fraction of retirement-cycles dealing with repeat instructions 00tma_info_system_average_frequency Power;Summary tma_info_system_turbo_utilization * TSC / 1e9 / duration_time Measured Average Frequency for unhalted processors [GHz] 00tma_info_system_cpu_utilization HPC;Summary cpu_core@CPU_CLK_UNHALTED.REF_TSC@ / TSC Average CPU Utilization 00tma_info_system_dram_bw_use HPC;Mem;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_mem_bandwidth, tma_sq_full 00tma_info_system_gflops Cor;Flops;HPC (cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@) + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine 00tma_info_system_ipfarbranch Branches;OS cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.FAR_BRANCH@u tma_info_system_ipfarbranch < 1e6 Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate] 00tma_info_system_kernel_cpi OS CPU_CLK_UNHALTED.THREAD_P:k / cpu_core@INST_RETIRED.ANY_P@k Cycles Per Instruction for the Operating System (OS) Kernel mode 00tma_info_system_kernel_utilization OS CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD tma_info_system_kernel_utilization > 0.05 Fraction of cycles spent in the Operating System (OS) Kernel mode 00tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_ARB_DAT_OCCUPANCY.RD / UNC_ARB_DAT_OCCUPANCY.RD@cmask\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC (UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 01tma_info_system_mem_request_latency Mem;SoC (UNC_ARB_TRK_OCCUPANCY.ALL + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.ALL Average latency of all requests to external memory (in Uncore cycles) 01tma_info_system_smt_2t_utilization SMT (1 - cpu_core@CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE@ / cpu_core@CPU_CLK_UNHALTED.REF_DISTRIBUTED@ if #SMT_on else 0) Fraction of cycles where both hardware Logical Processors were active 00tma_info_system_socket_clks SoC UNC_CLOCK.SOCKET Socket actual clocks when any core is active on that socket 00tma_info_system_turbo_utilization Power tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC Average Frequency Utilization relative nominal frequency 00tma_info_thread_clks Pipeline cpu_core@CPU_CLK_UNHALTED.THREAD@ Per-Logical Processor actual clocks when the Logical Processor is active 00tma_info_thread_cpi Mem;Pipeline 1 / tma_info_thread_ipc Cycles Per Instruction (per Logical Processor) 00tma_info_thread_execute_per_issue Cor;Pipeline cpu_core@UOPS_EXECUTED.THREAD@ / UOPS_ISSUED.ANY The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage 00tma_info_thread_ipc Ret;Summary cpu_core@INST_RETIRED.ANY@ / tma_info_thread_clks Instructions Per Cycle (per Logical Processor) 00tma_info_thread_slots TmaL1;tma_L1_group cpu_core@TOPDOWN.SLOTS@ Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward) 00tma_info_thread_slots_utilization SMT;TmaL1;tma_L1_group (tma_info_thread_slots / (cpu_core@TOPDOWN.SLOTS@ / 2) if #SMT_on else 1) Fraction of Physical Core issue-slots utilized by this Logical Processor 00tma_info_thread_uoppi Pipeline;Ret;Retire tma_retiring * tma_info_thread_slots / INST_RETIRED.ANY tma_info_thread_uoppi > 1.05 Uops Per Instruction 00tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 9 Instruction per taken branch 00tma_int_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_int_vector_128b + tma_int_vector_256b + tma_shuffles tma_int_operations > 0.1 & tma_light_operations > 0.6 This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired) This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of "Uops" CountDomain 100% 00tma_int_vector_128b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (cpu_core@INT_VEC_RETIRED.ADD_128@ + cpu_core@INT_VEC_RETIRED.VNNI_128@) / (tma_retiring * tma_info_thread_slots) tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_int_vector_256b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (cpu_core@INT_VEC_RETIRED.ADD_256@ + cpu_core@INT_VEC_RETIRED.MUL_256@ + cpu_core@INT_VEC_RETIRED.VNNI_256@) / (tma_retiring * tma_info_thread_slots) tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_itlb_misses BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@ICACHE_TAG.STALLS@ / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100% 00tma_l1_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 00tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 9 * tma_info_system_average_frequency * cpu_core@MEM_LOAD_RETIRED.L3_HIT@ * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency 100% 00tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB cpu_core@DECODE.LCP@ / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100% 00tma_light_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group max(0, tma_retiring - tma_heavy_operations) tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST 100% TopdownL2 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group cpu_core@UOPS_DISPATCHED.PORT_2_3_10@ / (3 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100% 00tma_load_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group tma_dtlb_load - tma_load_stlb_miss tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB) 100% 00tma_load_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@ / tma_info_thread_clks tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ - cpu_core@L2_RQSTS.ALL_RFO@) + cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@ * (10 * cpu_core@L2_RQSTS.RFO_HIT@ + min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 00tma_lsd FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@LSD.CYCLES_ACTIVE@ - cpu_core@LSD.CYCLES_OK@) / tma_info_core_core_clks / 2 tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure 100% 00tma_machine_clears BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn max(0, tma_bad_speculation - tma_branch_mispredicts) tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2 00tma_mem_bandwidth MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_mem_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_memory_latency, tma_l3_hit_latency 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group cpu_core@topdown\-mem\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 00tma_memory_fence TopdownL6;tma_L6_group;tma_serializing_operation_group 13 * cpu_core@MISC2_RETIRED.LFENCE@ / tma_info_thread_clks tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))) This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions 100% 02tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * cpu_core@MEM_UOP_RETIRED.ANY@ / (tma_retiring * tma_info_thread_slots) tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 00tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS cpu_core@UOPS_RETIRED.MS@ / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM tma_branch_mispredicts / tma_bad_speculation * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.MITE_CYCLES_ANY@ - cpu_core@IDQ.MITE_CYCLES_OK@) / tma_info_core_core_clks / 2 tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100% 00tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group 160 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_clks tma_mixing_vectors > 0.05 The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu_core@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (tma_retiring * tma_info_thread_slots / cpu_core@UOPS_ISSUED.ANY@) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_non_fused_branches Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ - cpu_core@INST_RETIRED.MACRO_FUSED@) / (tma_retiring * tma_info_thread_slots) tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100% 00tma_nop_instructions Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * cpu_core@INST_RETIRED.NOP@ / (tma_retiring * tma_info_thread_slots) tma_nop_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100% 00tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100% 00tma_page_faults TopdownL5;tma_L5_group;tma_assists_group 99 * cpu_core@ASSISTS.PAGE_FAULT@ / tma_info_thread_slots tma_page_faults > 0.05 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_0@ / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_1@ / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_6@ / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ + tma_serializing_operation * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) + (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@)) / tma_info_thread_clks if cpu_core@ARITH.DIV_ACTIVE@ < cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ else (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ / tma_info_thread_clks + tma_serializing_operation * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ / tma_info_thread_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.2_PORTS_UTIL@ / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 02tma_ports_utilized_3m PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu_core@UOPS_EXECUTED.CYCLES_GE_3@ / tma_info_thread_clks tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 02tma_retiring Default;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-retiring@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) + 0 * tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100% TopdownL1;Default TopdownL1 00tma_serializing_operation PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group cpu_core@RESOURCE_STALLS.SCOREBOARD@ / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100% 00tma_shuffles HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group cpu_core@INT_VEC_RETIRED.SHUFFLES@ / (tma_retiring * tma_info_thread_slots) tma_shuffles > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents Shuffle (cross "vector lane" data transfers) uops fraction the CPU has retired 100% 00tma_slow_pause TopdownL6;tma_L6_group;tma_serializing_operation_group cpu_core@CPU_CLK_UNHALTED.PAUSE@ / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST 100% 02tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu_core@LD_BLOCKS.NO_SR@ / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 00tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group cpu_core@MEM_INST_RETIRED.SPLIT_STORES@ / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_sq_full MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (cpu_core@XQ.FULL_CYCLES@ + cpu_core@L1D_PEND_MISS.L2_STALLS@) / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@EXE_ACTIVITY.BOUND_ON_STORES@ / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * cpu_core@LD_BLOCKS.STORE_FORWARD@ / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100% 00tma_store_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (cpu_core@MEM_STORE_RETIRED.L2_HIT@ * 10 * (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) + (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) * min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 00tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.PORT_4_9@ + cpu_core@UOPS_DISPATCHED.PORT_7_8@) / (4 * tma_info_core_core_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100% 00tma_store_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group tma_dtlb_store - tma_store_stlb_miss tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB) 100% 00tma_store_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@ / tma_info_core_core_clks tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk 100% 00tma_streaming_stores MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group 9 * cpu_core@OCR.STREAMING_WR.ANY_RESPONSE@ / tma_info_thread_clks tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full 100% 00tma_unknown_branches BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100% 00tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / UOPS_EXECUTED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00Backend Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet Bad BadSpec BigFoot BrMispredicts Branches CacheMisses CodeGen Compute Cor DSB DSBmiss DataSharing Fed FetchBW FetchLat Flops FpScalar FpVector Frontend HPC IcMiss InsType IntVector L2Evicts MachineClears Mem MemoryBW MemoryBound MemoryLat MemoryTLB Memory_BW Memory_Lat MicroSeq OS Offcore PGO Pipeline PortsUtil Power Prefetches Ret Retire SMT Server Snoop SoC Summary TmaL1 TmaL2 TmaL3mem TopdownL1 Metrics for top-down breakdown at level 1 TopdownL2 Metrics for top-down breakdown at level 2 TopdownL3 Metrics for top-down breakdown at level 3 TopdownL4 Metrics for top-down breakdown at level 4 TopdownL5 Metrics for top-down breakdown at level 5 TopdownL6 Metrics for top-down breakdown at level 6 tma_L1_group tma_L2_group tma_L3_group tma_L4_group tma_L5_group tma_L6_group tma_alu_op_utilization_group Metrics contributing to tma_alu_op_utilization category tma_assists_group Metrics contributing to tma_assists category tma_backend_bound_aux_group Metrics contributing to tma_backend_bound_aux category tma_backend_bound_group Metrics contributing to tma_backend_bound category tma_bad_speculation_group Metrics contributing to tma_bad_speculation category tma_base_group Metrics contributing to tma_base category tma_branch_resteers_group Metrics contributing to tma_branch_resteers category tma_core_bound_group Metrics contributing to tma_core_bound category tma_dram_bound_group Metrics contributing to tma_dram_bound category tma_dtlb_load_group Metrics contributing to tma_dtlb_load category tma_dtlb_store_group Metrics contributing to tma_dtlb_store category tma_fetch_bandwidth_group Metrics contributing to tma_fetch_bandwidth category tma_fetch_latency_group Metrics contributing to tma_fetch_latency category tma_fp_arith_group Metrics contributing to tma_fp_arith category tma_fp_vector_group Metrics contributing to tma_fp_vector category tma_frontend_bound_group Metrics contributing to tma_frontend_bound category tma_heavy_operations_group Metrics contributing to tma_heavy_operations category tma_int_operations_group Metrics contributing to tma_int_operations category tma_issue2P Metrics related by the issue $issue2P tma_issueBC Metrics related by the issue $issueBC tma_issueBM Metrics related by the issue $issueBM tma_issueBW Metrics related by the issue $issueBW tma_issueD0 Metrics related by the issue $issueD0 tma_issueFB Metrics related by the issue $issueFB tma_issueFL Metrics related by the issue $issueFL tma_issueL1 Metrics related by the issue $issueL1 tma_issueLat Metrics related by the issue $issueLat tma_issueMC Metrics related by the issue $issueMC tma_issueMS Metrics related by the issue $issueMS tma_issueMV Metrics related by the issue $issueMV tma_issueRFO Metrics related by the issue $issueRFO tma_issueSL Metrics related by the issue $issueSL tma_issueSO Metrics related by the issue $issueSO tma_issueSmSt Metrics related by the issue $issueSmSt tma_issueSpSt Metrics related by the issue $issueSpSt tma_issueSyncxn Metrics related by the issue $issueSyncxn tma_issueTLB Metrics related by the issue $issueTLB tma_l1_bound_group Metrics contributing to tma_l1_bound category tma_l3_bound_group Metrics contributing to tma_l3_bound category tma_light_operations_group Metrics contributing to tma_light_operations category tma_load_op_utilization_group Metrics contributing to tma_load_op_utilization category tma_machine_clears_group Metrics contributing to tma_machine_clears category tma_mem_latency_group Metrics contributing to tma_mem_latency category tma_mem_scheduler_group Metrics contributing to tma_mem_scheduler category tma_memory_bound_group Metrics contributing to tma_memory_bound category tma_microcode_sequencer_group Metrics contributing to tma_microcode_sequencer category tma_mite_group Metrics contributing to tma_mite category tma_nuke_group Metrics contributing to tma_nuke category tma_ports_utilization_group Metrics contributing to tma_ports_utilization category tma_ports_utilized_0_group Metrics contributing to tma_ports_utilized_0 category tma_ports_utilized_3m_group Metrics contributing to tma_ports_utilized_3m category tma_resource_bound_group Metrics contributing to tma_resource_bound category tma_retiring_group Metrics contributing to tma_retiring category tma_serializing_operation_group Metrics contributing to tma_serializing_operation category tma_store_bound_group Metrics contributing to tma_store_bound category tma_store_op_utilization_group Metrics contributing to tma_store_op_utilization category tma_alloc_restriction TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / tma_info_core_slots tma_alloc_restriction > 0.1 Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions 100% 00tma_backend_bound Default;TopdownL1;tma_L1_group TOPDOWN_BE_BOUND.ALL / tma_info_core_slots tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based 100% TopdownL1;Default TopdownL1 00tma_bad_speculation Default;TopdownL1;tma_L1_group (tma_info_core_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_core_slots tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100% TopdownL1;Default TopdownL1 00tma_base TopdownL2;tma_L2_group;tma_retiring_group (TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info_core_slots tma_base > 0.6 Counts the number of uops that are not from the microsequencer 100% TopdownL2 00tma_branch_detect TopdownL3;tma_L3_group;tma_fetch_latency_group TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_core_slots tma_branch_detect > 0.05 Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100% 00tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MISPREDICT / tma_info_core_slots tma_branch_mispredicts > 0.05 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts 100% TopdownL2 00tma_branch_resteer TopdownL3;tma_L3_group;tma_fetch_latency_group TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_core_slots tma_branch_resteer > 0.05 Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch 100% 00tma_cisc TopdownL3;tma_L3_group;tma_fetch_bandwidth_group TOPDOWN_FE_BOUND.CISC / tma_info_core_slots tma_cisc > 0.05 Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS) 100% 00tma_decode TopdownL3;tma_L3_group;tma_fetch_bandwidth_group TOPDOWN_FE_BOUND.DECODE / tma_info_core_slots tma_decode > 0.05 Counts the number of issue slots that were not delivered by the frontend due to decode stalls 100% 00tma_disambiguation TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW) tma_disambiguation > 0.02 Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation 100% 00tma_dram_bound TopdownL3;tma_L3_group;tma_memory_bound_group MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD tma_dram_bound > 0.1 Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM) 100% 00tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.FASTNUKE / tma_info_core_slots tma_fast_nuke > 0.05 Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming 100% 00tma_fetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_core_slots tma_fetch_bandwidth > 0.1 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations 100% TopdownL2 00tma_fetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_core_slots tma_fetch_latency > 0.15 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations 100% TopdownL2 00tma_fp_assist TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW) tma_fp_assist > 0.02 Counts the number of machine clears relative to the number of nuke slots due to FP assists 100% 00tma_fpdiv_uops TopdownL3;tma_L3_group;tma_base_group UOPS_RETIRED.FPDIV / tma_info_core_slots tma_fpdiv_uops > 0.2 Counts the number of floating point divide operations per uop 100% 00tma_frontend_bound Default;TopdownL1;tma_L1_group TOPDOWN_FE_BOUND.ALL / tma_info_core_slots tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls 100% TopdownL1;Default TopdownL1 00tma_icache_misses TopdownL3;tma_L3_group;tma_fetch_latency_group TOPDOWN_FE_BOUND.ICACHE / tma_info_core_slots tma_icache_misses > 0.05 Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses 100% 00tma_info_core_clks CPU_CLK_UNHALTED.CORE 00tma_info_core_clks_p CPU_CLK_UNHALTED.CORE_P 00tma_info_core_ipc INST_RETIRED.ANY / tma_info_core_clks Instructions Per Cycle 00tma_info_core_upi UOPS_RETIRED.ALL / INST_RETIRED.ANY Uops Per Instruction 00tma_info_frontend_inst_miss_cost_dramhit_percent 100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH Percent of instruction miss cost that hit in DRAM 00tma_info_frontend_inst_miss_cost_l2hit_percent 100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH Percent of instruction miss cost that hit in the L2 00tma_info_frontend_inst_miss_cost_l3hit_percent 100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH Percent of instruction miss cost that hit in the L3 00tma_info_inst_mix_branch_mispredict_ratio BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES Ratio of all branches which mispredict 00tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY Ratio between Mispredicted branches and unknown branches 00tma_info_inst_mix_fpdiv_uop_ratio 100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL Percentage of all uops which are FPDiv uops 00tma_info_inst_mix_idiv_uop_ratio 100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL Percentage of all uops which are IDiv uops 00tma_info_inst_mix_ipbranch INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES Instructions per Branch (lower number means higher occurrence rate) 00tma_info_inst_mix_ipcall INST_RETIRED.ANY / BR_INST_RETIRED.CALL Instruction per (near) call (lower number means higher occurrence rate) 00tma_info_inst_mix_ipfarbranch INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2) Instructions per Far Branch 00tma_info_inst_mix_ipload INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS Instructions per Load 00tma_info_inst_mix_ipmisp_cond_ntaken INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN) Instructions per retired conditional Branch Misprediction where the branch was not taken 00tma_info_inst_mix_ipmisp_cond_taken INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN Instructions per retired conditional Branch Misprediction where the branch was taken 00tma_info_inst_mix_ipmisp_indirect INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT Instructions per retired indirect call or jump Branch Misprediction 00tma_info_inst_mix_ipmisp_ret INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN Instructions per retired return Branch Misprediction 00tma_info_inst_mix_ipmispredict INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES Instructions per retired Branch Misprediction 00tma_info_inst_mix_ipstore INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES Instructions per Store 00tma_info_inst_mix_microcode_uop_ratio 100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL Percentage of all uops which are ucode ops 00tma_info_inst_mix_x87_uop_ratio 100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL Percentage of all uops which are x87 uops 00tma_info_l1_bound_address_alias_blocks 100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with a address aliasing block 00tma_info_l1_bound_load_splits 100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads that are splits 00tma_info_l1_bound_store_fwd_blocks 100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS Percentage of total non-speculative loads with a store forward or unknown store address block 00tma_info_memory_cycles_per_demand_load_dram_hit MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT Cycle cost per DRAM hit 00tma_info_memory_cycles_per_demand_load_l2_hit MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT Cycle cost per L2 hit 00tma_info_memory_cycles_per_demand_load_l3_hit MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT Cycle cost per LLC hit 00tma_info_memory_memloadpki 1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY load ops retired per 1000 instruction 00tma_info_system_cpu_utilization CPU_CLK_UNHALTED.REF_TSC / TSC Average CPU Utilization 00tma_info_system_kernel_utilization Summary cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE Fraction of cycles spent in Kernel mode 00tma_itlb_misses TopdownL3;tma_L3_group;tma_fetch_latency_group TOPDOWN_FE_BOUND.ITLB / tma_info_core_slots tma_itlb_misses > 0.05 Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses 100% 00tma_l1_bound TopdownL3;tma_L3_group;tma_memory_bound_group LD_HEAD.L1_BOUND_AT_RET / tma_info_core_clks tma_l1_bound > 0.1 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block 100% 00tma_l2_bound TopdownL3;tma_L3_group;tma_memory_bound_group MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD tma_l2_bound > 0.1 Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache 100% 00tma_l3_bound TopdownL3;tma_L3_group;tma_memory_bound_group MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD tma_l3_bound > 0.1 Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M 100% 00tma_ld_buffer TopdownL4;tma_L4_group;tma_mem_scheduler_group tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL tma_ld_buffer > 0.05 Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full 100% 00tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_core_slots tma_machine_clears > 0.05 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation 100% TopdownL2 00tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.MEM_SCHEDULER / tma_info_core_slots tma_mem_scheduler > 0.1 Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops 100% 00tma_memory_bound TopdownL2;tma_L2_group;tma_backend_bound_group min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_core_clks + tma_store_bound) tma_memory_bound > 0.2 Counts the number of cycles the core is stalled due to stores or loads 100% TopdownL2 00tma_memory_ordering TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW) tma_memory_ordering > 0.02 Counts the number of machine clears relative to the number of nuke slots due to memory ordering 100% 00tma_ms_uops TopdownL2;tma_L2_group;tma_retiring_group UOPS_RETIRED.MS / tma_info_core_slots tma_ms_uops > 0.05 Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS) Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows 100% TopdownL2 00tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / tma_info_core_slots tma_non_mem_scheduler > 0.1 Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops 100% 00tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.NUKE / tma_info_core_slots tma_nuke > 0.05 Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke) 100% 00tma_other_fb TopdownL3;tma_L3_group;tma_fetch_bandwidth_group TOPDOWN_FE_BOUND.OTHER / tma_info_core_slots tma_other_fb > 0.05 Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized 100% 00tma_other_l1 TopdownL4;tma_L4_group;tma_l1_bound_group LD_HEAD.OTHER_AT_RET / tma_info_core_clks tma_other_l1 > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks 100% 00tma_other_ret TopdownL3;tma_L3_group;tma_base_group (TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / tma_info_core_slots tma_other_ret > 0.3 Counts the number of uops retired excluding ms and fp div uops 100% 00tma_page_fault TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW) tma_page_fault > 0.02 Counts the number of machine clears relative to the number of nuke slots due to page faults 100% 00tma_predecode TopdownL3;tma_L3_group;tma_fetch_bandwidth_group TOPDOWN_FE_BOUND.PREDECODE / tma_info_core_slots tma_predecode > 0.05 Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes 100% 00tma_register TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REGISTER / tma_info_core_slots tma_register > 0.1 Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) 100% 00tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REORDER_BUFFER / tma_info_core_slots tma_reorder_buffer > 0.1 Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls) 100% 00tma_retiring Default;TopdownL1;tma_L1_group TOPDOWN_RETIRING.ALL / tma_info_core_slots tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots 100% TopdownL1;Default TopdownL1 00tma_rsv TopdownL4;tma_L4_group;tma_mem_scheduler_group tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL tma_rsv > 0.05 Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative 100% 00tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.SERIALIZATION / tma_info_core_slots tma_serialization > 0.1 Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) 100% 00tma_smc TopdownL4;tma_L4_group;tma_nuke_group tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW) tma_smc > 0.02 Counts the number of machine clears relative to the number of nuke slots due to SMC 100% 00tma_stlb_hit TopdownL4;tma_L4_group;tma_l1_bound_group LD_HEAD.DTLB_MISS_AT_RET / tma_info_core_clks tma_stlb_hit > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss 100% 00tma_stlb_miss TopdownL4;tma_L4_group;tma_l1_bound_group LD_HEAD.PGWALK_AT_RET / tma_info_core_clks tma_stlb_miss > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk 100% 00tma_store_bound TopdownL3;tma_L3_group;tma_memory_bound_group tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL) tma_store_bound > 0.1 Counts the number of cycles the core is stalled due to store buffer full 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group LD_HEAD.ST_ADDR_AT_RET / tma_info_core_clks tma_store_fwd_blk > 0.05 Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block 100% 00branch_misprediction_ratio branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn) Execution-Time Branch Misprediction Ratio (Non-Speculative) 100% 00all_l2_cache_accesses l2_cache l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 All L2 Cache Accesses 00l2_cache_accesses_from_l2_hwpf l2_cache l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 L2 Cache Accesses from L2 HWPF 00all_l2_cache_misses l2_cache l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 All L2 Cache Misses 00l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 L2 Cache Misses from L2 HWPF 00all_l2_cache_hits l2_cache l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2 All L2 Cache Hits 00l3_read_miss_latency l3_cache xi_sys_fill_latency * 16 / xi_ccx_sdp_req1.all_l3_miss_req_typs Average L3 Read Miss Latency (in core clocks) 1core clocks 00ic_fetch_miss_ratio l2_cache d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss) L1 Instruction Cache (32B) Fetch Miss Ratio 100% 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss L1 ITLB Misses 00all_remote_links_outbound data_fabric remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3 Approximate: Outbound data bytes for all Remote Links for a node (die) 3e-5MiB 00nps1_die_to_dram data_fabric dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7 Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) 6.1e-5MiB 01ic_fetch_miss_ratio l2_cache d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss) L1 Instruction Cache (32B) Fetch Miss Ratio 100% 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss L1 ITLB Misses 00l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 L2 Cache Misses from L2 Cache HWPF 00l3_read_miss_latency l3_cache xi_sys_fill_latency * 16 / xi_ccx_sdp_req1 Average L3 Read Miss Latency (in core clocks) 1core clocks 00op_cache_fetch_miss_ratio l2_cache d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses) Op Cache (64B) Fetch Miss Ratio 00ic_fetch_miss_ratio l2_cache d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses) Instruction Cache (32B) Fetch Miss Ratio 100% 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss L1 ITLB Misses 00macro_ops_dispatched decoder de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch Macro-ops Dispatched 00total_dispatch_slots 6 * ls_not_halted_cyc Total dispatch slots (upto 6 instructions can be dispatched in each cycle) 00frontend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots) Fraction of dispatch slots that remained unused because the frontend did not supply enough instructions/ops 100% 00bad_speculation PipelineL1 d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots) Fraction of dispatched ops that did not retire 100% 00backend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots) Fraction of dispatch slots that remained unused because of backend stalls 100% 00smt_contention PipelineL1 d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots) Fraction of dispatch slots that remained unused because the other thread was selected 100% 00retiring PipelineL1 d_ratio(ex_ret_ops, total_dispatch_slots) Fraction of dispatch slots used by ops that retired 100% 00frontend_bound_latency PipelineL2;frontend_bound_group d_ratio(6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@, total_dispatch_slots) Fraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses) 100% 00frontend_bound_bandwidth PipelineL2;frontend_bound_group d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - 6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@, total_dispatch_slots) Fraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth) 100% 00bad_speculation_mispredicts PipelineL2;bad_speculation_group d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects) Fraction of dispatched ops that were flushed due to branch mispredicts 100% 00bad_speculation_pipeline_restarts PipelineL2;bad_speculation_group d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects) Fraction of dispatched ops that were flushed due to pipeline restarts (resyncs) 100% 00backend_bound_memory PipelineL2;backend_bound_group backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete) Fraction of dispatch slots that remained unused because of stalls due to the memory subsystem 100% 00backend_bound_cpu PipelineL2;backend_bound_group backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)) Fraction of dispatch slots that remained unused because of stalls not related to the memory subsystem 100% 00retiring_fastpath PipelineL2;retiring_group retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops)) Fraction of dispatch slots used by fastpath ops that retired 100% 00retiring_microcode PipelineL2;retiring_group retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops) Fraction of dispatch slots used by microcode ops that retired 100% 00branch_misprediction_ratio branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn) Execution-time branch misprediction ratio (non-speculative) 100% 00all_l2_cache_accesses l2_cache l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all All L2 cache accesses 00l2_cache_accesses_from_l1_ic_misses l2_cache l2_request_g1.cacheable_ic_read L2 cache accesses from L1 instruction cache misses (including prefetch) 00l2_cache_accesses_from_l1_dc_misses l2_cache l2_request_g1.all_dc L2 cache accesses from L1 data cache misses (including prefetch) 00l2_cache_accesses_from_l2_hwpf l2_cache l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L2 cache accesses from L2 cache hardware prefetcher 00all_l2_cache_misses l2_cache l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all All L2 cache misses 00l2_cache_misses_from_l1_ic_miss l2_cache l2_cache_req_stat.ic_fill_miss L2 cache misses from L1 instruction cache misses 00l2_cache_misses_from_l1_dc_miss l2_cache l2_cache_req_stat.ls_rd_blk_c L2 cache misses from L1 data cache misses 00l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L2 cache misses from L2 cache hardware prefetcher 00all_l2_cache_hits l2_cache l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all All L2 cache hits 00l2_cache_hits_from_l1_ic_miss l2_cache l2_cache_req_stat.ic_hit_in_l2 L2 cache hits from L1 instruction cache misses 00l2_cache_hits_from_l1_dc_miss l2_cache l2_cache_req_stat.dc_hit_in_l2 L2 cache hits from L1 data cache misses 00l2_cache_hits_from_l2_hwpf l2_cache l2_pf_hit_l2.all L2 cache hits from L2 cache hardware prefetcher 00l3_cache_accesses l3_cache l3_lookup_state.all_coherent_accesses_to_l3 L3 cache accesses 00l3_misses l3_cache l3_lookup_state.l3_miss L3 misses (including cacheline state change requests) 00l3_read_miss_latency l3_cache l3_xi_sampled_latency.all * 10 / l3_xi_sampled_latency_requests.all Average L3 read miss latency (in core clocks) 1core clocks 00op_cache_fetch_miss_ratio d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses) Op cache miss ratio for all fetches 100% 00ic_fetch_miss_ratio d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses) Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit 100% 00l1_data_cache_fills_from_memory l1_dcache ls_any_fills_from_sys.dram_io_all L1 data cache fills from DRAM or MMIO in any NUMA node 00l1_data_cache_fills_from_remote_node l1_dcache ls_any_fills_from_sys.far_all L1 data cache fills from a different NUMA node 00l1_data_cache_fills_from_same_ccx l1_dcache ls_any_fills_from_sys.local_all L1 data cache fills from within the same CCX 00l1_data_cache_fills_from_different_ccx l1_dcache ls_any_fills_from_sys.remote_cache L1 data cache fills from another CCX cache in any NUMA node 00all_l1_data_cache_fills l1_dcache ls_any_fills_from_sys.all All L1 data cache fills 00l1_demand_data_cache_fills_from_local_l2 l1_dcache ls_dmnd_fills_from_sys.local_l2 L1 demand data cache fills from local L2 cache 00l1_demand_data_cache_fills_from_same_ccx l1_dcache ls_dmnd_fills_from_sys.local_ccx L1 demand data cache fills from within the same CCX 00l1_demand_data_cache_fills_from_near_cache l1_dcache ls_dmnd_fills_from_sys.near_cache L1 demand data cache fills from another CCX cache in the same NUMA node 00l1_demand_data_cache_fills_from_near_memory l1_dcache ls_dmnd_fills_from_sys.dram_io_near L1 demand data cache fills from DRAM or MMIO in the same NUMA node 00l1_demand_data_cache_fills_from_far_cache l1_dcache ls_dmnd_fills_from_sys.far_cache L1 demand data cache fills from another CCX cache in a different NUMA node 00l1_demand_data_cache_fills_from_far_memory l1_dcache ls_dmnd_fills_from_sys.dram_io_far L1 demand data cache fills from DRAM or MMIO in a different NUMA node 00l1_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all L1 instruction TLB misses 00l2_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_miss.all L2 instruction TLB misses and instruction page walks 00l1_dtlb_misses tlb ls_l1_d_tlb_miss.all L1 data TLB misses 00l2_dtlb_misses tlb ls_l1_d_tlb_miss.all_l2_miss L2 data TLB misses and data page walks 00all_tlbs_flushed tlb ls_tlb_flush.all All TLBs flushed 00macro_ops_dispatched decoder de_src_op_disp.all Macro-ops dispatched 00sse_avx_stalls fp_disp_faults.sse_avx_all Mixed SSE/AVX stalls 00macro_ops_retired ex_ret_ops Macro-ops retired 00dram_read_data_for_local_processor data_fabric local_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11 DRAM read data for local processor 6.103515625e-5MiB 00dram_write_data_for_local_processor data_fabric local_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11 DRAM write data for local processor 6.103515625e-5MiB 00dram_read_data_for_remote_processor data_fabric remote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11 DRAM read data for remote processor 6.103515625e-5MiB 00dram_write_data_for_remote_processor data_fabric remote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11 DRAM write data for remote processor 6.103515625e-5MiB 00local_socket_upstream_dma_read_data data_fabric local_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3 Local socket upstream DMA read data 6.103515625e-5MiB 00local_socket_upstream_dma_write_data data_fabric local_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3 Local socket upstream DMA write data 6.103515625e-5MiB 00remote_socket_upstream_dma_read_data data_fabric remote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3 Remote socket upstream DMA read data 6.103515625e-5MiB 00remote_socket_upstream_dma_write_data data_fabric remote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3 Remote socket upstream DMA write data 6.103515625e-5MiB 00local_socket_inbound_data_to_cpu data_fabric local_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7 Local socket inbound data to the CPU (e.g. read data) 3.0517578125e-5MiB 00local_socket_outbound_data_from_cpu data_fabric local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7 Local socket outbound data from the CPU (e.g. write data) 6.103515625e-5MiB 00remote_socket_inbound_data_to_cpu data_fabric remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7 Remote socket inbound data to the CPU (e.g. read data) 3.0517578125e-5MiB 00remote_socket_outbound_data_from_cpu data_fabric remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7 Remote socket outbound data from the CPU (e.g. write data) 6.103515625e-5MiB 00local_socket_outbound_data_from_all_links data_fabric local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7 Outbound data from all links (local socket) 6.103515625e-5MiB 00umc_data_bus_utilization memory_controller d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk) Memory controller data bus utilization 100% 00umc_cas_cmd_rate memory_controller d_ratio(umc_cas_cmd.all * 1e3, umc_mem_clk) Memory controller CAS command rate 00umc_cas_cmd_read_ratio memory_controller d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all) Ratio of memory controller CAS commands for reads 100% 00umc_cas_cmd_write_ratio memory_controller d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all) Ratio of memory controller CAS commands for writes 100% 00umc_mem_read_bandwidth memory_controller umc_cas_cmd.rd * 64 / 1e6 / duration_time Estimated memory read bandwidth 1MB/s 00umc_mem_write_bandwidth memory_controller umc_cas_cmd.wr * 64 / 1e6 / duration_time Estimated memory write bandwidth 1MB/s 00umc_mem_bandwidth memory_controller umc_cas_cmd.all * 64 / 1e6 / duration_time Estimated combined memory bandwidth 1MB/s 00umc_activate_cmd_rate memory_controller d_ratio(umc_act_cmd.all * 1e3, umc_mem_clk) Memory controller ACTIVATE command rate 00umc_precharge_cmd_rate memory_controller d_ratio(umc_pchg_cmd.all * 1e3, umc_mem_clk) Memory controller PRECHARGE command rate 00C3_Core_Residency Power cstate_core@c3\-residency@ / TSC C3 residency percent per core 100% 00tma_4k_aliasing TopdownL4;tma_L4_group;tma_l1_bound_group LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_thread_clks tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound) 100% 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_thread_slots tma_alu_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 02tma_assists TopdownL4;tma_L4_group;tma_microcode_sequencer_group 100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY 100% 00tma_backend_bound TmaL1;TopdownL1;tma_L1_group 1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound 100% TopdownL1 02tma_bad_speculation TmaL1;TopdownL1;tma_L1_group (UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots tma_bad_speculation > 0.15 This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example 100% TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100% TopdownL2 01tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group 12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_thread_clks tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100% 00tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources 100% 02tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_core_bound Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group tma_backend_bound - tma_memory_bound tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100% TopdownL2 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_divider TopdownL3;tma_L3_group;tma_core_bound_group ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100% 00tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 01tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END 100% TopdownL2 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@ / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_frontend_bound PGO;TmaL1;TopdownL1;tma_L1_group IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound 100% TopdownL1 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_microcode_sequencer tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences 100% TopdownL2 00tma_icache_misses BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFDATA_STALL / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses 100% 00tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_thread_slots / BR_MISP_RETIRED.ALL_BRANCHES Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_mispredicts_resteers 00tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts tma_info_inst_mix_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\,umask\=0xE4@) tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmispredict Bad;BadSpec;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES tma_info_bad_spec_ipmispredict < 200 Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate) 00tma_info_core_core_clks SMT (CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_thread_clks)) Core actual clocks when any Logical Processor is active on the Physical Core 00tma_info_core_coreipc Ret;SMT;TmaL1;tma_L1_group INST_RETIRED.ANY / tma_info_core_core_clks Instructions Per Cycle across hyper-threads (per physical core) 00tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_core_fp_arith_utilization Cor;Flops;HPC (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC) Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_inst_mix_iptb, tma_lcp 00tma_info_inst_mix_bptkbranch Branches;Fed;PGO BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN Branch instructions per taken branch 00tma_info_inst_mix_instructions Summary;TmaL1;tma_L1_group INST_RETIRED.ANY Total number of retired Instructions Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST 00tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW 00tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_scalar_dp Flops;FpScalar;InsType INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE tma_info_inst_mix_iparith_scalar_dp < 10 Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_scalar_sp Flops;FpScalar;InsType INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE tma_info_inst_mix_iparith_scalar_sp < 10 Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_ipbranch Branches;Fed;InsType INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES tma_info_inst_mix_ipbranch < 8 Instructions per Branch (lower number means higher occurrence rate) 00tma_info_inst_mix_ipcall Branches;Fed;PGO INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL tma_info_inst_mix_ipcall < 200 Instructions per (near) call (lower number means higher occurrence rate) 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_ipload InsType INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate) 00tma_info_inst_mix_ipstore InsType INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 9 Instruction per taken branch Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_core_l1d_cache_fill_bw Mem;MemoryBW 64 * L1D.REPLACEMENT / 1e9 / duration_time Average per-core data fill bandwidth to the L1 data cache [GB / sec] 00tma_info_memory_core_l2_cache_fill_bw Mem;MemoryBW 64 * L2_LINES_IN.ALL / 1e9 / duration_time Average per-core data fill bandwidth to the L2 cache [GB / sec] 00tma_info_memory_core_l3_cache_fill_bw Mem;MemoryBW 64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time Average per-core data fill bandwidth to the L3 cache [GB / sec] 00tma_info_memory_l1mpki CacheMisses;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY L1 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l2hpki_all CacheMisses;Mem 1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY L2 cache hits per kilo instruction for all request types (including speculative) 00tma_info_memory_l2hpki_load CacheMisses;Mem 1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY L2 cache hits per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki Backend;CacheMisses;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY L2 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l2mpki_all CacheMisses;Mem;Offcore 1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative) 00tma_info_memory_l2mpki_load CacheMisses;Mem 1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l3mpki CacheMisses;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY L3 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB) Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 01tma_info_memory_mlp Mem;MemoryBW;MemoryBound L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) 01tma_info_memory_oro_data_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Average Parallel L2 cache miss data reads 00tma_info_memory_oro_load_l2_miss_latency Memory_Lat;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD Average Latency for L2 cache miss demand Loads 00tma_info_memory_oro_load_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Average Parallel L2 cache miss demand Loads 00tma_info_memory_thread_l3_cache_access_bw_1t Mem;MemoryBW;Offcore 0 Average per-thread data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / tma_info_core_core_clks tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\,cmask\=1@ Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread 00tma_info_pipeline_retire Pipeline;Ret UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\,cmask\=1@ Average number of Uops retired in cycles where at least one uop has retired 00tma_info_system_cpu_utilization HPC;Summary CPU_CLK_UNHALTED.REF_TSC / TSC Average CPU Utilization 00tma_info_system_dram_bw_use HPC;Mem;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full 00tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine 00tma_info_system_ipfarbranch Branches;OS INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u tma_info_system_ipfarbranch < 1e6 Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate] 00tma_info_system_kernel_cpi OS CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k Cycles Per Instruction for the Operating System (OS) Kernel mode 00tma_info_system_mem_parallel_requests Mem;SoC UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST Average number of parallel requests to external memory Average number of parallel requests to external memory. Accounts for all requests 00tma_info_system_mem_request_latency Mem;SoC UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL Average latency of all requests to external memory (in Uncore cycles) 00tma_info_system_smt_2t_utilization SMT (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0) Fraction of cycles where both hardware Logical Processors were active 00tma_info_thread_clks Pipeline CPU_CLK_UNHALTED.THREAD Per-Logical Processor actual clocks when the Logical Processor is active 00tma_info_thread_execute_per_issue Cor;Pipeline UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage 00tma_info_thread_ipc Ret;Summary INST_RETIRED.ANY / tma_info_thread_clks Instructions Per Cycle (per Logical Processor) 00tma_info_thread_slots TmaL1;tma_L1_group 4 * tma_info_core_core_clks Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward) 00tma_info_thread_uoppi Pipeline;Ret;Retire UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY tma_info_thread_uoppi > 1.05 Uops Per Instruction 00tma_info_thread_uptb Branches;Fed;FetchBW UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 6 Instruction per taken branch 00tma_itlb_misses BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100% 00tma_l1_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB ILD_STALL.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100% 00tma_light_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_retiring - tma_heavy_operations tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST 100% TopdownL2 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 02tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 01tma_machine_clears BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn tma_bad_speculation - tma_branch_mispredicts tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2 01tma_mem_bandwidth MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_mem_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 2 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_2 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_core_clks tma_port_2 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2 100% 00tma_port_3 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_core_clks tma_port_3 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3 100% 00tma_port_4 TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group tma_store_op_utilization tma_port_4 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores 100% 00tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_port_7 TopdownL6;tma_L6_group;tma_store_op_utilization_group UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_core_clks tma_port_7 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,inv\,cmask\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_core_clks) tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) 100% 00tma_retiring TmaL1;TopdownL1;tma_L1_group UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS 100% TopdownL1 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS 100% 01tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group 2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_sq_full MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group RESOURCE_STALLS.SB / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100% 00tma_store_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 01tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_core_clks tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations 100% 00tma_unknown_branches BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY 100% 00tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group INST_RETIRED.X87 * tma_info_thread_uoppi / UOPS_RETIRED.RETIRE_SLOTS tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00tma_assists TopdownL4;tma_L4_group;tma_microcode_sequencer_group 100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_backend_bound TmaL1;TopdownL1;tma_L1_group 1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1 02tma_branch_mispredicts BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100% TopdownL2 01tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_divider TopdownL3;tma_L3_group;tma_core_bound_group ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 03tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2 00tma_frontend_bound PGO;TmaL1;TopdownL1;tma_L1_group IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100% TopdownL1 00tma_icache_misses BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFDATA_STALL / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_system_dram_bw_use HPC;Mem;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full 00tma_info_system_socket_clks SoC cbox_0@event\=0x0@ Socket actual clocks when any core is active on that socket 00tma_itlb_misses BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100% 00tma_l1_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 03tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100% 02tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 01tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_2 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_core_clks tma_port_2 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) 100% 00tma_port_3 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_core_clks tma_port_3 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) 100% 00tma_port_4 TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group tma_store_op_utilization tma_port_4 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Related metrics: tma_split_stores 100% 00tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_port_7 TopdownL6;tma_L6_group;tma_store_op_utilization_group UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_core_clks tma_port_7 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 00tma_retiring TmaL1;TopdownL1;tma_L1_group UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100% TopdownL1 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 01tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group 2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group RESOURCE_STALLS.SB / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100% 00tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_core_clks tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100% 00tma_unknown_branches BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100% 00cpi CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles 1per_instr 00cpu_operating_frequency CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 CPU operating frequency (in GHz) 1GHz 00cpu_utilization tma_info_system_cpu_utilization Percentage of time spent in the active CPU power state C0 100% 00dtlb_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00dtlb_store_mpi DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00io_bandwidth_read cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x19e@ * 64 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00io_bandwidth_write (cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x1c8\,filter_tid\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x180\,filter_tid\=0x3e@) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00itlb_large_page_mpi ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB 1per_instr 00itlb_mpi ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB 1per_instr 00l1_i_code_read_misses_with_prefetches_per_instr L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions 1per_instr 00l1d_demand_data_read_hits_per_instr MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions 1per_instr 00l1d_mpi L1D.REPLACEMENT / INST_RETIRED.ANY Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions 1per_instr 00l2_demand_code_mpi L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY Ratio of number of code read request missing L2 cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_hits_per_instr MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_mpi MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY Ratio of number of completed data read request missing L2 cache to the total number of completed instructions 1per_instr 00l2_mpi L2_LINES_IN.ALL / INST_RETIRED.ANY Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions 1per_instr 00llc_code_read_mpi_demand_plus_prefetch (cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x191@) / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_data_read_demand_plus_prefetch_miss_latency 1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests 1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests 1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00llc_data_read_mpi_demand_plus_prefetch (cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x192@) / INST_RETIRED.ANY Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00loads_per_instr MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY The ratio of number of completed memory load instructions to the total number completed instructions 1per_instr 00memory_bandwidth_read UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time DDR memory read bandwidth (MB/sec) 1MB/s 00memory_bandwidth_total (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time DDR memory bandwidth (MB/sec) 1MB/s 00memory_bandwidth_write UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time DDR memory write bandwidth (MB/sec) 1MB/s 00numa_reads_addressed_to_local_dram cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@) Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00numa_reads_addressed_to_remote_dram cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@) Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00percent_uops_delivered_from_decoded_icache IDQ.DSB_UOPS / UOPS_ISSUED.ANY Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_legacy_decode_pipeline IDQ.MITE_UOPS / UOPS_ISSUED.ANY Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_loop_stream_detector LSD.UOPS / UOPS_ISSUED.ANY Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_microcode_sequencer IDQ.MS_UOPS / UOPS_ISSUED.ANY Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue 100% 00qpi_data_transmit_bw UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec) 1MB/s 00stores_per_instr MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY The ratio of number of completed memory store instructions to the total number completed instructions 1per_instr 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182\,thresh\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\=0x182@) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_local_dram Server;TopdownL5;tma_L5_group;tma_mem_latency_group 200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS 100% 01tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 01tma_remote_dram Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 01uncore_frequency UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time Uncore operating frequency in GHz 1GHz 00dtlb_2mb_large_page_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB 1per_instr 00io_bandwidth_read (UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00io_bandwidth_write (UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00l1d_demand_data_read_hits_per_instr MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_hits_per_instr MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions 1per_instr 00l2_demand_data_read_mpi MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY Ratio of number of completed data read request missing L2 cache to the total number of completed instructions 1per_instr 00llc_code_read_mpi_demand_plus_prefetch cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x12CC0233@ / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_data_read_demand_plus_prefetch_miss_latency 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40433@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40433@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40432@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40431@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00llc_data_read_mpi_demand_plus_prefetch cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x12D40433@ / INST_RETIRED.ANY Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_miss_local_memory_bandwidth_read UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory 1MB/s 00llc_miss_local_memory_bandwidth_write UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory 1MB/s 00llc_miss_remote_memory_bandwidth_read UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory 1MB/s 00loads_per_instr MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY The ratio of number of completed memory load instructions to the total number completed instructions 1per_instr 00numa_reads_addressed_to_local_dram cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ / (cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ + cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00numa_reads_addressed_to_remote_dram cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@ / (cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ + cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00percent_uops_delivered_from_decoded_icache IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS) Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_legacy_decode_pipeline IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS) Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue 100% 00percent_uops_delivered_from_microcode_sequencer IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS) Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue 100% 00pmem_memory_bandwidth_read UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec) 1MB/s 00pmem_memory_bandwidth_total (UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec) 1MB/s 00pmem_memory_bandwidth_write UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec) 1MB/s 00stores_per_instr MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY The ratio of number of completed memory store instructions to the total number completed instructions 1per_instr 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_thread_slots tma_alu_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_assists TopdownL4;tma_L4_group;tma_microcode_sequencer_group 100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY 100% 00tma_backend_bound TmaL1;TopdownL1;tma_L1_group 1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound 100% TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2 01tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks + tma_unknown_branches tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100% 00tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources 100% 00tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + 44 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 44 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu@INST_DECODED.DECODERS\,cmask\=1@ - cpu@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35)) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100% 00tma_divider TopdownL3;tma_L3_group;tma_core_bound_group ARITH.DIVIDER_ACTIVE / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound - tma_pmm_bound if #has_pmem > 0 else CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 01tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% 00tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 100% 02tma_dtlb_store MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (9 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs 100% 00tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (110 * tma_info_system_average_frequency * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_average_frequency * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_fb_full MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 02tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 tma_heavy_operations - tma_microcode_sequencer tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100% 00tma_fp_arith HPC;TopdownL3;tma_L3_group;tma_light_operations_group tma_x87_use + tma_fp_scalar + tma_fp_vector tma_fp_arith > 0.2 & tma_light_operations > 0.6 This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired) This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of "Uops" CountDomain and FMA double-counting 100% 01tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@ / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 01tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fused_instructions Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples 100% 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences 100% TopdownL2 00tma_icache_misses BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group (ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@) / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_bad_spec_ipmispredict Bad;BadSpec;BrMispredicts tma_info_core_ipmispredict tma_info_bad_spec_ipmispredict < 200 Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate) 00tma_info_botlnk_l0_core_bound_likely Cor;SMT (100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0) tma_info_botlnk_l0_core_bound_likely > 0.5 Probability of Core Bound bottleneck hidden by SMT-profiling artifacts 01tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 01tma_info_bottleneck_big_code BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC 100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) tma_info_bottleneck_big_code > 20 Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses) Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_bottleneck_branching_overhead 01tma_info_bottleneck_branching_overhead Ret;tma_issueBC 100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_thread_slots) tma_info_bottleneck_branching_overhead > 10 Total pipeline cost of branch related instructions (used for program control-flow including function calls) Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_bottleneck_big_code 00tma_info_bottleneck_instruction_fetch_bw Fed;FetchBW;Frontend 100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code tma_info_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks 01tma_info_bottleneck_memory_bandwidth Mem;MemoryBW;Offcore;tma_issueBW 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) tma_info_bottleneck_memory_bandwidth > 20 Total pipeline cost of (external) Memory Bandwidth related bottlenecks Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 01tma_info_bottleneck_memory_data_tlbs Mem;MemoryTLB;Offcore;tma_issueTLB 100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store 01tma_info_bottleneck_memory_latency Mem;MemoryLat;Offcore;tma_issueLat 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) tma_info_bottleneck_memory_latency > 20 Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches) Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency 01tma_info_bottleneck_mispredictions Bad;BadSpec;BrMispredicts;tma_issueBM 100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_bottleneck_mispredictions > 20 Total pipeline cost of Branch Misprediction related bottlenecks Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 01tma_info_branches_callret Bad;Branches (BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are CALL or RET 00tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are non-taken conditionals 00tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are taken conditionals 00tma_info_branches_jump Bad;Branches (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are unconditional (direct or indirect) jumps 01tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 01tma_info_core_fp_arith_utilization Cor;Flops;HPC (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1) Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core 00tma_info_core_ipmispredict Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES Number of Instructions per non-speculative Branch Misprediction (JEClear) TopdownL1 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_dsb_switch_cost DSBmiss DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details 00tma_info_frontend_fetch_upc Fed;FetchBW UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\,cmask\=1@ Average number of Uops issued by front-end when it issued something 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ + 2 Average Latency for L1 instruction cache misses 00tma_info_frontend_ipdsb_miss_ret DSBmiss;Fed INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS tma_info_frontend_ipdsb_miss_ret < 50 Instructions per non-speculative DSB miss (lower number means higher occurrence rate) 00tma_info_frontend_l2mpki_code IcMiss 1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY L2 cache true code cacheline misses per kilo instruction 00tma_info_frontend_l2mpki_code_all IcMiss 1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY L2 cache speculative code cacheline misses per kilo instruction 00tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW 01tma_info_inst_mix_iparith_avx512 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx512 < 10 Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 01tma_info_inst_mix_ipload InsType INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate) 00tma_info_inst_mix_ipstore InsType INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate) 00tma_info_inst_mix_ipswpf Prefetches INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\,umask\=0xF@ tma_info_inst_mix_ipswpf < 100 Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 9 Instruction per taken branch Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_core_l2_evictions_nonsilent_pki L2Evicts;Mem;Server 1e3 * L2_LINES_OUT.NON_SILENT / tma_info_inst_mix_instructions Rate of non silent evictions from the L2 cache per Kilo instruction 00tma_info_memory_core_l2_evictions_silent_pki L2Evicts;Mem;Server 1e3 * L2_LINES_OUT.SILENT / tma_info_inst_mix_instructions Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory) 00tma_info_memory_core_l3_cache_access_bw Mem;MemoryBW;Offcore 64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time Average per-core data access bandwidth to the L3 cache [GB / sec] 00tma_info_memory_fb_hpki CacheMisses;Mem 1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries) 00tma_info_memory_l1mpki CacheMisses;Mem 1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY L1 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l1mpki_load CacheMisses;Mem 1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY L1 cache true misses per kilo instruction for all demand loads (including speculative) 00tma_info_memory_l2mpki Backend;CacheMisses;Mem 1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY L2 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_l3mpki CacheMisses;Mem 1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY L3 cache true misses per kilo instruction for retired demand loads 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT) Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 00tma_info_memory_mlp Mem;MemoryBW;MemoryBound L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) 00tma_info_memory_tlb_code_stlb_mpki Fed;MemoryTLB 1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_load_stlb_mpki Mem;MemoryTLB 1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 02tma_info_memory_tlb_store_stlb_mpki Mem;MemoryTLB 1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk) 00tma_info_system_dram_bw_use HPC;Mem;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_mem_bandwidth, tma_sq_full 00tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine 01tma_info_system_io_read_bw IoBW;Mem;Server;SoC (UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Reads [GB / sec] 00tma_info_system_io_write_bw IoBW;Mem;Server;SoC (UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Writes [GB / sec] 00tma_info_system_mem_dram_read_latency Mem;MemoryLat;Server;SoC 1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\=0x0@ Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_pmm_read_latency Mem;MemoryLat;Server;SoC (1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\=0x0@ if #has_pmem > 0 else 0) Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_info_system_pmm_read_bw Mem;MemoryBW;Server;SoC (64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0) Average 3DXP Memory Bandwidth Use for reads [GB / sec] 00tma_info_system_pmm_write_bw Mem;MemoryBW;Server;SoC (64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0) Average 3DXP Memory Bandwidth Use for Writes [GB / sec] 00tma_info_system_power_license0_utilization Power (CORE_POWER.LVL0_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_core_clks) Fraction of Core cycles where the core was running with power-delivery for baseline license level 0 Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes 00tma_info_system_power_license1_utilization Power (CORE_POWER.LVL1_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks) tma_info_system_power_license1_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 1 Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions 00tma_info_system_power_license2_utilization Power (CORE_POWER.LVL2_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks) tma_info_system_power_license2_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX) Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions 00tma_info_system_socket_clks SoC cha_0@event\=0x0@ Socket actual clocks when any core is active on that socket 00tma_itlb_misses BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_64B.IFTAG_STALL / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100% 00tma_l2_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks) tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 01tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 00tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 17 * tma_info_system_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency 100% 00tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB ILD_STALL.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100% 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 00tma_load_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group tma_dtlb_load - tma_load_stlb_miss tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB) 100% 02tma_load_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_thread_clks tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk 100% 00tma_local_dram Server;TopdownL5;tma_L5_group;tma_mem_latency_group 59.5 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 00tma_mem_bandwidth MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_mem_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_memory_latency, tma_l3_hit_latency 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions 100% 00tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY tma_mixing_vectors > 0.05 The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100% 00tma_non_fused_branches Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100% 00tma_nop_instructions Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS tma_nop_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100% 00tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100% 00tma_pmm_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 0)) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module 100% 01tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_core_core_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / tma_info_core_core_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_core_core_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) 100% 00tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (89.5 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 89.5 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 02tma_remote_dram Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 127 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00tma_serializing_operation PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100% 00tma_slow_pause TopdownL6;tma_L6_group;tma_serializing_operation_group 40 * ROB_MISC_EVENTS.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100% 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 02tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 00tma_sq_full MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group EXE_ACTIVITY.BOUND_ON_STORES / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100% 00tma_store_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 02tma_store_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_core_clks tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk 100% 00tma_unknown_branches BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group 9 * BACLEARS.ANY / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY 100% 00tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00uncore_frequency UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time Uncore operating frequency in GHz 1GHz 00upi_data_receive_bw UNC_UPI_RxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec) 1MB/s 00upi_data_transmit_bw UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec) 1MB/s 00IoBW LLC_MISSES.PCIE_READ UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus 4Bytes 00LLC_MISSES.PCIE_WRITE UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus 4Bytes 00UNC_M_PMM_BANDWIDTH.TOTAL UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts 6.103515625E-5MB/sec 00UNC_M_PMM_READ_LATENCY UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all 6000000000ns 00power_channel_ppd UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100 Cycles where DRAM ranks are in power down (CKE) mode+C37 Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of 00power_self_refresh UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS * 100 Cycles Memory is in self refresh power mode Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases 00IPC INST_RETIRED.ANY / cycles Instructions Per Cycle (per Logical Processor) 00CPI 1 / IPC Cycles Per Instruction (per Logical Processor) 00CLKS cycles Per-Logical Processor actual clocks when the Logical Processor is active 00IpMispredict INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES Number of Instructions per non-speculative Branch Misprediction (JEClear) 00IpBranch INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES Instructions per Branch (lower number means higher occurrence rate) 00Instructions INST_RETIRED.ANY Total number of retired Instructions 00L3_Cache_Fill_BW 64 * LONGEST_LAT_CACHE.MISS / 1e9 Average per-core data fill bandwidth to the L3 cache [GB / sec] 00CPU_Utilization CPU_CLK_UNHALTED.REF_TSC / msr@tsc@ Average CPU Utilization 00Average_Frequency cycles / CPU_CLK_UNHALTED.REF_TSC * msr@tsc@ / 1e9 Measured Average Frequency for unhalted processors [GHz] 00Turbo_Utilization cycles / CPU_CLK_UNHALTED.REF_TSC Average Frequency Utilization relative nominal frequency 00Kernel_Utilization cycles:k / cycles Fraction of cycles spent in the Operating System (OS) Kernel mode 00tma_divider TopdownL3;tma_L3_group;tma_core_bound_group 10 * ARITH.DIVIDER_UOPS / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 01tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END 100% TopdownL2 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil (UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@)) Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_core_clks tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_itlb_misses BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100% 00tma_l1_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_mem_bandwidth MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=6@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group ((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,inv\,cmask\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_core_clks) tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / tma_info_core_core_clks) tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / tma_info_core_core_clks) tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / tma_info_core_core_clks tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) 100% 00tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group INST_RETIRED.X87 * tma_info_thread_uoppi / UOPS_RETIRED.RETIRE_SLOTS tma_x87_use > 0.1 This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00io_bandwidth_write cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x1c8\,filter_tid\=0x3e@ * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00percent_uops_delivered_from_loop_stream_detector (UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue 100% 00tma_4k_aliasing TopdownL4;tma_L4_group;tma_l1_bound_group LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_thread_clks tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound) 100% 02tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * tma_info_core_core_clks) tma_alu_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_assists TopdownL4;tma_L4_group;tma_microcode_sequencer_group 100 * ASSISTS.ANY / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_backend_bound Default;TmaL1;TopdownL1;tma_L1_group topdown\-be\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\,cmask\=1\,edge@ / tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1;Default TopdownL1 00tma_branch_instructions Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_thread_slots) tma_branch_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions 100% 00tma_branch_mispredicts BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (29 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 23.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu@INST_DECODED.DECODERS\,cmask\=1@ - cpu@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35)) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 01tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100% 00tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 100% 00tma_dtlb_store MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs 100% 00tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 32.5 * tma_info_system_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fb_full MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group L1D_PEND_MISS.FB_FULL / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100% 00tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2 00tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group (5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@ / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_frontend_bound Default;PGO;TmaL1;TopdownL1;tma_L1_group topdown\-fe\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100% TopdownL1;Default TopdownL1 00tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\,cmask\=1@) / IDQ.MITE_UOPS tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences 100% TopdownL2 00tma_icache_misses BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_16B.IFDATA_STALL / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_thread_slots / BR_MISP_RETIRED.ALL_BRANCHES Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 01tma_info_bad_spec_ipmisp_cond_ntaken Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN tma_info_bad_spec_ipmisp_cond_ntaken < 200 Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_cond_taken Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN tma_info_bad_spec_ipmisp_cond_taken < 200 Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate) 00tma_info_bad_spec_ipmisp_ret Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.RET tma_info_bad_spec_ipmisp_ret < 500 Instructions per retired mispredicts for return branches (lower number means higher occurrence rate) 00tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 01tma_info_botlnk_l2_ic_misses Fed;FetchLat;IcMiss;tma_issueFL 100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_botlnk_l2_ic_misses > 5 Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: 01tma_info_bottleneck_branching_overhead Ret;tma_issueBC 100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_thread_slots) tma_info_bottleneck_branching_overhead > 10 Total pipeline cost of branch related instructions (used for program control-flow including function calls) Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_bottleneck_big_code 00tma_info_bottleneck_memory_bandwidth Mem;MemoryBW;Offcore;tma_issueBW 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) tma_info_bottleneck_memory_bandwidth > 20 Total pipeline cost of (external) Memory Bandwidth related bottlenecks Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 01tma_info_bottleneck_memory_data_tlbs Mem;MemoryTLB;Offcore;tma_issueTLB 100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store 01tma_info_bottleneck_memory_latency Mem;MemoryLat;Offcore;tma_issueLat 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) tma_info_bottleneck_memory_latency > 20 Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches) Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency 01tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are non-taken conditionals 00tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are taken conditionals 00tma_info_branches_jump Bad;Branches (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES Fraction of branches that are unconditional (direct or indirect) jumps 00tma_info_core_core_clks SMT CPU_CLK_UNHALTED.DISTRIBUTED Core actual clocks when any Logical Processor is active on the Physical Core 00tma_info_core_flopc Flops;Ret (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\,umask\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\,umask\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / UOPS_ISSUED.ANY tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_dsb_switch_cost DSBmiss DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\,cmask\=1\,edge@ Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ Average Latency for L1 instruction cache misses 00tma_info_frontend_lsd_coverage Fed;LSD LSD.UOPS / UOPS_ISSUED.ANY Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache) 00tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\,umask\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\,umask\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 11 Instruction per taken branch Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_l2mpki_all CacheMisses;Mem;Offcore 1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / tma_info_inst_mix_instructions L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative) 00tma_info_memory_oro_load_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,cmask\=1@ Average Parallel L2 cache miss demand Loads 00tma_info_memory_oro_load_l3_miss_latency Memory_Lat;Offcore cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,umask\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Average Latency for L3 cache miss demand Loads 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_pipeline_retire Pipeline;Ret tma_retiring * tma_info_thread_slots / cpu@UOPS_RETIRED.SLOTS\,cmask\=1@ Average number of Uops retired in cycles where at least one uop has retired 00tma_info_system_gflops Cor;Flops;HPC (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\,umask\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\,umask\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine 00tma_info_system_power_license0_utilization Power CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_core_clks Fraction of Core cycles where the core was running with power-delivery for baseline license level 0 Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes 00tma_info_system_power_license1_utilization Power CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks tma_info_system_power_license1_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 1 Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions 00tma_info_system_power_license2_utilization Power CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks tma_info_system_power_license2_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX) Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions 00tma_info_system_smt_2t_utilization SMT (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0) Fraction of cycles where both hardware Logical Processors were active 00tma_info_thread_slots TmaL1;tma_L1_group TOPDOWN.SLOTS Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward) 00tma_info_thread_slots_utilization SMT;TmaL1;tma_L1_group (tma_info_thread_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1) Fraction of Physical Core issue-slots utilized by this Logical Processor 00tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 7.5 Instruction per taken branch 00tma_l2_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks) tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 01tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 02tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 9 * tma_info_system_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency 100% 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED.PORT_2_3 / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 01tma_lsd FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_core_clks / 2 tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 00tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 01tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS tma_retiring * tma_info_thread_slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2 tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100% 00tma_mite_4wide DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group (cpu@IDQ.MITE_UOPS\,cmask\=4@ - cpu@IDQ.MITE_UOPS\,cmask\=5@) / tma_info_thread_clks tma_mite_4wide > 0.05 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35)) This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_nop_instructions Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_thread_slots) tma_nop_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100% 00tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100% 01tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((cpu@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ / tma_info_thread_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group EXE_ACTIVITY.1_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_ports_utilized_3m PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 00tma_retiring Default;TmaL1;TopdownL1;tma_L1_group topdown\-retiring / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100% TopdownL1;Default TopdownL1 00tma_serializing_operation PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100% 00tma_slow_pause TopdownL6;tma_L6_group;tma_serializing_operation_group 140 * MISC_RETIRED.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100% 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100% 00tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100% 02tma_sq_full MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group L1D_PEND_MISS.L2_STALL / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100% 02tma_store_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 00tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_core_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100% 00tma_streaming_stores MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group 9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_thread_clks tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full 100% 00tma_unknown_branches BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group 10 * BACLEARS.ANY / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY 100% 00dtlb_2nd_level_2mb_large_page_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB 1per_instr 00dtlb_2nd_level_load_mpi DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00dtlb_2nd_level_store_mpi DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr 00io_bandwidth_write (UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00itlb_2nd_level_large_page_mpi ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB 1per_instr 00itlb_2nd_level_mpi ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB 1per_instr 00llc_code_read_mpi_demand_plus_prefetch (UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_demand_data_read_miss_latency 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds 1ns 00llc_demand_data_read_miss_latency_for_local_requests 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_demand_data_read_miss_latency_for_remote_requests 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00llc_demand_data_read_miss_to_pmem_latency 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds 1ns 00llc_miss_remote_memory_bandwidth_write UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory 1MB/s 00memory_extra_write_bw_due_to_directory_updates (UNC_CHA_DIR_UPDATE.HA + UNC_CHA_DIR_UPDATE.TOR + UNC_M2M_DIRECTORY_UPDATE.ANY) * 64 / 1e6 / duration_time Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM) 1MB/s 00numa_reads_addressed_to_local_dram (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00numa_reads_addressed_to_remote_dram (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 43.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43.5 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 48 * tma_info_system_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_info_bottleneck_memory_data_tlbs Mem;MemoryTLB;Offcore;tma_issueTLB 100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store 01tma_info_system_io_read_bw IoBW;Mem;Server;SoC (UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Reads [GB / sec] 00tma_info_system_io_write_bw IoBW;Mem;Server;SoC UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time Average IO (network or disk) Bandwidth Use for Writes [GB / sec] 00tma_info_system_mem_dram_read_latency Mem;MemoryLat;Server;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\=0x0@ Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_pmm_read_latency Mem;MemoryLat;Server;SoC (1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\=0x0@ if #has_pmem > 0 else 0) Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 19 * tma_info_system_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency 100% 00tma_local_dram Server;TopdownL5;tma_L5_group;tma_mem_latency_group 43.5 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS 100% 00tma_pmm_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 0)) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module 100% 00tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (97 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 97 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 00tma_remote_dram Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 108 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00tma_slow_pause TopdownL6;tma_L6_group;tma_serializing_operation_group 37 * MISC_RETIRED.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100% 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5) / (3 * tma_info_core_core_clks) tma_alu_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 02tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_dtlb_store MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100% 00tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_icache_misses BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFETCH_STALL / tma_info_thread_clks - tma_itlb_misses tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses 100% 00tma_info_core_flopc Flops;Ret (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 00tma_info_inst_mix_iparith Flops;InsType 1 / (tma_fp_scalar + tma_fp_vector) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW 00tma_info_memory_l3mpki CacheMisses;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY L3 cache true misses per kilo instruction for retired demand loads 00tma_info_system_gflops Cor;Flops;HPC (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine 00tma_itlb_misses BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100% 00tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100% 02tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks) tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 00tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS 100% 01tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100% 01tma_local_dram Server;TopdownL5;tma_L5_group;tma_mem_latency_group 200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS 100% 01tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 01tma_remote_dram Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 01tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp 100% 00tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100% 00tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_lcp 100% TopdownL2 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100% 00tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\,cmask\=1@) Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_lcp 00tma_info_system_dram_bw_use HPC;Mem;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth 00tma_info_thread_execute_per_issue Cor;Pipeline UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage 00tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB ILD_STALL.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage 100% 00tma_machine_clears BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn tma_bad_speculation - tma_branch_mispredicts tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2 01tma_mem_bandwidth MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=6@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_system_dram_bw_use 100% 00tma_mem_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: 100% 00tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\,cmask\=1@ - (cpu@UOPS_DISPATCHED.THREAD\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2 01tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\,cmask\=1@ - (cpu@UOPS_DISPATCHED.THREAD\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 01tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100% 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC (UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_info_system_mem_request_latency Mem;SoC (UNC_ARB_TRK_OCCUPANCY.ALL + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.ALL Average latency of all requests to external memory (in Uncore cycles) 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100% 03tma_info_system_dram_bw_use HPC;Mem;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth 00tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100% 03tma_mem_bandwidth_group Metrics contributing to tma_mem_bandwidth category io_bandwidth_read UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU 1MB/s 00io_bandwidth_write (UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU 1MB/s 00llc_code_read_mpi_demand_plus_prefetch UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_data_read_mpi_demand_plus_prefetch (UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions 1per_instr 00llc_demand_data_read_miss_to_dram_latency 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds 1ns 00tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_core_clks) tma_alu_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations 100% 00tma_amx_busy Compute;HPC;Server;TopdownL5;tma_L5_group;tma_ports_utilized_0_group EXE.AMX_BUSY / tma_info_core_core_clks tma_amx_busy > 0.5 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations 100% 00tma_assists TopdownL4;tma_L4_group;tma_microcode_sequencer_group 100 * cpu@ASSISTS.ANY\,umask\=0x1B@ / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100% 00tma_avx_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 63 * ASSISTS.SSE_AVX_MIX / tma_info_thread_slots tma_avx_assists > 0.1 This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists 100% 00tma_backend_bound Default;TmaL1;TopdownL1;tma_L1_group topdown\-be\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100% TopdownL1;Default TopdownL1 00tma_branch_mispredicts BadSpec;BrMispredicts;Default;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM topdown\-br\-mispredict / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers 100% TopdownL2;Default TopdownL2 00tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (76 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 75.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_core_bound Backend;Compute;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group max(0, tma_backend_bound - tma_memory_bound) tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100% TopdownL2;Default TopdownL2 00tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 75.5 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu@INST_DECODED.DECODERS\,cmask\=1@ - cpu@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35)) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100% 00tma_divider TopdownL3;tma_L3_group;tma_core_bound_group ARITH.DIV_ACTIVE / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100% 00tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks - tma_pmm_bound if #has_pmem > 0 else MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks) tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS 100% 00tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100% 00tma_dtlb_load MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs 100% 00tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 80 * tma_info_system_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_fetch_bandwidth Default;FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100% TopdownL2;Default TopdownL2 00tma_fetch_latency Default;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group topdown\-fetch\-lat / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100% TopdownL2;Default TopdownL2 00tma_fp_amx Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_L4_group;tma_fp_arith_group cpu@AMX_OPS_RETIRED.BF16\,cmask\=1@ / (tma_retiring * tma_info_thread_slots) tma_fp_amx > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine) This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp 100% 00tma_fp_arith HPC;TopdownL3;tma_L3_group;tma_light_operations_group tma_x87_use + tma_fp_scalar + tma_fp_vector + tma_fp_amx tma_fp_arith > 0.2 & tma_light_operations > 0.6 This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired) This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of "Uops" CountDomain and FMA double-counting 100% 00tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 30 * ASSISTS.FP / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100% 00tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR) / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@ + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_fused_instructions Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * tma_info_thread_slots) tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples 100% 00tma_heavy_operations Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group topdown\-heavy\-ops / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY 100% TopdownL2;Default TopdownL2 00tma_icache_misses BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_DATA.STALLS / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100% 00tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 00tma_info_bottleneck_memory_bandwidth Mem;MemoryBW;Offcore;tma_issueBW 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) tma_info_bottleneck_memory_bandwidth > 20 Total pipeline cost of (external) Memory Bandwidth related bottlenecks Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full 00tma_info_bottleneck_memory_data_tlbs Mem;MemoryTLB;Offcore;tma_issueTLB 100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store 00tma_info_bottleneck_memory_latency Mem;MemoryLat;Offcore;tma_issueLat 100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) tma_info_bottleneck_memory_latency > 20 Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches) Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency 00tma_info_core_flopc Flops;Ret cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\,umask\=0x18@ + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\,umask\=0x60@) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16 Floating Point Operations Per Cycle 00tma_info_core_fp_arith_utilization Cor;Flops;HPC (FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_core_clks) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common) 00tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / UOPS_ISSUED.ANY tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp 00tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\,cmask\=1\,edge@ Average Latency for L1 instruction cache misses 00tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR + (cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@ + FP_ARITH_INST_RETIRED2.VECTOR)) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW 00tma_info_inst_mix_iparith_amx_f16 Flops;FpVector;InsType;Server INST_RETIRED.ANY / AMX_OPS_RETIRED.BF16 tma_info_inst_mix_iparith_amx_f16 < 10 Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate) Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions 00tma_info_inst_mix_iparith_amx_int8 InsType;IntVector;Server INST_RETIRED.ANY / AMX_OPS_RETIRED.INT8 tma_info_inst_mix_iparith_amx_int8 < 10 Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate) Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions 00tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_iparith_avx512 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) tma_info_inst_mix_iparith_avx512 < 10 Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting 00tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / tma_info_core_flopc tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 00tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 13 Instruction per taken branch Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp 00tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY Actual Average Latency for L1 data-cache miss demand load operations (in core cycles) 00tma_info_memory_oro_load_l3_miss_latency Memory_Lat;Offcore OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Average Latency for L3 cache miss demand Loads 00tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses 00tma_info_pipeline_ipassist Pipeline;Ret;Retire INST_RETIRED.ANY / cpu@ASSISTS.ANY\,umask\=0x1B@ tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate) 00tma_info_pipeline_strings_cycles Pipeline;Ret INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\,cmask\=1@ tma_info_pipeline_strings_cycles > 0.1 Estimated fraction of retirement-cycles dealing with repeat instructions 00tma_info_system_gflops Cor;Flops;HPC tma_info_core_flopc / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine 00tma_info_system_mem_dram_read_latency Mem;MemoryLat;Server;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\=0x1@ Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_pmm_read_latency Mem;MemoryLat;Server;SoC (1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\=0x1@ if #has_pmem > 0 else 0) Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 01tma_info_system_socket_clks SoC uncore_cha_0@event\=0x1@ Socket actual clocks when any core is active on that socket 00tma_info_system_tiops Cor;HPC;IntVector;Server 8 * AMX_OPS_RETIRED.INT8 / 1e12 / duration_time Tera Integer (matrix) Operations Per Second 00tma_info_system_upi_data_transmit_bw Server;SoC UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1e6 Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec] 00tma_int_amx Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_L4_group;tma_int_operations_group cpu@AMX_OPS_RETIRED.INT8\,cmask\=1@ / (tma_retiring * tma_info_thread_slots) tma_int_amx > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine) This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp 100% 00tma_int_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_int_vector_128b + tma_int_vector_256b + tma_shuffles + tma_int_amx tma_int_operations > 0.1 & tma_light_operations > 0.6 This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired) This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of "Uops" CountDomain 100% 00tma_int_vector_128b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * tma_info_thread_slots) tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_int_vector_256b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_thread_slots) tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_itlb_misses BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_TAG.STALLS / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100% 00tma_l1_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 data cache This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100% 00tma_l2_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS 100% 00tma_l3_bound CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100% 00tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 33 * tma_info_system_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency 100% 00tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DECODE.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100% 00tma_light_operations Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group max(0, tma_retiring - tma_heavy_operations) tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST 100% TopdownL2;Default TopdownL2 00tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED.PORT_2_3_10 / (3 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100% 00tma_local_dram Server;TopdownL5;tma_L5_group;tma_mem_latency_group 71 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 00tma_machine_clears BadSpec;Default;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn max(0, tma_bad_speculation - tma_branch_mispredicts) tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100% TopdownL2;Default TopdownL2 00tma_mba_stalls MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group INT_MISC.MBA_STALLS / tma_info_thread_clks tma_mba_stalls > 0.1 & (tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling) 100% 00tma_memory_bound Backend;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group topdown\-mem\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 0 * tma_info_thread_slots tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100% TopdownL2;Default TopdownL2 00tma_memory_fence TopdownL6;tma_L6_group;tma_serializing_operation_group 13 * MISC2_RETIRED.LFENCE / tma_info_thread_clks tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))) This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions 100% 02tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * tma_info_thread_slots) tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses 100% 00tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.MS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100% 00tma_mispredicts_resteers BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions 100% 00tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2 tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 6 > 0.35) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100% 00tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group 160 * ASSISTS.SSE_AVX_MIX / tma_info_thread_clks tma_mixing_vectors > 0.05 The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100% 00tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (tma_retiring * tma_info_thread_slots / UOPS_ISSUED.ANY) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100% 00tma_non_fused_branches Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_thread_slots) tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100% 00tma_page_faults TopdownL5;tma_L5_group;tma_assists_group 99 * ASSISTS.PAGE_FAULT / tma_info_thread_slots tma_page_faults > 0.05 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost 100% 00tma_pmm_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 0)) * (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module 100% 00tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 00tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100% 00tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((cpu@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\,umask\=0xc@) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100% 00tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ / tma_info_thread_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100% 00tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100% 02tma_ports_utilized_3m PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100% 02tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (135.5 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 135.5 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100% 00tma_remote_dram Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 149 * tma_info_system_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100% 00tma_shuffles HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group INT_VEC_RETIRED.SHUFFLES / (tma_retiring * tma_info_thread_slots) tma_shuffles > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents Shuffle (cross "vector lane" data transfers) uops fraction the CPU has retired 100% 00tma_slow_pause TopdownL6;tma_L6_group;tma_serializing_operation_group CPU_CLK_UNHALTED.PAUSE / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST 100% 02tma_sq_full MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth 100% 00tma_store_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 00tma_unknown_branches BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100% 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (18.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 16.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 22 * tma_info_system_average_frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@ / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100% 01tma_info_bottleneck_memory_data_tlbs Mem;MemoryTLB;Offcore;tma_issueTLB 100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_info_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store 01tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_core_clks Floating Point Operations Per Cycle 01tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0x3c@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW 01tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) 01tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine 01tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@cmask\=1@ Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches 00tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ) / (tma_info_system_socket_clks / duration_time) Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only) 00tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 6.5 * tma_info_system_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency 100% 00tma_lock_latency Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100% 00tma_store_latency MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100% 02llc_data_read_demand_plus_prefetch_miss_latency 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40433@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40433@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40432@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds 1ns 00llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests 1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40431@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds 1ns 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 44 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 44 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (110 * tma_info_system_average_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_average_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 01uncore_frequency UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time Uncore operating frequency in GHz 1GHz 00power_channel_ppd UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100 Cycles where DRAM ranks are in power down (CKE) mode Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of 00LLC_MISSES.PCIE_READ UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 4Bytes 00LLC_MISSES.PCIE_WRITE UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 4Bytes 00power_channel_ppd UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100 Cycles where DRAM ranks are in power down (CKE) mode Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of 00power_self_refresh UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS * 100 Cycles Memory is in self refresh power mode Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases 00tma_contested_accesses DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (49 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 48 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_data_sharing Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 48 * tma_info_system_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100% 01tma_false_sharing DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 54 * tma_info_system_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100% 00tma_info_system_dram_bw_use HPC;Mem;MemoryBW;SoC;tma_issueBW 64 * (arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@) / 1e6 / duration_time / 1e3 Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_mem_bandwidth, tma_sq_full 00tma_info_system_mem_request_latency Mem;SoC (UNC_ARB_TRK_OCCUPANCY.ALL + UNC_ARB_DAT_OCCUPANCY.RD) / arb@event\=0x81\,umask\=0x1@ Average latency of all requests to external memory (in Uncore cycles) 00tma_l3_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 17.5 * tma_info_system_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency 100% 00 P ƏP P ƏP P ƏP P ƏP P ƏP .P ƏP 7P ƏP CP ƏP KP ƏP SP ƏP WP ƏP [P ƏP cP ƏP oP ƏP sP ƏP {P ƏP P ƏP P ƏP P ƏP P ƏP P ƏP P ƏP P ƏP P ƏP (T ƏP P ƏP (/ ƏP ːP ƏP ِP ƏP ݐP ƏP P ƏP P ƏP P ƏP P ƏP P ƏP P ƏP $P ƏP 'P ƏP /P ƏP 3P ƏP <P ƏP FP ƏP LP ƏP WP ƏP [P ƏP bP ƏP fP ƏP mP ƏP sP ƏP wP ƏP P ƏP P ƏP P ƏP P P ȑP ґP P P 0P :P dP nP P P ̒P P ْP ґP P P P :P P nP P P P 7P oP P P ʓP P P LP fP P P ԔP P #P 8P hP }P P P P P 5P OP P P ϖP P P $P SP lP P P P P >P JP pP |P P P ԘP P P P 8P DP jP vP P P ΙP ۙP P P 4P @P fP rP P P ̚P ؚP P P 0P >P fP tP P P ֛P P P P KP ^P P P ݜP P 4P MP -AV EAV P P ȝP P P *P \P zP P P P P %P AP xP P ɟP P P 5P iP |P P ʠP P P LP kP 'K K K OK K #K ˸N K SK K &K K K kK K OK K K K K X K K V K K $ K K K K K sK K PK `}N }N K k J J 2K K SK K >K 2K l~N b2K 2K H3K ~N 3K \N XN 4K 4K GN N J BJ J :J J J J J aJ J 5J J .J J %J K K wK K <K K rK K K SK K HK K ;K J 4K 5K E5K N 5K N #J J J SJ bJ J hJ J 8J J TJ J J KJ J J ZJ J hJ J J GJ J }J J J b J 0 J J J U J J J v J J ] J /!J !J J !J 7"J "J "J n#J #J #J $J $J %J p$J U%J %J &J l&J &J +'J 'J 'J D(J (J )J )J )J ?*J *J +J +J z+J 6,J J xN J MJ J J K ,J ,J #K K K {K K dK ,J J e-J .J .J I/J /J 0J /1J 1J o2J 3J 3J S4J 4J 5J 06J 6J S7J 6K 7J m8J 8J h9J 9J |:J 7K N N N 9N =J MN M iM M $M M M ?>J nM M ^M M uM M M M >J &?J [J J ?J A@J @J AJ JBJ CJ CJ yJ 0DJ DJ rEJ FJ J FJ J 5J EGJ GJ fHJ IJ IJ JJ KJ J KJ ZLJ MJ MJ _J @NJ J J NJ ]OJ OJ PJ iQJ RJ RJ J RSJ SJ TJ 1UJ J UJ EJ J jVJ VJ WJ BXJ XJ YJ <ZJ eJ ZJ w[J #\J \J J Z]J J J ]J g^J ^J _J O`J `J J gaJ aJ bJ )cJ -J cJ J XJ qdJ eJ eJ fJ EgJ hJ hJ J diJ jJ jJ ykJ J 'lJ MJ J lJ amJ nJ nJ oJ tpJ qJ }J qJ MrJ rJ sJ (J TtJ J pJ tJ uJ 4vJ vJ wJ |xJ yJ J yJ jzJ "{J {J J q|J SJ J }J }J Q~J J J J 4J J J J ?J J .J J J kJ 6J J kJ /J J J JJ J J J RJ J J J KJ J FJ ЍJ yJ <J J J TJ J J J YJ J J J J PJ AJ J `J J ͗J J J J NJ J J J 1J xJ J J bJ J ΞJ J MJ J J J 5J J J MJ 6J J J ݤJ gJ J ӦJ J RJ J "J J :J J J J ;J dJ J J jJ J ԮJ J QJ J J J 6J J J 6J 4J J mJ ٴJ aJ J ɶJ J DJ ۸J J J &J ںJ }J J !J DJ J ļJ JJ J J hJ %J J pJ cJ J J TJ J yJ K K o K K ; K K K k K K . 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" # D$ ߿N 5Q CN N N nN N O N N V6Q p9Q :Q >Q uBQ uEQ HQ KQ iNQ QQ WQ YQ b^Q `Q cQ eQ iQ \mQ qQ 6tQ wQ zQ jO +}Q Q Q RQ $Q #Q GQ Q Q >Q IQ }Q !Q Q ֙Q Q VO Q 0Q Q Q Q @Q Q Q ^Q $Q Q Q RQ Q -Q ӭQ Q )Q Q Q WQ Q Q Q Q еQ Q QQ O @O Q O Q Q qQ O 0Q Q Q Q LQ vO Q Q Q O O sQ .O Q Q Q 6Q Q dQ Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q $R IR R R k R R 0R R <R 3R R . R '"R %R 'R )R ,R w/R .3R 6R 7R L:R /8 1% & & ' ]( 1) ) * + t, @- . . / I0 1 1 2 3 6 6 7 = ç + w E ȱ 3 " & $ $ @ Һ н Z < T Z ei 6 ` Y ( Z 1 8 9 : ; ; < = ]? @ A B C 'D D `E F H wI jJ \ [ E o Ժ K t b 3 x R Q o k J 9 U g O 1 y P @ z L ,M @N N pO O P Q HS T B 9 E { u f ] l G _ 6 " e j k G S g X q F P : # ~ W z A v * D = ~ = $ g l n Z M > z F e 5 x k y Z a 9 ! u ! A" " A r Z K t# $ $ U% % & 4' ' ( T( m) B ) ~* b w 5 ! g! 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T y > 7 P ϶ ʷ Ѹ H Z 1 ? H 9 r r u (x { } M~ ~ } F v D z ۇ O ` ' x u ~ * Y G p W J u } = z g ߏ +# & k e T 1 >3 (4 $5 -6 _7 8 9 : ; N= > @ C A D E <G [I J L AM aN O xU 9 d ; ~o / D " t q w x Qy z { S| } } ~ L P { " ˃ o Ǣ ѣ o ٥ P c / # > " F S %# # & ' + () * 3, , >. / 0 x1 2 2 ]3 8 C; @ < > <A A C ]E E J gL ,T }[ c g s ? b fv z 4 A b z > u W! % і D % < I ( >* + , . G/ 0 0 P wQ 1R R S GT T U V W |Z $] _ xb e g pj m m = /p r s p 2 u rv ~ " z s W ñ Ҵ S n Ի I R 2 Y i # | T ; < N ĽN N >N N HN pN 1N ξN N N N N N VN " N W H G %d [ , %s%d ] /sys /proc /sys/kernel/debug /debug /sys/kernel/tracing /sys/kernel/debug/tracing /tracing /trace /sys/fs/bpf sysfs procfs debugfs tracefs hugetlbfs bpf r /proc/mounts %*s %4096s %99s %*s %*d %*d fs/fs.c !fs->path fs->path PERF_%s_ENVIRONMENT %d %s/%s %s/sys/%s fs__init_once %s/%s tracing/ %s/events/%s events * sdt_ Error: File %s/events/%s not found. Hint: SDT event cannot be directly recorded on. Please first use 'perf probe %s:%s' before recording it. Error: File %s/events/%s not found. Hint: Perhaps this kernel misses some CONFIG_ setting to enable this feature?. Error: Unable to find debugfs/tracefs Hint: Was your kernel compiled with debugfs/tracefs support? Hint: Is the debugfs/tracefs filesystem mounted? Hint: Try 'sudo mount -t debugfs nodev /sys/kernel/debug' %s Error: No permissions to read %s/events/%s Hint: Try 'sudo mount -o remount,mode=755 %s' r /proc/mounts cgroup , devices/system/cpu/online devices/system/cpu/cpu%d/cpufreq/cpuinfo_max_freq INTERNAL ERROR: strerror_r(%d, [buf], %zd)=%d /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/linux/refcount.h !(new == (~0U)) !(!refcount_inc_not_zero(r)) !(new > val) cpu_map refcnt unbalanced libperf: Number of online CPUs (%d) differs from the number configured (%d) the CPU map will only cover the first %d CPUs. r /sys/devices/system/cpu/online cpumap.c j <= nr_cpus %u%c Perf can support %d CPUs. Consider raising MAX_NR_CPUS libperf: Unexpected characters at end of cpu list ('%s'), using online CPUs. k <= tmp_len refcount_inc refcount_inc_not_zero refcount_sub_and_test cpu_map__trim_new perf_cpu_map__merge /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/linux/refcount.h !(new == (~0U)) !(!refcount_inc_not_zero(r)) !(new > val) thread map refcnt unbalanced refcount_inc refcount_inc_not_zero refcount_sub_and_test Clibperf: idx %d: mmapping fd %d libperf: idx %d: set output fd %d -> %d libperf: %s: nr cpu values (may include -1) %d nr threads %d libperf: Miscounted nr_mmaps %d vs %d libperf: %s: nr cpu values %d nr threads %d mmap_per_thread mmap_per_cpu /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/linux/refcount.h !(new == (~0U)) !(!refcount_inc_not_zero(r)) !(new > val) mmap.c !(map->base && refcount_read(&map->refcnt) == 0) libperf: %s: buf=%p, start=%lx libperf: Finished reading overwrite ring buffer: rewind libperf: Finished reading overwrite ring buffer: get start libperf: move evt_head: %lx failed to keep up with mmap data. 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F , |S ~ AC M7 H , S ~* AC DEEL A , S ~* AC DEEL A , T ~ AC eg A , <T м~B EJ DEJn H , lT ~b AC IJ A T 0~ EC A| K , T ~ EF DEFd B < T ~ EC V R n R P P P L P F , 0U \~ EJ FEK A , `U <~N AC e J U \~ EC G U ~ EJ A J ( U ~) EJ BH G 0 V ~ ES BIIEK F 8V ~J EH u C XV D~P EH { C xV t~J EH u C V ~z EC l A V ~P EH { C V 0~L EH w C $ V `~h EC t T P C $ $W ~h EC t T P C $ LW ~h EC s U P C $ tW 8~h EC t T P C $ W ~h EC t T P C $ W ~h EC s U P C $ W ~h EC t T P C $ X X~h EC t T P C $ <X ~h EC t T P C $ dX ~X EF p E P C X ~] EX z A X `~] EX z A X ~K EC y E X ~K EC w G , Y ~ EF DHED~ B ( <Y ~ EC BEDo F hY ~z EH AI A Y p~z EH AI A Y ~z EH AI A Y (~z EH AI A ( Y ~ EC BEDD I , $Z (~ AC M I ( TZ ~' AU M I , Z ~ AC FII E , Z ~A AC BEEN A Z ~ EL s \ [ ~n EC ` A $[ ~Z EC L A ( H[ EI BF G , t[ 3 AC P A , [ = AC BEGHi A , [ ( AC DEED{ G ( \ AC G A , 0\ EF DIJD< F , `\ \ EF DIJD< F , \ EF FJH G 0 \ EC BEIHD F 0 \ ( EF BEIEI D , (] 0 EF DIJD G , X] !( EF DIGD B , ] #( EF DIGD B , ] % EF KEJD E , ] ) EC BJGH A , ^ * EL BpJ A H^ G; EC j D h^ G; EC j D ^ G= EC l D ^ G= EC l D ^ H= EC l D ^ 4HR EE D $ _ tHX EC p H P C $ 0_ HX EC q G P C $ X_ HX EC q G P C $ _ IX EC q G P C $ _ TIX EC q G P C $ _ IX EC q G P C _ I1 EC c A , ` Iz AC BGJ@ I , H` 4K- EF M A , x` 4N| EF M D ( ` O EF M A ( ` xP EF M I ( a R EC DJv D $ ,a R EC GS A , Ta 8S AJ I/ E a TQ EC E a TQ EC E ( a 8U AV Kh A 0 a V EC g B V ` b $ $b W EC BHS K ( Lb X EF BEFi A $ xb tY EC BM~ K ( b Z EC DH] G b Zz EC l A , b Z AC FN A , c [) AO FTM A , Pc d EC c D d P X , c <f EC c D d P X , c g EC c D d P X ( c i4 EJ DFp G d 0kd EC V A , 0d |k EC BGEHl F ( `d \l EJ FD1 F , d @n EJ HD1 D , d p4 EJ HD D , d r] EJ FEH: D , e Pt# EC FED K , Le Pu EJ BJ G , |e 0|' EC \ A e h EC F J e w EC i A e XK EH v C f K EH v C 4f K EH v C $ Tf X EC q G P C |f 3 EC c C $ f @X EC q G P C $ f xX EC q G P C $ f X EF p E P C g 3 EC c C $ 4g p EI ~ L P C ( \g P AC A~ E q G , g AC FEDc J , g īY EC BEHH C , g EC DEI A ( h EC DKp A 0 Dh EC BEDM H [ A ( xh d* AU BEOj J h h AC Ar I $ h R AG BD A , h L AC BQ A i ,M AS n F , @i \ EC HD E , pi AC DFIH C , i \@ EC I B ( i l AC DJ^ H , i ( AC BEED D , ,j AC BNH5 A , \j AC BJEJ G , j EC DEI A ( j P EC BEHy H , j 4p EC FED F , k tV EF BELI J , Hk EF BEEPx A , xk 4U EC DHP C , k d EC BEHM2 J 0 k $ EC BEEHK\ A , l EC BID A , <l P EC BGEK A , ll j EC BEJD A , l @8 EC \C A l ' EP IP B $ l ( EC Iz A m ( EE AV G 4 <m )~ EC FED I K tm y ( m (, EC BIt A ( m , EC DLDx D , m `- EC HGZ G n 0 EC m K ( <n 0 EC DHe G , hn 1 AC BEEH E n 1? EG k C , n 2j EC DL A , n D3 AF BEEEH J $ o 4i EC BGN E $ @o 4i EC BGN E $ ho 45i EC BGN E $ o |5i EC BGN E $ o 5i EC BGN E $ o 6f EC BGK E , p T6 AF DEEH J 8p y $ Xp 7 EC E A , p 8] EC BEEW# B , p <: EC DLHG H ( p ;x EC DEDp K , q = EC DGGp F , <q `>u EC HG K , lq @ EC HGZ G , q `C EC HGZ G , q F EC HG$ E , q Hu EC HG K , ,r KK! ET DpH A \r l? EC q A |r @l? EC q A r `l> EC p A r l? EC q A r l; EC m A r lm EC T A s sm EC \ A Ds Xy EC l A hs m EC \ A s @q EC T A s EC T A s 5 EC c E s (E EC w A t XD EC v A 4t 3 EC e A Tt B EC r C tt ؓB EC r C , t EC DEJ! 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EJ I F d X EC k A T EC u A ğ EH D ̿ @ EO ] A ̢ E[ H A X EV l A 4 ȣ EC D A ( X t EC L7 E $ 8S EG BH F p EC H A EC I A , EC P K ( $ 8 AC K D , P EC P A , ҄ AC DHU A ( Ԅ EH FH D քM EO n F $ ׄ= OH BD F , $ ( AC DL G T لd EJ E G x dڄ@ EC i J ڄW EO $ ڄ EO Cw B , `ۄH EC DIIH A , ܄; EH KS G < ߄b EC R C $ ` ߄ EC IT K ( d" AC DED` G , h ES FQ J $ X AM BDt H ( AC eD C , 8 EL BNIH H $ h t EC U A Bry , AC BIG D , p AC Y G , AC Y H , < AC Y H , l Pf AC \2 F 0 EC BEIHH K , \ E] DHL G , A EC DEG G 0 6 EC c F P 6 EC c F , p ' AG FEK E 0 m EM BLLIH| G X!6 EC c F , x! AH M@ J ( $ 8% EC K J P ,)3 EC c C , p L) EH FTs A .W EC AH A $ 8/| AC V E , 0l AC i F $ 9_ EE l J P J $ D : EC BMi A l p: EC A , ;d EO BRIH E , L@ EC BIIJ A , D EC Y+ D ( G EO G@ E $ L pI EF G A t HJ9 EF h A hJu AC QZ A $ J0 EH C F ( K EC DDC E @Lr E] J A 0 L6 EC h A P L6 EC h A $ p Ln EC I D $N; EC m A $ DN EC Cx A N; EC m A N@ EC r A N5 EC e C $ @ O EC C A h O? EC v OR EC I O? EC v O EC tP? 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AF BIH~ H A , T Q EC DH C ( EC BJ F ( EC DF I ( P AC DEK C $ 4 EC G E ( 0 ̌ EC BJK I , \ PG EC DEJH A 4 p EC BEGD D U E ( H, EJ BEJ A ( L EC DEGI G , AG HN K ( L Т AC I A , x Q EC DGH F , Ħ AC hW A , t EK DLIH E , 久 EK DEIH K , 8 D EC DGH F , h EC DGH D , 3 EC DGH B , ' EC DNK C $ Dž EO n N ` J $ DžX EC q G P C H $ȅ` EJ K A l `ȅQ EJ | A ȅ= EC o A ȅ= EC o A ȅ> EC p A 4 Ʌi EC BILD H [ A $ 8ʅi EC Et G , H ʅ EC BEEHK I , x d˅, EC M H 0 d΅ EC M J k E 0 υ EC M M s E \х EC A E $ 4 х EN y T ` H , \ `҅ EC C] H W A ( ҅ EJ At L T A ( DӅ EJ At L T A ( Ӆ EJ At L V A LԅY EC I 0 |gyH EC c X ( P lԅ EH DDu F | օK EC y E ( 0օ EG BH H , ׅN EC I E ( 4܅I EC DF E $ X݅W EF @ G H ݅ EF A , l ޅ EC FJ A , ޅ: EC M H EC x H $ | EC BDF D ( D EC M A ( D EC DF B p q EC J F EC A| K ( EC e E E EC w A (g EC Y A ( ( t EC I K ( T EC e H EG n A 8H EJ h L hC EC c S $ EF Gp F ` EC w A , , ` EC DEEH1 A , \ EC M A 5 EC g A EF s B X EC ~ M , K EC BEF0 A ( @& EM T Z P X ( H D@ EC DD J $ t X EC Q O g H ( EM s [ P Q ( 0 EC DD D $ EC Gx I @Y EC H D $ @ |v EC I G T E h G EH t A $ EC Gx I , j EC M A , EF DEJH A ( z EC BJ\ E ( < EC Ey J [ E h T EG s A j EC \ A , @ EC BIH9 D EC l D | EJ ^ C ( $ EF BFr A P < AC D t s EG Az I ( T EF BF A , V AF M! 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EC FH F $ H EC BHb D $ H EC BHb D $ DI; EC G A 4 0 \J EH BK A G O h MZ EC m K ( DML EC BLK A ( hNL EC BLK A O_ EC v B OH EI j K $ Oh EH GZ A $ H DQj EC BMM A , p QE EC e A , R EC BD K p A S] EC EJ A $ HS EC G A ( Tb EC Es H T A H UM EO n F h 4U EC Ab E U EC A , V EC FJD D , W AC DIEN K |Z= EC c M 0 Z7 EC c G P Z< EC c L , p Z\ AC M F 4 \ AC DEF G C ^` EJ I C _J EC A{ A $ <_p EC H H P C $ H _p EC I G P C $ p _ EC ] K P C $ 4`p EC I G P C , |` EC I F [ A $ ah EF | I P C $ Tax EC O I P C $ @ ax EF Q D P C $ h bP EC j F P C , ,bR EJ FF1 A , \co EC J C l D , d EG BGF0 E 4 |i EC FED D L , X Dk EC DEED H n AC Hl H ( o EC BED M ( o EC A H ^ Q ( p EC BIDg B ( 0 q EC BED D \ q EC A D ( r EC BIDc F s_ EC } K , @s EC HPr E v\ EC AM A $ vR EC Gp A ( H $x EC DED A ( t x" EC M| G , y' EC FED A ( z EH DUZ A {[ EC E{ H \{O EC Er A D {S EC A@ E ( h { EC I I , (~ EC BHs K z A $ ~ EC Lw E $ ~_ EC Gr G $ (b EC Gu D , < p EC FJ` A , l EC FJ F , EC Md G , 0 EC BEEG^ A $ ] EC BDI A 4 $ EF Q \ P X P ` P C \ pX EC J A i EC AS A i EC AS A ( D EC K E n EY H C , d] EJ HK5 A H T ER u C h ԇ8 EC c H 8 EC c H 8 EC c H 48 EC c H T8 EC c H t8 EC c H ( 8 EC c H H 8 EC c H h Ԉ8 EC c H 8 EC c H 8 EC c H 48 EC c H Tx EM ^ C ( EC FD B ( 8 EC BJg E ( d EG DHg A 8 EC c H <8 EC c H \[ EN @ C 8 EC c H 8 EC c H 4 ، E^ g C X TS EN x C x P EN u C č EF o F c EN H C Y EN ~ C , < EC BJHK^ K ( 0 ̐Z EJ BEF I \ 8 EC c H , | EC BGED| J 4 EC DIEDf L ` A , ! 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EJ HD J , U !C AC DH A , V ( EC HH G , 0V ) EC HD A `V l*S EI A $ V *m EC BDY A V *Z EC L A , V 0+ EC BTJ H V .3 EC c C W .3 EC e A <W .4 EC f A ( \W / AC h I W 1P EC ~ E W 1P EC ~ E W 1P EC ~ E W $2P EC ~ E $ X T2w EJ BDX E 0X 2P EC ~ E PX 2W EC E E ( tX 3 EK FI A X 3W EC E E X 3I EC c Y X 4P EC ~ E Y H4P EC ~ E $Y x4I EC c Y DY 4I EC c Y dY 4I EC c Y , Y 5 EK BPM A Y 5q EJ D Y 4 Y 6 EC BIH B E , Z 8 EC HH E , @Z 9 EC HH E , pZ 9 EJ FP A ( Z |: EH DE D ( Z `;@ EC M K 4 Z t<; EC FJ E I E ( 0[ |= EC M A , \[ >I EK HM E $ [ @? EH Cd D [ ?? EE o A ( [ @r AC P E 0 \ \A EC HH J u E 0 4\ 8B EC I E q O h\ Dm EC E~ E \ `D EC ED G ( \ D AC BED C $ \ 0F| EC m K q F ] F3 EC c C , $] F AC FF5 K , T] hH AC hT H ] Jh EC z F , ] HKj AC e, K 4 ] O EC I I E ( ^ 0Q AC BGH B ( 8^ $R EJ M J ( d^ S AC BGH B ^ T| EC A` G , ^ hT EC I] B , ^ (V EC DL4 D $ _ W EC Cf G <_ @X EC Ac D , `_ X EC BQb C $ _ |[ EC Gx I , _ d\! EC BIH C ( _ d]% EC FH F $ ` h^ EC C B 0 <` _K EC BEH E w A ( p` `j EC K E , ` 0b EC I F ( ` g> AC G E $ ` ie EC CT A $ a Lie EC CT A $ Ha ie EC CT A $ pa ie EC CT A $ a $je EC CT A $ a lje EC CT A $ a jr EC BH F , b l EC M/ D 0 @b m EC DH F U K , tb (oX EC I D , b Xq AC DEJ= D $ b s EC Cm H , b @t- EC I A , ,c @v EC BN F \c x EC A K $ c \z EC C+ J , c } EC I D ( c V EC Ev E , d EC FJ H , 4d ؆4 EC M A ( dd 艉L EC G F , d EC M B , d AC I H , d ܙF EC I A 4 e EC BJ A B E , Xe ԜN EH Ia I e G EM o A e $I EO o A e TH EE x A , e EC BGEH D , f t AG FJD E , Hf EC HD C , xf 䮉 EC HHD D , f d+ EC I A , f di EC HD+ A , g Y EC HG C , 8g Դ EC I> A $ hg D EC GY H ( g EC G H ( g ` EC G H ( g EC G H , h ȸ{ EC Y D ( Dh EJ M G , ph * EC HH D , h EC FID E 4 h E EC BEEEH G A A i É3 EC c C ( (i É EH DKe G Ti hĉ6 EC c F ( ti ĉ EH FEy G ( i ʼnC E\ DOS I , i @Ɖ EC HD> F , i lj EC HH C , ,j Pˉ EC HD, H \j @Љ EH As G j Љ; EC c K j Љh EH U A j (щ= EC c M , j Hщ EC DGIL H k 8Ӊg OC O A ( 8k Ӊ EC BGF E , dk hՉ EC BGM3 G ( k ܉ EG K1 H ( k lމf EJ BK~ F , k ߉ EC FJ B $ l w EC BD G ( Dl EC e E , pl EJ I( H $ l < AC BH E ( l $ AC DH J , l ? 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EF M H , s T" EC DFJf F ( s " EC DH| A t h#m EJ U D $ 8t #- EC C E , `t $ EC G F W A , t l% EC BGEH D < t ) EC BIH E J < u \/: EC Ig H n J W A R N @u qx \u @18 EC j A |u `18 EC j A u 1 EF K u L2 EC m K , u 2 AC DEMe A v \4 EC F 4v (5 EC F ( Xv 5 EC P J $ v 7 EI Cw H v 9 EC E v : EC | D $ v H;l EC l D e J w ; EJ ER J @w <p EC ` C dw h<R EC o V $ w < EH E A ( w 0= EJ BH E w =a EC J F , w > EC HH G , ,x ?c AC DNHH G , \x @ AG DEFG E $ x D EC BDM E 4 x 8E AC BEH K H 4 x G AC BEEJ M A , $y hIE AC IC H L , Ty J AC Y H , y K EC FF D , y hNw AC \@ H , y R AC i E , z X_ AC BQ# F , Dz c AI FM I , tz k AF P2 G , z i EC BGJJ A , z 聊 EC FJq A ( { H AC Gq A $ 0{ K EC h E P A ( X{ Ԅb EC Es H T A { U EO Az A $ { TN EC h H P A , { | EC BGEH G | lZ EC EG A $| j EC W A ( H| F EC Wj G $ t| EC \ L ` G , | n EC FEH J ( | Њn EC M K $ | p EC IY A } \[ EC EH A 4 D} EC BGFH E V D , |} ` EC BEI A , } @ EC BFEJ I ( } EC BG G $ ~ 4Z EI i I P E , 0~ l EC DGD H , `~ \ EC DGD E $ ~ ̖~ EC BDT F ~ $G EJ p C ~ TJ EM p C ~ V EC l L ėV EC l L 8 V EC l L X DV EC l L , x m EC HD B , Ěo EC BEH E ( EC BFv A h< EC c L , $ EC BEEF~ A ( T EC Y F , ܝ EC DLFH A $ | EL H ] E ( Ԟ EC DEH G 4 AC DIEDt B I , < 0 EC MMk C l 3 EC c C $ 0 EC I A ( EC DJ A ( w EH DHX A T EC EA A 0 3 EC c C $ P < EC BD F , x Ĩ EC I4 K d EH Ea E $ ̂ ЬX EC p E P F , EC Y E $ $ h EH G C , L ) EC FED G , | EC FED H , гz EC BGJ K , ܃ k EC HD F , ` EC FF H h < EC MY B \ L d L d L \ L L L D L L p H , EC HD A , $D EC P& A 8 D EC M I T D x E , D EC BFIEHU E , t EC DEFDv A \ EC } K ( ą 8 EC M E ÊZ EC EG A XÊZ EC EG A $ 8 ÊX EC o I P C $ ` Ê EC GR G ( TĊ EC FH` J HŊ< EC c L Ԇ hŊ> EC c N ( Ŋ EC DIHp C , \Ɗ EC DPy K P Ɗ< EC j E ( p Ɗ EC DDa G `Ȋe EC AV A , Ȋ6 EC \m G ( ϊ EC BJH A @Њb EC q G < |x T xЊQ EC { E t Њg EC Y A ъ EC Eb A pъF EE t C ܈ ъ= EC o A ъJ EC Aw E ( ъ EC EP C g E L `ҊC EC u A l ҊQ EC AB A $ Ҋ` EC EM F 0 Ԋ EC BHT J | A 4 `Պ EC FEDc F ~ A ( $ ֊ EC FDg G $ P ,؊ EH Gl A x ؊c EI M C $ ؊ EF E F , Ċ ي EC IK D 0 h܊3 EC K J b F , ( t݊a EC BN J X ފE EC Av A ( | ފ EC BF F ߊ EF E H ̋ S EC C C <Q EC x H |g EC x H 0 EC } K P <u EF F , p q AC HDk E $ EC Gh I Ȍ t AI ET E , @A AF BJv G 4 `| AC FF I A $ T EC BMs A | Y EC H D 0 L! EC KU H E $ ԍ H_ EC BDK A $ X EC BD@ E $ 9 EC k A , D EC DEEH I ( t EC I E , ,I EC FEG D , Ў LV EC BM A $ |_ EC BDK A , ( k EC DH H ( X EC BIG E 0 EC BEH] L [ A T EF As A , [ EC HH D $ v EC BDb A 4 X EC A I , X $ EC FID H c EC Ay N Q EC AB A А 5 EC c E <8 EC j A ( \ EF AZ Z \ D $ < EC I a L d xt EC B F I EC u C ? EJ h C ȑ $? EJ h C D? EJ h C d? EJ h C ( ? EJ h C , H @ EC DGD? J x ^ EC z F ^ EC z F 4^ EC z F ؒ t^ EC z F ^ EC z F ^ EC z F 8 4^ EC z F X tE EC w A x d EC V A : EC l A k EC ] A \h EC Z A 7 EC i A $ h EC A{ L H E EC l L h DF EC m L $ t EC I G k K $ EF D _ H ؔ @ EC k H , V AC FFD A ( 5 EC c E 0 H AC DJ E H 0 | P AC My F J m EC _ A ( ԕ EF 5 H A G EC A $ $ xu EC } K X H $ L EC e C X H $ t H EC b F X H ( EC Gy H | E , Ȗ 4 EE C G y E , EC GZ G | E ( ( AC DP I T 8? EJ h C t X? EJ h C , x AJ HHr C $ ė AC Ug A pE EC w A $ EC BKV E $ 4 e EC v B X H $ \ Pu EC G A X H $ u EC G A X H ( EC Gt E | E , ؘ d AC BGID D Пx , ( $ AC HD E , X $3 EJ M H H $( AC BEEED G Q G E C , ԙ x/! AC DNG H x0R EC } H ( $ 0 AC M C , P 3 AC DL G 4 5q EC FED G F 6S EC A@ E ( ܚ 7i EC Az E W E 0 d7 EC BEEEIJ D $ < :N EC h H P A d ; EC F , @ EC M F D< EC c L ؛ D] EC AF A , E EC FEDy H , , E EC DEED F , \ PG' EC ff D PIQ EC C A IC EC c S М IS EJ Ey A , I EC FM D $ Wy EC k A , H X EC BEEMr A x X< EC c L X< EC c L ( X EC BEK~ A HY< EC c L hYY EC E C ( ( YL EI I A , T Z EC Iw H Y A , H[ EC Mz A $ _ EC E G ( ܞ _ EC BJe G D D`J EC Mu F H N ] K D P Lhl EC PA G M E E , tq EC M J ȟ r= EC k E ( s] EH K2 A HtI EC Av E 8 ttG EC y A , X t EC BNv B ( $u EC M A ( u EC M} A , v AJ BEJ C , |w AC P E @ | EG Ay J ( d h} EC M H 7 EC c G ,= EC c M С LI EG m G |{ EC m A , c EC MH A $ D EC C A ( l S AC M C 䅋J EC | A $ EC Ie J 5 EC c E ( r EC d5 G $ , EC Gs F T Y EC H D ( x Ĉ EC EP C k E $ h EC I A ̣ 5 EC g A 5 EC g A 02 EC d A , P2 EC d A L p1 EC c A l 5 EC g A ( 7 EC WN C ċ EC E| G ܤ EC A E $ l EC BH F ( TT EJ A , H ; AC BKEH H , x EC BEEMl C , $" EC BGID J ( إ $ EC DHQ K 5 EC g A $ ؑ^ EC AO A H 8 EC j A , h 4# EC HH E , 4Y EC FJH F $ Ȧ d EC C K Y EC H D $ Hv EC I G T E ( < i EC BGR A , h 䖋 EC BEGE A tH EG v A EG U G , ܧ EC BIEED D , ] EY HE I $ < y EC BHX F $ d h EC It K ( EC DEH H , tx EE BDy G ^ E 4 ěB EC DGD F a G , ܝ EC DIED] A $ P < EC n J s E , x T EC BGED D ( ԟ EC M A ԩ ; EC j D , AH P9 A , $ 8l AG W A ( T x# EW DF A $ |l EH BJM A Ħ: EC c J Ȫ 䦋5 EC c E 0 EC Gy H E K W E , 7 EG M G 4 L EC v R P H P P P G , ( EQ DIK A , ; EC M A ( EC DJ A ` EC R A ( 4 EC Kz A ` l< AR $ | AC CD E ( 8{ EC BF E , Ь C EC DEJH G , EC FF H 0 x , P # EC I A ( |ԋ EC ER I d A ԋ EC g A $ Э lՋ EC I F $ EC G E ( c EC K' F , L ؋- EL DEIG F $ | ًR EC BDz E ڋ2 EC d A Į (ڋQ EC z F hڋQ EC z F ڋ3 EC e A $ ڋ3 EC e A D ڋ2 EC d A d ۋ6 EC h A (ۋ4 EC f A HۋT EC z A į ۋT EC z A ۋ5 EC g A ۋ5 EC g A $ ܋2 EC d A D (܋4 EC f A d H܋6 EC h A h܋8 EC j A ܋6 EC h A İ ܋8 EC j A ܋| EC ED G $ $ EC GZ G $ 0 EC C J X Dދ5 EC c E x dދ5 EC c E ދ5 EC c E ދ6 EC c F $ ر ދ AC BHi E D ,ߋ AF IH H ` H ] K h H H , H S& EC \ D x E EC s E , 4 y EC BD C b B , Ȳ G AC e A $ AC U A $ < AC U A $ H AC U F , p AC HD J $ \ AC Uw H ( ȳ z AC ZF D $ h AC U G , P EC FEH A ( L l AC Ww F ( x o AC MH G ( 8 AC ez E , д AC DGED] K ( "# EC MT G , , # AC Y E , \ & EC DH^ F (< EC n A , (v EC DEEJ. A , ܵ @+ EC BGJH| A $ + EC BOL K 4 H,7 EC c G ( T h, EH BHEc A ,H EC c X $ ,-^ EC j V P A ȶ d-1 EC c A $ - EC BM A , <. EC I O Y A @ .C EC s C ( ` / EC BKf E , 0 EC BEGLQ E ( 1 EC DKk F ( t1 EC Mz A ( 1 EC M A , @ l2 EK HU F ( p 7 EC DIf A $ 7} EJ BGL D ĸ 75 EC g A 7R EC n J $ 88 EC GH I $ , 8 EC CQ D , T 9 EG P C >O EC A A ( 4> EC DD~ A $ Թ > EC CH E ( 0? EC Y H $ ( @ EC BK A ( P @ EC Y H ( | A EC \ E , DDR EI FED D $ غ tF EC I A F9 EC k A , G EC BDI I Y A P lG EC Q\ A 4 t G EC DEED H v E $ H EC U^ A $ Ի Hh EH q R P C $ @I EH BK A , $ J EC DJEH F , T L EC DFJ E ( Na EC P K ( OX EC DJ K ( ܼ Q AC BIH| E , Qs EC GF K J 0 8 4S AC FJ@ D ) l U EC O I $ VI EC G I , 4W EC FEH D ( W EC K A ( X EC M H $ @ Z' EC BL A 0 h $[ EC FH~ D K ( \J EC DHa K Ⱦ $] EC B F , ] EC FJ C ^ EC A , @ _ EF I B 4 p b) EC FEHC J A c EC A ̿ 0dK EQ o A 0 `dF EJ G{ O B f E |eY EC Em F D en EC ` A h f< AR $ (f AC CD E ( f{ EC BF E , $hC EC DEJH G , Di EC FF H 8 wx , X j EC BN\ A ( w EC ER I d A x EC g A $ x EC I F $ y EC G E ( ( zc EC K' F , T {- EL DEIG F $ |R EC BDz E }2 EC d A @}Q EC z F }Q EC z F }3 EC e A , }3 EC e A L ~2 EC d A l ~6 EC h A @~4 EC f A `~T EC z A ~T EC z A ~5 EC g A 5 EC g A , 2 EC d A L @4 EC f A l `6 EC h A 8 EC j A | EC ED G $ EC GZ G $ t EC C F 5 EC c E @ ,5 EC c E ` L5 EC c E l6 EC c F 0 z EU BPIED D 4 ؇ EC BEELD K X 4 0 EI BGED H I G 4 D 莌 EI BEGD L I G 4 | EI BEGD H I G ( xc EI Q X H 0 EC I N a G 4 h EC I F K 4 L $ EF M E G , { EC PQ G 4 o EC M N K , @ EC I9 F 0 ~ EC FHC G A 4 P EC I J G 0 Ի EC BL M E 0 Ps EC I J i G ( EC d X A , EC G| E W A , L Č EC GN K W A | pnj EC E H <Ɍj EC \ A , Ɍ EK HK A , ͌ AC Y E ( $ Ќ AC e K , P ,Ҍ AC FEKa E $ Ԍ EC G D ՌX EC J A , Ռ EC OK' G ( x EC DD@ H $ ( EJ II G P <3 EC c C p \1 EC c A |S ET o F S ET o F S ET o F <S ET o F |3 EC c C 0 j EF Y A ( T EC Ed O G A ( EC Ed O G A ( 0 AC Y D $ l EC BHF H 0 \ EC BEH E ^ A 4 L EC Ay E 0 X $ EC BEH E ` A , EC BH E ^ A ( P EC DHY C ( EC DHY C ( X EC DHY C @ X EC AI A d 8 EC f E ( 8 EG DID A ( EG DFD A , @ EC DFQ A , EC FFO A < < EC c L \ 5 EC c E ( | EC AU A y E ( AC M A ( q AC c F ( b EC f I , @E EC u C L po EC L D p E EC w A E EC w A = EC m C <M EC A l= EC o A = EC m C 0 L EC ~ A P = EC o A p | EC Q G X| EC U C V EE F A V EE F A ,i EH V A $ xq EH ^ A H r EH _ A l 0o EH \ A |= EC o A = EC o A = EC o A i EH V A (V EE F A 8 dV EE F A \ = EC o A | l EC L D l EC L D X= EC o A x~ EC ^ J v EC \ D , 0 EC X H P F EL n B p S EL q F S EL q F L^ EE n H ^ EE n H $ ! AC BL G , EC BEED A H DN EL s E h tX EI @ E X EI @ E N EL s E c EL | Q lQ EL v E U EL z E 0 R EL w E P , EL H W t N EL s E S EL x E N EL s E HS EL x E N EL s E S EL x E , 4 EC DEER A d EI K W EI K W $ EI ~ L P X $ EI t ^ ` H P n EI | V R EL w E ( < n EC BEDQ E $ h $ g EC BHO A l | EF J K y EF J K $ g EC Et G ( p EC DDi G ( g EC Et G ( L ` EC DDi G $ x EC BDM E 0 EC DED E E ( 8 EQ DQIW A $ AC I D $ ( T EC BDM E P 5 EC c E $ p EJ BDH K ( t EC DIIc G ( AG DH H ( v EC KE H ( ~ EC DID_ A ( H T~ EC DID_ A ( t ~ EC DID_ A ( ~ EC DID_ A ( P~ EC DID_ A ( v EC BED] A ( $ r EC BEDY A $ P L EC BDQ I ( x EC BEDR K (U EC k E ( h EC BGHY F ( < EC M{ H 0 5 EC DL G P L EC ~ A 4 p L EI F T P X P X P Q , EI } ] P X P X $ EC G_ B ( EC DED A , k EC Em F $ P L j EC n J ` E x v EC h A v EC h A L f EC X A $ EL L K d N !b EC T A 0 \!b EC T A T !Y EC K A x !5 EC c E "5 EC c E ( $" EC BS K ` P " EI W [ 4 T# EC FED E z F 4 @ $ EC FED; F z N $ x 'g EC BHO A $ 'g EC BHO A $ $( EC BDM E ( EC Em F $ ) EC BDh J < ) EC X H ` )~ EP G T $ H* EC BDM E + EP P [ ( l+ EC FDq E $ `,7 AC BI A $ x- EI W [ ( H . EC G\ E ( t . EC G\ E $ / EC Gn C ( 40 EC DDi G ( 0 EC DDi G ( |1 EC DHT H $ L 2m AC Iu F t X3 EC z F 3' EC E ( 5 EC Kx E ( 5X EC FDJ D 7 EC D 8 8 EC D $ \ p9< EC G E $ :< EC G E 4 ; EC FED E z F H= EC H $> EC H $ , ? EC G G $ T ? EC G G $ | @H EC C@ E 0 Ci AC FLa I E ( TD EC Y J , 8G_ EC HDi C , 4 hIO EC ME F d Rx , hKO EC ME F NRx , hM EC M G Rx 4 $ P EC FED; F z N $ \ pS EC BD G 8TJ EC x E hT6 EC c F T3 EC c C T4 EC c D ( T EC Gq H v E 0 ,U= EC o A P LUO EJ z A p |UO EJ z A UO EJ z A UO EJ z A VO EJ z A <VO EJ z A lVO EJ z A , 0 V EC FJ C ` LWB EJ m A |W= EC o A W EC g A X EI Ew F , XT EC e D h| EJ g A ( < @i EC FL D , h m EC DIEDt F Ts EJ A t< EC n A , u EC M E `} EN L , 0 S EC BKEI* A ` <3 EC c C \5 EC c E |< EC c L W EC AH A L EC A} A , AC DEJo J 8 dT EC A~ A $ \ EC IB E $ hp EC CX A | EC Af A , EC BDP J Y A ( l AC M A ( , AC DD A X EC A` G | `3 EC c C , [ AC HD J ( ' AC K I 3 EC c C Ԕ3 EC c C $ 8 EC L L ` C ` \ EM A A , AG FF% G $ h AC BD D , 0 AC DL A , AC DEF| A ( < EK I D $ h ğ EC C A , M EH DH A r EK AT A EC A| A , u AG M K , 8 䧍 AI HH F ( h D AE K H , 讍 AG HO A ; EE k A ; EE k A ȱK EE { A $ _ EM G A $ H 4 EC q G B N ( p o EC BS A $ @{ EC GX I @ EC r A b ER E| E } EK g A 0 , ` EC BEEEDX K ( ` ̶ EC K A ( p EC K A $ EC C K ( ̹ AC DD E ( 4 AC K A , 8 EC FJ C ( h tF EC M G , EC M G , EF CM E F E ( s EC DHY A ( EC ME A L ̍@ EG n A l ̍T EC F A ̍ EI C O X͍ EC E K ͍A EC o E ͍B EC p E $h EC z F 8 t EC A{ A \ EC AF A Lύ@ EC E B , hЍ EC BH| J o I , Hэ EC BHy E o A , (ҍ# EC BH O o A , 4 (Ӎ EC BH O o A d ԍ< EE l A 8ԍ8 EC j A XԍD EC v A ԍ7 EC i A 4 ԍ EF BN/ F m E 4 @֍ EC ML A k E T ؍ EC m K 4 x Tٍ3 EC HDX D I , \ۍ EC M D ݍE EC w A , Lݍ EC BMD J 0 EC AF A T 8 EC A| K $ x EC BD A L| EV Ep H N EL w A ( AC \ D AC Q A $ 4 h EC C} A \ 8 EC j A | 8 EC j A x EJ Ab A lx EC Ew D R EC D A ( EC P A , 4 EO DNJ; A d h< EC c L 8 EC j A , EC BEL J xH EC z A O EJ z A EC A| K , 8 D EC DEJD H $ h 4 EC BHf H i EI AC F , 8 EC E F J N $ EC U A , # EC DEHH F $ < z AC S] A $ d 8 AC G I $ 2 AC S J s EC w A h AC Q H $ EH D 4 * EC DJ E Y E $ P e EC CT A x EF An A 0H EJ s A `v EC Ag A , EC DEJ A H EJ s A ( 0 EC DSK A \ pH EJ s A , | EC DUK A , ` EC DKG A P EC A^ I G EG r D J EC k E @ ,L EC s E ` \L EC s E c EC s E , EC e I 0 <3 EC BHEHD A $ Hs EH C] A , , EC BELP E \ S EC m K | @ x EC i G j EC h H ? EG j D ( EC BJ A ( EC DDV J ( 4 ( EC EB I T D ` AC TQ G , H AC YU F , EC G G W A $ EC Iu A ( * EC M F ( 8 EC M H d o EC m K , EC h F ( Hk EC BJM E , EC M A ( u EC BEDX E $ < P AC a H ( d AC Y E $ EC Io H ( T EC c C ( EC TC A ( EC BEM\ H ( 4 ( EC BEJ B ( ` ! EC EP C p E !Y EC H D ! EC y A , (" EC I A , $ EC P F , 4 8+ EC BEL A d (,^ EC P A ( d, EC BIDu A ( , EC DIG E ( -n EC YY F / EC < D ( 0 L2 EC P G \ 3 EN ] H , 3 AC DHED D , |4 EC DEJ A $ l5s EC BDL F 57 EC c G ( 5: EC c J H 6D EC v A $ h 46 EC Ix A , 6 EC IC L a A <7a EC EN A 7D EH o C 7T EH A@ A ( 78 EC c H H 85 EC c E h 485 EC c E $ T8P EC h H P C $ |8P EC h H P C ( 8 EC BO A $ h9N EC h H P A , 95 EC c E L 9y EC Ex K , p : EC GS N G A , : EC FID I $ l> EJ BKO E ( > EC BEMj J ( $ h?r EC E@ K T A P ?J EC Aw E t ?N EC Ew E ( @ EC FH G $ @q EC C` A A3 EC e A @A8 EC j A , `A EC C P A6 EC h A p B EG u O ~ BW EG k I , B EC DEEHg A , HC EC DEJ A ( E EC BJ A $ @ lF EC BH A $ h F EC BH` F $ LGw EC BHN H , GL EC M1 A .,x H EC A , , I EC DEMm E , \ N EC M G , 0Q EC P A ( TG EC FH A ( 4U EJ DIm A Ug EU E C $ 8 U EK L A 0 ` V EC BEED F s M , X EC BKD B , X- AC DH A $ Zx AC A@ K , _ AC BNQ K , L a1 EC BD H r F 4 | b EC DEEI H } A , c EC BN I p B , d1 EC BD H r F , e1 EC BD H r F , D f1 EC BD H r F , t g1 EC BD H r F , h1 EC BD H r F , i1 EC BD H r F , j1 EC BD H r F , 4 l1 EC BD H r F d mq EG _ A ( tm EC BEHx A , m EC BEEME J 4 s EC BEEED E ] K puj EF ~ G < u5 EC g A \ u1 EC c A , | v EJ DDc F a E 0 v= EC G F s M 4 w AC BDE A I l E ( dx EC EZ Y a L ( D xw EC BGD` K , p Lz" AG DED K L| AF HDL A j F V J K t L l L C E } K ] K P H e K { M e K Z E v E $ < p EH BKu A 4 d 胎3 AI u A R f f R | d ( EC BK A ( " EC DF G ( EC M O ( L EC P] K ( L EC P` H ( x D EC P] K @ 荎 AC BEED J i G r F s M $ EC G A 4 L AC BJ H " F , H o AC FEK G ( x D EC Kh A 0 3 EJ BEEED B , EO Mn A , D EO Mj E , 8 Է EO Mj E , h d EO Mj E $ EH Q A EV e H , ( EO Mj E , EO Mj E , D H EC BID H $ t EC C C , Î@ EC BEEH D $ 0Ď EC G_ B 0 Ď AC BEEED< K , ( tƎ AC HD K , X $ AG FF? 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EC v ڗ0 EC g ڗ EC ܗ` 4ޗ 0ޗ 0 <ޗ D ޗ X ޗ l ޗ EP ޗS ߗ ߗh AE J W \ߗ| E[0S CA ߗ E[P CA 0 D FLM D@y AABH D L BHE D(D0U8H@NHNPN0m(A BBB4 8\ BAD G CABB `w EU0T CA EU@c CA ( EUPd CA 8 w EU0T CA \ EUPd CA \ EUPp CA EUPd CA Dm EU0J CA 4 Y BAD A ABE EAB ` $ FBB E(D0C8DPC 8A0A(B BBBI G8A0A(B BBB H $ BEE H(D0D8DPw 8J0A(B BBBF H BBB J(A0A8D@ 8D0A(B BBBI ,c H } K < # P . d ET CA 4 D FLG Gm AABG , AFG AAE ( l ERD AAA EdPa CA @ @ l BDA m ABI T ABQ OAD L BBD A(D0K (D ABBG t (D ABBA d BEB B(A0A8D`H 8F0A(B BBBH 8A0A(B BBBA < P" HY T h ER CA ( x 4# BAA AB 8 DK 8 @K FJD HBL | ABA , T BAA ABA ( $ 8 < FBA D(I (A ABBA ` x BBB B(A0A8G L@I@f@I@x@A@ 8C0A(B BBBD 0 p BKD G DABC L Lo BBB B(A0A8G* 8C0A(B BBBI 8 ` l EPUGOCb AAH 0 FOR G CABH ( 0 EOX CAK < ^ BBA A(GH (D ABBB H < BBA A(D0_ (D ABBF D (C DBBI \ d BNA A(D0T (C ABBF u (F ABBH K (E ABBK 0 w AMH X DAE |AA 4 f ADG AAD JFL d T XA BBB B(A0A8Da 8A0A(B BBBG D 8C0A(B BBBH @ Dj B H 4 BBB B(A0D8Q`| 8C0A(B BBBJ D $ BBB A(A0G I 0C(A BBBI D l k BBB A(A0G L# 0C(A BBBE < FBB A(A0E (A BBBH X < ADm AE 8 t BBA D(G (D ABBI 8 T BBA A(G~ (D ABBD DV F X p BFB B(A0D8Gp,xQexAps 8A0A(B BBBH @ BAA G I s H g t AABB L Ft F @ H p L BEB E(A0A8Dp 8C0A(B BBBK ( h BHA d AFJ H DT BBB B(A0D8G 8D0A(B BBBG \ 4 X BEB E(D0C8GpxLTCOp. 8C0A(B BBBI 0 ] BIC G CABC L BBA D(D0= (C ABBF { (F ABBA H t BBA A(D0z (D ABBC D (D DBBH H d p BBD D(F0} (D ABBH D(F ABB @ KBA D(L0N (A ABBF X < xM BFD A(Jj (D ABBF 4 4 [ EFD ` AAG T AAB 4 l [ EFD ` AAG T AAB a J@ F P ( ! g FDD UAB 8 D! X BDF @ ABA a ABD < ! BBE D(D0 (A BBBF ! L ! FEB B(A0A8G 8A0A(B BBBB $" ( 8" (3 ^T D P" <( FGB D(D0DQ 0C(A BBBJ " ) " )- SQ " *P E` K _ ( " 8* bHA d AFJ 8 # * BBA A(D0 (D ABBH x L# , MBE E(H0D8G@8HePHHA@P 8A0A(B BBBD k 8F0A(B BBBF # D. BBB B(A0A8J! 8A0A(B BBBA F`ArFsD UH gRY H T$ 7 BBB B(A0A8G 8C0A(B BBBF H $ l: BEB B(D0D8IPt 8A0A(B BBBF l $ : BBB B(D0D8IhG\A~ 8A0A(B BBBC PUA H \% =d FBB B(D0D8GPY 8C0A(B BBBH % $?Q EK % h?! JO p % |? FEB B(A0D8GpxTDBSpa 8C0A(B BBBA D8F0A(B BBBl T& @ BBB E(A0D8O M T A ^ 8A0A(B BBBK Y F X A & HD & DD H & PD9 FBB B(K0A8G 8C0A(B BBBA @ 8' DE6 FBB A(D0GO 0C(A BBBA L |' @F FDA ] ABE N ABG Z ABK ] ABA 0 ' FI EDG l CAA AAA ( F ( F X (( F OBA A(G0 (D ABBE T (A ABBF P ( xI& TQ ( I ( I ( I ( I, WT < ( I NAG n AAJ [FAAF 0) <J ka( H) Jd FFD PAB ` t) K? FBB B(A0A8G I Y B ` A @ 8D0A(B BBBI p ) K FBB B(A0A8G I m B ` A 8C0A(B BBBJ D B d A L* M a d* 8N x* 4N * 0N * ,N * (N1 \T * PN * LN * HN + DN L + @N WMD D(G0@ (A ABBG `F0 l+ N= HP A + N + NP {T + N + N3 ^T + O + O3 ^T , @O , <O0 [T 8, TO L, POF d `, O| FEE E(A0A8G@Y 8A0A(B BBBG s 8A0A(B BBBK , , Qw FAA ABI ( , R FAA h ABA $- hS# 8- S# L- S# `- S# t- Sr X - DT% FBB E(A0C8G\KZH 8D0A(B BBBH ( - V EAD t AAA . VE pT 4 (. Vl EAD t DAE W DAD @ `. V BAA G I s I ^ M AABA d . W BBB B(A0D8G 8D0A(B BBBA 8A0N(B BBBM 0 / _` FAA G CABB P @/ aG FAA F ABG N ABG Z ABC { ABA / b / b> ]T / c / c> ]T / @c 0 <cB ]T 0 tc ,0 pc> ]T D0 c X0 c> ]T p0 c H 0 c! FBB B(A0A8DP 8D0A(B BBBI 0 f 0 f 0 fz H} K 1 f (1 g <1 g P1 f> ]T ( h1 $g ED j FG w CA 1 g HR F T D ( 1 h AAD P CAF ` 1 xi FBB B(A0A8G I G Z A b 8C0A(B BBBH 4 H2 jM FDD P ABG aAB ` 2 j FBB B(A0A8G I G ^ A 8D0A(B BBBA 4 2 HlZ FDD P ABG nAB 3 plM L 03 l FEF A(D0p (D ABBA f (D ABBA l 3 ,m BBB B(A0A8GAPBNSOAA 8A0A(B BBBI 3 Lr!4 BBB B(A0A8JJ 8A0A(B BBBH +EZB5DCHSNCFS=PqDUGA A_AC]B 4 w 4 U Eb I Q G D 5 ĥ FBA A(DdGy_ (D ABBF P5 LU Eb I Q G \ t5 BBB B(A0A8DPo 8F0A(B BBBD D8C0A(B BBB 5 ئW H_ I T A 5 9 ET G O A 6 4h H g A 46 < H6 EAD I CAI O CAE NCA 6 ԧ 6 Ч 8 6 ̧ FBA D(D0I (D ABBE 6 P" HY \ 7 h" FBA A(D0e (C ABBE X (C ABBH O (C ABBA 4 d7 8~ EDD a CAF q AAA L 7 l FBB B(D0C8Js 8A0A(B BBBF 7 8 | FFB B(D0A8JiDLADK^B 8D0A(B BBBJ SG\AGOBJG\A0 8 x FLD G` AABJ 8 [ H@M A L 8 X FFD D(JIaA (A ABBH 0 D9 FOD D@ AABG 4 x9 T EID T AAA N AAG L 9 츘Z FFB B(A0D8G 8D0A(B BBBD 0 : R FOD Dp AABJ P 4: ( FBB B(A0A8G L#g 8D0A(B BBBK 8 : Ř^ FMD D(G (D ABBH : Ƙ( FBB B(A0A8G L@LF 8D0A(B BBBA FAGhFAFFCGLFAFcFKGxFBFFXGMFAFFFGOFBFFDG{FBFWFXGMFAF 8 ; ,ј{ FMA D(G (C ABBB ; pӘh HPZ A X ; ӘZ FEE B(D0D8JJPAp 8D0A(B BBBG 8 D< 8 FLA D(DP\ (C ABBA L < ֘ FFE E(D0A8G> 8D0A(B BBBC \ < L٘O FBA D(G0u (A ABBA (A ABBG R (A ABBH 0= <ژ @ D= 8ژD FBB A(D0G 0D(A BBBF H = Dۘ FHI B(D0D8D@R 8C0A(B BBBE = ۘ = ۘ = ۘ > ۘ $> ۘ 8> ۘ L> ܘ K+ J l> ݘ K+ J @ > ߘ FAG G AABG Z FABM < > ,t FFA D(Gk (D ABBD 4 ? l[ EFD ` AAG T AAB < H? FFA D(J (D ABBH ? ED V DE 0 ? / FAA D0 AABK ( ? | EAD0n AAF < @ OAA f ABF QABD L@ p H `@ l FDB D(A0| (D BBBI F(A EBH @ @ J H] A @ V Hi A @ TV Hb E T A 4 A } FAA A ABD iAB 8 PA ; FBA A(D@q (D ABBH H A FEB I(D0D8D` 8C0A(B BBBG H A FBE J(D0A8G| 8C0A(B BBBE ( $B h AHD@s CAD ( PB { AAD L CAJ P |B 0 BFE D(D0LWL` 0D(A BBBF \ B BBB B(A0A8G]OA 8C0A(B BBBC 0C LZ1 BBB B(A0A8G 8C0A(B BBBH HLfA|UB_UBC}AZ CB CNHKLMTB THB{\HAEVB ,D ) $ @D ) ^ MM U(J0U(A \ hD *y FEJ J(D0P (A BBBF N (A BBBK D(G EBB \ D *y FEJ J(D0P (A BBBF N (A BBBK D(G EBB X (E *x FGI D(D0Q (C ABBI O (C ABBI G(G ABB \ E *y FEJ J(D0P (A BBBF N (A BBBK D(G EBB X E +x FGI D(D0Q (C ABBI O (C ABBI G(G ABB H @F <+p BBB B(D0A8Gj 8D0A(B BBBE 4 F `1 FKD G" DABK F 2 EH` DA F d4 H F p4M FEB B(A0D8DP 8A0A(B BBBH H HG t5A FBE B(A0A8D` 8A0A(B BBBA G x79 Jb H G 7~ FBE B(A0A8DP 8A0A(B BBBF 4 G 8 FBA A(D0(D ABB, 4H X9Q MDA tABG , dH 9 KAD cDB D H 9 BEB E(D0A8Fp8A0A(B BBB H : AL H : AQR CI $ I ; AQ CA H DI < FBB E(D0A8FPl 8C0A(B BBBF 8 I ,=< FGA A(G (A ABBH I 0>0 [T I H> H0o I L J > FEE E(D0C8J 8C0A(B BBBF H PJ B FEE E(D0D8J 8A0A(B BBBH J `J Kr A J J Ks A J HK Kr A J K Ks A K 0L Kr A (K L| Kk A DK M Kv A `K |M~ Km A |K Mi KX A K 4N% HIH K K DN+ HDB \ K TN+ HDB \ K dN& HGK K L tN? K A 4L Ow Kf A 8 PL O FLA A(G^ (C ABBG 8 L P FBA A(G (C ABBH L dR K A L HTm H`_ A M T K H M PV 0M \V DM XVi KX A `M V K3 B 8 M |X FLA A(GT (C ABBI $ M @Y EG AG ( M [ EHJ AAA $ N l\ EGx AK 8N _ LN _ `N _ tN _ 8 N _ FBA A(G (C ABBG 8 N Xa FLA A(G\ (C ABBA 8 O b FBA A(G (C ABBG 8 <O c FLA A(G\ (C ABBA 8 xO dd FBA A(G (C ABBG 8 O e FLA A(G\ (C ABBA 8 O f FBA A(G (C ABBG 8 ,P 0h FLA A(G\ (C ABBA hP h EXX CH P pi EXX CH P i EXX CH P hj EXX CH P j EXX CH 8 Q `k FGA A(G^ (C ABBD L XQ $l FBB B(D0C8J 8D0A(B BBBA H Q t FBB B(D0D8J 8C0A(B BBBF @ Q Hx FNG A(D0J 0C(A BBBA 8 8R y FLA A(GL (C ABBA tR y' K A H R z0 FBE J(G0H8F@[ 8A0A(B BBBG R { R { H` D S | S | 4S | HS | \S |i pS |i S 8}6 ( S d} N E _ I `C( S ~ AND DAG S _ T ` T z 4T xf HT Ԃ: H \T ] BBB B(A0D8Da 8D0A(B BBBA T ^H T ̅H BBB B(A0A8G@y 8C0A(B BBBJ ( U Іn ACF x AAD 8U H LU . BIB B(A0A8G@ 8D0A(B BBBB | U tt BBB B(D0A8DP 8A0A(B BBBF 8F0A(B BBBA 8D0A(B BBBF t V t FHB E(D0A8DP 8A0A(B BBBF N 8A0A(B BBBH D8C0A(B BBB, V { BOM G ABA V \> \Z A V V | W x) W V DQH 0W BBE E(H0H8GP% 8C0A(B BBBJ |W hv P W P/ ZT W h W dG EX C f ( W M H W A K A X x NW K YG 8X 0 EV E O XX 0 ET G O H xX b FFB B(A0A8D 8C0A(B BBBA X 8 X 4 X 0 0 Y , FDA G0N DABI 4 4Y s ECG y DAC O CAE \ lY BBB E(A0A8DP 8A0A(B BBBA D8F0A(B BBB Y ,v P Y / YP 4 Z EAG AAD EAF H @Z \ FIB B(A0D8D@ 8D0A(B BBBF Z v @ H Z FBB D(K0 (A BBBA C(A BBB Z (v 0 \ [ BBB B(A0A8D@ 8A0A(B BBBJ g8C0A(B BBB x[ v @ [ [ H [ , BBB J(I0A8G@ 8D0A(B BBBB \ p0 EV E O 8 ,\ BBA K(D@z (D ABBI h\ 0 EV E O \ 0 ET G O \ H \ w FBB B(D0H8D 8D0A(B BBBF 0 ] DU EDD l DAB ODA 0 <] pU EAD k DAF ODA ( p] o FDD y ABF ( ] ਙu FAA W ABF 8 ] 4 FDD I ABF N ABA 0 ^ FAA G0 CABF L 8^ $ BBB A(A0o (A BBBJ P (A BBBA L ^ BEE D(A0b (A BBBF P (A BBBI ` ^ BBB B(A0D8DP 8A0A(B BBBK t 8A0A(B BBBB L <_ FBB A(A0 (A BBBL Q (A BBBH L _ FBA A(D0 (A ABBK T (A ABBF _ L _ , FDA A(D0n (A ABBL T (A ABBF @` T` H h` ĭ. FBB B(A0C8DP 8D0A(B BBBH ` 8 ` FBA A(D0 (A ABBA a H 8 a T FBA A(D0N (A ABBA < Ta EAD a NAF C AAK OFA a 9 dT a @ a L a X a d9 dT 8 b FAA Y ABD P ABA 4 <b EAD U AAO T AAA < tb H FBB A(A0; (D BBBG L b FBB A(A0 (A BBBJ Q (A BBBH L c 8 FBA A(D0 (A ABBJ T (A ABBF < Tc ȶg FBB D(A0' (D BBBA L c FBB A(A0 (A BBBJ Q (A BBBH c Q Js K AG 8 d ĸ FBI H(D`9 (D ABBA L Dd BBE B(A0A8G 8D0A(B BBBJ 4 d v EDL b AAG a CAK 4 d пv EDL b AAG a CAK 8 e FDD i ABF C ABJ 8 @e | FDD z ABE C ABJ |e P e FBB B(A0A8G L$> 8D0A(B BBBD 0 e H FNP DZ DABG H f ÙU FBA D(D0w (G ABBL ~ (A ABBD < df ęN FBB D(D0o (D BBBE 8 f (ř FBD D(DP (C ABBH L f ƙ FBB B(A0A8D 8C0A(B BBBE H 0g <ș FBB B(D0D8G@T 8A0A(B BBBG ` |g ə FBB E(D0A8G@~ 8A0A(B BBBE n 8A0A(B BBBH L g ,ʙ- FBB B(D0A8G 8C0A(B BBBA 0h v< @ Ph ޙ EAD { AAI u CAG o FAA @ h ߙb FDG T ABH D(L0Y(D AAB h ߙ ESL CI 8 h p FEE H(OL (A ABBG 8i h ES0G CA \i EG` AA 0 i FIH J AABG ( i ? BDD oCB H i BBE J(I0A8G 8C0A(B BBBI ,j 0 AGb AE Pj V $ dj H AG AJ j EO CA j H j } FKB B(D0A8J 8D0A(B BBBE 0 k FHA F`a CABD Dk x E I , dk 4 Ec H i G h A x G \ k (W FFB B(A0A8GaPA 8C0A(B BBBF k (8 E` A $ l Lw EK CA 8l A Jj H Tl FBB B(A0A8D` 8D0A(B BBBA l < Hn J Q l b HA G Q 0 l ) BAA G AABG 4 m EPN@q AAJ AAA < Lm W BBA A(G L! (A ABBC m v ! m ED0W CE H m FIJ E(A0E8M` 8C0A(B BBBA 8 n ` FBA A(G (D ABBH , Tn EAG I } CAI n ( ( n Q FDI q ABA ( n 8w FDA hAB n 1 JU I AG o (o d <o FEB B(D0D8Gp 8A0A(B BBBA H 8F0A(B BBBA H o H FED D(D0t (A ABBG D(C ABB \ o FEE B(D0D8DP 8A0A(B BBBG D8C0A(B BBB Pp < . dp X HN 8 |p ` BBB A(A0X (A BBBI , p P IDF xABA , p i BDA W ABA ` q T BEB B(A0A8DP 8A0A(B BBBF L 8D0A(B BBBG |q G A , q LDG K AAD pL q 7 BBB B(A0D8DW 8A0A(B BBBF r c D{ A 0 4r X BGD D@ AABH , hr M AC HD G d r - BBB B(A0D8G`F 8A0A(B BBBD 8F0A(B BBBK $ s c ADG NCA8 (s BEB D(C0x (A BBBA 8 ds BGA D(G@ (D ABBG s BBB B(H0D8G` 8K0C(B BBBM 8J0H(D BBBH l 8F0H(B BBBF $ 8F0A(B BBBM H 8t $!{ BHB E(D0A8Gp 8A0A(B BBBF d t X" BEB B(A0E8G 8A0A(B BBBB \ 8M0A(B BBBN 8 t & RDC D ABH AAB 4 (u $'k BAD F ABH KAB | `u \' BBB B(A0A8DP 8A0A(B BBBC 8A0A(B BBBF [ 8L0C(B BBBN ` u + BBB B(A0A8D` 8A0A(B BBBD a 8M0A(B BBBI \ Dv -: BEE E(A0A8M{ 8C0A(B BBBI NFA P v >) OBD A(D0 (D ABBE D(A ABBA L v ? FED A(G0_ (D ABBA (D ABBC D Hw A FAC h ABK P ABE F ABG P w A< FDA F0h CABA J ACBH f CABD @ w B FIE D(D0Dp{ 0C(A BBBK H (x D BBD A(D0n (D ABBD R(A ABB $ tx (EO ADG yDA $ x PE] ADD JDA x EV AP L x E FEJ E(A0A8G 8D0A(B BBBE 0y \H 8 Dy hHM FBD D(F0 (D ABBG L y |I FBA A(D0J (D ABBG T (A AEBA l y I FDE A(A0` (D BBBE M (A IBBE F (A KBBJ M(A BBB @z ,J Tz (J. \Q lz @J z <J z 8J z DJ z @J 0 z <JH EAD ` CAB SCA { XJ 4 { dJ FAC D DABD P{ M) d{ (M% x{ DM Hi G Q G H { ME FBB B(A0A8Dp 8D0A(B BBBG { N6 { N# HZ L | O2 FJJ A(A0 (D BBBG j (D BBBD d| O9 Ja E AG | P | P 8 | P FBA D(J@v (A ABBE 8 | P FEA A(J@ (A ABBD (} Q5 ]W H @} ,Q' bBE B(A0D8G@ 8A0A(B BBBK H } R BBE A(A0 (D BBBA C(D BBBH } R BEB A(A0 (A BBBA A(C BBB $~ R EP @~ R# KT 4 X~ Ss BAD X DBD CAE P ~ LS LBE A(A0p (A BBBD C0 \ ~ T BBB I(A0D8Gk 8A0A(B BBBH FZD \ D Y4 BBB B(A0A8Gy 8A0A(B BBBD #KFA 4 [ BBA D(D0(D ABB< P\ BBE D(D0 (A BBBE ( \O BAD w ABG H \ De G Y G H h d] FFB D(O0 (D BBBA C(A EBB ] , Ȁ ] FAD [ ABG \ db* FGB B(D0A8G 8D0A(B BBBA KUB X 6v L x y FBB B(A0A8D 8C0A(B BBBA H ȁ 䓚# BBB B(A0A8D` 8A0A(B BBBF H Ȕ BEB E(A0A8DP 8D0A(B BBBA 4 ` y IAD zABEH 8 ԕ BOK D(D0} (G HBBL ( Ԃ (R BDL xAB ( \q BHN QAB 4 , BEM G(G0O(O ABB@ d 6 BMJ A(D0N 0A(A BBBE G A ă G A L[ AL $ @ AIK aDA 4 $ BDD \(K0k8J@a AAB4 \ BBD A(G0(K ABB$ M AFV aIA C H Є FBB G(I0C8G@H8I0A(B BBB 8 @ FBA A(G0r (A ABBA X 1 JY @ t ؝2 FFB D(K0O 0A(A BBBA l Ԟ FHB E(G0A8J&Z]Ai 8A0A(B BBBH uZPA 4 ( t EDI@gHcPKHA@` AAA \ ` ̡ FEE J(A0A8D@c 8A0A(B BBBA L8A0A(B BBB4 s FAA [ ABA HAB L d FEJ E(A0M8J 8A0A(B BBBD L H ĭ FFB G(D0J8O 8A0A(B BBBA @ d$ FKI D(A0O 0A(A BBBA 0 ܇ P FMA O AABA 찚 H $ ȱ BBB B(D0A8Gpm 8A0A(B BBBE $ p Aj E O A I @ d BDA } ABI O DBK OAD ( ܈ ADG C AAG % BOE E(D0D8GPgXL`PXBPZ 8A0A(B BBBE DXL`QXAP{ 8A0A(B BBBA |XK`NXFP H ~ BBE B(A0A8Do 8A0A(B BBBF x ܉ FBB B(A0D8Gp 8A0A(B BBBD L 8D0A(E BBBD d 8F0A(B BBBE \ X 4 FBE B(A0D8G2 8A0A(B BBBI ;NMA FHD D(G@H]PHHA@F (A ABBH fHEPPXD`K@HLPRHD@zHMPbHA@FHWPHHD@HIPPHB@FHIPOHA@jHJPSHA@FHIPOHA@ h Ěq FBB I(D0D8G@ZHJPFXI`L@ 8D0A(B BBBJ hHDP[HB@C HAPC XH\PKHA@uHLPZHA@ ǚ FBE B(A0D8J 8D0A(B BBBK xUZBST}ATYAYOB9VABR d 0К FBB B(A0A8D 8A0A(B BBBH , 8A0A(B BBBJ Ԛ Ԛ. , ՚# EY \ H ՚( FBA D(F0 (C ABBH k (A ABBG Z (A ABBA ՚ HN @ ՚ BEE D(D0D@ 0A(A BBBB H ֚ BED H(D0A (F ABBE W(A ABB t P ֚ BBB B(A0A8G L@IAAKAYAAAOASAUAAA 8C0A(B BBBA L Ȏ dٚ FIA D(D0 (D ABBG [ (D ABBA ٚ9 JY M AG < ښ FIB B(A0A8JK 8A0A(B BBBD \RHI^KPAMCDABBB^IHHBA^+HjAcU_BmN]H8 DO ` 8 FIA A(D0$ (D ABBF C (I ABBG R (D ABBE ` ER H d FBB B(A0A8D` 8A0A(B BBBE H 9 BBF F(A0A8GP 8A0A(B BBBJ L d N BBE E(I0A8J 8A0A(B BBBD 0 FID Go CABA ! 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N$ L}( ~P$ j U0T~Q~R1 L % % $ J $ () ") t F) D) h Q) O) \ ]) [) % )E U| T~Q1R $ $ U~T $G+ $ $% U~T G+ j$ j O% U| T~Qs R0 $ j s% U0T~R0 $ j % U| T~Q~ R1 $ % U~T |+ $ % U~T Bb* $$ j & U| T~Q~ R1 $ >% j O& U| T~Qs R0 W% j U| T~Q~ R1 ' $ ' ( g) e) > $ s>> x) r) 2> ) ) &> ) ) $ K Us $ &3$~"T~ Q $ &3$ i= ? % ? % Z' x= ) ) S % U: < +% ' < ) ) >% U2Ts $ ' U v$ r ' U| T~ ] % ' U _% K !@ q L ( ctx q6 ! L ( ctx 7 L L arg &< ]&/ e=opt i >& ( ctx 9 y L ] Յ &L >x ( arg % ? ! k L ) p k3 arg kB l0 n ] o o. pL pL &" u& &E ={\ w Յ xL !օ Y L ) p Y4 YL &" [ i E L $ :: Ap E. r* * Aopt F , , jՅ F&L , 4, Bs H ~Barg H ~M͚ I S . . Nerr JL . . "o , Bmsg U :: ~#4= M$ M$ % \* [= >/ </ O= Q/ O/ C= _/ [/ r$ K U TQ2RX + : r$ _, '; u/ q/ ; / / ; / / : '$ + ; '; / / ; / / < '$ '$ < / / < / / @$ , T2Q $+ X < $ $, < 0 0 < 0 0 $ , T2Q ;+ X < $ $ < 0 0 < 20 00 "$ , T2Q U+ 4= $ $ * Y[= =0 ;0 O= P0 N0 C= ^0 Z0 $ K U TQ2RX b. " 2 Oh :: ~Mm z 0 p0 4= '$ = - [= 0 0 O= 0 0 C= 0 0 E$ K U TQ2R : $ H . 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O& n = c 1 H L& [ k 12I \n Xn f! 1=U wn sn _ 1WD n n O L& 7 1 P .O n n L& L& (۲ o n O L& 7 (.O 1o /o % L& L& ) 4 6 @o >o L& v L& v L& k UUT0 V u1D J& t u14I go Mo 'z v1( o o # x1L }? y1|V ~_ z1D ap Up X {1H p p {1H p p Q)@ |1V J& I7 ~1 q q 8q 0q _q [q q wq J& J& % 0 q q q q J& U~T v. Q + K& U~T pv. Q + F J& [7 1 L X q q J& v f !K& k7 1 W v q q <L& <L& # r r <L& <L& .r ,r AL& v `L& `L& # ?r =r `L& `L& Pr Nr eL& v F 3L& 3L& 1 X ar _r F rL& 7 1 ¶ X sr qr wL& v FK& q ߶ U1T nK& It U| T~QLR} K& v L& v L& )t L U} T~Q 3L& t U~T . [L& U~T s. rL& n > O1D H& t O1II r r )@ P1H r r F Q1~ Os =s 9 S1H s s 0#7 ʸ J b1L ~ F JI& JI& f1 | X s s OI& v CI& yp UQTs I& / Uv Ts Q + R~ I& 67 p1 s s 5I& UUT0 F I& I& ^1 O X t t I& v I& f U0 J& n L4 .1D pF& .16I At )t + .1@H t t 'z /1% Lu 4u # 11L ~B2 21V u u / 31H u u G& 7 51 v v Bv :v jv fv v v G& G& ' 0 v v v v UG& Ϻ UXT v. Q + JH& UXT pv. Q + F UG& UG& ?1 B X v v ZG& v G& / o UUQ + R~ G& UX vH& n V> 1D `D& 13I w v + 1=H w rw 'z 1 x w # 1L ~B2 1V x x / 1H x x D& 6 1( x x y x /y +y Qy Iy E& E& ' 0ü }y yy y y EE& UXT v. Q + :F& UXT pv. Q + F EE& EE& 1 j X y y JE& v xE& / UUQ + R~ E& UX fF& n = 1D @D& = 1DI y y + 1NH y y 5RD& / UUTTQ + R0 7 0D D& 05I y y 2 0?H z z 52D& / UUTTQ + R0 0D D& / 06I #z z [& 0@H >z :z 5D& / UUTTQ R* R0 0D @[% T 01I ez Uz )@ 0 H z z 0$~ &{ { 'z 0,ot { u{ IC 0 { { ? 0|V ~_ 0D { { X 0H )| | 0H `| V| f g[% : 0 v | | ?\% ?\% # | | ?\% ?\% | | D\% v p\% p\% # | | p\% p\% | | u\% v u [% [% 0A } } F 9\% 9\% 0 v X } } F `\% `\% 0 X -} +} e\% v F \% Q 0 X >} <} \% v [% q U1T [% It / U~ T| R [% v \% v \% )t o U~ T~Q 9\% Us T s. R} `\% Us T s. \% n G 0 H 01I f! 0<U _ 0VD 0 H A 03I f! 0>U _ 0XD 7: 0D _ 0DI ^ 0D C& 0KI Q} M} 'z 0$ l} h} 5C& UUTT L= 7 0D 0FI * 0D e% M K 0NI } } 'z 0' ~ } 0L }? 0|V ~_ 0D Z~ L~ X 0H ~ ~ pfd 0H ~ ~ f% z 0 < 4 b ^ z ,f% ,f% " 0 ef% U U~T v. Q d+ 5g% U~T pv. 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Q_R_X % n 'N ?> ,+ / $"X > GC QH -Y i H ~ H > ~1C d $"X 3H d, -Y -Y y n: 0% #? 2k1 y*\ U2k2 y9\ T2ctx yC` Q t2 % b? 2key t+\ U2ctx t6` T C nH 0% @ T n,%N q m d+ n=V o%N ώ o'V ¯ 5B% q UUTTQQRRX0Y 7[ hH O@ T h1%N d+ hBV i %N ώ i,V j @ obj (F T ?%N $ PV ] M #@ j } %N v m! ~ t: 2 err !H i ! H F P I H 0% D obj 0F ٯ ( $ ~ ] * & btf \ V @ ] ~1id V ~1len V ~err H Ȱ fd H ( B % v% B W U h f x v v% 5B " O Ç% B .O Ç% Ç% (B ձ ͱ O v% (.O % v% v% ) B 6 {% v % W C Us T: % em /C T} % v ؆% fC U0T h. Qv % Nm %% v J% C U0T . Rv % s C U T| Q~ % 2m C U % n D UsTsQ C% u %D U~ h% v =D U % mD U0T . Q~ Xv % v D U % v % D U2T (. % v % D U0T Ȃ. Rv % n @ H p% VI ] .QN % t: 2 M I %N n d ~ H #@ %j ܲ QN $QN t v v = 7 j5 ~ _ Y m! ~ { 2 n H i H ˳ dz % G % F , % F , % % F % % ! 7% 7% FG v% G ! v% v% nG , ) ' % - % H ! 8 6 % nH , G E % - Ґ% ! H V T n d ! % 6r T# $ &4$ % v % hr ͏% Rr H Uv % v H Uv Ts 4% v H Uv Q% oI H U} n% u 'I UT} Q Ɛ% U2T p. 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Rv H T obj ;F map tA i H err H H aT obj 5F map JtA Y I i fd H err H H T obj 5F map JtA }  i fd H err H ' H Z& HV 2obj 6F V2map KtA S6A Un: Q /J ~def HV , ~ ]err !H !H \Z\& k U 1cp l R? l |V ~ Z& 8 U F[& 8 *U n[& 8 3U [& 8 |V u \& \& Y n: mV map 2 }3 H V obj 6F map KtA lt Y cp ? |V err H !; H H -W map 'tA cp ? |V err H bB H j, n: W map 7 @H # msg |V V err H 71 n: X obj /G != IP B X ret H = X 4W " ] U__c __u W =BX 44X " ] U__c __u X =zX 4lX " ] U__c __u GX =X 4X " ] U__c __u X )4 X " ] U__c __u X 2^ - = H @ % w Y y ?Y s ~ @Y X Sn % % D |Y en ` \ % v Us % )s Y UXT<Q s R8 % n ' Y ,+ Y 'V Y ,+ W! 1 H @% | Z S 3Z Pret 7H z t Q 7 H Sn % % : yZ en % v Us % tt Z U2T0Q L+ RPX2Y0 % n ' Z ,+ H &% q\ E H ~ L }S Z @X H H ػ err H vA + } '% [ ( & : 6 '% tt [ U2T~Q L+ R@X2Y~ 0(% It \ Uv T Q0R} 7(% v E(% v >\ Uv (% v V\ Us (% v (% n H p% ] S Z @X H Y Q H } w err H % tt ] U5T0Q L+ R@X2Y0 % It @] Uv T Q)R0 % v % v e] Uv % v }] Us - % v 8 % n + H p*% _ y ._ r ~ ! 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Qv Rs R6% n Z H x obj 6F map KtA id H H y obj 3F N D\ L= T\ v( ~ ~ $ 2 k "2 C d, -Y err H i H H ~ V scn o \ sym w rel w C % mz obj KG $ 2 2 l H # r H @ > m 'H T N C s m mz % % "z z n: z :I G2 6 H { :C 3 -Y V &~ sym { rel 1{ (Y 2 Q 2 obj F B V Y " ~ map tA ) k H i H n H ext ] H6 6 Y { obj AG JH B= n: { obj @G H Z: n: &| obj @G H 7W C ^| obj ;G ~ C n: | obj 6G UI 8 H } obj ;F sec n " n +n t v ext ] i H n H off H H ~ ~ x? 2 scn o sh \ =l} sym w =} iH ( ov )vs } ͂ vt ~n ) ' v , j H =} __y P )vs ͂ . H h~ btf +\ i H H 9 H !H vs >* sec v )vt v H "% Y btf .%N t v i H n H "% "% : "% "% V , / - l "% "% o ~ > < "% Rr Uv "% v Uv Ts -" H `% S _a $ Q K _b 4 s m a N b N p% iv G q5Z i% btf q8%N id qAH w r 6 * t tv m e u~ 0& enc ~H 8j% 8j% ~ i% i% | # , i% G U| TTQ0 i% v _ U| j% iv ~ T x+ }j% U| Q0 t9 X H btf X/\ ' X8H vs Y >* t Zv i [H j [ H n [ H 7 H X btf 71%N 7B~ t 9v % :~ i ;H n ; H & n: sym &-{ 6 &6H (H )H ' n: ̂ sym ,{ H i H | obj i 7F k ] elf l /S n m \ n \ idx o H err o H p ~ L= q \ scn r o sh s \ ) H ] H `% ݃ 2_a ] " U2_b ] 2 Ta _ I b ` I ; n: hdr ; ,\ ; =~ W3 5 n: * 5 +~ - w W L= - ,\ idx - 92 % w obj % ;G idx % G2 ; \ d% obj 8G 0 $ scn Fo k a L= \ e% o Us T0 )e% q U 7e% 5 Uv Ts Pe% Pp M Us le% U0T 0v. Rv X} Y| ~ c% T obj :G scn Ho ~ sh \ 9 c% j ن X - ) K G A j e i c 9 d% d% * Æ X K e d% q U 2d% U0T u. Q} Rs c% o Q} c% T Us Tv <d% q U Gd% Pp ' Uv `d% U0T u. Rs X} \ pA% ( obj 9G scn Go N \ A% o ʇ Us A% q U A% Pp Us A% U0T h. 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Y IK6 =6 tuz| t r Y4 Js=4 tgw v < = e J . t J < u v fvJ v X < X . t K < <# gsYv % J v J < uJ t< Xt<YW=YY y tP<z<<t Xz< v ;f yJ| |J 'u#s |( | X (J X.f/x3 u$ 1 < J tK}` J < { < f u Y {X! J< tK ,[=9 y<,v 1$ PJ1 <0J<3 Pt yX!pt <t X < t fu6 |< f 1 y. .Y 7 YX;suK< J X<XX<& Qt : J <X ! 0 % zt t X 0t t )X)#K I2 J < t J . f <z< ~X=~J J X }X> } < 2 ;=YZ ) vJ } < J <~J fg X <fz"vs"-<z<YXtfv < v" Jv zXfX g # NXJ J XB<X <;= tyJ X < X XK A = X= .Mv J v < #JJ < .X<i xt'D. v < X <w ~ww . XwJ F f D c ~ JwJ D J X J..C9v J v J (J v<<. H >KK XJ b K>3 !w J!w Ju u 1 X /J~~ - + 5 J J K@ ~"xv v X x"x %xJ .N ! w.) J <X ~X o wF 3 s . X! m * X J e q * g D D ; \ c J ( K" Ky H0g = ItK ufK$ ?JY= X p( K$KJ[ * JhQv K tJ J X< .* uX f !MG_ KzQ X z<<<t ..xy yJJJ y XK)NX ..dtKIKf.fJ z.K K, XY{t< X . < X yX' X' Y [ / X K =X... l. X/ _ !._< " K 2 I ( J ^) .HZJ.zX<X<.y& JsX st XsX/ z< X? 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M w Mt~ { . t|/ J > <> ) X 6 { { Ȃ zJ< zJ<Kz XOX|KKv u Yf KIuKjt X KY < u`x<<u e K uK |t <Ju-J { n " }X w~ J; XF JA <5 f <* / J J X% X Ui< ~ fA~ Y </ X J* W / J JX5#J >#<> > .K @ "X X" X| s X| s } X ~ g XJfu; XpoXw tv ? <?w wXJ wty wt - XL<| |~<X | < jX{XTNJt X {t} ~ !x | .t1X Y / Xy| < |< J X| s ,T *j<| f}X.}< X| X|~ J ~ Y / u.X XX} J;X Dg OX X g} JzX tXs~b fJX X ^ V q g * I \ J 0( K~~.t~X X= Y -/Z 2; =v H <Kv' Sow X [ WK f1 =`$ <[==9' *.9Of' t+ =;Y d#~X . `J . <d /sY.ttyx. gsY XK =fY= X 0( 8K H> \~ .$ t<< w. ? 9X t~<$ JmK' gJ JX' g ~ X$ .w< YX4t.~X<, <"m$ < f . i*~t$ .w~$ ~J .=~$ #J\=~.<Y~J~X~XJ % % q & & D I J D ( K <<~f xJ% 9 .% sJ XZt !Z =Z [ EK K vY uIgegb$JX. K V X*Qy/O <1 Y'' Y Zu* KWK XK% gK%rXK gj f &XX.f'' Y Z X< XL'.' Z K X \ n.eX < t < t . < 3tS/ XqP] I= /".r Y ./ t < t x. W X . < t /WY ]wKWI<Y= tt h J % '=z t .P M$EXJ6J;J <>Z- ? - <-<< ) X f0.b t# Q/KJX Y XJM / w X 8 XJ=!X< 0r X.XJ<f.< X $ X q XYs X < t X^<< X=Z} <=}Yt .<QyXXK J0 X>}XX %Y : JKK ]h J $ Y~|JW-<J:-~<-~JJ|<Z J }<=> tK } L/xJX X ) v f0ރ g|<< XX<9 K<Z! f |m Z u`X< X 9?Y KJJX9S _yXuu Y< X v s J ~ Y M } -}XX-}< wX XmX) z J!k| [t! c X XW X= 2 test_workload __sighandler_t sighandler workload_fnptr long long unsigned int leaf alarm long double __sig_atomic_t atoi argc long long int workload__leafloop GNU C11 13.3.0 -mtune=generic -march=x86-64 -g -O6 -O0 -std=gnu11 -fstack-protector-all -fno-inline -fno-omit-frame-pointer -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection GNU C11 13.3.0 -mtune=generic -march=x86-64 -g -O6 -O0 -std=gnu11 -fno-omit-frame-pointer -fstack-protector-all -fno-inline -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection workload__sqrtloop __pid_t sqrt rand brstack_foo brstack_foo_ind brstack_bar brstack_bench workload__brstack num_loops buf1 data1 data2 workload__datasym _SC_MAPPED_FILES _SC_MAPPED_FILES __S_TYPEISSEM(buf) ((buf)->st_mode - (buf)->st_mode) __ldiv_t_defined 1 _POSIX_THREADS 200809L __S_IFDIR 0040000 __FLT64X_HAS_QUIET_NAN__ 1 __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__ __UINT16_MAX__ 0xffff __SIZEOF_PTHREAD_CONDATTR_T 4 __ILP32_OFF32_CFLAGS "-m32" __OPEN_NEEDS_MODE(oflag) (((oflag) & O_CREAT) != 0 || ((oflag) & __O_TMPFILE) == __O_TMPFILE) __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 _unused2 _CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGS _SC_SIGSTKSZ _SC_SIGSTKSZ _SC_LINE_MAX _SC_LINE_MAX _SC_XOPEN_XCU_VERSION _SC_XOPEN_XCU_VERSION __FLT32_DIG__ 6 _WCHAR_T_DEFINED ESPIPE 29 _fileno __glibc_has_attribute(attr) __has_attribute (attr) _SC_CLK_TCK _SC_CLK_TCK _SC_ARG_MAX _SC_ARG_MAX _SC_V7_ILP32_OFFBIG _SC_V7_ILP32_OFFBIG __ASMNAME(cname) __ASMNAME2 (__USER_LABEL_PREFIX__, cname) EMEDIUMTYPE 124 __FLT64_MANT_DIG__ 53 __GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION _SC_BC_SCALE_MAX _SC_BC_SCALE_MAX __FLT_MAX_10_EXP__ 38 __SQUAD_TYPE long int __USE_MISC 1 __LITTLE_ENDIAN 1234 _POSIX_MESSAGE_PASSING 200809L F_SHLCK 8 _XOPEN_XPG2 1 __INT32_C(c) c __INT_LEAST64_WIDTH__ 64 R_OK 4 _POSIX_ASYNC_IO 1 _BITS_ENDIAN_H 1 _SC_GETGR_R_SIZE_MAX _SC_GETGR_R_SIZE_MAX __fortify_function __extern_always_inline __attribute_artificial__ __DEC64_MIN_EXP__ (-382) __FLT64_MIN_10_EXP__ (-307) WNOWAIT 0x01000000 __ATOMIC_HLE_RELEASE 131072 __PTRDIFF_MAX__ 0x7fffffffffffffffL ETOOMANYREFS 109 _SC_PII_INTERNET_DGRAM _SC_PII_INTERNET_DGRAM __WCHAR_TYPE__ int __STDC__ 1 _STATBUF_ST_RDEV __LDBL_REDIR(name,proto) name proto _SC_PAGE_SIZE _SC_PAGESIZE __UINT_FAST16_MAX__ 0xffffffffffffffffUL __DEC128_MIN_EXP__ (-6142) ERFKILL 132 __LEAF_ATTR __attribute__ ((__leaf__)) POLLHUP 0x010 __DBL_MAX_10_EXP__ 308 __attribute_warn_unused_result__ __attribute__ ((__warn_unused_result__)) _SC_NETWORKING _SC_NETWORKING _SC_LEVEL4_CACHE_LINESIZE _SC_LEVEL4_CACHE_LINESIZE __API_FD_ARRAY__ _SC_RTSIG_MAX _SC_RTSIG_MAX __getc_unlocked_body(_fp) (__glibc_unlikely ((_fp)->_IO_read_ptr >= (_fp)->_IO_read_end) ? __uflow (_fp) : *(unsigned char *) (_fp)->_IO_read_ptr++) _SC_PII_XTI _SC_PII_XTI __GLIBC_USE_DEPRECATED_GETS 1 __ELF__ 1 __LDBL_DIG__ 18 ENOTSUP EOPNOTSUPP __USE_DYNAMIC_STACK_SIZE _POSIX_SPAWN 200809L EWOULDBLOCK EAGAIN _XOPEN_VERSION 700 priv ENOBUFS 105 __WCHAR_T__ EBADE 52 _STDLIB_H 1 _SC_SYSTEM_DATABASE_R _SC_SYSTEM_DATABASE_R __need___va_list EMULTIHOP 72 EMFILE 24 _ASM_GENERIC_ERRNO_BASE_H ENOTUNIQ 76 __putc_unlocked_body(_ch,_fp) (__glibc_unlikely ((_fp)->_IO_write_ptr >= (_fp)->_IO_write_end) ? __overflow (_fp, (unsigned char) (_ch)) : (unsigned char) (*(_fp)->_IO_write_ptr++ = (_ch))) _SC_2_PBS_CHECKPOINT _SC_2_PBS_CHECKPOINT __VERSION__ "13.3.0" __DBL_HAS_INFINITY__ 1 __REDIRECT_NTH(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROW _CS_XBS5_LP64_OFF64_LINTFLAGS _CS_XBS5_LP64_OFF64_LINTFLAGS _SC_PRIORITIZED_IO _SC_PRIORITIZED_IO __FLT_HAS_INFINITY__ 1 __FLT16_MAX__ 6.55040000000000000000000000000000000e+4F16 __FLT128_MIN_10_EXP__ (-4931) _XOPEN_SHM 1 _BITS_BYTESWAP_H 1 __FD_SETSIZE 1024 __STD_TYPE typedef __THROWNL __attribute__ ((__nothrow__)) __FLT16_EPSILON__ 9.76562500000000000000000000000000000e-4F16 _SC_POLL _SC_POLL EILSEQ 84 __BFLT16_DENORM_MIN__ 9.18354961579912115600575419704879436e-41BF16 _SC_SIGNALS _SC_SIGNALS calloc EXDEV 18 fdarray__dup_entry_from __off_t _PC_PATH_MAX _PC_PATH_MAX ENFILE 23 S_IXGRP (S_IXUSR >> 3) __U32_TYPE unsigned int __struct_FILE_defined 1 _IO_USER_LOCK 0x8000 _CS_POSIX_V7_LPBIG_OFFBIG_LIBS _CS_POSIX_V7_LPBIG_OFFBIG_LIBS S_IRGRP (S_IRUSR >> 3) EADV 68 __DEV_T_TYPE __UQUAD_TYPE _POSIX_RAW_SOCKETS 200809L SEEK_SET 0 EISNAM 120 __USE_MISC __UINT_FAST64_MAX__ 0xffffffffffffffffUL __FLT16_HAS_DENORM__ 1 __BFLT16_HAS_INFINITY__ 1 _PC_NO_TRUNC _PC_NO_TRUNC _SC_BC_STRING_MAX _SC_BC_STRING_MAX _VA_LIST_DEFINED __DEC128_MANT_DIG__ 34 __nlink_t_defined __SHRT_MAX__ 0x7fff _POSIX_SHELL 1 _POSIX_VDISABLE '\0' __INTPTR_TYPE__ long int __FLT_IS_IEC_60559__ 1 __wchar_t__ __FLT32_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F32 ETXTBSY 26 O_SYNC 04010000 __FLT_DIG__ 6 __USE_XOPEN_EXTENDED _POSIX_THREAD_PRIO_INHERIT 200809L _POSIX_V6_LPBIG_OFFBIG -1 POLLWRBAND 0x200 L_tmpnam 20 __MODE_T_TYPE __U32_TYPE __f64x(x) x ##f64x __INT_LEAST64_TYPE__ long int __INT32_MAX__ 0x7fffffff __FLT128_MIN__ 3.36210314311209350626267781732175260e-4932F128 __GNUC_PATCHLEVEL__ 0 O_EXCL 0200 _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS _SC_EQUIV_CLASS_MAX _SC_EQUIV_CLASS_MAX __GCC_ATOMIC_CHAR_LOCK_FREE 2 POSIX_FADV_DONTNEED __POSIX_FADV_DONTNEED __FLT128_MANT_DIG__ 113 __UINT_FAST32_TYPE__ long unsigned int O_RDONLY 00 _SC_SINGLE_PROCESS _SC_SINGLE_PROCESS _CS_POSIX_V6_ILP32_OFF32_CFLAGS _CS_POSIX_V6_ILP32_OFF32_CFLAGS __INO_T_MATCHES_INO64_T 1 __SIZEOF_INT__ 4 O_NOFOLLOW __O_NOFOLLOW __glibc_c99_flexarr_available 1 __FLT32X_MAX_10_EXP__ 308 POSIX_FADV_RANDOM 1 S_IWOTH (S_IWGRP >> 3) __SIG_ATOMIC_TYPE__ int _BSD_SIZE_T_DEFINED_ __BIGGEST_ALIGNMENT__ 16 __FLT16_NORM_MAX__ 6.55040000000000000000000000000000000e+4F16 __INT_FAST16_WIDTH__ 64 __BFLT16_MAX__ 3.38953138925153547590470800371487867e+38BF16 __UINT16_C(c) c __F_GETSIG 11 F_SETFL 4 _SYS_SELECT_H 1 ENOTEMPTY 39 __HAVE_DISTINCT_FLOAT128 1 __pic__ 2 __glibc_has_extension(ext) 0 __NFDBITS (8 * (int) sizeof (__fd_mask)) __S_IFLNK 0120000 __DADDR_T_TYPE __S32_TYPE __SCHAR_MAX__ 0x7f _XOPEN_XPG3 1 F_GETFL 3 ___int_wchar_t_h EEXIST 17 L_SET SEEK_SET _SC_THREAD_DESTRUCTOR_ITERATIONS _SC_THREAD_DESTRUCTOR_ITERATIONS __FLT16_DENORM_MIN__ 5.96046447753906250000000000000000000e-8F16 __UINTPTR_TYPE__ long unsigned int _BITS_STAT_H 1 _SC_LEVEL1_ICACHE_LINESIZE _SC_LEVEL1_ICACHE_LINESIZE __DBL_EPSILON__ ((double)2.22044604925031308084726333618164062e-16L) __bswap_constant_32(x) ((((x) & 0xff000000u) >> 24) | (((x) & 0x00ff0000u) >> 8) | (((x) & 0x0000ff00u) << 8) | (((x) & 0x000000ffu) << 24)) _POSIX_VERSION 200809L __SIZE_MAX__ 0xffffffffffffffffUL S_IXOTH (S_IXGRP >> 3) __FLT32X_MAX__ 1.79769313486231570814527423731704357e+308F32x _POSIX2_C_BIND __POSIX2_THIS_VERSION __always_inline __UINT8_TYPE__ unsigned char __HAVE_FLOAT16 0 S_IROTH (S_IRGRP >> 3) __USE_LARGEFILE64 1 __FLT32_MIN_10_EXP__ (-37) EBADRQC 56 _POSIX_PRIORITY_SCHEDULING 200809L __FLT128_MIN_EXP__ (-16381) __STDC_UTF_32__ 1 __INT_LEAST16_MAX__ 0x7fff _LFS_LARGEFILE 1 S_IRWXO (S_IRWXG >> 3) _PC_SOCK_MAXBUF _PC_SOCK_MAXBUF __LDBL_DECIMAL_DIG__ 21 _SC_THREADS _SC_THREADS __GLIBC_USE_C2X_STRTOL _IO_write_end _POSIX_THREAD_PROCESS_SHARED 200809L _SC_TRACE_SYS_MAX _SC_TRACE_SYS_MAX __UINT16_TYPE__ short unsigned int __F_SETSIG 10 _CS_LFS_LINTFLAGS _CS_LFS_LINTFLAGS _SC_TTY_NAME_MAX _SC_TTY_NAME_MAX _CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGS le32toh(x) __uint32_identity (x) __STDC_IEC_559__ 1 _BITS_UINTN_IDENTITY_H 1 __attribute_malloc__ __attribute__ ((__malloc__)) __UWORD_TYPE unsigned long int EREMOTE 66 _T_SIZE_ _SC_V7_LPBIG_OFFBIG _SC_V7_LPBIG_OFFBIG _SC_ADVISORY_INFO _SC_ADVISORY_INFO htobe64(x) __bswap_64 (x) __FLT32X_HAS_INFINITY__ 1 O_FSYNC O_SYNC ENETDOWN 100 __FD_ISSET(d,s) ((__FDS_BITS (s)[__FD_ELT (d)] & __FD_MASK (d)) != 0) _SC_LEVEL1_ICACHE_SIZE _SC_LEVEL1_ICACHE_SIZE __glibc_objsize(__o) __bos (__o) __FLT16_IS_IEC_60559__ 1 __UINT64_MAX__ 0xffffffffffffffffUL __INT8_C(c) c __stub_chflags __FLT16_MAX_EXP__ 16 __FLT32_HAS_INFINITY__ 1 ____mbstate_t_defined 1 EINVAL 22 __WCOREDUMP(status) ((status) & __WCOREFLAG) _SC_LEVEL1_DCACHE_ASSOC _SC_LEVEL1_DCACHE_ASSOC __FLT_MAX_EXP__ 128 __ATOMIC_SEQ_CST 5 EIDRM 43 _GCC_SIZE_T __stub_setlogin __HAVE_FLOAT128X 0 _IO_read_end _SC_PAGESIZE _SC_PAGESIZE LOCK_SH 1 _CS_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVS _SC_2_PBS_LOCATE _SC_2_PBS_LOCATE st_ctime st_ctim.tv_sec __FLT32_MANT_DIG__ 24 __stub_stty __WORDSIZE 64 __FLT64X_IS_IEC_60559__ 1 __attr_access(x) __attribute__ ((__access__ x)) _CS_LFS_LDFLAGS _CS_LFS_LDFLAGS _POSIX_SPORADIC_SERVER -1 ELIBEXEC 83 _SC_LEVEL1_ICACHE_ASSOC _SC_LEVEL1_ICACHE_ASSOC __INT_LEAST8_WIDTH__ 8 __uid_t_defined ENOTNAM 118 LOCK_NB 4 ESRCH 3 ECONNRESET 104 _XBS5_LPBIG_OFFBIG -1 _POSIX_SYNCHRONIZED_IO 200809L revents S_IFMT __S_IFMT _SC_2_FORT_DEV _SC_2_FORT_DEV __WIFSIGNALED(status) (((signed char) (((status) & 0x7f) + 1) >> 1) > 0) __GCC_IEC_559_COMPLEX 2 _SC_XBS5_LPBIG_OFFBIG _SC_XBS5_LPBIG_OFFBIG __S32_TYPE int _SC_TYPED_MEMORY_OBJECTS _SC_TYPED_MEMORY_OBJECTS __FLT16_HAS_QUIET_NAN__ 1 __O_TMPFILE (020000000 | __O_DIRECTORY) __USER_LABEL_PREFIX__ S_IFLNK __S_IFLNK _SIZE_T_DECLARED __USE_FORTIFY_LEVEL 0 __DECIMAL_DIG__ 21 __GLIBC_USE_LIB_EXT2 0 __UINT_LEAST32_MAX__ 0xffffffffU _BITS_TYPESIZES_H 1 _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS __FLT16_MIN_10_EXP__ (-4) P_tmpdir "/tmp" _POSIX2_VERSION __POSIX2_THIS_VERSION __attribute_format_arg__(x) __attribute__ ((__format_arg__ (x))) EL2HLT 51 _SC_XOPEN_VERSION _SC_XOPEN_VERSION __ino_t_defined __BFLT16_DECIMAL_DIG__ 4 BYTE_ORDER __BYTE_ORDER _SC_TRACE _SC_TRACE __DEC_EVAL_METHOD__ 2 __GLIBC_USE_IEC_60559_TYPES_EXT EBADF 9 __LP64_OFF64_LDFLAGS "-m64" __FLT32_MIN_EXP__ (-125) F_ULOCK 0 _BITS_ENDIANNESS_H 1 POLLWRNORM 0x100 fdarray__filter __O_LARGEFILE 0 alloca MB_CUR_MAX (__ctype_get_mb_cur_max ()) _BITS_STRUCT_STAT_H 1 __timeval_defined 1 _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVS __FLT32X_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F32x __FLT_MIN_10_EXP__ (-37) _CS_POSIX_V6_LP64_OFF64_CFLAGS _CS_POSIX_V6_LP64_OFF64_CFLAGS _CS_XBS5_LPBIG_OFFBIG_LDFLAGS _CS_XBS5_LPBIG_OFFBIG_LDFLAGS F_SETLKW F_SETLKW64 _POSIX_SPIN_LOCKS 200809L __CFLOAT32X _Complex _Float32x __INT_FAST64_MAX__ 0x7fffffffffffffffL _POSIX2_CHAR_TERM 200809L __DBL_MANT_DIG__ 53 _SC_THREAD_CPUTIME _SC_THREAD_CPUTIME __WCHAR_MIN__ (-__WCHAR_MAX__ - 1) ENOSR 63 _UNISTD_H 1 __k8 1 __USE_POSIX 1 _XOPEN_XPG4 1 __USE_POSIX _SC_WORD_BIT _SC_WORD_BIT __INT_WCHAR_T_H __gid_t_defined __LDBL_NORM_MAX__ 1.18973149535723176502126385303097021e+4932L ENODEV 19 __DEC32_EPSILON__ 1E-6DF _CS_XBS5_LP64_OFF64_LIBS _CS_XBS5_LP64_OFF64_LIBS __O_PATH 010000000 __INTPTR_MAX__ 0x7fffffffffffffffL _CS_POSIX_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVS _SC_DEVICE_SPECIFIC _SC_DEVICE_SPECIFIC __glibc_macro_warning(message) __glibc_macro_warning1 (GCC warning message) __USE_ISOC99 1 __FD_ZERO(s) do { unsigned int __i; fd_set *__arr = (s); for (__i = 0; __i < sizeof (fd_set) / sizeof (__fd_mask); ++__i) __FDS_BITS (__arr)[__i] = 0; } while (0) _POSIX_SOURCE __size_t __WINT_MAX__ 0xffffffffU EBADFD 77 _SC_SPIN_LOCKS _SC_SPIN_LOCKS FD_SET(fd,fdsetp) __FD_SET (fd, fdsetp) __FLT_EPSILON__ 1.19209289550781250000000000000000000e-7F AT_FDCWD -100 __BFLT16_HAS_QUIET_NAN__ 1 _CS_POSIX_V6_LPBIG_OFFBIG_LIBS _CS_POSIX_V6_LPBIG_OFFBIG_LIBS __errordecl(name,msg) extern void name (void) __attribute__((__error__ (msg))) _CS_POSIX_V6_ILP32_OFFBIG_LIBS _CS_POSIX_V6_ILP32_OFFBIG_LIBS WIFSTOPPED(status) __WIFSTOPPED (status) __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 __CET__ 3 __UINT_LEAST64_MAX__ 0xffffffffffffffffUL __GLIBC_USE_IEC_60559_BFP_EXT __glibc_likely(cond) __builtin_expect ((cond), 1) __UINT8_C(c) c fdarray__delete __mode_t_defined O_RDWR 02 __FLT32_MAX__ 3.40282346638528859811704183484516925e+38F32 __f32x(x) x ##f32x _SC_XOPEN_XPG3 _SC_XOPEN_XPG3 ERESTART 85 _SC_THREAD_THREADS_MAX _SC_THREAD_THREADS_MAX _SC_XOPEN_CRYPT _SC_XOPEN_CRYPT __INTMAX_TYPE__ long int S_ISUID __S_ISUID __amd64 1 __SEG_GS 1 __HAVE_GENERIC_SELECTION 1 _SC_THREAD_ROBUST_PRIO_PROTECT _SC_THREAD_ROBUST_PRIO_PROTECT __ORDER_LITTLE_ENDIAN__ 1234 _SC_MQ_PRIO_MAX _SC_MQ_PRIO_MAX _IO_lock_t _SC_LEVEL2_CACHE_ASSOC _SC_LEVEL2_CACHE_ASSOC __FLT32_MAX_10_EXP__ 38 E2BIG 7 __S_ISVTX 01000 _CS_POSIX_V7_ILP32_OFFBIG_LIBS _CS_POSIX_V7_ILP32_OFFBIG_LIBS POLLIN 0x001 __DBL_MAX_EXP__ 1024 _STATBUF_ST_NSEC __USE_ISOC95 __USE_ISOC99 __UINT_LEAST16_MAX__ 0xffff _PC_CHOWN_RESTRICTED _PC_CHOWN_RESTRICTED _POSIX_THREAD_SAFE_FUNCTIONS 200809L __FLT32X_MAX_EXP__ 1024 _SC_MULTI_PROCESS _SC_MULTI_PROCESS __SIG_ATOMIC_MAX__ 0x7fffffff ENXIO 6 __SIZEOF_SIZE_T__ 8 __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL __SIZEOF_PTHREAD_RWLOCKATTR_T 8 _BITS_STDINT_INTN_H 1 __x86_64__ 1 _CS_GNU_LIBC_VERSION _CS_GNU_LIBC_VERSION __REDIRECT_LDBL(name,proto,alias) __REDIRECT (name, proto, alias) __PTRDIFF_WIDTH__ 64 BIG_ENDIAN __BIG_ENDIAN __USE_XOPEN2K __USE_POSIX199506 __NTH(fct) __attribute__ ((__nothrow__ __LEAF)) fct __unix__ 1 _SC_SCHAR_MAX _SC_SCHAR_MAX __LDBL_MIN__ 3.36210314311209350626267781732175260e-4932L EDESTADDRREQ 89 be64toh(x) __bswap_64 (x) F_DUPFD_CLOEXEC 1030 _PC_SYNC_IO _PC_SYNC_IO _BITS_POSIX_OPT_H 1 __UINT_LEAST64_TYPE__ long unsigned int _CS_XBS5_ILP32_OFF32_LDFLAGS _CS_XBS5_ILP32_OFF32_LDFLAGS timeout __wur __DBL_DECIMAL_DIG__ 17 __SIZEOF_LONG_LONG__ 8 __NTHNL(fct) __attribute__ ((__nothrow__)) fct __WIFCONTINUED(status) ((status) == __W_CONTINUED) __FLT64X_MAX_10_EXP__ 4932 __FLT32_DECIMAL_DIG__ 9 _SC_STREAMS _SC_STREAMS _POSIX_THREAD_CPUTIME 0 _SC_THREAD_KEYS_MAX _SC_THREAD_KEYS_MAX __clock_t_defined 1 _DEFAULT_SOURCE 1 _WCHAR_T_DEFINED_ _SC_NL_ARGMAX _SC_NL_ARGMAX __FSWORD_T_TYPE __SYSCALL_SLONG_TYPE _SC_RE_DUP_MAX _SC_RE_DUP_MAX __FLT128_MAX_10_EXP__ 4932 _SC_SYSTEM_DATABASE _SC_SYSTEM_DATABASE _SC_ATEXIT_MAX _SC_ATEXIT_MAX _POSIX_V6_LP64_OFF64 1 fdarray_flags __END_DECLS _POSIX_MEMLOCK 200809L __THROW __attribute__ ((__nothrow__ __LEAF)) __intptr_t_defined __INT16_MAX__ 0x7fff __LDBL_REDIR1(name,proto,alias) name proto __FLT_MANT_DIG__ 24 __W_STOPCODE(sig) ((sig) << 8 | 0x7f) __glibc_objsize0(__o) __bos0 (__o) _POSIX2_C_VERSION __POSIX2_THIS_VERSION ENOTSOCK 88 __FLT64_HAS_QUIET_NAN__ 1 __UQUAD_TYPE unsigned long int AT_REMOVEDIR 0x200 __USE_XOPEN2K8XSI __timer_t_defined 1 _SC_THREAD_PRIORITY_SCHEDULING _SC_THREAD_PRIORITY_SCHEDULING EDEADLK 35 __SIZE_WIDTH__ 64 __need___va_list ELIBSCN 81 __HAVE_DISTINCT_FLOAT16 __HAVE_FLOAT16 __TIMESIZE __WORDSIZE __INT_LEAST8_MAX__ 0x7f _IO_write_ptr __FLT_MIN_EXP__ (-125) __FLT64X_EPSILON__ 1.08420217248550443400745280086994171e-19F64x __dev_t_defined _LARGEFILE64_SOURCE 1 __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ ____sigset_t_defined __FLT_RADIX__ 2 __BFLT16_MIN_EXP__ (-125) EPROTO 71 __LDBL_IS_IEC_60559__ 1 __FLT32X_DIG__ 15 _SC_PII_INTERNET _SC_PII_INTERNET __LDBL_REDIR1_NTH(name,proto,alias) name proto __THROW _POSIX_FSYNC 200809L __FLT_EVAL_METHOD_TS_18661_3__ 0 _SC_XOPEN_REALTIME _SC_XOPEN_REALTIME ECHILD 10 EBADR 53 __DEC128_MAX_EXP__ 6145 _POSIX2_SW_DEV __POSIX2_THIS_VERSION __HAVE_DISTINCT_FLOAT64 0 _SC_MB_LEN_MAX _SC_MB_LEN_MAX __FLT128_MAX__ 1.18973149535723176508575932662800702e+4932F128 __O_CLOEXEC 02000000 _SC_2_PBS_ACCOUNTING _SC_2_PBS_ACCOUNTING __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF __KERNEL_STRICT_NAMES __COMPAR_FN_T __UINTMAX_TYPE__ long unsigned int __U64_TYPE unsigned long int __FLT32X_MANT_DIG__ 53 _BITS_TIME64_H 1 __ONCE_ALIGNMENT POLLOUT 0x004 __UINT_FAST8_TYPE__ unsigned char __CHAR32_TYPE__ unsigned int __ID_T_TYPE __U32_TYPE __INT_WIDTH__ 32 FFSYNC O_FSYNC __UINT64_TYPE__ long unsigned int __WEXITSTATUS(status) (((status) & 0xff00) >> 8) POSIX_FADV_WILLNEED 3 FAPPEND O_APPEND __USE_LARGEFILE64 _POSIX_TIMEOUTS 200809L __FLT32_IS_IEC_60559__ 1 __BIT_TYPES_DEFINED__ 1 __always_inline __inline __attribute__ ((__always_inline__)) __LP64__ 1 F_SETFD 2 __U16_TYPE unsigned short int htobe32(x) __bswap_32 (x) __nonnull(params) __attribute_nonnull__ (params) _SC_REGEXP _SC_REGEXP _CS_XBS5_ILP32_OFF32_LIBS _CS_XBS5_ILP32_OFF32_LIBS __POSIX_FADV_DONTNEED 4 _SC_V6_ILP32_OFFBIG _SC_V6_ILP32_OFFBIG __LDBL_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951L __SEG_FS 1 __attribute_pure__ __attribute__ ((__pure__)) __FLT32X_DECIMAL_DIG__ 17 __LONG_MAX__ 0x7fffffffffffffffL __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 __INT16_TYPE__ short int __FLT128_DIG__ 33 ENETUNREACH 101 __KERNEL_STRICT_NAMES __HAVE_FLOAT64 1 _SC_TRACE_EVENT_FILTER _SC_TRACE_EVENT_FILTER _SC_NL_TEXTMAX _SC_NL_TEXTMAX POSIX_FADV_NORMAL 0 _SC_NL_MSGMAX _SC_NL_MSGMAX __pid_t_defined UTIME_OMIT ((1l << 30) - 2l) __INTMAX_MAX__ 0x7fffffffffffffffL __BFLT16_NORM_MAX__ 3.38953138925153547590470800371487867e+38BF16 __GCC_ATOMIC_LONG_LOCK_FREE 2 PDP_ENDIAN __PDP_ENDIAN _CS_POSIX_V6_LP64_OFF64_LDFLAGS _CS_POSIX_V6_LP64_OFF64_LDFLAGS O_ASYNC 020000 ETIME 62 ERANGE 34 EAFNOSUPPORT 97 __TIME_T_TYPE __SYSCALL_SLONG_TYPE __WINT_MIN__ 0U __S_IFREG 0100000 _PC_2_SYMLINKS _PC_2_SYMLINKS _SC_LEVEL3_CACHE_ASSOC _SC_LEVEL3_CACHE_ASSOC __stub_fchflags L_ctermid 9 __ULONGWORD_TYPE unsigned long int _SC_TIMERS _SC_TIMERS __INT_MAX__ 0x7fffffff _BITS_ATOMIC_WIDE_COUNTER_H __USE_XOPEN __amd64__ 1 _DEFAULT_SOURCE __GLIBC_USE(F) __GLIBC_USE_ ## F __BFLT16_HAS_DENORM__ 1 __UINT_LEAST32_TYPE__ unsigned int __WORDSIZE_TIME64_COMPAT32 1 __HAVE_SPECULATION_SAFE_VALUE 1 _LFS64_ASYNCHRONOUS_IO 1 __attr_access_none(argno) __attribute__ ((__access__ (__none__, argno))) _GCC_WCHAR_T __attribute_copy__(arg) __attribute__ ((__copy__ (arg))) _SC_PII_OSI_CLTS _SC_PII_OSI_CLTS ___int_size_t_h POLLERR 0x008 O_LARGEFILE __O_LARGEFILE EPERM 1 EKEYREVOKED 128 __DBL_MIN_10_EXP__ (-307) _IO_save_base __LDBL_REDIR_DECL(name) ENETRESET 102 __need_size_t _THREAD_MUTEX_INTERNAL_H 1 O_ACCMODE 0003 _LFS64_LARGEFILE 1 __LDBL_MIN_EXP__ (-16381) __clockid_t_defined 1 _BSD_WCHAR_T_ _SC_NPROCESSORS_CONF _SC_NPROCESSORS_CONF __GCC_HAVE_DWARF2_CFI_ASM 1 __CFLOAT128 _Complex _Float128 _SC_XBS5_ILP32_OFF32 _SC_XBS5_ILP32_OFF32 LITTLE_ENDIAN __LITTLE_ENDIAN __BFLT16_MAX_10_EXP__ 38 __FLT16_MAX_10_EXP__ 4 _POSIX_CHOWN_RESTRICTED 0 _SC_PII_OSI_M _SC_PII_OSI_M W_OK 2 _SC_SIGQUEUE_MAX _SC_SIGQUEUE_MAX __need_size_t __FLT64X_MAX_EXP__ 16384 _SC_SYMLOOP_MAX _SC_SYMLOOP_MAX __bswap_constant_16(x) ((__uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8))) EL3HLT 46 _shortbuf _CS_XBS5_LP64_OFF64_CFLAGS _CS_XBS5_LP64_OFF64_CFLAGS _CS_XBS5_LPBIG_OFFBIG_LINTFLAGS _CS_XBS5_LPBIG_OFFBIG_LINTFLAGS UTIME_NOW ((1l << 30) - 1l) __DEC128_MIN__ 1E-6143DL _SC_NL_NMAX _SC_NL_NMAX __INT64_TYPE__ long int __DEC64_MANT_DIG__ 16 __DEC32_MIN__ 1E-95DF __FLT_HAS_QUIET_NAN__ 1 __REDIRECT_FORTIFY_NTH __REDIRECT_NTH __USE_UNIX98 nr_alloc __INT_LEAST16_TYPE__ short int __CONCAT(x,y) x ## y EDEADLOCK EDEADLK _CS_POSIX_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVS WSTOPSIG(status) __WSTOPSIG (status) F_DUPFD 0 __SCHAR_WIDTH__ 8 __stub_gtty _POSIX_MEMORY_PROTECTION 200809L __ORDER_PDP_ENDIAN__ 3412 __OFF_T_MATCHES_OFF64_T 1 __FD_CLR(d,s) ((void) (__FDS_BITS (s)[__FD_ELT(d)] &= ~__FD_MASK(d))) __LONG_LONG_MAX__ 0x7fffffffffffffffLL _POSIX_ASYNCHRONOUS_IO 200809L _SC_HOST_NAME_MAX _SC_HOST_NAME_MAX _BITS_FLOATN_COMMON_H S_ISVTX __S_ISVTX __BIG_ENDIAN 4321 __SSE2__ 1 _SC_REALTIME_SIGNALS _SC_REALTIME_SIGNALS _CS_XBS5_ILP32_OFF32_CFLAGS _CS_XBS5_ILP32_OFF32_CFLAGS __WINT_WIDTH__ 32 __RLIM_T_MATCHES_RLIM64_T 1 _SC_PII _SC_PII __f128(x) x ##f128 __fsblkcnt_t_defined _SC_BARRIERS _SC_BARRIERS __FLT16_MANT_DIG__ 11 _SC_SHRT_MIN _SC_SHRT_MIN _LFS64_STDIO 1 __INTMAX_WIDTH__ 64 _SC_XOPEN_XPG4 _SC_XOPEN_XPG4 __GNUC_VA_LIST F_RDLCK 0 __FLT64X_MIN_10_EXP__ (-4931) _BITS_TYPES___LOCALE_T_H 1 __fsfilcnt_t_defined _SC_SELECT _SC_SELECT WNOHANG 1 _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS _SC_AIO_PRIO_DELTA_MAX _SC_AIO_PRIO_DELTA_MAX O_APPEND 02000 __SIZEOF_PTHREAD_COND_T 48 __ATOMIC_RELAXED 0 __UINTMAX_MAX__ 0xffffffffffffffffUL _CS_POSIX_V6_ILP32_OFF32_LIBS _CS_POSIX_V6_ILP32_OFF32_LIBS __STDC_IEC_60559_COMPLEX__ 201404L _XOPEN_UNIX 1 fdarray_flag__nonfilterable __GNU_LIBRARY__ _CS_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVS __USE_ATFILE 1 _CS_PATH _CS_PATH _POSIX_MEMLOCK_RANGE 200809L ENOSTR 60 _SC_PII_SOCKET _SC_PII_SOCKET _IONBF 2 ENOSYS 38 S_IFBLK __S_IFBLK __DBL_DENORM_MIN__ ((double)4.94065645841246544176568792868221372e-324L) __socklen_t_defined __GCC_IEC_559 2 __REDIRECT_NTHNL(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROWNL _SC_TRACE_LOG _SC_TRACE_LOG TMP_MAX 238328 __GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION F_OK 0 WSTOPPED 2 __BFLT16_IS_IEC_60559__ 0 ENOTCONN 107 __UINTPTR_MAX__ 0xffffffffffffffffUL __blksize_t_defined __have_pthread_attr_t 1 WEXITED 4 _SC_XOPEN_SHM _SC_XOPEN_SHM __INT_FAST16_MAX__ 0x7fffffffffffffffL ENOMEDIUM 123 EPROTONOSUPPORT 93 _POSIX_SEMAPHORES 200809L _PC_FILESIZEBITS _PC_FILESIZEBITS _WCHAR_T_DECLARED __GLIBC_USE_IEC_60559_FUNCS_EXT _PC_PIPE_BUF _PC_PIPE_BUF __ATOMIC_RELEASE 3 __INT64_MAX__ 0x7fffffffffffffffL __LOCK_ALIGNMENT __SSE_MATH__ 1 ENOMEM 12 __GNUC__ 13 __FLT64X_NORM_MAX__ 1.18973149535723176502126385303097021e+4932F64x _POSIX_MAPPED_FILES 200809L __FLT64X_MAX__ 1.18973149535723176502126385303097021e+4932F64x ENOPROTOOPT 92 fdarray__poll fdarray__grow _SC_T_IOV_MAX _SC_T_IOV_MAX __FDS_BITS(set) ((set)->__fds_bits) __INT_LEAST32_WIDTH__ 32 __BFLT16_MIN__ 1.17549435082228750796873653722224568e-38BF16 _SC_BASE _SC_BASE ENOEXEC 8 __FLT32X_NORM_MAX__ 1.79769313486231570814527423731704357e+308F32x _POSIX_TIMERS 200809L __DBL_IS_IEC_60559__ 1 __FLT128_HAS_DENORM__ 1 _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V7_LP64_OFF64_LINTFLAGS _CS_POSIX_V7_LP64_OFF64_LINTFLAGS __SIZEOF_WINT_T__ 4 __S_IFBLK 0060000 __FLT64_MAX_10_EXP__ 308 __HAVE_FLOAT64X 1 __FLT64X_MIN__ 3.36210314311209350626267781732175260e-4932F64x __off_t_defined EADDRNOTAVAIL 99 __va_arg_pack() __builtin_va_arg_pack () _SC_INT_MAX _SC_INT_MAX le16toh(x) __uint16_identity (x) F_WRLCK 1 __GXX_ABI_VERSION 1018 WCONTINUED 8 fdarray__fprintf _POSIX_THREAD_ROBUST_PRIO_INHERIT 200809L _CS_POSIX_V6_LP64_OFF64_LINTFLAGS _CS_POSIX_V6_LP64_OFF64_LINTFLAGS __SLONGWORD_TYPE long int ENOLCK 37 ESTRPIPE 86 __FLT64_IS_IEC_60559__ 1 _SC_AIO_LISTIO_MAX _SC_AIO_LISTIO_MAX _PC_SYMLINK_MAX _PC_SYMLINK_MAX __SIZEOF_WCHAR_T__ 4 __FLT_EVAL_METHOD__ 0 __GLIBC__ 2 _SC_XOPEN_XPG2 _SC_XOPEN_XPG2 __INT8_MAX__ 0x7f __ATOMIC_ACQUIRE 2 _SC_SEM_NSEMS_MAX _SC_SEM_NSEMS_MAX __SIZEOF_PTHREAD_MUTEXATTR_T 4 _SC_V7_ILP32_OFF32 _SC_V7_ILP32_OFF32 __P(args) args __HAVE_FLOAT128_UNLIKE_LDBL (__HAVE_DISTINCT_FLOAT128 && __LDBL_MANT_DIG__ != 113) __PIC__ 2 _SC_VERSION _SC_VERSION _SYS_SIZE_T_H __RLIM_T_TYPE __SYSCALL_ULONG_TYPE ESOCKTNOSUPPORT 94 __useconds_t_defined _CS_V6_ENV _CS_V6_ENV __FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64 _CS_POSIX_V7_LP64_OFF64_LIBS _CS_POSIX_V7_LP64_OFF64_LIBS _IO_EOF_SEEN 0x0010 __x86_64 1 _SC_BC_DIM_MAX _SC_BC_DIM_MAX EMSGSIZE 90 _PC_MAX_CANON _PC_MAX_CANON _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS __USE_FORTIFY_LEVEL F_GETLK64 5 __USE_ISOC11 F_SETLK F_SETLK64 _IO_save_end __suseconds_t_defined __attribute_alloc_align__(param) __attribute__ ((__alloc_align__ param)) ESHUTDOWN 108 __USECONDS_T_TYPE __U32_TYPE _THREAD_SHARED_TYPES_H 1 ENOKEY 126 FD_CLR(fd,fdsetp) __FD_CLR (fd, fdsetp) POSIX_FADV_NOREUSE __POSIX_FADV_NOREUSE _SC_REGEX_VERSION _SC_REGEX_VERSION __USE_XOPEN2K8 EPFNOSUPPORT 96 _SC_SPORADIC_SERVER _SC_SPORADIC_SERVER __FD_SET(d,s) ((void) (__FDS_BITS (s)[__FD_ELT(d)] |= __FD_MASK(d))) __SUSECONDS_T_TYPE __SYSCALL_SLONG_TYPE __need_NULL _SC_JOB_CONTROL _SC_JOB_CONTROL __GLIBC_USE_DEPRECATED_SCANF _SC_DELAYTIMER_MAX _SC_DELAYTIMER_MAX __SYSCALL_WORDSIZE 64 __USE_LARGEFILE __DEC32_MIN_EXP__ (-94) __SWORD_TYPE long int _POSIX_SAVED_IDS 1 __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 ECONNABORTED 103 __ILP32_OFFBIG_CFLAGS "-m32 -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64" __USE_POSIX199309 1 __UINT32_TYPE__ unsigned int _SC_COLL_WEIGHTS_MAX _SC_COLL_WEIGHTS_MAX __attribute_maybe_unused__ __attribute__ ((__unused__)) __FLT64X_DIG__ 18 _SC_CHARCLASS_NAME_MAX _SC_CHARCLASS_NAME_MAX O_DSYNC __O_DSYNC _____fpos64_t_defined 1 __LDBL_MAX_10_EXP__ 4932 O_DIRECTORY __O_DIRECTORY EDOM 33 __DEC64_EPSILON__ 1E-15DD FILENAME_MAX 4096 _SC_NL_LANGMAX _SC_NL_LANGMAX _SC_FILE_SYSTEM _SC_FILE_SYSTEM _STRING_H 1 _SC_THREAD_ROBUST_PRIO_INHERIT _SC_THREAD_ROBUST_PRIO_INHERIT __DEC32_MAX_EXP__ 97 _GETOPT_CORE_H 1 __OFF_T_TYPE __SYSCALL_SLONG_TYPE __FLT32X_IS_IEC_60559__ 1 _POSIX_BARRIERS 200809L EISCONN 106 _SC_CHAR_BIT _SC_CHAR_BIT _LFS_ASYNCHRONOUS_IO 1 __glibc_macro_warning1(message) _Pragma (#message) __FLT128_EPSILON__ 1.92592994438723585305597794258492732e-34F128 __SIZEOF_INT128__ 16 _SC_IPV6 _SC_IPV6 __FLT128_IS_IEC_60559__ 1 __HAVE_FLOATN_NOT_TYPEDEF 1 __DBL_NORM_MAX__ ((double)1.79769313486231570814527423731704357e+308L) _SC_DEVICE_IO _SC_DEVICE_IO ELNRNG 48 _STATBUF_ST_BLKSIZE __SIZEOF_FLOAT128__ 16 __size_t__ __USE_XOPEN2K 1 _SC_LEVEL1_DCACHE_LINESIZE _SC_LEVEL1_DCACHE_LINESIZE _SC_LEVEL1_DCACHE_SIZE _SC_LEVEL1_DCACHE_SIZE __FLT64X_HAS_INFINITY__ 1 __attribute_used__ __attribute__ ((__used__)) __GLIBC_USE_C2X_STRTOL 0 __CHAR_BIT__ 8 __time_t_defined 1 be32toh(x) __bswap_32 (x) __bswap_constant_64(x) ((((x) & 0xff00000000000000ull) >> 56) | (((x) & 0x00ff000000000000ull) >> 40) | (((x) & 0x0000ff0000000000ull) >> 24) | (((x) & 0x000000ff00000000ull) >> 8) | (((x) & 0x00000000ff000000ull) << 8) | (((x) & 0x0000000000ff0000ull) << 24) | (((x) & 0x000000000000ff00ull) << 40) | (((x) & 0x00000000000000ffull) << 56)) EOF (-1) __GLIBC_USE_IEC_60559_TYPES_EXT 0 _XOPEN_REALTIME_THREADS 1 __stub___compat_bdflush __BFLT16_MIN_10_EXP__ (-37) _SC_TRACE_INHERIT _SC_TRACE_INHERIT _SC_2_C_DEV _SC_2_C_DEV _SC_C_LANG_SUPPORT_R _SC_C_LANG_SUPPORT_R __ONCE_FLAG_INIT { 0 } _SC_PRIORITY_SCHEDULING _SC_PRIORITY_SCHEDULING _FEATURES_H 1 __f64(x) x ##f64 __FLT64X_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951F64x _BSD_SIZE_T_ __va_arg_pack_len() __builtin_va_arg_pack_len () _SC_ASYNCHRONOUS_IO _SC_ASYNCHRONOUS_IO _SYS_POLL_H 1 __attribute_deprecated__ __attribute__ ((__deprecated__)) _POSIX_TRACE_LOG -1 _SC_MESSAGE_PASSING _SC_MESSAGE_PASSING _BITS_PTHREADTYPES_COMMON_H 1 _PC_REC_XFER_ALIGN _PC_REC_XFER_ALIGN __WCLONE 0x80000000 __off64_t _SC_2_SW_DEV _SC_2_SW_DEV _POSIX_JOB_CONTROL 1 _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS O_NOCTTY 0400 _CS_POSIX_V7_ILP32_OFF32_LDFLAGS _CS_POSIX_V7_ILP32_OFF32_LDFLAGS AT_SYMLINK_FOLLOW 0x400 __GCC_ATOMIC_POINTER_LOCK_FREE 2 FD_ZERO(fdsetp) __FD_ZERO (fdsetp) __S_TYPEISSHM(buf) ((buf)->st_mode - (buf)->st_mode) _IO_read_base WIFEXITED(status) __WIFEXITED (status) __OFF64_T_TYPE __SQUAD_TYPE _ASM_GENERIC_ERRNO_H __HAVE_FLOAT32X 1 _SC_XOPEN_LEGACY _SC_XOPEN_LEGACY POSIX_FADV_SEQUENTIAL 2 _PC_REC_MAX_XFER_SIZE _PC_REC_MAX_XFER_SIZE __fortified_attr_access(a,o,s) __attr_access ((a, o, s)) S_IXUSR __S_IEXEC __DEC64_MAX_EXP__ 385 _IO_buf_end __PRAGMA_REDEFINE_EXTNAME 1 O_RSYNC O_SYNC __UID_T_TYPE __U32_TYPE F_LOCK 1 __LDBL_HAS_DENORM__ 1 __LEAF , __leaf__ _CS_POSIX_V6_LP64_OFF64_LIBS _CS_POSIX_V6_LP64_OFF64_LIBS __REDIRECT_FORTIFY __REDIRECT __GCC_ATOMIC_INT_LOCK_FREE 2 __UINT32_C(c) c ## U _SC_TIMER_MAX _SC_TIMER_MAX AT_EACCESS 0x200 __INT_FAST32_MAX__ 0x7fffffffffffffffL F_SETOWN __F_SETOWN S_IFSOCK __S_IFSOCK _SC_NGROUPS_MAX _SC_NGROUPS_MAX psize EL2NSYNC 45 S_IRUSR __S_IREAD _SC_TRACE_USER_EVENT_MAX _SC_TRACE_USER_EVENT_MAX STDIN_FILENO 0 __REDIRECT_NTH_LDBL(name,proto,alias) __REDIRECT_NTH (name, proto, alias) _XOPEN_ENH_I18N 1 _POSIX_V7_LP64_OFF64 1 _SC_UCHAR_MAX _SC_UCHAR_MAX _IO_write_base _SC_READER_WRITER_LOCKS _SC_READER_WRITER_LOCKS _SC_2_C_VERSION _SC_2_C_VERSION __SSIZE_T_TYPE __SWORD_TYPE O_NONBLOCK 04000 __key_t_defined __f32(x) x ##f32 L_XTND SEEK_END ETIMEDOUT 110 __INO_T_TYPE __SYSCALL_ULONG_TYPE _SC_PII_OSI _SC_PII_OSI SEEK_CUR 1 htole16(x) __uint16_identity (x) __GID_T_TYPE __U32_TYPE __LONG_LONG_PAIR(HI,LO) LO, HI __INT_LEAST16_WIDTH__ 16 __S_IFIFO 0010000 __linux__ 1 ECONNREFUSED 111 _CS_XBS5_ILP32_OFFBIG_LINTFLAGS _CS_XBS5_ILP32_OFFBIG_LINTFLAGS _SC_LEVEL4_CACHE_ASSOC _SC_LEVEL4_CACHE_ASSOC __ptr_t void * FOPEN_MAX 16 __SLONG32_TYPE int O_TRUNC 01000 _POSIX2_C_DEV __POSIX2_THIS_VERSION __O_NOATIME 01000000 __STDC_HOSTED__ 1 __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD __INT_FAST32_TYPE__ long int __k8__ 1 __SIZEOF_FLOAT80__ 16 __USE_POSIX_IMPLICITLY 1 __INT_LEAST32_MAX__ 0x7fffffff __FLT32_MAX_EXP__ 128 __USE_ISOCXX11 _SC_THREAD_SAFE_FUNCTIONS _SC_THREAD_SAFE_FUNCTIONS _SC_OPEN_MAX _SC_OPEN_MAX _IO_ERR_SEEN 0x0020 __DBL_HAS_DENORM__ 1 __REGISTER_PREFIX__ __UINT32_MAX__ 0xffffffffU _PC_ALLOC_SIZE_MIN _PC_ALLOC_SIZE_MIN __FLT16_DECIMAL_DIG__ 5 _CS_XBS5_ILP32_OFFBIG_LIBS _CS_XBS5_ILP32_OFFBIG_LIBS __glibc_clang_prereq(maj,min) 0 __INTMAX_C(c) c ## L S_IWGRP (S_IWUSR >> 3) _SC_XOPEN_UNIX _SC_XOPEN_UNIX __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 _IO_marker _SC_FILE_ATTRIBUTES _SC_FILE_ATTRIBUTES __GNUC_STDC_INLINE__ 1 stdin stdin __FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32x ELIBACC 79 __SIZEOF_PTHREAD_RWLOCK_T 56 ECHRNG 44 __PMT(args) args _CS_POSIX_V7_ILP32_OFF32_CFLAGS _CS_POSIX_V7_ILP32_OFF32_CFLAGS _POSIX_TYPED_MEMORY_OBJECTS -1 __WCHAR_WIDTH__ 32 FOPEN_MAX __FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64 FNDELAY O_NDELAY _SC_THREAD_ATTR_STACKADDR _SC_THREAD_ATTR_STACKADDR _SC_THREAD_PRIO_PROTECT _SC_THREAD_PRIO_PROTECT _STRUCT_TIMESPEC 1 __STDC_IEC_60559_BFP__ 201404L EXIT_SUCCESS 0 _CS_GNU_LIBPTHREAD_VERSION _CS_GNU_LIBPTHREAD_VERSION EBFONT 59 __WCHAR_MAX__ 0x7fffffff _POSIX_THREAD_ATTR_STACKADDR 200809L F_TEST 3 __FLT32_HAS_DENORM__ 1 _SC_V7_LP64_OFF64 _SC_V7_LP64_OFF64 _SYS_CDEFS_H 1 __bos(ptr) __builtin_object_size (ptr, __USE_FORTIFY_LEVEL > 1) stdout stdout __SSP_STRONG__ 3 __SIZE_T __FSID_T_TYPE struct { int __val[2]; } _SYS_TYPES_H 1 __SHRT_WIDTH__ 16 _IO_codecvt _SC_2_PBS_TRACK _SC_2_PBS_TRACK __CFLOAT32 _Complex _Float32 __GCC_ATOMIC_SHORT_LOCK_FREE 2 F_GETFD 1 __ferror_unlocked_body(_fp) (((_fp)->_flags & _IO_ERR_SEEN) != 0) __F_SETOWN 8 __BLKCNT_T_TYPE __SYSCALL_SLONG_TYPE __GCC_ASM_FLAG_OUTPUTS__ 1 __BLKSIZE_T_TYPE __SYSCALL_SLONG_TYPE __SIZEOF_POINTER__ 8 __FLT128_NORM_MAX__ 1.18973149535723176508575932662800702e+4932F128 _FILE_OFFSET_BITS 64 _SC_LEVEL2_CACHE_LINESIZE _SC_LEVEL2_CACHE_LINESIZE _PC_REC_MIN_XFER_SIZE _PC_REC_MIN_XFER_SIZE _T_SIZE __FLT64X_MANT_DIG__ 64 __CFLOAT64 _Complex _Float64 __FD_ELT(d) ((d) / __NFDBITS) _CS_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVS _SC_NPROCESSORS_ONLN _SC_NPROCESSORS_ONLN __code_model_small__ 1 __USE_POSIX2 1 _POSIX_TRACE_INHERIT -1 __DEFINED_wchar_t __cookie_io_functions_t_defined 1 __flexarr [] __CFLOAT64X _Complex _Float64x __GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) __ASMNAME2(prefix,cname) __STRING (prefix) cname _BITS_TYPES_H 1 __FLT64_HAS_INFINITY__ 1 __GCC_DESTRUCTIVE_SIZE 64 POLLRDBAND 0x080 F_TLOCK 2 __REDIRECT(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __GLIBC_USE_IEC_60559_BFP_EXT_C2X 0 _SIGSET_NWORDS (1024 / (8 * sizeof (unsigned long int))) EBUSY 16 _T_WCHAR_ __GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE" S_ISGID __S_ISGID __STDC_VERSION__ 199901L _POSIX_C_SOURCE __POSIX2_THIS_VERSION 200809L _CS_POSIX_V6_ILP32_OFF32_LINTFLAGS _CS_POSIX_V6_ILP32_OFF32_LINTFLAGS RAND_MAX 2147483647 __BFLT16_EPSILON__ 7.81250000000000000000000000000000000e-3BF16 F_UNLCK 2 O_WRONLY 01 _SC_SCHAR_MIN _SC_SCHAR_MIN __GCC_ATOMIC_LLONG_LOCK_FREE 2 _CS_XBS5_LP64_OFF64_LDFLAGS _CS_XBS5_LP64_OFF64_LDFLAGS __INT_FAST32_WIDTH__ 64 _PC_ASYNC_IO _PC_ASYNC_IO _SC_BC_BASE_MAX _SC_BC_BASE_MAX _POSIX2_LOCALEDEF __POSIX2_THIS_VERSION _SC_2_PBS_MESSAGE _SC_2_PBS_MESSAGE __FLT_MAX__ 3.40282346638528859811704183484516925e+38F _POSIX_REALTIME_SIGNALS 200809L __LONG_LONG_WIDTH__ 64 _SC_2_C_BIND _SC_2_C_BIND _PC_REC_INCR_XFER_SIZE _PC_REC_INCR_XFER_SIZE _SC_SEM_VALUE_MAX _SC_SEM_VALUE_MAX __SIZEOF_PTHREAD_BARRIER_T 32 S_IFDIR __S_IFDIR _CS_LFS64_LIBS _CS_LFS64_LIBS __INO64_T_TYPE __UQUAD_TYPE __stub_sigreturn _SC_2_LOCALEDEF _SC_2_LOCALEDEF __HAVE_DISTINCT_FLOAT32 0 WIFSIGNALED(status) __WIFSIGNALED (status) __GLIBC_USE_IEC_60559_EXT __UINT_LEAST16_TYPE__ short unsigned int _SC_LOGIN_NAME_MAX _SC_LOGIN_NAME_MAX __LDBL_HAS_QUIET_NAN__ 1 O_CLOEXEC __O_CLOEXEC _SC_CHAR_MAX _SC_CHAR_MAX __NO_INLINE__ 1 __FLT64_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F64 __KEY_T_TYPE __S32_TYPE WUNTRACED 2 _IO_buf_base _XOPEN_XCU_VERSION 4 htole64(x) __uint64_identity (x) _POSIX_C_SOURCE 200809L __attribute_nonnull__(params) __attribute__ ((__nonnull__ params)) EDQUOT 122 GNU C99 13.3.0 -mtune=generic -march=x86-64 -ggdb3 -std=gnu99 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection EUNATCH 49 _SC_NL_SETMAX _SC_NL_SETMAX _CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGS __attribute_artificial__ __attribute__ ((__artificial__)) EISDIR 21 _POSIX_IPV6 200809L _SC_PIPE _SC_PIPE _CS_POSIX_V7_ILP32_OFF32_LINTFLAGS _CS_POSIX_V7_ILP32_OFF32_LINTFLAGS STDERR_FILENO 2 _POSIX_CLOCK_SELECTION 200809L __FSBLKCNT64_T_TYPE __UQUAD_TYPE _SIZE_T_DEFINED __LDBL_EPSILON__ 1.08420217248550443400745280086994171e-19L ENAMETOOLONG 36 AT_SYMLINK_NOFOLLOW 0x100 _SC_NZERO _SC_NZERO __INTPTR_WIDTH__ 64 __STD_TYPE _SC_CHAR_MIN _SC_CHAR_MIN __USE_FILE_OFFSET64 1 __CLOCKID_T_TYPE __S32_TYPE F_SETLKW64 7 WTERMSIG(status) __WTERMSIG (status) __SYSCALL_ULONG_TYPE __ULONGWORD_TYPE __ULONG32_TYPE unsigned int __HAVE_FLOAT32 1 _IO_FILE __INT_FAST64_TYPE__ long int __need_NULL F_GETOWN __F_GETOWN fdarray__add _IO_wide_data LOCK_UN 8 _POSIX_THREAD_PRIORITY_SCHEDULING 200809L __SIZEOF_LONG__ 8 __LDBL_MANT_DIG__ 64 S_IRWXU (__S_IREAD|__S_IWRITE|__S_IEXEC) _BITS_STDIO_LIM_H 1 ELIBMAX 82 __UINT_FAST64_TYPE__ long unsigned int _SC_MEMLOCK_RANGE _SC_MEMLOCK_RANGE NULL ((void *)0) __ORDER_BIG_ENDIAN__ 4321 __gnu_linux__ 1 _SC_C_LANG_SUPPORT _SC_C_LANG_SUPPORT __PTHREAD_RWLOCK_INITIALIZER(__flags) 0, 0, 0, 0, 0, 0, 0, 0, __PTHREAD_RWLOCK_ELISION_EXTRA, 0, __flags __S_IREAD 0400 _CS_POSIX_V6_ILP32_OFF32_LDFLAGS _CS_POSIX_V6_ILP32_OFF32_LDFLAGS __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 __FLT64X_HAS_DENORM__ 1 _SC_MONOTONIC_CLOCK _SC_MONOTONIC_CLOCK _BITS_ERRNO_H 1 _SC_LONG_BIT _SC_LONG_BIT __SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1) _SC_EXPR_NEST_MAX _SC_EXPR_NEST_MAX __attr_dealloc(dealloc,argno) __attribute__ ((__malloc__ (dealloc, argno))) _SC_THREAD_PRIO_INHERIT _SC_THREAD_PRIO_INHERIT _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS __STDC_IEC_559_COMPLEX__ 1 _SC_STREAM_MAX _SC_STREAM_MAX __sigset_t_defined 1 __INT_LEAST8_TYPE__ signed char _CS_XBS5_ILP32_OFFBIG_CFLAGS _CS_XBS5_ILP32_OFFBIG_CFLAGS __LDBL_REDIR_NTH(name,proto) name proto __THROW __extern_inline extern __inline __attribute__ ((__gnu_inline__)) __need_wchar_t __FLT_DECIMAL_DIG__ 9 O_NDELAY O_NONBLOCK __glibc_has_builtin(name) __has_builtin (name) EOVERFLOW 75 _SC_TRACE_EVENT_NAME_MAX _SC_TRACE_EVENT_NAME_MAX ENOANO 55 __GLIBC_USE_IEC_60559_BFP_EXT 0 ENOTTY 25 EOWNERDEAD 130 __linux 1 _XOPEN_LEGACY 1 __GLIBC_PREREQ(maj,min) ((__GLIBC__ << 16) + __GLIBC_MINOR__ >= ((maj) << 16) + (min)) EXFULL 54 __FLT128_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F128 __FINITE_MATH_ONLY__ 0 __attribute_returns_twice__ __attribute__ ((__returns_twice__)) __HAVE_DISTINCT_FLOAT64X 0 __pad5 __id_t_defined EUCLEAN 117 _CS_POSIX_V7_LP64_OFF64_LDFLAGS _CS_POSIX_V7_LP64_OFF64_LDFLAGS _SC_FIFO _SC_FIFO _RWLOCK_INTERNAL_H __W_EXITCODE(ret,sig) ((ret) << 8 | (sig)) EADDRINUSE 98 __FLT32X_MIN__ 2.22507385850720138309023271733240406e-308F32x _SC_2_CHAR_TERM _SC_2_CHAR_TERM __INT_LEAST64_MAX__ 0x7fffffffffffffffL EAGAIN 11 _SC_SHELL _SC_SHELL __PTHREAD_MUTEX_INITIALIZER(__kind) 0, 0, 0, 0, __kind, 0, 0, { 0, 0 } _STDC_PREDEF_H 1 _SC_USER_GROUPS _SC_USER_GROUPS EFAULT 14 __daddr_t_defined __extern_always_inline extern __always_inline __attribute__ ((__gnu_inline__)) EL3RST 47 _XOPEN_REALTIME 1 _SC_XOPEN_ENH_I18N _SC_XOPEN_ENH_I18N __BFLT16_DIG__ 2 __WALL 0x40000000 __INT32_TYPE__ int _SC_USER_GROUPS_R _SC_USER_GROUPS_R __S_IFCHR 0020000 __bos0(ptr) __builtin_object_size (ptr, 0) __FLT64X_DECIMAL_DIG__ 21 __BYTE_ORDER __LITTLE_ENDIAN be16toh(x) __bswap_16 (x) _CS_V7_ENV _CS_V7_ENV __GLIBC_USE_DEPRECATED_GETS __FLT64_DIG__ 15 _SC_ULONG_MAX _SC_ULONG_MAX __GCC_ATOMIC_BOOL_LOCK_FREE 2 __DEC64_MAX__ 9.999999999999999E384DD _POSIX_MONOTONIC_CLOCK 0 _SC_TRACE_NAME_MAX _SC_TRACE_NAME_MAX __SIZEOF_PTHREAD_MUTEX_T 40 __USE_FILE_OFFSET64 __W_CONTINUED 0xffff __DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L) F_SETLK64 6 __ILP32_OFFBIG_LDFLAGS "-m32" stderr stderr _SC_IOV_MAX _SC_IOV_MAX _SC_SHARED_MEMORY_OBJECTS _SC_SHARED_MEMORY_OBJECTS _SC_DEVICE_SPECIFIC_R _SC_DEVICE_SPECIFIC_R _SC_THREAD_STACK_MIN _SC_THREAD_STACK_MIN EKEYEXPIRED 127 __FLT16_HAS_INFINITY__ 1 htole32(x) __uint32_identity (x) _SC_THREAD_ATTR_STACKSIZE _SC_THREAD_ATTR_STACKSIZE entry_destructor __BLKCNT64_T_TYPE __SQUAD_TYPE L_INCR SEEK_CUR __PDP_ENDIAN 3412 _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS __GCC_CONSTRUCTIVE_SIZE 64 __WIFEXITED(status) (__WTERMSIG(status) == 0) __SIZEOF_DOUBLE__ 8 __FLOAT_WORD_ORDER __BYTE_ORDER __LP64_OFF64_CFLAGS "-m64" __POSIX_FADV_NOREUSE 5 __SUSECONDS64_T_TYPE __SQUAD_TYPE _ATFILE_SOURCE 1 FD_CLOEXEC 1 __FLT128_MAX_EXP__ 16384 __FLT32_MIN__ 1.17549435082228750796873653722224568e-38F32 _BSD_WCHAR_T_ __attr_dealloc_fclose __attr_dealloc (fclose, 1) __lldiv_t_defined 1 __attribute_noinline__ __attribute__ ((__noinline__)) _SC_V6_ILP32_OFF32 _SC_V6_ILP32_OFF32 _SC_TIMEOUTS _SC_TIMEOUTS __BFLT16_MAX_EXP__ 128 S_IFCHR __S_IFCHR __S_TYPEISMQ(buf) ((buf)->st_mode - (buf)->st_mode) EROFS 30 ENOTRECOVERABLE 131 _PC_LINK_MAX _PC_LINK_MAX __USE_GNU __FLT64_NORM_MAX__ 1.79769313486231570814527423731704357e+308F64 __WIFSTOPPED(status) (((status) & 0xff) == 0x7f) __USE_POSIX2 __ino64_t_defined errno (*__errno_location ()) EUSERS 87 _SC_2_UPE _SC_2_UPE S_IRWXG (S_IRWXU >> 3) _SC_MQ_OPEN_MAX _SC_MQ_OPEN_MAX EDOTDOT 73 POLLNVAL 0x020 EREMCHG 78 _SC_XBS5_LP64_OFF64 _SC_XBS5_LP64_OFF64 _SC_RAW_SOCKETS _SC_RAW_SOCKETS _SC_CLOCK_SELECTION _SC_CLOCK_SELECTION _SC_AIO_MAX _SC_AIO_MAX EOPNOTSUPP 95 __S_ISGID 02000 __need_wchar_t __USE_XOPEN2KXSI POLLRDNORM 0x040 __S_ISUID 04000 __O_DSYNC 010000 __blkcnt_t_defined __ATOMIC_ACQ_REL 4 _SC_MEMORY_PROTECTION _SC_MEMORY_PROTECTION __WNOTHREAD 0x20000000 _T_WCHAR _SIZET_ __INT8_TYPE__ signed char __SSE2_MATH__ 1 EFBIG 27 __MMX__ 1 __CPU_MASK_TYPE __SYSCALL_ULONG_TYPE X_OK 1 __TIME64_T_TYPE __TIME_T_TYPE _IOLBF 1 __ILP32_OFF32_LDFLAGS "-m32" ENOCSI 50 ENOLINK 67 _SC_LEVEL4_CACHE_SIZE _SC_LEVEL4_CACHE_SIZE __FLT64_MIN_EXP__ (-1021) __F_SETOWN_EX 15 __off64_t_defined __STATFS_MATCHES_STATFS64 1 __SIZEOF_PTHREAD_ATTR_T 56 _ALLOCA_H 1 _SC_PASS_MAX _SC_PASS_MAX EBADSLT 57 _____fpos_t_defined 1 __FXSR__ 1 __INT_FAST8_TYPE__ signed char __USE_POSIX199309 _POSIX_TRACE_EVENT_FILTER -1 EPROTOTYPE 91 _SC_PII_INTERNET_STREAM _SC_PII_INTERNET_STREAM __FLT32X_MIN_EXP__ (-1021) _CS_POSIX_V7_ILP32_OFF32_LIBS _CS_POSIX_V7_ILP32_OFF32_LIBS __WCHAR_T _PC_NAME_MAX _PC_NAME_MAX _GETOPT_POSIX_H 1 __F_GETOWN_EX 16 __u_char_defined _POSIX_REENTRANT_FUNCTIONS 1 _freeres_buf __ATOMIC_HLE_ACQUIRE 65536 __DEC64_MIN__ 1E-383DD __INT16_C(c) c __FD_MASK(d) ((__fd_mask) (1UL << ((d) % __NFDBITS))) __WINT_TYPE__ unsigned int __INT_FAST8_MAX__ 0x7f __HAVE_DISTINCT_FLOAT32X 0 __GLIBC_USE_ISOC2X 0 _SC_2_VERSION _SC_2_VERSION __FLT128_HAS_INFINITY__ 1 _POSIX_THREAD_ROBUST_PRIO_PROTECT -1 __SIZEOF_SHORT__ 2 __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 1 __UINT_FAST16_TYPE__ long unsigned int _cur_column __LONG_WIDTH__ 64 _SC_LEVEL3_CACHE_SIZE _SC_LEVEL3_CACHE_SIZE S_IFIFO __S_IFIFO __UINT8_MAX__ 0xff _SC_CHILD_MAX _SC_CHILD_MAX __HAVE_FLOAT128 1 EREMOTEIO 121 __DECIMAL_BID_FORMAT__ 1 _SC_LEVEL3_CACHE_LINESIZE _SC_LEVEL3_CACHE_LINESIZE __GLIBC_USE_IEC_60559_FUNCS_EXT 0 _SC_TZNAME_MAX _SC_TZNAME_MAX __UINT_FAST8_MAX__ 0xff __FLT64_EPSILON__ 2.22044604925031308084726333618164062e-16F64 __FLT64_MAX_EXP__ 1024 __BEGIN_DECLS _SC_SPAWN _SC_SPAWN __restrict_arr __restrict _SC_UINT_MAX _SC_UINT_MAX _CS_POSIX_V7_LP64_OFF64_CFLAGS _CS_POSIX_V7_LP64_OFF64_CFLAGS __O_DIRECT 040000 ECOMM 70 _BITS_FLOATN_H __FLT64_DECIMAL_DIG__ 17 _POSIX_NO_TRUNC 1 nfds_t ENAVAIL 119 __USE_POSIX199506 1 fdarray_flag__non_perf_event __HAVE_FLOAT64X_LONG_DOUBLE 1 _SC_UIO_MAXIOV _SC_UIO_MAXIOV __FLT32_EPSILON__ 1.19209289550781250000000000000000000e-7F32 __UINT64_C(c) c ## UL __SIZEOF_PTHREAD_BARRIERATTR_T 4 __ATOMIC_CONSUME 1 __attribute_copy__ __stub_revoke _SC_XBS5_ILP32_OFFBIG _SC_XBS5_ILP32_OFFBIG __glibc_unlikely(cond) __builtin_expect ((cond), 0) EIO 5 _SC_FILE_LOCKING _SC_FILE_LOCKING __WTERMSIG(status) ((status) & 0x7f) EINPROGRESS 115 _CS_LFS64_LDFLAGS _CS_LFS64_LDFLAGS __BFLT16_MANT_DIG__ 8 _IO_backup_base __USE_XOPEN2K8 1 __RLIM64_T_TYPE __UQUAD_TYPE _POSIX_TRACE -1 __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 _SC_CPUTIME _SC_CPUTIME _IO_read_ptr fdarray_flag__default __INT_LEAST32_TYPE__ int BUFSIZ 8192 EMLINK 31 __SIZEOF_PTRDIFF_T__ 8 POLLPRI 0x002 _PC_PRIO_IO _PC_PRIO_IO _POSIX_REGEXP 1 _FORTIFY_SOURCE WIFCONTINUED(status) __WIFCONTINUED (status) O_CREAT 0100 _STRINGS_H 1 _SC_V6_LPBIG_OFFBIG _SC_V6_LPBIG_OFFBIG STDOUT_FILENO 1 __ssize_t_defined __FLT32X_HAS_QUIET_NAN__ 1 _SC_SSIZE_MAX _SC_SSIZE_MAX __FLT16_DIG__ 3 __GNUC_EXECUTION_CHARSET_NAME "UTF-8" _ATFILE_SOURCE EHWPOISON 133 _freeres_list __attr_dealloc_fclose __attr_dealloc_free __attr_dealloc (__builtin_free, 1) __SIG_ATOMIC_WIDTH__ 32 __DBL_MIN_EXP__ (-1021) __GLIBC_USE_DEPRECATED_SCANF 0 FD_ISSET(fd,fdsetp) __FD_ISSET (fd, fdsetp) ENOTBLK 15 _SC_SAVED_IDS _SC_SAVED_IDS __WCOREFLAG 0x80 __GLIBC_USE_IEC_60559_FUNCS_EXT_C2X __HAVE_DISTINCT_FLOAT128X __HAVE_FLOAT128X FNONBLOCK O_NONBLOCK _SC_LEVEL2_CACHE_SIZE _SC_LEVEL2_CACHE_SIZE S_IWUSR __S_IWRITE __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 __attribute_alloc_size__(params) __attribute__ ((__alloc_size__ params)) _SC_SEMAPHORES _SC_SEMAPHORES _POSIX_SHARED_MEMORY_OBJECTS 200809L _POSIX_SOURCE 1 _SC_FD_MGMT _SC_FD_MGMT ENOSPC 28 _BITS_PTHREADTYPES_ARCH_H 1 __S_IWRITE 0200 _POSIX_ADVISORY_INFO 200809L alloca(size) __builtin_alloca (size) __DEC32_MAX__ 9.999999E96DF _SC_SS_REPL_MAX _SC_SS_REPL_MAX _old_offset __F_GETOWN 9 __FLT128_HAS_QUIET_NAN__ 1 _POSIX_THREAD_PRIO_PROTECT 200809L __attribute_nonstring__ __attribute__ ((__nonstring__)) __TIMER_T_TYPE void * st_atime st_atim.tv_sec ENOTDIR 20 ELOOP 40 __FLT32X_HAS_DENORM__ 1 __COLD __attribute__ ((__cold__)) htobe16(x) __bswap_16 (x) __FLT32_HAS_QUIET_NAN__ 1 __GNU_LIBRARY__ 6 NFDBITS __NFDBITS ENONET 64 __FSFILCNT64_T_TYPE __UQUAD_TYPE _SC_V6_LP64_OFF64 _SC_V6_LP64_OFF64 _CS_LFS_CFLAGS _CS_LFS_CFLAGS _flags2 _SC_2_PBS _SC_2_PBS _SC_GETPW_R_SIZE_MAX _SC_GETPW_R_SIZE_MAX EXIT_FAILURE 1 EHOSTDOWN 112 WEXITSTATUS(status) __WEXITSTATUS (status) __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL _SC_XOPEN_REALTIME_THREADS _SC_XOPEN_REALTIME_THREADS _CS_LFS64_LINTFLAGS _CS_LFS64_LINTFLAGS _SC_THREAD_SPORADIC_SERVER _SC_THREAD_SPORADIC_SERVER printed __FLT16_MIN_EXP__ (-13) _POSIX_CPUTIME 0 __feof_unlocked_body(_fp) (((_fp)->_flags & _IO_EOF_SEEN) != 0) __DEFINED_size_t _CS_XBS5_LPBIG_OFFBIG_LIBS _CS_XBS5_LPBIG_OFFBIG_LIBS ELIBBAD 80 _SC_PHYS_PAGES _SC_PHYS_PAGES __PTHREAD_MUTEX_HAVE_PREV 1 S_IFREG __S_IFREG __WSTOPSIG(status) __WEXITSTATUS(status) _SC_INT_MIN _SC_INT_MIN __attribute_deprecated_msg__(msg) __attribute__ ((__deprecated__ (msg))) EBADMSG 74 __DBL_MAX__ ((double)1.79769313486231570814527423731704357e+308L) EINTR 4 ENOPKG 65 __PMT __FSBLKCNT_T_TYPE __SYSCALL_ULONG_TYPE __SSE__ 1 __DBL_HAS_QUIET_NAN__ 1 __DEC32_MANT_DIG__ 7 __USE_ATFILE _SC_MINSIGSTKSZ _SC_MINSIGSTKSZ __FLT_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F ESRMNT 69 EKEYREJECTED 129 st_mtime st_mtim.tv_sec __FLT32X_MIN_10_EXP__ (-307) _SC_AVPHYS_PAGES _SC_AVPHYS_PAGES __PTHREAD_RWLOCK_ELISION_EXTRA 0, { 0, 0, 0, 0, 0, 0, 0 } __unix 1 __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI 0 __GLIBC_USE_IEC_60559_BFP_EXT_C2X __LDBL_HAS_INFINITY__ 1 _CS_LFS64_CFLAGS _CS_LFS64_CFLAGS _SC_MEMLOCK _SC_MEMLOCK ENOENT 2 __attribute_format_strfmon__(a,b) __attribute__ ((__format__ (__strfmon__, a, b))) __S_IEXEC 0100 _IOFBF 0 __FLT16_MIN__ 6.10351562500000000000000000000000000e-5F16 __GLIBC_USE_ISOC2X __GLIBC_USE_IEC_60559_EXT 0 ECANCELED 125 __FLT_NORM_MAX__ 3.40282346638528859811704183484516925e+38F _SC_2_FORT_RUN _SC_2_FORT_RUN __CLOCK_T_TYPE __SYSCALL_SLONG_TYPE __FLT64X_MIN_EXP__ (-16381) _CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS _CS_XBS5_ILP32_OFF32_LINTFLAGS _CS_XBS5_ILP32_OFF32_LINTFLAGS __SIZEOF_LONG_DOUBLE__ 16 _PC_MAX_INPUT _PC_MAX_INPUT __INT_FAST16_TYPE__ long int _BITS_TYPES_LOCALE_T_H 1 fdarray__init __FSFILCNT_T_TYPE __SYSCALL_ULONG_TYPE BUILD_STR(s) #s __S_IFSOCK 0140000 __FLT64_HAS_DENORM__ 1 _POSIX_READER_WRITER_LOCKS 200809L __FLT128_DECIMAL_DIG__ 36 __FLT_HAS_DENORM__ 1 _PC_VDISABLE _PC_VDISABLE _markers SEEK_END 2 __PID_T_TYPE __S32_TYPE _XBS5_LP64_OFF64 1 _POSIX_V7_LPBIG_OFFBIG -1 FASYNC O_ASYNC __O_NOFOLLOW 0400000 _SC_FSYNC _SC_FSYNC ____FILE_defined 1 __LDBL_MAX__ 1.18973149535723176502126385303097021e+4932L __SIZEOF_FLOAT__ 4 _CS_LFS_LIBS _CS_LFS_LIBS EPIPE 32 __DEC128_EPSILON__ 1E-33DL __SIZE_T__ _SC_PII_OSI_COTS _SC_PII_OSI_COTS _POSIX_PRIORITIZED_IO 200809L __UINT_LEAST8_TYPE__ unsigned char __NLINK_T_TYPE __SYSCALL_ULONG_TYPE __STDC_ISO_10646__ 201706L __LDBL_MIN_10_EXP__ (-4931) F_EXLCK 4 __warnattr(msg) __attribute__((__warning__ (msg))) __STRING(x) #x LOCK_EX 2 _SC_XOPEN_STREAMS _SC_XOPEN_STREAMS __CHAR16_TYPE__ short unsigned int _POSIX_THREAD_ATTR_STACKSIZE 200809L EALREADY 114 fdarray le64toh(x) __uint64_identity (x) ENODATA 61 _SC_SHRT_MAX _SC_SHRT_MAX _CS_XBS5_LPBIG_OFFBIG_CFLAGS _CS_XBS5_LPBIG_OFFBIG_CFLAGS __attribute_const__ __attribute__ ((__const__)) __S_IFMT 0170000 __GLIBC_USE_IEC_60559_FUNCS_EXT_C2X 0 __returns_nonnull __attribute__ ((__returns_nonnull__)) __FLT_MIN__ 1.17549435082228750796873653722224568e-38F __SYSCALL_SLONG_TYPE __SLONGWORD_TYPE __LDBL_REDIR2_DECL(name) __SIZE_TYPE__ long unsigned int __LDBL_MAX_EXP__ 16384 _POSIX_THREAD_SPORADIC_SERVER -1 F_GETLK F_GETLK64 __MMX_WITH_SSE__ 1 __S16_TYPE short int __GNUC_MINOR__ 3 _SC_THREAD_PROCESS_SHARED _SC_THREAD_PROCESS_SHARED __STDC_UTF_16__ 1 fdarray__exit __INT_FAST64_WIDTH__ 64 _LP64 1 _vtable_offset __S64_TYPE long int FD_SETSIZE __FD_SETSIZE __UINT_FAST32_MAX__ 0xffffffffffffffffUL __O_DIRECTORY 0200000 npos _SC_SYNCHRONIZED_IO _SC_SYNCHRONIZED_IO fdarray__new __INT_FAST8_WIDTH__ 8 __UINTMAX_C(c) c ## UL __PTRDIFF_TYPE__ long int EHOSTUNREACH 113 _CS_XBS5_ILP32_OFFBIG_LDFLAGS _CS_XBS5_ILP32_OFFBIG_LDFLAGS __UINT_LEAST8_MAX__ 0xff __FLT32_NORM_MAX__ 3.40282346638528859811704183484516925e+38F32 __USE_ISOC95 1 ESTALE 116 _SC_USHRT_MAX _SC_USHRT_MAX __INT64_C(c) c ## L EACCES 13 __GLIBC_MINOR__ 39 nr_autogrow __GLIBC_USE_LIB_EXT2 _FCNTL_H 1 __DBL_DIG__ 15 ENOMSG 42 TIOCM_RTS 0x004 SIOCSIFNETMASK 0x891c MS_RMT_MASK (MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK|MS_I_VERSION| MS_LAZYTIME) __CPU_SET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] |= __CPUMASK (__cpu)) : 0; })) f_ffree __align N_PROFIBUS_FDL 10 TIOCM_CD TIOCM_CAR _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) __pthread_mutex_s SHRT_MAX __SHRT_MAX__ sysfs__read_str TCSETX 0x5433 INT_LEAST8_MAX (127) STATMOUNT_MNT_ROOT 0x00000008U MOVE_MOUNT_F_AUTOMOUNTS 0x00000002 MS_RDONLY 1 TIOCSLCKTRMIOS 0x5457 __isprint_l(c,l) __isctype_l((c), _ISprint, (l)) TIOCPKT_START 8 FSPICK_SYMLINK_NOFOLLOW 0x00000002 PTHREAD_MUTEX_NORMAL _POSIX_THREAD_KEYS_MAX 128 _POSIX_THREAD_DESTRUCTOR_ITERATIONS 4 __sched_priority sched_priority TIOCGSOFTCAR 0x5419 _BITS_POSIX1_LIM_H 1 XATTR_SIZE_MAX 65536 UCHAR_MAX (SCHAR_MAX * 2 + 1) _BITS_POSIX2_LIM_H 1 ispunct(c) __isctype((c), _ISpunct) _LINUX_LIMITS_H __CPU_SETSIZE 1024 CLOCK_REALTIME_COARSE 5 __BITS_PER_LONG 64 N_SLIP 1 NCC 8 TIMER_ABSTIME 1 N_R3964 9 isalnum_l(c,l) __isalnum_l ((c), (l)) MOUNT_ATTR_NOSUID 0x00000002 fs__check_mounts _POSIX2_LINE_MAX 2048 _GCC_NEXT_LIMITS_H MS_SILENT 32768 MS_RDONLY MS_RDONLY CWERASE CTRL('w') MOUNT_ATTR_RDONLY 0x00000001 _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) PIPE_BUF 4096 _POSIX2_BC_BASE_MAX 99 _STDBOOL_H SCHAR_MAX __SCHAR_MAX__ UINT_MAX (INT_MAX * 2U + 1U) SIOCSIFMEM 0x8920 MNT_FORCE MNT_FORCE SIOCGIFENCAP 0x8925 MS_RMT_MASK _POSIX_TIMER_MAX 32 N_HCI 15 __CPU_ZERO_S(setsize,cpusetp) do __builtin_memset (cpusetp, '\0', setsize); while (0) INT_MIN (-INT_MAX - 1) fs__hugetlbfs MS_KERNMOUNT MS_KERNMOUNT __isupper_l(c,l) __isctype_l((c), _ISupper, (l)) PTHREAD_KEYS_MAX 1024 __isctype(c,type) ((*__ctype_b_loc ())[(int) (c)] & (unsigned short int) type) SIOCGIFMTU 0x8921 INT_LEAST16_MIN (-32767-1) _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) sysfs__read_ull BLKRASET _IO(0x12, 98) FSOPEN_CLOEXEC 0x00000001 __fsid_t INT32_MIN (-2147483647-1) TIOCGSERIAL 0x541E UINT64_MAX (__UINT64_C(18446744073709551615)) __user WCHAR_MIN __WCHAR_MIN MS_ACTIVE (1<<30) MS_REMOUNT MS_REMOUNT bpf_fs_init_once procfs__mount _BITS_TYPES_STRUCT_SCHED_PARAM 1 BLKSECTGET __ASM_GENERIC_POSIX_TYPES_H LLONG_MIN (-LLONG_MAX-1) _POSIX_STREAM_MAX 8 MNT_ID_REQ_SIZE_VER0 24 INT16_MAX (32767) _POSIX_ARG_MAX 4096 MS_UNBINDABLE (1<<17) __ispunct_l(c,l) __isctype_l((c), _ISpunct, (l)) _POSIX2_EXPR_NEST_MAX 32 BLKFLSBUF _IO(0x12, 97) _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) PTHREAD_MUTEX_TIMED_NP XATTR_NAME_MAX 255 TIOCSERSETMULTI 0x545B f_frsize CLNEXT CTRL('v') _T_PTRDIFF_ MS_LAZYTIME MS_LAZYTIME SIOCSIFMTU 0x8922 _SYS_MOUNT_H 1 ACCESSPERMS (S_IRWXU|S_IRWXG|S_IRWXO) SIOCDARP 0x8953 UINT_FAST8_MAX (255) _POSIX_THREAD_THREADS_MAX 64 SEM_VALUE_MAX (2147483647) filename__read_xll _POSIX_PATH_MAX 256 SIOCGIFBR 0x8940 SIOCSIFSLAVE 0x8930 _IOC_NRSHIFT 0 _POSIX_LINK_MAX 8 MS_NOEXEC MS_NOEXEC N_SYNC_PPP 14 INT_FAST64_MAX (__INT64_C(9223372036854775807)) LINK_MAX 127 TIOCM_CAR 0x040 pthread_once FSPICK_EMPTY_PATH 0x00000008 PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS MS_REC MS_REC sysctl BLKSECTSET MS_NOATIME MS_NOATIME _GCC_NEXT_LIMITS_H CSUSP CTRL('z') BLKBSZSET _IOW(0x12,113,size_t) __owner LLONG_MIN (-LLONG_MAX - 1LL) __isspace_l(c,l) __isctype_l((c), _ISspace, (l)) __isxdigit_l(c,l) __isctype_l((c), _ISxdigit, (l)) st_fs tracefs__configured filename__write_int S_ISCHR(mode) __S_ISTYPE((mode), __S_IFCHR) _SYS_TTYDEFAULTS_H_ BLOCK_SIZE_BITS 10 SCHED_RR 2 __struct_tm_defined 1 TIOCSCTTY 0x540E SIOCSIFNAME 0x8923 _POSIX_NAME_MAX 14 STATMOUNT_MNT_BASIC 0x00000002U _ISbit(bit) ((bit) < 8 ? ((1 << (bit)) << 8) : ((1 << (bit)) >> 8)) _IOC_TYPECHECK(t) (sizeof(t)) __CPUMASK(cpu) ((__cpu_mask) 1 << ((cpu) % __NCPUBITS)) CDISCARD CTRL('o') __lock sysfs__mountpoint MS_MANDLOCK MS_MANDLOCK UINT_FAST32_MAX (18446744073709551615UL) COLL_WEIGHTS_MAX 255 offsetof __undef_OPEN_MAX PTHREAD_MUTEX_DEFAULT __pthread_list_t fopen SIOCSIFBR 0x8941 MS_NOSYMFOLLOW MS_NOSYMFOLLOW __fsfilcnt64_t procfs_init_once strdup _POSIX2_BC_STRING_MAX 1000 TIOCCBRK 0x5428 TIOCSERCONFIG 0x5453 TIOCGEXCL _IOR('T', 0x40, int) BLKRRPART BPF_FS_MAGIC 0xcafe4a11 _SYS_STATFS_H 1 ULLONG_MAX __WCHAR_MAX __WCHAR_MAX__ TIOCSSERIAL 0x541F MOVE_MOUNT_T_SYMLINKS 0x00000010 _IOC_DIRBITS 2 isprint(c) __isctype((c), _ISprint) MS_NODIRATIME 2048 __toascii(c) ((c) & 0x7f) sysctl__read_int BLKROSET SIOCSIFMAP 0x8971 DEBUGFS_MAGIC 0x64626720 CQUIT 034 CLOCK_BOOTTIME 7 __API_DEBUG_H__ MS_ACTIVE MS_ACTIVE _IOC_SIZEBITS 14 strlen SIOCDELMULTI 0x8932 _GCC_PTRDIFF_T __S_ISTYPE(mode,mask) (((mode) & __S_IFMT) == (mask)) _POSIX_NGROUPS_MAX 8 UINT_FAST16_MAX (18446744073709551615UL) XATTR_LIST_MAX 65536 MS_SYNCHRONOUS MS_SYNCHRONOUS MS_LAZYTIME (1<<25) RE_DUP_MAX (0x7fff) CHAR_BIT __CHAR_BIT__ false 0 timeout_ms CLOCK_REALTIME 0 PTHREAD_MUTEX_INITIALIZER { { __PTHREAD_MUTEX_INITIALIZER (PTHREAD_MUTEX_TIMED_NP) } } FIONBIO 0x5421 SIOCSIFBRDADDR 0x891a temp TIOCPKT_NOSTOP 16 BLKGETSIZE64 _IOR(0x12,114,size_t) BLKGETSIZE64 pr_warn(fmt,...) __pr(__pr_warn, fmt, ##__VA_ARGS__) FSPICK_NO_AUTOMOUNT 0x00000004 TIOCMBIC 0x5417 MS_STRICTATIME (1<<24) TIOCGSID 0x5429 __isdigit_l(c,l) __isctype_l((c), _ISdigit, (l)) isblank_l(c,l) __isblank_l ((c), (l)) INT_FAST8_MIN (-128) hugetlbfs__configured SIOCSIFPFLAGS 0x8934 CLOCK_PROCESS_CPUTIME_ID 2 _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) __isblank_l(c,l) __isctype_l((c), _ISblank, (l)) PTHREAD_CANCEL_ASYNCHRONOUS PTHREAD_CANCEL_ASYNCHRONOUS _BITS_STDINT_UINTN_H 1 INT_FAST16_MIN (-9223372036854775807L-1) MS_SLAVE (1<<19) ALLPERMS (S_ISUID|S_ISGID|S_ISVTX|S_IRWXU|S_IRWXG|S_IRWXO) ARG_MAX 131072 CREPRINT CTRL('r') CRPRNT CREPRINT _PTRDIFF_T_DECLARED pthread_mutex_t MS_SHARED (1<<20) TCSETSF2 _IOW('T', 0x2D, struct termios2) _LINUX_IOCTL_H __API_FS__ N_PPP 3 _IOC_NONE 0U pthread_mutex_lock PTHREAD_CANCEL_ENABLE PTHREAD_CANCEL_ENABLE SIOCDELRT 0x890C TTYDEF_SPEED (B9600) iscntrl_l(c,l) __iscntrl_l ((c), (l)) TIOCPKT_STOP 4 __API_IO__ SIOCGIFBRDADDR 0x8919 TIOCSERGWILD 0x5454 SHRT_MIN (-SHRT_MAX - 1) STATMOUNT_PROPAGATE_FROM 0x00000004U SIOCDIFADDR 0x8936 _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) BC_BASE_MAX _POSIX2_BC_BASE_MAX SIOCSIFENCAP 0x8926 HOST_NAME_MAX 64 PTHREAD_EXPLICIT_SCHED PTHREAD_EXPLICIT_SCHED _SYS_IOCTL_H 1 UINT_LEAST8_MAX (255) procfs__mountpoint FS(lower_name,fs_name,upper_name) static struct fs fs__ ##lower_name = { .name = #fs_name, .mounts = lower_name ##__known_mountpoints, .magic = upper_name ##_MAGIC, .mount_mutex = PTHREAD_MUTEX_INITIALIZER, }; static void lower_name ##_init_once(void) { struct fs *fs = &fs__ ##lower_name; fs__init_once(fs); } const char *lower_name ##__mountpoint(void) { static pthread_once_t init_once = PTHREAD_ONCE_INIT; struct fs *fs = &fs__ ##lower_name; pthread_once(&init_once, lower_name ##_init_once); return fs__mountpoint(fs); } const char *lower_name ##__mount(void) { const char *mountpoint = lower_name ##__mountpoint(); struct fs *fs = &fs__ ##lower_name; if (mountpoint) return mountpoint; return fs__mount(fs); } bool lower_name ##__configured(void) { return lower_name ##__mountpoint() != NULL; } __kind PTHREAD_SCOPE_PROCESS PTHREAD_SCOPE_PROCESS TCSETSW2 _IOW('T', 0x2C, struct termios2) MS_NOEXEC 8 __ASM_GENERIC_IOCTLS_H MOUNT_ATTR_NOATIME 0x00000010 CEOL _POSIX_VDISABLE TIOCSWINSZ 0x5414 AIO_PRIO_DELTA_MAX 20 INT_LEAST32_MAX (2147483647) TIOCGPKT _IOR('T', 0x38, int) _POSIX_CHILD_MAX 25 TTYDEF_IFLAG (BRKINT | ISTRIP | ICRNL | IMAXBEL | IXON | IXANY) _toupper(c) ((int) (*__ctype_toupper_loc ())[(int) (c)]) __cold TIOCPKT_DATA 0 fs__procfs S_TYPEISSEM(buf) __S_TYPEISSEM(buf) UINT_FAST64_MAX (__UINT64_C(18446744073709551615)) STR(x) _STR(x) INT_FAST8_MAX (127) INT64_MAX (__INT64_C(9223372036854775807)) INTPTR_MIN (-9223372036854775807L-1) HUGETLBFS_MAGIC 0x958458f6 sysfs__write_int MS_I_VERSION (1<<23) TIOCGETD 0x5424 isxdigit_l(c,l) __isxdigit_l ((c), (l)) CLOCKS_PER_SEC ((__clock_t) 1000000) TIOCOUTQ 0x5411 _IOC_NRBITS 8 __ASSERT_VOID_CAST (void) TCSBRK 0x5409 bpf_fs__known_mountpoints S_BLKSIZE 512 f_files _PTHREAD_H 1 fs__read_mounts isalpha_l(c,l) __isalpha_l ((c), (l)) MS_BIND MS_BIND pr_debug(fmt,...) __pr(__pr_debug, fmt, ##__VA_ARGS__) MS_POSIXACL (1<<16) CHARCLASS_NAME_MAX 2048 CEOF CTRL('d') procfs__read_str TIOCPKT_FLUSHREAD 1 EXPR_NEST_MAX _POSIX2_EXPR_NEST_MAX STATMOUNT_MNT_POINT 0x00000010U BLKGETSIZE INT_FAST32_MAX (9223372036854775807L) tracefs__known_mountpoints ULONG_MAX (LONG_MAX * 2UL + 1UL) MOVE_MOUNT_BENEATH 0x00000200 isspace_l(c,l) __isspace_l ((c), (l)) BC_DIM_MAX _POSIX2_BC_DIM_MAX f_bfree fs__valid_mount DEFFILEMODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) MS_DIRSYNC 128 PTHREAD_MUTEX_ERRORCHECK_NP TCGETX 0x5432 __bool_true_false_are_defined 1 MS_NOUSER (1<<31) line_out _POSIX_SEM_NSEMS_MAX 256 _IOC_READ 2U PTHREAD_COND_INITIALIZER { { {0}, {0}, {0, 0}, {0, 0}, 0, 0, {0, 0} } } PTHREAD_MUTEX_RECURSIVE CLOCK_REALTIME_ALARM 8 assert(expr) ((void) sizeof ((expr) ? 1 : 0), __extension__ ({ if (expr) ; else __assert_fail (#expr, __FILE__, __LINE__, __ASSERT_FUNCTION); })) __count TTYDEF_OFLAG (OPOST | ONLCR | XTABS) TCSETXW 0x5435 MS_MOVE MS_MOVE _LIBC_LIMITS_H_ 1 isprint_l(c,l) __isprint_l ((c), (l)) TIOCSERGETMULTI 0x545A _POSIX_CLOCKRES_MIN 20000000 sysfs__read_xll MS_NOSUID 2 MS_NOSUID MS_NOSUID S_ISFIFO(mode) __S_ISTYPE((mode), __S_IFIFO) NR_OPEN 1024 __kernel_old_dev_t __kernel_old_dev_t _POSIX_PIPE_BUF 512 _UAPI__ASM_GENERIC_BITS_PER_LONG LSMT_ROOT 0xffffffffffffffff OPEN_TREE_CLOEXEC O_CLOEXEC MOUNT_ATTR_IDMAP 0x00100000 TIOCM_ST 0x008 TIOCGWINSZ 0x5413 hugetlbfs_init_once _IOC_WRITE 1U __need_ptrdiff_t SIOCGIFNETMASK 0x891b MOUNT_ATTR_NODEV 0x00000004 TIOCSBRK 0x5427 INT_MAX __INT_MAX__ TIOCLINUX 0x541C IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) PTHREAD_ONCE_INIT 0 SIOCSIFLINK 0x8911 _GCC_WRAP_STDINT_H __isascii(c) (((c) & ~0x7f) == 0) debugfs__known_mountpoints MOVE_MOUNT_SET_GROUP 0x00000100 BLKSSZGET BLKROSET _IO(0x12, 93) __undef_LINK_MAX _ASM_GENERIC_TYPES_H _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) SIOCGIFTXQLEN 0x8942 PTHREAD_THREADS_MAX SIOCGIFMEM 0x891f __isgraph_l(c,l) __isctype_l((c), _ISgraph, (l)) SIOCADDRT 0x890B __undef_LINK_MAX __pthread_internal_list INT_LEAST8_MIN (-128) __prev MS_NOSYMFOLLOW 256 CKILL CTRL('u') _ASM_X86_POSIX_TYPES_64_H pthread_cleanup_push(routine,arg) do { __pthread_unwind_buf_t __cancel_buf; void (*__cancel_routine) (void *) = (routine); void *__cancel_arg = (arg); int __not_first_call = __sigsetjmp_cancel (__cancel_buf.__cancel_jmp_buf, 0); if (__glibc_unlikely (__not_first_call)) { __cancel_routine (__cancel_arg); __pthread_unwind_next (&__cancel_buf); } __pthread_register_cancel (&__cancel_buf); do { TCSETS2 _IOW('T', 0x2B, struct termios2) TIOCSERSWILD 0x5455 mount_mutex hugetlbfs__mount N_6PACK 7 __isalpha_l(c,l) __isctype_l((c), _ISalpha, (l)) ULLONG_MAX (LLONG_MAX * 2ULL + 1) CLOCK_MONOTONIC_COARSE 6 _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) SCHED_OTHER 0 _POSIX2_COLL_WEIGHTS_MAX 2 fopen64 TIOCPKT_DOSTOP 32 SIOCGIFNAME 0x8910 __aligned_u64 __u64 __attribute__((aligned(8))) TIOCMSET 0x5418 sizep tracefs__mount small_const_nbits(nbits) (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG && (nbits) > 0) bpf_fs__configured CTIME 0 isgraph_l(c,l) __isgraph_l ((c), (l)) __ssize_t islower_l(c,l) __islower_l ((c), (l)) SIOCGIFHWADDR 0x8927 LONG_MIN (-LONG_MAX - 1L) INT_LEAST64_MIN (-__INT64_C(9223372036854775807)-1) CHAR_MIN SCHAR_MIN __kernel_old_uid_t __kernel_old_uid_t TIOCMBIS 0x5416 _STATFS_F_FRSIZE f_spare __undef_ARG_MAX MS_KERNMOUNT (1<<22) MQ_PRIO_MAX 32768 DEBUGFS_DEFAULT_PATH "/sys/kernel/debug" _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) TCGETA 0x5405 debugfs__configured MS_DIRSYNC MS_DIRSYNC _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) MS_MOVE 8192 S_IEXEC S_IXUSR SIOCGIFPFLAGS 0x8935 N_MOUSE 2 line_len_out _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) LLONG_MIN _POSIX2_RE_DUP_MAX 255 INTMAX_MIN (-__INT64_C(9223372036854775807)-1) _POSIX2_BC_SCALE_MAX 99 INT32_MAX (2147483647) MOUNT_ATTR_NOEXEC 0x00000008 __undef_OPEN_MAX S_ISDIR(mode) __S_ISTYPE((mode), __S_IFDIR) CLOCK_BOOTTIME_ALARM 9 BLKBSZGET _IOR(0x12,112,size_t) SIOCSARP 0x8955 MS_POSIXACL MS_POSIXACL MS_I_VERSION MS_I_VERSION TIOCSERGSTRUCT 0x5458 _POSIX_AIO_MAX 1 buf_pos mem_toupper magic islower(c) __isctype((c), _ISlower) f_bsize NGROUPS_MAX 65536 isdigit_l(c,l) __isdigit_l ((c), (l)) _POSIX_OPEN_MAX 20 LONG_MAX __LONG_MAX__ isalnum(c) __isctype((c), _ISalnum) MOVE_MOUNT__MASK 0x00000377 PTHREAD_PROCESS_PRIVATE PTHREAD_PROCESS_PRIVATE __pr(func,fmt,...) do { if ((func)) (func)("libapi: " fmt, ##__VA_ARGS__); } while (0) S_ISBLK(mode) __S_ISTYPE((mode), __S_IFBLK) TIOCGRS485 0x542E _POSIX_AIO_LISTIO_MAX 2 INT8_MAX (127) TTYDEF_LFLAG (ECHO | ICANON | ISIG | IEXTEN | ECHOE|ECHOKE|ECHOCTL) __assert_fail offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) isspace(c) __isctype((c), _ISspace) mount_overload TRACEFS_MAGIC 0x74726163 TIOCGLCKTRMIOS 0x5456 TIOCEXCL 0x540C N_MASC 8 INT64_MIN (-__INT64_C(9223372036854775807)-1) S_TYPEISMQ(buf) __S_TYPEISMQ(buf) _POSIX_MAX_CANON 255 CLOCK_MONOTONIC 1 err_out pthread_once_t UINT_LEAST32_MAX (4294967295U) CSTATUS _POSIX_VDISABLE TIOCSRS485 0x542F N_HDLC 13 f_fsid _BITS_CPU_SET_H 1 __elision __NCPUBITS (8 * sizeof (__cpu_mask)) _IOC_NRMASK ((1 << _IOC_NRBITS)-1) TIOCSTI 0x5412 sysfs_init_once override_path BC_SCALE_MAX _POSIX2_BC_SCALE_MAX CERASE 0177 TIOCSSOFTCAR 0x541A MS_NOATIME 1024 _POSIX_TZNAME_MAX 6 IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) PTHREAD_SCOPE_SYSTEM PTHREAD_SCOPE_SYSTEM BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) __SANE_USERSPACE_TYPES__ __force MS_RELATIME (1<<21) filename__read_ull_base MS_RELATIME MS_RELATIME filename CSTART CTRL('q') INTMAX_MAX (__INT64_C(9223372036854775807)) TIOCGPTPEER _IO('T', 0x41) PTHREAD_CANCEL_DEFERRED PTHREAD_CANCEL_DEFERRED procfs__known_mountpoints __cleanup_fct_attribute MOUNT_ATTR__ATIME 0x00000070 TCSBRKP 0x5425 BLKROGET _IO(0x12, 94) TIOCSER_TEMT 0x01 pfds TCSETAW 0x5407 SIOCGIFADDR 0x8915 __isleap(year) ((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0)) TCSETSF 0x5404 CLOCK_MONOTONIC_RAW 4 SIOCSIFDSTADDR 0x8918 _ASM_GENERIC_INT_LL64_H MOVE_MOUNT_F_SYMLINKS 0x00000001 CSTOP CTRL('s') IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) pthread_cleanup_pop(execute) do { } while (0); } while (0); __pthread_unregister_cancel (&__cancel_buf); if (execute) __cancel_routine (__cancel_arg); } while (0) isdigit(c) __isctype((c), _ISdigit) _ANSI_STDDEF_H statfs64 _IOC(dir,type,nr,size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT)) RTSIG_MAX 32 MOUNT_ATTR_NOSYMFOLLOW 0x00200000 PTHREAD_PROCESS_SHARED PTHREAD_PROCESS_SHARED TIOCM_RNG 0x080 _POSIX_MQ_OPEN_MAX 8 TIOCPKT_IOCTL 64 MS_SYNCHRONOUS 16 BLKSECTSET _IO(0x12,102) __undef_NR_OPEN INT_FAST64_MIN (-__INT64_C(9223372036854775807)-1) TCGETS2 _IOR('T', 0x2A, struct termios2) TIOCNOTTY 0x5422 TIOCSETD 0x5423 isupper(c) __isctype((c), _ISupper) SIOCADDDLCI 0x8980 isascii(c) __isascii (c) TIOCM_DTR 0x002 isupper_l(c,l) __isupper_l ((c), (l)) TIOCSISO7816 _IOWR('T', 0x43, struct serial_iso7816) MS_NOSEC (1<<28) _POSIX_SSIZE_MAX 32767 TCSETS 0x5402 __CPU_CLR_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] &= ~__CPUMASK (__cpu)) : 0; })) UINTPTR_MAX (18446744073709551615UL) PTHREAD_CREATE_JOINABLE PTHREAD_CREATE_JOINABLE __exctype_l(name) extern int name (int, locale_t) __THROW BLOCK_SIZE (1<<BLOCK_SIZE_BITS) _POSIX2_CHARCLASS_NAME_MAX 14 UINT32_MAX (4294967295U) N_X25 6 tracefs__mountpoint SIOCRTMSG 0x890D CFLUSH CDISCARD N_SMSBLOCK 12 INT8_MIN (-128) UINT8_MAX (255) BLKFRAGET _IO(0x12,101) _STATFS_F_FLAGS __CPU_OP_S(setsize,destset,srcset1,srcset2,op) (__extension__ ({ cpu_set_t *__dest = (destset); const __cpu_mask *__arr1 = (srcset1)->__bits; const __cpu_mask *__arr2 = (srcset2)->__bits; size_t __imax = (setsize) / sizeof (__cpu_mask); size_t __i; for (__i = 0; __i < __imax; ++__i) ((__cpu_mask *) __dest->__bits)[__i] = __arr1[__i] op __arr2[__i]; __dest; })) __bitwise SIOCDELDLCI 0x8981 __CPU_EQUAL_S(setsize,cpusetp1,cpusetp2) (__builtin_memcmp (cpusetp1, cpusetp2, setsize) == 0) _IOC_TYPEBITS 8 TCSETXF 0x5434 sysfs__read_bool _POSIX_RTSIG_MAX 8 __jmp_buf_tag_defined 1 TIOCINQ FIONREAD BITS_PER_LONG_LONG 64 SIOCGIFINDEX 0x8933 BLKRAGET _BITS_WCHAR_H 1 MS_VERBOSE 32768 CDSUSP CTRL('y') MS_NOUSER MS_NOUSER S_TYPEISSHM(buf) __S_TYPEISSHM(buf) CBRK CEOL TTY_NAME_MAX 32 _GCC_LIMITS_H_ FIONCLEX 0x5450 TCSETA 0x5406 PTHREAD_RWLOCK_INITIALIZER { { __PTHREAD_RWLOCK_INITIALIZER (PTHREAD_RWLOCK_DEFAULT_NP) } } iscntrl(c) __isctype((c), _IScntrl) BLKFRASET _IO(0x12,100) FIOCLEX 0x5451 TIOCMIWAIT 0x545C sysfs__read_ull_base f_blocks TIOCCONS 0x541D TIOCM_RI TIOCM_RNG __undef_ARG_MAX CLOCK_THREAD_CPUTIME_ID 3 UINT_LEAST16_MAX (65535) MS_REMOUNT 32 TCGETS 0x5401 CTRL(x) (x&037) PTHREAD_INHERIT_SCHED PTHREAD_INHERIT_SCHED MOVE_MOUNT_T_EMPTY_PATH 0x00000040 INT_LEAST32_MIN (-2147483647-1) S_ISLNK(mode) __S_ISTYPE((mode), __S_IFLNK) FIOASYNC 0x5452 LOGIN_NAME_MAX 256 __errno_location debugfs__mountpoint isblank(c) __isctype((c), _ISblank) INT_FAST16_MAX (9223372036854775807L) io__init TIOCSPTLCK _IOW('T', 0x31, int) _LINUX_MOUNT_H SIOCGIFMETRIC 0x891d __PTRDIFF_T buf_len __spins __isalnum_l(c,l) __isctype_l((c), _ISalnum, (l)) __nusers hugetlbfs__mountpoint __WCHAR_MIN __WCHAR_MIN__ _CTYPE_H 1 true 1 f_bavail filename__read_int PTHREAD_CANCELED ((void *) -1) SIOCGIFDSTADDR 0x8917 sysfs__configured debugfs_init_once fs__env_override MOUNT_ATTR_RELATIME 0x00000000 N_TTY 0 CLOCK_TAI 11 io__get_char TRACEFS_DEFAULT_PATH "/sys/kernel/tracing" __CPU_COUNT_S(setsize,cpusetp) __sched_cpucount (setsize, cpusetp) WCHAR_MAX __WCHAR_MAX N_IRDA 11 fs__debugfs SIOCGIFSLAVE 0x8929 BLKBSZGET MS_MANDLOCK 64 INTPTR_MAX (9223372036854775807L) _T_PTRDIFF BLKSSZGET _IO(0x12,104) _BITS_SETJMP_H 1 __API_DEBUG_INTERNAL_H__ BLKRASET __exctype(name) extern int name (int) __THROW MOUNT_ATTR_STRICTATIME 0x00000020 SIOCGRARP 0x8961 FSPICK_CLOEXEC 0x00000001 bpf_fs__mount MS_REC 16384 __itimerspec_defined 1 __tobody(c,f,a,args) (__extension__ ({ int __res; if (sizeof (c) > 1) { if (__builtin_constant_p (c)) { int __c = (c); __res = __c < -128 || __c > 255 ? __c : (a)[__c]; } else __res = f args; } else __res = (a)[(int) (c)]; __res; })) CINTR CTRL('c') BLKRRPART _IO(0x12, 95) __islower_l(c,l) __isctype_l((c), _ISlower, (l)) SIZE_MAX (18446744073709551615UL) PTHREAD_MUTEX_RECURSIVE_NP FIONREAD 0x541B TIOCMGET 0x5415 SIG_ATOMIC_MIN (-2147483647-1) SIOCPROTOPRIVATE 0x89E0 _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) SIOCDRARP 0x8960 filename__read_str SSIZE_MAX LONG_MAX f_namelen io__getdelim _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) isgraph(c) __isctype((c), _ISgraph) TIOCVHANGUP 0x5437 __isoc99_fscanf isascii_l(c,l) __isascii_l ((c), (l)) _POSIX_SIGQUEUE_MAX 32 TIOCGICOUNT 0x545D UMOUNT_NOFOLLOW UMOUNT_NOFOLLOW TIOCPKT_FLUSHWRITE 2 _POSIX2_BC_DIM_MAX 2048 MS_NODIRATIME MS_NODIRATIME statfs __fsblkcnt64_t TIOCM_LE 0x001 _ASSERT_H 1 UINT_LEAST64_MAX (__UINT64_C(18446744073709551615)) _POSIX_HOST_NAME_MAX 255 _LIMITS_H___ _tolower(c) ((int) (*__ctype_tolower_loc ())[(int) (c)]) SCHAR_MIN (-SCHAR_MAX - 1) MNT_EXPIRE MNT_EXPIRE pr_info(fmt,...) __pr(__pr_info, fmt, ##__VA_ARGS__) fs__init_once S_IWRITE S_IWUSR line_len TIOCSERGETLSR 0x5459 SIOCSIFHWBROADCAST 0x8937 _POSIX_MAX_INPUT 255 _BITS_SCHED_H 1 _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) __toascii_l(c,l) ((l), __toascii (c)) TIOCNXCL 0x540D UINT16_MAX (65535) INT_LEAST16_MAX (32767) TIOCGISO7816 _IOR('T', 0x42, struct serial_iso7816) _STDDEF_H_ __must_check CMIN 1 _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) _POSIX_RE_DUP_MAX 255 SIOCADDMULTI 0x8931 MS_PRIVATE (1<<18) SIOCSIFHWADDR 0x8924 _BITS_STDINT_LEAST_H 1 MS_SLAVE MS_SLAVE procfs__configured PTRDIFF_MIN (-9223372036854775807L-1) sysfs__mount TIOCGDEV _IOR('T', 0x32, unsigned int) __isascii_l(c,l) ((l), __isascii (c)) TIOCM_DSR 0x100 PATH_MAX 4096 MS_BIND 4096 filename__read_ull __undef_NR_OPEN _BSD_PTRDIFF_T_ debugfs__mount TIOCSIG _IOW('T', 0x36, int) __CPUELT(cpu) ((cpu) / __NCPUBITS) BLKFRAGET OPEN_TREE_CLONE 1 MS_SHARED MS_SHARED CHAR_MAX SCHAR_MAX FSMOUNT_CLOEXEC 0x00000001 TIOCGPGRP 0x540F SIOCDEVPRIVATE 0x89F0 PTHREAD_CANCEL_DISABLE PTHREAD_CANCEL_DISABLE __list SYSFS_MAGIC 0x62656572 PTHREAD_STACK_MIN 16384 _STDINT_H 1 ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) _STR(x) #x S_ISREG(mode) __S_ISTYPE((mode), __S_IFREG) _ASSERT_H_DECLS isalpha(c) __isctype((c), _ISalpha) MS_PRIVATE MS_PRIVATE TCSETAF 0x5408 PTHREAD_CREATE_DETACHED PTHREAD_CREATE_DETACHED toascii(c) __toascii (c) CEOT CEOF TIOCSPGRP 0x5410 SIOCSIFFLAGS 0x8914 INT_FAST32_MIN (-9223372036854775807L-1) PTHREAD_MUTEX_ERRORCHECK TIOCGPTLCK _IOR('T', 0x39, int) _POSIX_DELAYTIMER_MAX 32 BLKRAGET _IO(0x12, 99) N_STRIP 4 getenv fs__sysfs SIOCSIFMETRIC 0x891e _BITS_TIME_H 1 pthread_mutex_unlock TIOCGPTN _IOR('T', 0x30, unsigned int) STATMOUNT_FS_TYPE 0x00000020U SIOCGIFCOUNT 0x8938 SCHED_FIFO 1 __CPU_ALLOC(count) __sched_cpualloc (count) __CPU_FREE(cpuset) __sched_cpufree (cpuset) __ASSERT_FUNCTION __extension__ __PRETTY_FUNCTION__ MS_NOREMOTELOCK (1<<27) UINTMAX_MAX (__UINT64_C(18446744073709551615)) bool _Bool ___int_ptrdiff_t_h FS(name) const char *name ##__mountpoint(void); const char *name ##__mount(void); bool name ##__configured(void); __isctype_l(c,type,locale) ((locale)->__ctype_b[(int) (c)] & (unsigned short int) type) SIOCSIFADDR 0x8916 SIOCGIFCONF 0x8912 MOUNT_ATTR_NODIRATIME 0x00000080 BLKFRASET MS_NODEV 4 __CPU_ISSET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? ((((const __cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] & __CPUMASK (__cpu))) != 0 : 0; })) FIOQSIZE 0x5460 hugetlbfs__known_mountpoints PROC_SUPER_MAGIC 0x9fa0 bpf_fs__mountpoint WINT_MIN (0u) TCFLSH 0x540B BLKBSZSET isxdigit(c) __isctype((c), _ISxdigit) _ASM_GENERIC_IOCTL_H SIOGIFINDEX SIOCGIFINDEX TTYDEF_CFLAG (CREAD | CS7 | PARENB | HUPCL) __iscntrl_l(c,l) __isctype_l((c), _IScntrl, (l)) MS_UNBINDABLE MS_UNBINDABLE MS_MGC_VAL MS_STRICTATIME MS_STRICTATIME MS_RMT_MASK (MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK|MS_I_VERSION |MS_LAZYTIME) _POSIX_SYMLOOP_MAX 8 SIG_ATOMIC_MAX (2147483647) ispunct_l(c,l) __ispunct_l ((c), (l)) LLONG_MAX __LONG_LONG_MAX__ _SYS_STAT_H 1 MOVE_MOUNT_T_AUTOMOUNTS 0x00000020 _POSIX_LOGIN_NAME_MAX 9 BLKFLSBUF toascii_l(c,l) __toascii_l ((c), (l)) LINE_MAX _POSIX2_LINE_MAX PTRDIFF_MAX (9223372036854775807L) MOUNT_ATTR_SIZE_VER0 32 WINT_MAX (4294967295u) PTHREAD_BARRIER_SERIAL_THREAD -1 tracefs_init_once MS_SILENT MS_SILENT INT16_MIN (-32767-1) fs__tracefs BLKSECTGET _IO(0x12,103) sysfs__read_int TIOCPKT 0x5420 MS_BORN (1<<29) PTHREAD_MUTEX_ADAPTIVE_NP MS_SUBMOUNT (1<<26) _POSIX_SYMLINK_MAX 255 TCSETSW 0x5403 _POSIX_TTY_NAME_MAX 9 S_ISSOCK(mode) __S_ISTYPE((mode), __S_IFSOCK) __val fs__bpf_fs SIOCSRARP 0x8962 TIOCM_SR 0x010 MOVE_MOUNT_F_EMPTY_PATH 0x00000004 BLKGETSIZE _IO(0x12, 96) BLKROGET N_AX25 5 USHRT_MAX (SHRT_MAX * 2 + 1) MNT_DETACH MNT_DETACH S_IREAD S_IRUSR MS_NODEV MS_NODEV strcmp _POSIX_MQ_PRIO_MAX 32 _POSIX_SEM_VALUE_MAX 32767 __CPU_ALLOC_SIZE(count) ((((count) + __NCPUBITS - 1) / __NCPUBITS) * sizeof (__cpu_mask)) MS_MGC_MSK 0xffff0000 MS_MGC_VAL 0xC0ED0000 __fsword_t IOCSIZE_SHIFT (_IOC_SIZESHIFT) INT_LEAST64_MAX (__INT64_C(9223372036854775807)) MS_MGC_VAL 0xc0ed0000 __ASM_X86_BITSPERLONG_H DELAYTIMER_MAX 2147483647 _TOOLS_LINUX_TYPES_H_ upper_name SIOCGIFFLAGS 0x8913 IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) SIOCGIFMAP 0x8970 TIOCM_CTS 0x020 STATMOUNT_SB_BASIC 0x00000001U _STATFS_F_NAMELEN __DEFINED_ptrdiff_t BC_STRING_MAX _POSIX2_BC_STRING_MAX TCXONC 0x540A SIOCSIFTXQLEN 0x8943 SIOCGARP 0x8954 sysfs__known_mountpoints tracing_path_mount _DYNAMIC_STACK_SIZE_SOURCE 1 CLOSE_RANGE_UNSHARE (1U << 1) tracing _ISOC95_SOURCE RENAME_WHITEOUT (1 << 2) IFTODT(mode) (((mode) & 0170000) >> 12) RENAME_NOREPLACE (1 << 0) DT_UNKNOWN DT_UNKNOWN _DIRENT_HAVE_D_NAMLEN UINTMAX_WIDTH 64 mntpt _LINUX_CLOSE_RANGE_H tracing_path_debugfs_mount _POSIX_FD_SETSIZE _POSIX_OPEN_MAX _ISOC99_SOURCE _PRINTF_NAN_LEN_MAX 4 __GLIBC_USE_LIB_EXT2 1 _DIRENT_HAVE_D_RECLEN DT_CHR DT_CHR tracing_path_tracefs_mount MAXNAMLEN NAME_MAX DT_WHT DT_WHT _GNU_SOURCE DT_SOCK DT_SOCK UINT_LEAST16_WIDTH 16 str_error_r put_tracing_file SEEK_DATA 3 tracing_path__strerror_open_tp _DIRENT_MATCHES_DIRENT64 1 __USE_DYNAMIC_STACK_SIZE 1 __FDS_BITS(set) ((set)->fds_bits) d_reclen namelist get_events_file __USE_XOPEN2K8XSI 1 _ISOC99_SOURCE 1 PTHREAD_STACK_MIN __sysconf (__SC_THREAD_STACK_MIN_VALUE) __USE_XOPEN2KXSI 1 UINT_FAST16_WIDTH __WORDSIZE DT_BLK DT_BLK __USE_GNU 1 _ISOC2X_SOURCE 1 __GLIBC_USE_IEC_60559_EXT 1 _POSIX_HIWAT _POSIX_PIPE_BUF _DIRENT_H 1 UINT32_WIDTH 32 __tracing_path_set DTTOIF(dirtype) ((dirtype) << 12) _XOPEN_SOURCE_EXTENDED 1 WINT_WIDTH 32 DT_DIR DT_DIR alphasort64 _ISOC11_SOURCE TEMP_FAILURE_RETRY(expression) (__extension__ ({ long int __result; do __result = (long int) (expression); while (__result == -1L && errno == EINTR); __result; })) __GLIBC_USE_C2X_STRTOL 1 _XOPEN_SOURCE_EXTENDED UINT8_WIDTH 8 __GLIBC_USE_IEC_60559_TYPES_EXT 1 __API_FS_TRACING_PATH_H tracing_events__scandir_alphasort _XOPEN_SOURCE 700 __error_t_defined 1 sbuf __dirstream SEEK_HOLE 4 _ISOC2X_SOURCE UINT_LEAST8_WIDTH 8 scandir UINT64_WIDTH 64 put_events_file _TOOLS_LINUX_STRING_H_ UINT_FAST8_WIDTH 8 __GLIBC_USE_IEC_60559_BFP_EXT_C2X 1 PTRDIFF_WIDTH __WORDSIZE __USE_XOPEN_EXTENDED 1 UINT_LEAST32_WIDTH 32 __GLIBC_USE_DEPRECATED_GETS 0 UINT_FAST64_WIDTH 64 _DIRENT_HAVE_D_OFF _DYNAMIC_STACK_SIZE_SOURCE _D_EXACT_NAMLEN(d) (strlen ((d)->d_name)) __SC_THREAD_STACK_MIN_VALUE 75 __USE_LARGEFILE 1 __GLIBC_USE_IEC_60559_BFP_EXT 1 _LARGEFILE64_SOURCE __USE_ISOC11 1 DT_REG DT_REG _LARGEFILE_SOURCE scandir64 dirent _XOPEN_SOURCE _DIRENT_HAVE_D_TYPE get_tracing_file DT_LNK DT_LNK RENAME_EXCHANGE (1 << 1) tracing_path L_cuserid 9 _POSIX_QLIMIT 1 UINT16_WIDTH 16 _LARGEFILE_SOURCE 1 UINT_LEAST64_WIDTH 64 __GLIBC_USE_ISOC2X 1 __ino64_t strdupa(s) (__extension__ ({ const char *__old = (s); size_t __len = strlen (__old) + 1; char *__new = (char *) __builtin_alloca (__len); (char *) memcpy (__new, __old, __len); })) CLOSE_RANGE_CLOEXEC (1U << 2) UINTPTR_WIDTH __WORDSIZE tracing_events__opendir SIG_ATOMIC_WIDTH 32 _ISOC11_SOURCE 1 strndupa(s,n) (__extension__ ({ const char *__old = (s); size_t __len = strnlen (__old, (n)); char *__new = (char *) __builtin_alloca (__len + 1); __new[__len] = '\0'; (char *) memcpy (__new, __old, __len); })) zput_events_file(ptr) ({ free(*ptr); *ptr = NULL; }) DT_FIFO DT_FIFO _POSIX_UIO_MAXIOV 16 WCHAR_WIDTH 32 __GLIBC_USE_IEC_60559_FUNCS_EXT 1 d_fileno d_ino SIZE_WIDTH __WORDSIZE __USE_UNIX98 1 __USE_XOPEN 1 UINT_FAST32_WIDTH __WORDSIZE _ISOC95_SOURCE 1 __GLIBC_USE_IEC_60559_FUNCS_EXT_C2X 1 _D_ALLOC_NAMLEN(d) (((char *) (d) + (d)->d_reclen) - &(d)->d_name[0]) strcpy cgroupfs_find_mountpoint __stringify(x...) __stringify_1(x) cached __LINUX_STRINGIFY_H strncpy subsys cgroupfs_cache_entry strchr getline strstr __stringify_1(x...) #x maxlen __API_CPU__ cpu__get_max_freq __base_pr __pr_debug __pr_warn __gnuc_va_list __pr_info fp_offset libapi_print_fn_t __va_list_tag _VA_LIST_ _STDARG_H _VA_LIST_T_H __builtin_va_list gp_offset overflow_arg_area reg_save_area _ANSI_STDARG_H_ libapi_set_print __va_copy(d,s) __builtin_va_copy(d,s) va_arg(v,l) __builtin_va_arg(v,l) va_end(v) __builtin_va_end(v) __va_list__ va_start(v,l) __builtin_va_start(v,l) vfprintf errnum __xpg_strerror_r _GNU_SOURCE buflen GNU C17 13.3.0 -mtune=generic -march=x86-64 -g -fPIC -fvisibility=hidden -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection LIBPERF_DEBUG libperf_print_fn_t __libperf_pr LIBPERF_ERR LIBPERF_DEBUG2 LIBPERF_DEBUG3 libperf_init libperf_print LIBPERF_INFO libperf_print_level LIBPERF_WARN page_size _ISgraph nr_cpus_conf cpu_map__new_sysconf __u16 __u8 orig __perf_cpu_map__nr cmp_cpu perf_cpu_map__intersect __compar_fn_t __u32 nr_cpus perf_cpu_map out_free_tmp refcount_t perf_cpu_map__merge merged __u32_alias_t _ISprint __ret high payload_size perf_cpu_map__put perf_cpu_map__read __ret_warn_on __ptr cpu_map__delete cpu_map__trim_new __read_once_size _ISpunct tmp_len __perf_cpu_map__cpu onlnf __uint64_t _ISalnum tmp_cpus _max1 _max2 __u16_alias_t refcount_read perf_cpu_map__new_online_cpus _ISxdigit _ISupper __ctype_b_loc _IScntrl perf_cpu_map__get __ret_warn_once refcount_inc cpu_a cpu_b atomic_read refcount_struct start_cpu cpu_map__new_sysfs_online perf_cpu_map__has perf_cpu_map__refcnt atomic_set perf_cpu_map__max perf_cpu_map__alloc __u8_alias_t qsort perf_cpu_map__new_any_cpu _ISalpha __warned refcount_inc_not_zero _ISblank atomic_cmpxchg _ISspace refs __u64_alias_t perf_cpu_map__set_nr refcount_set __old _ISlower new_max perf_cpu perf_cpu_map__has_any_cpu_or_is_empty perf_cpu_map__min perf_cpu_map__equal cpu_at_idx perf_cpu_map__idx cpu_list _ISdigit perf_cpu_map__is_any_cpu_or_is_empty perf_cpu_map__new refcount_sub_and_test perf_cpu_map__is_empty refcount_dec_and_test perf_cpu_map__has_any_cpu perf_cpu_map__is_subset end_cpu perf_thread_map__comm thread_map_data perf_thread_map perf_thread_map__delete err_thread perf_thread_map__pid perf_thread_map__realloc perf_thread_map__reset perf_thread_map__set_pid perf_thread_map__new_dummy nr_threads perf_thread_map__new_array perf_thread_map__put perf_thread_map__get perf_thread_map__nr ncpus perf_evsel__apply_filter PERF_FORMAT_TOTAL_TIME_RUNNING probe_offset perf_evsel__read_size row_size perf_evsel__read __reserved_1 exclude_hv comm_exec zalloc perf_mmap__init aux_sample_size perf_evsel__alloc_fd empty_cpu_map perf_evsel__attr perf_evsel__mmap inherit_thread use_clockid is_pmu_core perf_mmap__read_self perf_evsel__free_fd unmap_cb perf_evsel__new wakeup_events sample_id_all perf_evsel__alloc_id sample_regs_user PERF_FORMAT_GROUP INIT_LIST_HEAD perf_counts_values__scale __u64 perf_mmap xyarray__max_x xyarray__max_y perf_evsel__free_id precise_ip remove_on_exec empty_thread_map sample_period exclusive pages PERF_FORMAT_TOTAL_TIME_ENABLED perf_evsel__cpus perf_mmap__munmap config1 config2 config3 inherit perf_evsel__threads xyarray__new disabled uprobe_path context_switch nr_members perf_evsel__alloc_mmap perf_evsel__enable_thread get_group_fd perf_evsel__close_fd perf_evsel__enable perf_evsel__run_ioctl perf_evsel__close sample_stack_user perf_evsel__init PERF_FORMAT_ID libperf_unmap_cb_t enable_on_exec sample_max_stack wakeup_watermark own_cpus kprobe_addr sig_data exclude_guest perf_event_read_format exclude_kernel text_poke xyarray perf_evsel__mmap_base mmap_data __zfree sample_regs_intr event_copy PERF_FORMAT_MAX prot bp_addr perf_evsel__delete perf_evsel perf_evsel__ioctl perf_mmap__mmap __xyarray__entry perf_evsel__munmap perf_evsel__disable perf_evsel__disable_cpu __s32 exclude_user sample_freq contents exclude_callchain_user aux_watermark kprobe_func perf_evsel__close_fd_cpu perf_evsel__close_cpu bp_len exclude_host entry_size perf_evsel__enable_cpu nthreads evsel_fd pscaled inherit_stat perf_evsel__read_group bp_type perf_evsel__adjust_values perf_evsel__open exclude_callchain_kernel exclude_idle sys_perf_event_open write_backward event_copy_sz branch_sample_type aux_output perf_mmap_param sigtrap PERF_FORMAT_LOST requires_cpu xyarray__delete perf_counts_values cpu_map_idx __s8 __reserved_2 __reserved_3 perf_event_attr perf_evlist__alloc_mmap perf_evlist__open perf_evlist__mmap_cb_mmap perf_evlist__add_pollfd perf_evlist__init perf_evlist__delete mmap_per_evsel user_requested_cpus all_cpus fdarray__available_entries revents_and_mask flgs heads perf_evlist__mmap_ops __list_del nfds nr_entries mmap_ovw perf_evlist_mmap__cb_idx_t list_add_tail out_err perf_evlist__close perf_evlist__nr_groups perf_evlist__exit perf_evlist__add perf_evlist__id_add_fd out_unmap perf_mmap__get vcpu perf_evlist_mmap__cb_mmap_t perf_evlist__purge machine_pid perf_evlist__set_mmap_first has_user_cpus perf_evlist__id_add perf_evlist__go_system_wide perf_evlist__filter_pollfd perf_evlist__mmap perf_evlist_mmap_ops needs_map_propagation hlist_add_head hlist_node perf_evlist__enable list_del_init read_data perf_evlist__new pprev perf_evlist__mmap_cb_get __perf_evlist__set_leader evlist_cpu mmap_per_thread perf_evlist__next_mmap perf_evlist__nr_mmaps mmap_per_cpu perf_evlist__first perf_evlist__poll perf_evlist__id_hash perf_evlist__remove __list_del_entry perf_evlist__reset_id_hash perf_evlist perf_evlist__alloc_pollfd revent perf_evlist__disable perf_evlist__read_format perf_evlist__munmap_filtered perf_evlist__next hlist_head perf_evlist__set_maps perf_sample_id __write_once_size perf_evlist_mmap__cb_get_t mmap_ovw_first fcntl perf_mmap__put cpu_idx __list_add hash_64_generic perf_evsel__set_sid_idx __mptr _output_overwrite __func__ perf_evlist__munmap __perf_evlist__propagate_maps perf_record_header_feature next_prev_tid time_cycles pheader perf_record_header_build_id perf_record_switch perf_record_cpu_map cap_user_time_zero perf_record_auxtrace_error reference next_prev_pid perf_record_header_tracing_data perf_record_lost cap_bit0 perf_record_thread_map cap_user_rdpmc perf_record_mask_cpu_map32 ino_generation perf_record_throttle ring_buffer_write_tail pgoff mask64_data perf_record_auxtrace perf_record_cpu_map_data ptid perf_record_header_attr ksym_type perf_record_thread_map_entry time_enabled range_cpu_data cap_user_time perf_record_stat perf_record_aux_output_hw_id pack old_len perf_mmap__empty id_index_entry event_id feat_id perf_record_text_poke_event mask32_data perf_record_bpf_event time_mask perf_record_id_index perf_record_mask_cpu_map64 perf_record_lost_samples reserved2__ perf_record_ksymbol perf_mmap__consume time_offset reserved1__ read_timestamp ring_buffer_read_head time_running cap_____res evcnt perf_mmap__read_head __reserved stream_id perf_mmap__mmap_len perf_mmap__read_event build_id_size perf_record_mmap2 perf_record_compressed perf_record_cgroup perf_event_mmap_page time_shift perf_trace_event_type __pad aux_size startp ppid unit evt_head data_tail __int64_t compat_version __perf_mmap__read_init read_perf_counter nr_namespaces reserved__ _min1 _min2 perf_ns_link_info perf_record_auxtrace_info mul_u64_u32_shr perf_record_read capabilities perf_record_comm cap_user_time_short cpu_map_entries ___p1 misc data_head cpus_data aux_offset perf_mmap__read perf_record_event_update perf_record_stat_round perf_mmap__write_tail time_mult overwrite_rb_find_range new_len perf_record_stat_config perf_record_mmap perf_record_header_event_type perf_record_fork aux_tail perf_record_range_cpu_map __s64 data_offset perf_record_event_update_scale perf_record_time_conv perf_record_sample pmc_width perf_record_itrace_start delta perf_record_event_update_cpus feat perf_mmap__read_done perf_record_namespaces perf_record_stat_config_entry aux_head cap_bit0_is_deprecated perf_record_aux long_size perf_event_header ylen xyarray__reset is_read writen pread preadn buf_start STATX__RESERVED 0x80000000U __getcwd_chk STATX_UID 0x00000008U _TOOLS_LINUX_COMPILER_H_ _compiletime_assert(condition,msg,prefix,suffix) __compiletime_assert(condition, msg, prefix, suffix) __SUBCMD_UTIL_H __glibc_unsigned_or_positive(__l) ((__typeof (__l)) 0 < (__typeof (__l)) -1 || (__builtin_constant_p (__l) && (__l) > 0)) pager_env execv_cmd __aligned(x) __attribute__((aligned(x))) pwd_stat __acquires(x) __glibc_fortify_n(f,__l,__s,__osz,...) (__glibc_safe_or_unknown_len (__l, __s, __osz) ? __ ## f ## _alias (__VA_ARGS__) : (__glibc_unsafe_len (__l, __s, __osz) ? __ ## f ## _chk_warn (__VA_ARGS__, (__osz) / (__s)) : __ ## f ## _chk (__VA_ARGS__, (__osz) / (__s)))) st_uid __same_type(a,b) __builtin_types_compatible_p(typeof(a), typeof(b)) __always_inline inline __attribute__((always_inline)) __ap st_blksize __fmt STATX_MODE 0x00000002U WRITE_ONCE(x,val) ({ union { typeof(x) __val; char __c[1]; } __u = { .__val = (val) }; __write_once_size(&(x), __u.__c, sizeof(x)); __u.__val; }) st_gid argv0 __syscall_slong_t __fortified_attr_access(a,o,s) __attribute__ ((__access__ (a, o))) st_nlink __PERF_SUBCMD_CONFIG_H __packed __attribute__((packed)) st_ctim STATX_BLOCKS 0x00000400U _BITS_STDIO2_DEC_H 1 _BITS_STDIO_H 1 __scanf(a,b) __attribute__((format(scanf, a, b))) fread_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ char *__ptr = (char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) { int __c = getc_unlocked (__stream); if (__c == EOF) break; *__ptr++ = __c; } ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fread_unlocked (ptr, size, n, stream)))) __strlcpy_chk __rcu __stack_chk_fail STATX_BASIC_STATS 0x000007ffU OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) st_atim __compiletime_error(message) __attribute__((error(message))) fwrite_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ const char *__ptr = (const char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) if (putc_unlocked (*__ptr++, __stream) == EOF) break; ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fwrite_unlocked (ptr, size, n, stream)))) STATX_ATTR_APPEND 0x00000020 __uid_t ALLOC_GROW(x,nr,alloc) do { if ((nr) > alloc) { if (alloc_nr(alloc) < (nr)) alloc = (nr); else alloc = alloc_nr(alloc); x = xrealloc((x), alloc * sizeof(*(x))); } } while(0) set_argv_exec_path __blkcnt_t __glibc_fortify(f,__l,__s,__osz,...) (__glibc_safe_or_unknown_len (__l, __s, __osz) ? __ ## f ## _alias (__VA_ARGS__) : (__glibc_unsafe_len (__l, __s, __osz) ? __ ## f ## _chk_warn (__VA_ARGS__, __osz) : __ ## f ## _chk (__VA_ARGS__, __osz))) __getcwd_alias READ_ONCE(x) ({ union { typeof(x) __val; char __c[1]; } __u = { .__c = { 0 } }; __read_once_size(&(x), __u.__c, sizeof(x)); __u.__val; }) __asprintf_chk old_path __wur __attribute_warn_unused_result__ __fprintf_chk __mode_t __glibc_objsize0(__o) __builtin_dynamic_object_size (__o, 0) __SUBCMD_EXEC_CMD_H STATX_ATTR_ENCRYPTED 0x00000800 __FD_ELT noinline __attribute__((noinline)) __maybe_unused __attribute__((unused)) STATX_ATTR_AUTOMOUNT 0x00001000 STATX_BTIME 0x00000800U STATX_SIZE 0x00000200U __PASTE(a,b) ___PASTE(a, b) __STRINGS_FORTIFIED 1 GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) add_path fallthrough __attribute__((__fallthrough__)) __releases(x) make_nonrelative_path _BITS_STDIO2_H 1 STATX_TYPE 0x00000001U get_pwd_cwd system_path __acquire(x) (void)0 __nlink_t st_mode STATX_ATTR_MOUNT_ROOT 0x00002000 __stream _BITS_SELECT_DECL_H 1 __cond_lock(x,c) (c) STATX_MNT_ID 0x00001000U get_argv_exec_path __src __noreturn __attribute__((noreturn)) STATX_ATTR_NODUMP 0x00000040 is_dir_sep(c) ((c) == '/') __glibc_safe_len_cond(__l,__s,__osz) ((__l) <= (__osz) / (__s)) strndup STATX_ATTR_IMMUTABLE 0x00000010 asm_goto_output(x...) asm goto(x) __statx_timestamp_defined 1 stat64 __FD_ELT(d) __extension__ ({ long int __d = (d); (__builtin_constant_p (__d) ? (0 <= __d && __d < __FD_SETSIZE ? (__d / __NFDBITS) : __fdelt_warn (__d)) : __fdelt_chk (__d)); }) subcmd_config __time_t astrcatf(out,fmt,...) ({ char *tmp = *(out); if (asprintf((out), "%s" fmt, tmp ?: "", ## __VA_ARGS__) == -1) die("asprintf failed"); free(tmp); }) STATX_MNT_ID_UNIQUE 0x00004000U _GNU_SOURCE 1 likely(x) __builtin_expect(!!(x), 1) __blksize_t STATX_NLINK 0x00000004U __read_mostly compiletime_assert(condition,msg) _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) MAX_ARGS 32 execvp __strlcpy_alias __USE_EXTERN_INLINES 1 report __attribute_const__ extract_argv0_path _FORTIFY_SOURCE 3 _LINUX_STAT_H __dest unreachable() __builtin_unreachable() __STDIO_INLINE __glibc_objsize(__o) __builtin_dynamic_object_size (__o, 1) __builtin___memcpy_chk STATX_ALL 0x00000fffU STATX_INO 0x00000100U __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) __getcwd_chk_warn __must_hold(x) setup_path exec_cmd_init __printf(a,b) __attribute__((format(printf, a, b))) STATX_GID 0x00000010U is_absolute_path unlikely(x) __builtin_expect(!!(x), 0) __init new_path __LINUX_COMPILER_TYPES_H ___PASTE(a,b) a ##b zfree(ptr) ({ free(*ptr); *ptr = NULL; }) fread_unlocked __is_constexpr(x) (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8))) __dev_t __glibc_reserved slash __weak __attribute__((weak)) __glibc_safe_or_unknown_len(__l,__s,__osz) ((__builtin_constant_p (__osz) && (__osz) == (__SIZE_TYPE__) -1) || (__glibc_unsigned_or_positive (__l) && __builtin_constant_p (__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), (__s), (__osz))) && __glibc_safe_len_cond ((__SIZE_TYPE__) (__l), (__s), (__osz)))) __pad0 tv_nsec barrier() __asm__ __volatile__("": : :"memory") STATX_ATIME 0x00000020U STATX_DIOALIGN 0x00002000U STATX_CTIME 0x00000080U __STDIO_INLINE __extern_inline st_rdev st_dev __OPTIMIZE__ 1 __pure __attribute__((pure)) __glibc_unsafe_len(__l,__s,__osz) (__glibc_unsigned_or_positive (__l) && __builtin_constant_p (__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), __s, __osz)) && !__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), __s, __osz)) STATX_ATTR_VERITY 0x00100000 __gid_t getcwd __builtin___vsnprintf_chk nargv st_blocks __buf STATX_ATTR_COMPRESSED 0x00000004 __STDLIB_MB_LEN_MAX 16 GNU C99 13.3.0 -mtune=generic -march=x86-64 -ggdb3 -O6 -std=gnu99 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection _BITS_UNISTD_DECL_H 1 __always_unused __attribute__((__unused__)) exec_name cwd_stat __used __attribute__((__unused__)) vsnprintf prepare_exec_cmd st_ino execl_cmd __ino_t __compiletime_assert(condition,msg,prefix,suffix) do { extern void prefix ## suffix(void) __compiletime_error(msg); if (!(condition)) prefix ## suffix(); } while (0) astrcat __release(x) (void)0 alloc_nr(x) (((x)+16)*3/2) __USE_FORTIFY_LEVEL 3 STATX_ATTR_DAX 0x00200000 __statx_defined 1 st_mtim STATX_MTIME 0x00000040U exec_path_env _BITS_STRING_FORTIFIED_H 1 CR0 0000000 other_cmds B300 0000007 ONLCR 0000004 B200 0000006 ECHOPRT 0002000 IEXTEN 0100000 NCCS 32 FF1 0100000 B150 0000005 list_commands_in_dir B4000000 0010017 readdir64 TCSADRAIN 1 FLUSHO 0010000 B460800 0010004 INLCR 0000100 ECHOKE 0004000 XTABS 0014000 NL0 0000000 IUTF8 0040000 putchar B1000000 0010010 CREAD 0000200 __printf_chk VMIN 6 __builtin_memset ONLRET 0000040 __isoc23_strtol TCIFLUSH 0 TCIOFF 2 ECHO 0000010 add_cmdname B1500000 0010012 __SUBCMD_HELP_H TAB2 0010000 IXANY 0004000 PARENB 0000400 B57600 0010001 exclude_cmds OFILL 0000100 VT1 0040000 VEOL2 16 TCSAFLUSH 2 ISIG 0000001 ICRNL 0000400 B3000000 0010015 B50 0000001 load_command_list main_cmds cmdname_compare B1800 0000012 _HAVE_STRUCT_TERMIOS_C_ISPEED 1 ICANON 0000002 B75 0000002 B600 0000010 CMSPAR 010000000000 entlen mput_char pretty_print_string_list VQUIT 1 CEOL '\0' ECHOE 0000020 B3500000 0010016 _TERMIOS_H 1 strstarts TCOON 1 title xrealloc get_term_dimensions TCOOFF 0 BS0 0000000 ECHOK 0000040 B110 0000003 B1152000 0010011 VEOF 4 HUPCL 0002000 OPOST 0000001 B500000 0010005 ws_row TCIOFLUSH 2 VERASE 2 B2000000 0010013 VKILL 3 extlen B19200 0000016 ECHONL 0000100 CSIZE 0000060 rows CIBAUD 002003600000 OFDEL 0000200 ECHOCTL 0001000 TAB0 0000000 TCION 3 TABDLY 0014000 PENDIN 0040000 VSTOP 9 IMAXBEL 0020000 B2500000 0010014 NLDLY 0000400 CBAUD 000000010017 IXOFF 0010000 OCRNL 0000010 BSDLY 0020000 longest CR3 0003000 B230400 0010003 VWERASE 14 winsize EXTA B19200 NL1 0000400 VEOL 11 CLOCAL 0004000 __nptr uniq IGNBRK 0000001 NOFLSH 0000200 BRKINT 0000002 B4800 0000014 __len XCASE 0000004 is_executable is_in_cmdlist FF0 0000000 VSUSP 10 ISTRIP 0000040 FFDLY 0100000 INPCK 0000020 PARODD 0001000 TAB3 0014000 __MAX_BAUD B4000000 B9600 0000015 VTDLY 0040000 PARMRK 0000010 B38400 0000017 CR1 0001000 colon EXTPROC 0200000 B134 0000004 TAB1 0004000 B1200 0000011 excludes B115200 0010002 CSTATUS '\0' TCOFLUSH 1 B2400 0000013 VSTART 8 max_cols IUCLC 0001000 CRTSCTS 020000000000 CS5 0000000 list_commands CSTOPB 0000100 B576000 0010006 closedir clean_cmdnames CBAUDEX 000000010000 CS6 0000020 _HAVE_STRUCT_TERMIOS_C_OSPEED 1 ONOCR 0000020 ADDRB 04000000000 VREPRINT 12 IGNPAR 0000004 EXTB B38400 CCEQ(val,c) ((c) == (val) && (val) != _POSIX_VDISABLE) ws_ypixel ws_xpixel CS8 0000060 CS7 0000040 CRDLY 0003000 ws_col has_extension TCSANOW 0 IXON 0002000 VSWTC 7 BS1 0020000 VTIME 5 VT0 0000000 IGNCR 0000200 OLCUC 0000002 TOSTOP 0000400 env_path VLNEXT 15 VDISCARD 13 readdir prefix_len VINTR 0 CR2 0002000 B921600 0010007 sigchain_fun si_status _sifields._sigchld.si_status SIGALRM 14 __stack_t_defined 1 si_call_addr _sifields._sigsys._call_addr POLL_OUT POLL_OUT SIGCLD SIGCHLD BUS_MCEERR_AR BUS_MCEERR_AR SIGRTMIN (__libc_current_sigrtmin ()) __SUBCMD_RUN_COMMAND_H ILL_PRVOPC ILL_PRVOPC isatty si_lower _sifields._sigfault._bounds._addr_bnd._lower _BITS_SIGINFO_CONSTS_ARCH_H 1 POLL_PRI POLL_PRI SA_NOCLDWAIT 2 SEGV_MTEAERR SEGV_MTEAERR SEGV_ACCADI SEGV_ACCADI SI_QUEUE SI_QUEUE si_syscall _sifields._sigsys._syscall BUS_MCEERR_AO BUS_MCEERR_AO si_upper _sifields._sigfault._bounds._addr_bnd._upper SIGEV_NONE SIGEV_NONE _BITS_SIGSTACK_H 1 SIGINT 2 _NSIG (__SIGRTMAX + 1) REG_CR2 REG_CR2 SIGPROF 27 REG_RDI REG_RDI SA_STACK SA_ONSTACK REG_RIP REG_RIP _BITS_SS_FLAGS_H 1 spawned_pager sa_sigaction __sigaction_handler.sa_sigaction sigev_notify_function _sigev_un._sigev_thread._function _SIGNAL_H FPE_INTDIV FPE_INTDIV no_stderr __SI_ASYNCIO_AFTER_SIGIO 1 __SI_CLOCK_T __clock_t SEGV_MAPERR SEGV_MAPERR REG_RDX REG_RDX SEGV_ACCERR SEGV_ACCERR __SUBCMD_PAGER_H pager_init SI_USER SI_USER FPE_INTOVF FPE_INTOVF SIGURG 23 SIGBUS 7 SIGCHLD 17 REG_R11 REG_R11 FPE_FLTUNK FPE_FLTUNK REG_R12 REG_R12 REG_R13 REG_R13 si_addr _sifields._sigfault.si_addr REG_R14 REG_R14 atexit SIGSYS 31 REG_R15 REG_R15 pager_process SEGV_PKUERR SEGV_PKUERR __fd_mask sigmask(sig) __glibc_macro_warning ("sigmask is deprecated") ((int)(1u << ((sig) - 1))) __sigevent_t_defined 1 __fdelt_chk REG_R10 REG_R10 SIGIOT SIGABRT FPE_FLTINV FPE_FLTINV TRAP_HWBKPT TRAP_HWBKPT exception SI_KERNEL SI_KERNEL _BITS_SIGNUM_ARCH_H 1 fflush __SI_ERRNO_THEN_CODE 1 MINSIGSTKSZ 2048 ILL_PRVREG ILL_PRVREG __SIGRTMIN 32 si_ptr _sifields._rt.si_sigval.sival_ptr REG_TRAPNO REG_TRAPNO _SYS_UCONTEXT_H 1 __suseconds_t SEGV_ADIPERR SEGV_ADIPERR ILL_ILLTRP ILL_ILLTRP tv_usec wait_for_pager SIGXCPU 24 __SI_MAX_SIZE 128 SA_RESETHAND 0x80000000 sigchain_push_common REG_RSI REG_RSI si_stime _sifields._sigchld.si_stime si_timerid _sifields._timer.si_tid SEGV_ADIDERR SEGV_ADIDERR SIGILL 4 SIGTTIN 21 TRAP_BRKPT TRAP_BRKPT _BITS_SIGCONTEXT_H 1 _BITS_SIGNUM_GENERIC_H 1 no_stdout no_stdin SA_SIGINFO 4 __SUBCMD_SIGCHAIN_H si_overrun _sifields._timer.si_overrun __SIGEV_MAX_SIZE 64 SIGSEGV 11 preexec_cb select ____sigval_t_defined __SI_BAND_TYPE long int MINSIGSTKSZ SIGSTKSZ _BITS_SIGINFO_CONSTS_H 1 SA_INTERRUPT 0x20000000 SI_ASYNCIO SI_ASYNCIO si_uid _sifields._kill.si_uid _BITS_SIGACTION_H 1 SIGPWR 30 pager_get_columns REG_OLDMASK REG_OLDMASK REG_R8 REG_R8 CLD_CONTINUED CLD_CONTINUED _BITS_SIGTHREAD_H 1 REG_CSGSFS REG_CSGSFS __ctx(fld) fld fds_bits IS_RUN_COMMAND_ERR(x) (-(x) >= ERR_RUN_COMMAND_FORK) si_value _sifields._rt.si_sigval REG_R9 REG_R9 FPE_FLTUND FPE_FLTUND pager_columns FPE_CONDTRAP FPE_CONDTRAP __NGREG 23 FPE_FLTRES FPE_FLTRES CLD_EXITED CLD_EXITED SEGV_MTESERR SEGV_MTESERR CLD_DUMPED CLD_DUMPED pager_preexec __SIGEV_PAD_SIZE ((__SIGEV_MAX_SIZE / sizeof (int)) - 4) FPE_FLTSUB FPE_FLTSUB si_band _sifields._sigpoll.si_band SIGUSR1 10 SIGUSR2 12 stdout_to_stderr __sig_atomic_t_defined 1 __fdelt_warn SA_ONSTACK 0x08000000 SIG_ERR ((__sighandler_t) -1) SS_DISABLE SS_DISABLE SA_ONESHOT SA_RESETHAND SIGKILL 9 SI_MESGQ SI_MESGQ SA_NOCLDSTOP 1 REG_RAX REG_RAX si_pid _sifields._kill.si_pid SIGXFSZ 25 __SI_SIGFAULT_ADDL FP_XSTATE_MAGIC2 0x46505845U POLL_HUP POLL_HUP ILL_COPROC ILL_COPROC timeval SEGV_BNDERR SEGV_BNDERR SIGTTOU 22 SIGSTKSZ 8192 ILL_ILLOPN ILL_ILLOPN SIG_IGN ((__sighandler_t) 1) SIG_BLOCK 0 __siginfo_t_defined 1 SIGRTMAX (__libc_current_sigrtmax ()) fd_set __sigstack_defined 1 SIGTRAP 5 CLD_KILLED CLD_KILLED REG_RSP REG_RSP __SIGRTMAX 64 FP_XSTATE_MAGIC2_SIZE sizeof (FP_XSTATE_MAGIC2) ILL_ILLADR ILL_ILLADR SIGFPE 8 finish_command SIGPOLL 29 forced_pager si_fd _sifields._sigpoll.si_fd __arr SIGWINCH 28 SIGQUIT 3 TRAP_UNK TRAP_UNK SIGTERM 15 REG_ERR REG_ERR force_pager SIGIO SIGPOLL NSIG _NSIG SA_NODEFER 0x40000000 SI_SIGIO SI_SIGIO SEGV_CPERR SEGV_CPERR signo si_utime _sifields._sigchld.si_utime __SI_ALIGNMENT REG_RBP REG_RBP pager_argv ILL_BADSTK ILL_BADSTK SIGHUP 1 SIGSTKFLT 16 REG_RBX REG_RBX REG_EFL REG_EFL SIGTSTP 20 TRAP_BRANCH TRAP_BRANCH ILL_BADIADDR ILL_BADIADDR SIG_DFL ((__sighandler_t) 0) SI_ASYNCNL SI_ASYNCNL SIGEV_THREAD SIGEV_THREAD SA_NOMASK SA_NODEFER sa_handler __sigaction_handler.sa_handler _BITS_SIGINFO_ARCH_H 1 SIGPIPE 13 dup2 SIG_HOLD ((__sighandler_t) 2) FPE_FLTDIV FPE_FLTDIV SIGEV_SIGNAL SIGEV_SIGNAL raise __SI_HAVE_SIGSYS 1 si_int _sifields._rt.si_sigval.sival_int setup_pager FPE_FLTOVF FPE_FLTOVF POLL_IN POLL_IN RUN_COMMAND_NO_STDIN 1 RUN_COMMAND_STDOUT_TO_STDERR 4 sigchain_pop SIGEV_THREAD_ID SIGEV_THREAD_ID FP_XSTATE_MAGIC1 0x46505853U SI_DETHREAD SI_DETHREAD child_process SIGABRT 6 SIG_SETMASK 2 TRAP_TRACE TRAP_TRACE BUS_ADRERR BUS_ADRERR sigev_notify_attributes _sigev_un._sigev_thread._attribute SIGSTKSZ sysconf (_SC_SIGSTKSZ) _BITS_SIGEVENT_CONSTS_H 1 si_addr_lsb _sifields._sigfault.si_addr_lsb pager_in_use BUS_OBJERR BUS_OBJERR __ctx start_command CLD_STOPPED CLD_STOPPED SIG_UNBLOCK 1 POLL_MSG POLL_MSG SIGCONT 18 RUN_EXEC_CMD 2 BUS_ADRALN BUS_ADRALN wait_for_pager_signal SA_RESTART 0x10000000 SS_ONSTACK SS_ONSTACK SIGVTALRM 26 si_pkey _sifields._sigfault._bounds._pkey POLL_ERR POLL_ERR ILL_ILLOPC ILL_ILLOPC SI_TIMER SI_TIMER SI_TKILL SI_TKILL REG_RCX REG_RCX si_arch _sifields._sigsys._arch SIGSTOP 19 __SI_PAD_SIZE ((__SI_MAX_SIZE / sizeof (int)) - 4) CLD_TRAPPED CLD_TRAPPED NGREG __NGREG PARSE_OPT_LASTARG_DEFAULT PARSE_OPT_LIST_SUBCMDS cpu_to_le16 max(x,y) ({ typeof(x) _max1 = (x); typeof(y) _max2 = (y); (void) (&_max1 == &_max2); _max1 > _max2 ? _max1 : _max2; }) is_abbreviated PARSE_OPT_KEEP_DASHDASH roundup(x,y) ( { const typeof(y) __y = y; (((x) + (__y - 1)) / __y) * __y; } ) toupper(c) __tobody (c, toupper, *__ctype_toupper_loc (), (c)) ambiguous_option __PERF_ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) unknown options__order error_buf OPT_CALLBACK_OPTARG(s,l,v,d,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .flags = PARSE_OPT_OPTARG, .data = (d) } BUILD_BUG_ON_INVALID(e) ((void)(sizeof((__force long)(e)))) OPT_INCR(s,l,v,h) { .type = OPTION_INCR, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) } parse_opt_type excl_opt __builtin_memmove ambiguous_flags PARSE_OPT_DISABLED optwarning PARSE_OPT_OPTARG __SUBCMD_PARSE_OPTIONS_H PARSE_OPT_NOEMPTY subcommands strcasestr OPTION_SET_PTR OPTION_BOOLEAN OPT__VERBOSITY(var) { OPTION_CALLBACK, 'v', "verbose", (var), NULL, "be more verbose", PARSE_OPT_NOARG, &parse_opt_verbosity_cb, 0 }, { OPTION_CALLBACK, 'q', "quiet", (var), NULL, "be more quiet", PARSE_OPT_NOARG, &parse_opt_verbosity_cb, 0 } arg_end OPT_ULONG(s,l,v,h) { .type = OPTION_ULONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned long *), .help = (h) } cpu_to_le32 __round_mask(x,y) ((__typeof__(x))((y)-1)) shortopt round_down(x,y) ((x) & ~__round_mask(x, y)) __builtin___snprintf_chk defval internal_help PARSE_OPT_EXCLUSIVE parse_short_opt get_arg PARSE_OPT_NOARG __TOOLS_LINUX_KERNEL_H PARSE_OPT_NOBUILD static_assert _TOOLS_MATH_H PARSE_OPT_KEEP_UNKNOWN OPT_CALLBACK_DEFAULT_NOOPT(s,l,v,a,h,f,d) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .arg = (a), .help = (h), .callback = (f), .defval = (intptr_t)d, .flags = PARSE_OPT_LASTARG_DEFAULT | PARSE_OPT_NOARG} container_of(ptr,type,member) ({ const typeof(((type *)0)->member) * __mptr = (ptr); (type *)((char *)__mptr - offsetof(type, member)); }) toupper_l(c,locale) __toupper_l ((c), (locale)) le64_to_cpu __tolower_l(c,locale) __tobody (c, __tolower_l, (locale)->__ctype_tolower, (c, locale)) OPTION_GROUP check_typos bswap_64(x) __bswap_64 (x) usage_with_options can_skip be16_to_cpu bswap_16 PARSE_OPT_KEEP_ARGV0 _LINUX_BUILD_BUG_H PARSE_OPT_NONEG parse_options_usage assert_perror(errnum) (!(errnum) ? __ASSERT_VOID_CAST (0) : __assert_perror_fail ((errnum), __FILE__, __LINE__, __ASSERT_FUNCTION)) __isoc23_strtoul cpu_to_be64 bswap_64 BUG_ON(cond) assert(!(cond)) usage_with_options_internal min_t(type,x,y) min((type)x, (type)y) parse_options_start option__cmp BUG() BUG_ON(1) OPT_BOOLEAN(s,l,v,h) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h) } ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) USAGE_OPTS_WIDTH 24 OPTION_BIT parse_options_end option__in_argv PARSE_OPT_STOP_AT_NON_OPTION be64_to_cpu bswap_64 set_option_flag parse_long_opt bswap_16(x) __bswap_16 (x) be32_to_cpu bswap_32 OPT_STRING_OPTARG(s,l,v,a,h,d) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh =(a), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d) } BUILD_BUG_ON(condition) BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) OPT_CALLBACK(s,l,v,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f) } usage_with_options_msg max_t(type,x,y) max((type)x, (type)y) parse_opt_ctx_t USAGE_GAP 2 cpu_to_le64 OPT__QUIET(var) OPT_BOOLEAN('q', "quiet", (var), "be quiet") ASSERT_STRUCT_OFFSET(type,field,expected_offset) BUILD_BUG_ON_MSG(offsetof(type, field) != (expected_offset), "Offset of " #field " in " #type " has changed.") PARSE_OPT_HIDDEN clamp(val,lo,hi) min((typeof(val))max(val, lo), hi) tolower_l(c,locale) __tolower_l ((c), (locale)) synchronize_rcu() opterror OPTION_STRING OPT_STRING_OPTARG_SET(s,l,v,os,a,h,d) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d), .set = check_vtype(os, bool *)} parse_opt_cb static_assert _Static_assert OPT_UINTEGER_OPTARG(s,l,v,d,h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d) } OPTION_END BUILD_BUG_ON_MSG(cond,msg) compiletime_assert(!(cond), msg) min(x,y) ({ typeof(x) _min1 = (x); typeof(y) _min2 = (y); (void) (&_min1 == &_min2); _min1 < _min2 ? _min1 : _min2; }) parse_options_subcommand OPT_SET_UINT(s,l,v,h,i) { .type = OPTION_SET_UINT, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .defval = (i) } PARSE_OPT_HELP OPT_LONG(s,l,v,h) { .type = OPTION_LONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, long *), .help = (h) } OPT_CALLBACK_DEFAULT(s,l,v,a,h,f,d) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .defval = (intptr_t)d, .flags = PARSE_OPT_LASTARG_DEFAULT } BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0)) __isoc23_strtoull parse_options_step parse_opt_option_flags longopt __vasprintf_chk full __toupper_l(c,locale) __tobody (c, __toupper_l, (locale)->__ctype_toupper, (c, locale)) OPTION_CALLBACK nr_group reason build_opt PARSE_OPT_DONE ordered OPT_GROUP(h) { .type = OPTION_GROUP, .help = (h) } OPT_BOOLEAN_FLAG(s,l,v,h,f) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h), .flags = (f) } OPTION_LONG OPT_UINTEGER(s,l,v,h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h) } parse_options parse_opt_verbosity_cb DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) OPTION_ULONG OPT_CALLBACK_SET(s,l,v,os,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .set = check_vtype(os, bool *)} fputc OPTION_U64 excl_short_opt cpidx cpu_to_be32 bswap_32 round_up(x,y) ((((x)-1) | __round_mask(x, y))+1) nr_opts OPT_SET_PTR(s,l,v,h,p) { .type = OPTION_SET_PTR, .short_name = (s), .long_name = (l), .value = (v), .help = (h), .defval = (p) } abbrev_flags OPT_CALLBACK_NOOPT(s,l,v,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .flags = PARSE_OPT_NOARG } short_name OPT_INTEGER(s,l,v,h) { .type = OPTION_INTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) } cpu_to_be16 bswap_16 current_gfp_context(k) 0 OPT_SHORT 1 argh __int32_t PERF_ALIGN(x,a) __PERF_ALIGN_MASK(x, (typeof(x))(a)-1) unset PARSE_OPT_CANSKIP _TOOLS_LINUX_PANIC_H OPT_STRING_NOEMPTY(s,l,v,a,h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h), .flags = PARSE_OPT_NOEMPTY} print_option_help parse_opt_flags BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); }))) skip_prefix retry OPTION_UINTEGER le16_to_cpu bswap_32(x) __bswap_32 (x) OPT_BIT(s,l,v,h,b) { .type = OPTION_BIT, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h), .defval = (b) } OPT_STRING(s,l,v,a,h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h) } find_option check_vtype(v,type) ( BUILD_BUG_ON_ZERO(!__builtin_types_compatible_p(typeof(v), type)) + v ) PARSE_OPT_LIST_OPTS OPT_U64(s,l,v,h) { .type = OPTION_U64, .short_name = (s), .long_name = (l), .value = check_vtype(v, u64 *), .help = (h) } set_option_nobuild le32_to_cpu OPTION_INCR usagestr OPTION_ARGUMENT PARSE_OPT_UNKNOWN OPT__DRY_RUN(var) OPT_BOOLEAN('n', "dry-run", (var), "dry run") __ch __ctype_tolower_loc UINT_MAX (~0U) OPTION_SET_UINT OPT_PARENT(p) { .type = OPTION_END, .parent = (p) } OPT_END() { .type = OPTION_END } tolower(c) __tobody (c, tolower, *__ctype_tolower_loc (), (c)) OPT_ARGUMENT(l,h) { .type = OPTION_ARGUMENT, .long_name = (l), .help = (h) } OPT__VERBOSE(var) OPT_BOOLEAN('v', "verbose", (var), "be verbose") noarg OPT__ABBREV(var) { OPTION_CALLBACK, 0, "abbrev", (var), "n", "use <n> digits to display SHA-1s", PARSE_OPT_OPTARG, &parse_opt_abbrev_cb, 0 } optstr get_value OPT_BOOLEAN_SET(s,l,v,os,h) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h), .set = check_vtype(os, bool *)} _RET_IP_ ((unsigned long)__builtin_return_address(0)) OPT_UNSET 2 PARSE_OPT_NO_INTERNAL_HELP __BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON(((n) & ((n) - 1)) != 0) abbrev_option OPT_DATE(s,l,v,h) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = "time", .help = (h), .callback = parse_opt_approxidate_cb } vasprintf long_name OPTION_INTEGER BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") O_DIRECT __O_DIRECT F_SEAL_WRITE 0x0008 __path WAIT_ANY (-1) AT_NO_AUTOMOUNT 0x800 waitpid RWH_WRITE_LIFE_MEDIUM 3 close_pair prepare_run_command_v_opt DN_CREATE 0x00000004 ERR_RUN_COMMAND_FORK putenv STRERR_BUFSIZE 128 SPLICE_F_MOVE 1 O_NOATIME __O_NOATIME RWH_WRITE_LIFE_NOT_SET 0 F_OFD_SETLK 37 LOCK_READ 64 RWH_WRITE_LIFE_SHORT 2 SPLICE_F_MORE 4 dup_devnull MAX_HANDLE_SZ 128 ERR_RUN_COMMAND_WAITPID_SIGNAL DN_MODIFY 0x00000002 SYNC_FILE_RANGE_WRITE_AND_WAIT (SYNC_FILE_RANGE_WRITE | SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WAIT_AFTER) AT_STATX_FORCE_SYNC 0x2000 ERR_RUN_COMMAND_EXEC __open_2 RWF_WRITE_LIFE_NOT_SET RWH_WRITE_LIFE_NOT_SET FALLOC_FL_COLLAPSE_RANGE 0x08 F_SETPIPE_SZ 1031 W_STOPCODE(sig) __W_STOPCODE (sig) LOCK_WRITE 128 AT_STATX_SYNC_TYPE 0x6000 O_TMPFILE __O_TMPFILE __iovec_defined 1 __open_alias SYNC_FILE_RANGE_WAIT_BEFORE 1 run_command ERR_RUN_COMMAND_PIPE F_SEAL_SHRINK 0x0002 FALLOC_FL_KEEP_SIZE 0x01 __idtype_t_defined AT_RECURSIVE 0x8000 F_GETLEASE 1025 SPLICE_F_GIFT 8 AT_STATX_DONT_SYNC 0x4000 F_SETSIG __F_SETSIG F_SET_FILE_RW_HINT 1038 FALLOC_FL_UNSHARE_RANGE 0x40 ERR_RUN_COMMAND_WAITPID_NOEXIT WAIT_MYPGRP 0 F_OFD_SETLKW 38 O_PATH __O_PATH LOCK_MAND 32 ERR_RUN_COMMAND_WAITPID DN_MULTISHOT 0x80000000 waiting RWH_WRITE_LIFE_NONE 1 need_in chdir F_SEAL_FUTURE_WRITE 0x0010 need_err DN_ACCESS 0x00000001 need_out DN_DELETE 0x00000008 AT_STATX_SYNC_AS_STAT 0x0000 F_SET_RW_HINT 1036 SYNC_FILE_RANGE_WAIT_AFTER 4 F_GET_SEALS 1034 __open_missing_mode __open_too_many_args DN_RENAME 0x00000010 AT_EMPTY_PATH 0x1000 RWH_WRITE_LIFE_LONG 4 LOCK_RW 192 F_GETSIG __F_GETSIG wait_or_whine fderr __oflag SYNC_FILE_RANGE_WRITE 2 fdout WCOREDUMP(status) __WCOREDUMP (status) __open64_2 F_SETOWN_EX __F_SETOWN_EX _SYS_WAIT_H 1 F_OFD_GETLK 36 ERR_RUN_COMMAND_WAITPID_WRONG_PID DN_ATTRIB 0x00000020 F_GET_RW_HINT 1035 F_SETLEASE 1024 F_ADD_SEALS 1033 _FALLOC_H_ F_SEAL_SEAL 0x0001 RWH_WRITE_LIFE_EXTREME 5 FALLOC_FL_ZERO_RANGE 0x10 F_SEAL_GROW 0x0004 FALLOC_FL_INSERT_RANGE 0x20 F_SEAL_EXEC 0x0020 FALLOC_FL_NO_HIDE_STALE 0x04 fdin unsetenv F_GET_FILE_RW_HINT 1037 F_NOTIFY 1026 FALLOC_FL_PUNCH_HOLE 0x02 AT_HANDLE_FID AT_REMOVEDIR W_EXITCODE(ret,sig) __W_EXITCODE (ret, sig) F_GETOWN_EX __F_GETOWN_EX WCOREFLAG __WCOREFLAG SPLICE_F_NONBLOCK 2 F_GETPIPE_SZ 1032 signals sigchain_push SIGCHAIN_MAX_SIGNALS 32 sigchain_signal check_signum UNDEFINED "SUBCMD_HAS_NOT_BEEN_INITIALIZED" LL_DELTA (1 << 5) ET_CORE 4 EF_SPARCV9_MM 3 R_MIPS_CALL16 11 R_TILEGX_HW0 9 DT_PPC_NUM 2 AT_SYSINFO 32 EM_SLE9X 179 isascii(c) (((unsigned char)(c))<=0x7f) R_386_TLS_LDM_CALL 30 R_MN10300_NUM 35 R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 EF_ARM_HASENTRY 0x02 R_METAG_LO16_GOTOFF 33 R_METAG_TLS_DTPOFF 58 R_SPARC_16 2 R_SH_CODE 30 DT_MIPS_RLD_MAP_REL 0x70000035 ELF_NOTE_OS_FREEBSD 3 _X 0x40 R_MICROBLAZE_TLS 22 MIPS_AFL_ASE_MASK 0x00001fff PF_IA_64_NORECOV 0x80000000 MIPS_AFL_EXT_XLR 1 R_68K_TLS_GD8 27 R_68K_32 1 R_TILEGX_TLS_TPOFF32 111 NT_GNU_PROPERTY_TYPE_0 5 R_AARCH64_P32_COPY 180 R_PPC64_JMP_SLOT R_PPC_JMP_SLOT R_PARISC_LTOFF_TP14WR 227 DT_PROCNUM DT_MIPS_NUM islower(c) ((__ismask(c)&(_L)) != 0) EF_ARM_VFP_FLOAT 0x400 R_TILEPRO_IMM8_Y1 20 R_IA64_DTPMOD64LSB 0xa7 R_X86_64_GOT32 3 R_386_RELATIVE 8 R_PPC64_PLT16_HI R_PPC_PLT16_HI AT_EUID 12 GNU_PROPERTY_HIUSER 0xffffffff STT_NOTYPE 0 R_PPC_NONE 0 R_PPC_EMB_NADDR16_HI 104 R_SPARC_GOTDATA_OP_HIX22 82 R_386_GOTOFF 9 PPC64_OPT_MULTI_TOC 2 R_METAG_RELBRANCH 4 R_TILEGX_IMM16_X1_HW2_PCREL 55 SHT_HIUSER 0x8fffffff R_SPARC_GOTDATA_OP_LOX10 83 R_RISCV_RVC_JUMP 45 DT_GNU_LIBLISTSZ 0x6ffffdf7 DF_1_NODELETE 0x00000008 R_PPC64_GOT_TLSGD16_LO 80 R_386_GOT32 3 R_TILEPRO_TLS_TPOFF32 84 EM_ARC 45 R_TILEPRO_DEST_IMM8_X1 55 SHF_ARM_COMDEF 0x80000000 DT_AUDIT 0x6ffffefc DT_MIPS_INTERFACE 0x7000002a EM_NORC 218 EM_R32C 162 R_AARCH64_LDST16_ABS_LO12_NC 284 GNU_PROPERTY_X86_ISA_1_USED 0xc0010002 EF_MIPS_ABI_EABI32 0x00003000 EM_PDP10 64 MIPS_AFL_ASE_EVA 0x00000004 R_AARCH64_TLS_DTPREL 1029 EM_M16C 117 R_ARM_ME_TOO 128 DT_MIPS_TIME_STAMP 0x70000002 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 NT_ARM_HW_BREAK 0x402 SHN_HIPROC 0xff1f R_METAG_HIADDR16 0 R_IA64_DTPREL64LSB 0xb7 R_TILEPRO_IMM16_X0_TLS_GD_HI 70 R_CKCORE_TLS_LE32 51 EF_CSKY_ABIV2 0X20000000 SHF_LINK_ORDER (1 << 7) R_MIPS16_TLS_DTPREL_HI16 108 R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 R_CKCORE_PCREL_IMM26BY2 19 EM_UNICORE 110 PN_XNUM 0xffff EM_SPARC32PLUS 18 R_390_JMP_SLOT 11 R_LARCH_TLS_IE_HI20 91 R_MIPS_HI16 5 R_PARISC_LORESERVE 128 R_ARC_S21H_PCREL_PLT 0x4D R_ARC_24 0x3 R_ARM_TLS_LE32 108 R_MIPS_26 4 R_PARISC_GNU_VTINHERIT 233 R_ARM_TLS_DTPOFF32 18 R_SPARC_HI22 9 EF_ARM_EABI_UNKNOWN 0x00000000 R_CKCORE_TLS_TPOFF32 58 R_LARCH_ADD6 105 R_OR1K_TLS_IE_HI16 28 ispunct(c) ((__ismask(c)&(_P)) != 0) R_CKCORE_GOTPC_HI16 26 R_BPF_64_64 1 R_PPC_SDAREL16 32 R_LARCH_SOP_PUSH_PLT_PCREL 29 DT_BIND_NOW 24 MIPS_AFL_ASE_DSP 0x00000001 R_SPARC_SIZE64 87 EM_INTELGT 205 R_TILEPRO_IMM16_X1_HI 28 R_68K_TLS_DTPMOD32 40 R_MN10300_TLS_LE 29 EM_ECOG16 176 R_AARCH64_RELATIVE 1027 R_IA64_DTPREL14 0xb1 R_BPF_64_32 10 DT_ENCODING 32 R_MIPS_CALL_HI16 30 SHT_REL 9 R_AARCH64_ABS32 258 R_390_GOTPLT64 32 AT_UCACHEBSIZE 21 R_SPARC_GLOB_DAT 20 R_IA64_SUB 0x85 EF_MIPS_MACH_IAMR2 0x00930000 EF_MIPS_MACH_3900 0x00810000 NT_PPC_SPE 0x101 R_PARISC_TPREL14R 158 R_PARISC_PCREL17R 11 R_ARC_SDA16_LD1 0x17 R_X86_64_GOTPC32 26 PT_PARISC_UNWIND 0x70000001 R_MICROMIPS_HIGHER 151 EM_68HC16 69 NT_PSINFO 13 R_PARISC_PLTOFF16DF 119 R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 EM_H8_300H 47 OHW_R8KPFETCH 0x2 R_ARM_ABS12 6 _GCC_MAX_ALIGN_T DF_1_GLOBAUDIT 0x01000000 R_386_TLS_LDO_32 32 R_PARISC_TPREL64 216 R_ARM_ALU_SB_G1 73 R_ARC_PLT32 0x34 R_ALPHA_REFQUAD 2 EM_KM32 210 R_MICROMIPS_HI0_LO16 157 EF_SPARCV9_TSO 0 AT_NOTELF 10 R_OR1K_TLS_GD_HI16 22 SHN_XINDEX 0xffff R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 R_METAG_TLS_GD 47 R_ALPHA_DTPREL64 33 EF_PPC_RELOCATABLE_LIB 0x00008000 R_M32R_RELA_GNU_VTENTRY 44 EI_ABIVERSION 8 R_PPC64_TPREL16_HIGHESTA 100 EM_ST9PLUS 67 toascii(c) (((unsigned char)(c))&0x7f) R_IA64_FPTR64LSB 0x47 LL_DELAY_LOAD (1 << 4) R_AARCH64_NONE 0 DT_PLTGOT 3 R_CKCORE_GLOB_DAT 11 R_AARCH64_MOVW_SABS_G1 271 R_IA64_PCREL64I 0x7b symbol_name R_X86_64_GOTTPOFF 22 R_SPARC_WDISP10 88 VER_DEF_CURRENT 1 MIPS_AFL_REG_32 0x01 R_IA64_LTOFF22 0x32 R_TILEPRO_IMM16_X1_TLS_GD_LO 69 R_TILEGX_IMM16_X1_HW0_GOT 65 R_ARM_RSBREL32 250 R_TILEGX_IMM16_X1_HW0 37 EF_MIPS_XGOT 8 R_PPC_GOT_DTPREL16_HI 93 R_PPC_ADDR16_LO 4 NT_VMCOREDD 0x700 R_M32R_NONE 0 R_ARM_THM_MOVT_BREL 88 R_MN10300_PCREL8 6 R_AARCH64_MOVW_GOTOFF_G3 306 R_PARISC_TLS_DTPOFF64 245 R_PPC64_TPREL16_LO_DS 96 R_MICROMIPS_GOT_HI16 148 ELF64_R_SYM(i) ((i) >> 32) DF_STATIC_TLS 0x00000010 R_SPARC_TLS_LDO_ADD 66 EF_ARM_EABI_VER1 0x01000000 EM_M32 1 R_RISCV_BRANCH 16 R_68K_GOT16O 11 MIPS_AFL_EXT_3900 10 NT_PPC_TM_CTAR 0x10d DF_1_EDITED 0x00200000 R_68K_PLT8 15 R_386_TLS_DESC_CALL 40 R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 EM_XIMO16 170 R_PARISC_PCREL14DR 76 NT_ARM_PACG_KEYS 0x408 R_PARISC_SEGREL32 49 R_TILEGX_IMM16_X0_HW0_PCREL 50 DT_GNU_HASH 0x6ffffef5 R_TILEPRO_IMM16_X1_PCREL 32 PPC64_LOCAL_ENTRY_OFFSET(other) (((1 << (((other) & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT)) >> 2) << 2) NT_X86_XSTATE 0x202 R_PPC_EMB_RELST_HI 113 R_NDS32_32_RELA 20 ELFOSABI_NONE 0 R_LARCH_PCALA64_LO20 73 R_OR1K_TLS_TPOFF 32 DT_MIPS_OPTIONS 0x70000029 ELF64_ST_BIND(val) ELF32_ST_BIND (val) R_M32R_SDA16 10 R_TILEGX_HW3 12 R_ARC_S21W_PCREL 0xF R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 R_PPC_RELATIVE 22 R_PARISC_DIR16F 85 R_PPC_GOT_TLSGD16_HA 82 R_MIPS_HIGHEST 29 R_PPC_GOT_TLSGD16 79 R_ALPHA_DTPMOD64 31 R_PPC_EMB_MRKREF 110 tolower(c) __tolower(c) SHT_PARISC_DOC 0x70000002 EF_ARM_NEW_ABI 0x80 R_NIOS2_TLS_DTPREL 34 R_AARCH64_TLSLE_ADD_TPREL_HI12 549 R_LARCH_JUMP_SLOT 5 EM_SE_C33 107 R_NIOS2_IMM6 7 DT_MIPS_DELTA_SYM 0x7000001d R_PPC64_PLT64 45 STT_OBJECT 1 R_68K_GOT32O 10 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 AT_L1I_CACHESIZE 40 SHF_ARM_ENTRYSECT 0x10000000 MIPS_AFL_FLAGS1_ODDSPREG 1 R_M32R_GOTPC_HI_SLO 60 GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS (1U << 0) R_BPF_NONE 0 SHF_PARISC_SHORT 0x20000000 R_PPC64_PLTREL64 46 R_RISCV_SET16 55 R_ARC_S25H_PCREL_PLT 0x3D ODK_HWOR 8 R_LARCH_B21 65 R_MICROBLAZE_NONE 0 SHT_GNU_ATTRIBUTES 0x6ffffff5 R_ARM_GOT_ABS 95 R_TILEGX_IMM16_X1_HW0_TLS_GD 79 EM_XCORE 203 R_RISCV_PLT32 59 R_PARISC_PLABEL14R 70 DT_FILTER 0x7fffffff R_NIOS2_CALL26 4 R_SPARC_TLS_LDM_HI22 60 R_ARC_S21H_PCREL 0xE R_TILEGX_NUM 130 EF_MIPS_ARCH_32R2 0x70000000 R_ARM_TLS_DTPMOD32 17 R_AARCH64_MOVW_PREL_G0_NC 288 EM_SE_C17 139 PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) R_X86_64_TLSGD 19 R_TILEPRO_IMM8_X1 19 R_PPC64_GOT_TLSGD16_HI 81 EM_AARCH64 183 R_TILEGX_DEST_IMM8_X1 27 R_LARCH_SOP_SL 33 R_IA64_SECREL32LSB 0x65 EF_SH3E 0x8 LL_EXPORTS (1 << 3) R_ARM_ALU_SB_G0_NC 70 R_PPC_REL14 11 DT_MIPS_ICHECKSUM 0x70000003 R_PPC_ADDR32 1 PT_GNU_RELRO 0x6474e552 R_IA64_FPTR64I 0x43 R_RISCV_TLS_DTPREL32 8 R_ARM_ABS32_NOI 55 R_RISCV_32 1 R_PPC64_DTPREL64 78 EM_SPARCV9 43 R_TILEPRO_IMM16_X1 24 EF_ARM_ALIGN8 0x40 DT_PPC64_OPT (DT_LOPROC + 3) VER_DEF_NONE 0 NT_PPC_DEXCR 0x111 R_ARM_THM_PC22 10 MIPS_AFL_ASE_XPA 0x00001000 DT_MIPS_NUM 0x37 NT_S390_VXRS_LOW 0x309 R_ARM_MOVW_ABS_NC 43 R_LARCH_SUB32 55 OEX_FPU_DIV0 0x08 R_M32R_26_PCREL 6 R_MIPS16_TLS_TPREL_LO16 112 NT_LOONGARCH_HW_WATCH 0xa06 __toupper OHW_R4KEOP 0x1 R_PARISC_LTOFF_TP16F 229 R_CRIS_16 2 R_SPARC_NUM 253 DT_SYMINENT 0x6ffffdff EF_MIPS_MACH_4100 0x00830000 EF_RISCV_FLOAT_ABI_SOFT 0x0000 R_X86_64_PC8 15 R_PARISC_GPREL21L 26 R_X86_64_TLSDESC 36 kallsyms__is_function OEX_FPU_MAX 0x1f00 R_MIPS16_PC16_S1 113 R_ARM_SWI24 13 R_MN10300_PCREL32 4 R_MIPS16_HI16 104 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 R_PPC64_REL32 R_PPC_REL32 DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 R_PPC_REL14_BRNTAKEN 13 R_MICROBLAZE_TLSTPREL32 29 RHF_PIXIE (1 << 8) R_ARC_NONE 0x0 DT_ALPHA_PLTRO (DT_LOPROC + 0) STT_PARISC_MILLICODE 13 R_MICROMIPS_TLS_TPREL_HI16 169 R_CKCORE_ADDR_LO16 25 EV_NONE 0 R_CKCORE_DOFFSET_IMM18 44 R_PARISC_TPREL21L 154 PF_HP_NEAR_SHARED 0x00400000 DT_MIPS_DELTA_CLASS_NO 0x70000018 R_MICROBLAZE_64_PCREL 3 kallsyms__parse ELFCOMPRESS_ZSTD 2 R_PPC64_DTPREL16_HIGHERA 104 EM_VPP500 17 _L 0x02 R_METAG_GETSET_GOT 35 R_PPC64_GOT16_LO_DS 59 STT_NUM 7 R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 98 EM_FT32 222 AT_L2_CACHESIZE 44 R_ARM_MOVW_PREL_NC 45 R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 OEX_FPU_MIN 0x1f R_MICROMIPS_GOT_PAGE 146 R_MIPS_TLS_DTPREL64 41 R_AARCH64_LD64_GOTPAGE_LO15 313 R_PPC_REL14_BRTAKEN 12 R_CRIS_8 1 SHF_MIPS_ADDR 0x40000000 NT_ARM_SVE 0x405 R_IA64_TPREL64LSB 0x97 R_ARC_NPS_CMEM16 0x4E PF_PARISC_SBP 0x08000000 EM_OPEN8 196 R_IA64_PLTOFF22 0x3a EF_ARM_EABI_VER3 0x03000000 EF_SPARC_SUN_US1 0x000200 AT_HWCAP 16 R_TILEPRO_IMM16_X0_LO_PCREL 33 R_METAG_TLS_IENONPIC 53 STB_GLOBAL 1 R_PARISC_PCREL21L 10 ELFCOMPRESS_LOPROC 0x70000000 R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 R_390_GOTPLT16 30 R_IA64_PCREL21B 0x49 SHF_OS_NONCONFORMING (1 << 8) AT_FPUCW 18 DT_MIPS_DELTA_CLASSSYM 0x70000020 R_PPC64_ADDR16_LO_DS 57 R_TILEPRO_TLS_GD_CALL 60 R_CRIS_16_GOT 13 R_390_GOT64 24 NT_ARM_HW_WATCH 0x403 R_ARM_ALU_PC_G1 60 R_AC_SECTOFF_U8_2 0x25 R_IA64_LTOFF_FPTR64LSB 0x57 R_MIPS_PJUMP 35 R_TILEGX_COPY 16 NT_GWINDOWS 7 SHT_LOPROC 0x70000000 EM_MAX 102 R_PPC64_REL14 R_PPC_REL14 R_SPARC_PLT64 47 R_AARCH64_CONDBR19 280 R_TILEPRO_MMEND_X0 48 R_MICROBLAZE_JUMP_SLOT 17 R_RISCV_CALL_PLT 19 R_ARC_TLS_GD_GOT 0x45 R_ARM_BASE_ABS 31 R_LARCH_GOT64_PC_LO20 77 ELFOSABI_GNU 3 R_ARM_THM_MOVW_ABS_NC 47 STT_SECTION 3 R_X86_64_GOTPLT64 30 R_SH_DATA 31 R_68K_8 3 MIPS_AFL_EXT_4650 7 SHT_ALPHA_DEBUG 0x70000001 RHF_GUARANTEE_INIT (1 << 5) R_TILEGX_32_PCREL 6 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 EF_MIPS_ARCH_ASE_M16 0x04000000 R_ARM_TARGET1 38 DT_VALRNGHI 0x6ffffdff SHT_SHLIB 10 EM_88K 5 R_M32R_GOTPC_LO 61 R_ARM_ALU_PCREL_15_8 33 DF_1_SINGLETON 0x02000000 R_PPC_TPREL16 69 R_OR1K_TLS_DTPMOD 34 EM_OPENRISC 92 NT_PRXFPREG 0x46e62b7f R_CKCORE_TLS_GD32 53 R_M32R_24 3 NT_PPC_PMU 0x107 R_X86_64_NUM 43 MIPS_AFL_ASE_MIPS3D 0x00000020 NT_X86_SHSTK 0x204 R_TILEPRO_IMM16_X1_TLS_GD 67 R_PPC_DTPREL16_HA 77 R_CKCORE_TLS_DTPMOD32 56 R_CKCORE_PCREL32 5 R_68K_TLS_LE8 39 R_68K_RELATIVE 22 R_ARM_XPC25 15 R_PPC64_TPREL16_LO 70 R_ARM_AMP_VCALL9 12 R_PPC64_DTPREL16_HA 77 R_MIPS_PC16 10 EF_SH2 0x2 R_SH_TLS_DTPMOD32 149 R_CKCORE_TLS_LDM32 54 SHT_X86_64_UNWIND 0x70000001 R_PPC_GOT16 14 R_LARCH_SUB8 52 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 R_PARISC_LTOFF16F 101 DT_PREINIT_ARRAYSZ 33 R_TILEPRO_IMM16_X1_TLS_IE 75 R_ALPHA_SREL64 11 EM_CLOUDSHIELD 192 R_METAG_GLOB_DAT 46 R_M32R_GOTOFF_HI_SLO 63 SHF_STRINGS (1 << 5) AT_PAGESZ 6 R_MIPS16_CALL16 103 R_68K_GOT8O 12 R_386_TLS_TPOFF 14 AT_L1I_CACHESHAPE 34 R_TILEPRO_IMM16_X1_GOT 40 MIPS_AFL_EXT_SB1 12 R_ARC_COPY 0x35 R_NIOS2_GOTOFF_HA 25 R_ARM_THM_GOT_BREL12 131 EM_VAX 75 SHT_GNU_verneed 0x6ffffffe R_MICROBLAZE_GOT_64 14 R_PARISC_GPREL64 88 R_PPC64_TPREL16_HIGHERA 98 R_AC_SECTOFF_S9_2 0x28 DF_P1_GROUPPERM 0x00000002 R_LARCH_64_PCREL 109 R_TILEGX_JMP_SLOT 18 SHT_MIPS_DWARF 0x7000001e SHT_GNU_LIBLIST 0x6ffffff7 R_ARM_LDC_SB_G1 82 R_MIPS_GNU_VTINHERIT 253 R_TILEGX_IMM16_X0_HW0_PLT_PCREL 66 R_LARCH_TLS_GD_PC_HI20 97 R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 EM_VIDEOCORE 95 R_PPC64_ADDR16_HIGHER 39 R_CRIS_RELATIVE 12 STT_FILE 4 R_MN10300_TLS_TPOFF 32 R_ARM_ALU_PCREL_23_15 34 NT_S390_TIMER 0x301 R_TILEGX_HW1_LAST 14 NT_VERSION 1 R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45 R_PARISC_EPLT 130 PT_HP_CORE_KERNEL (PT_LOOS + 0x3) GNU C11 13.3.0 -mtune=generic -march=x86-64 -ggdb3 -std=gnu11 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection R_PPC_DIAB_RELSDA_LO 183 R_68K_PC8 6 R_PPC64_TOC16_LO_DS 64 EF_SH2A_SH4_NOFPU 0x15 R_AARCH64_TLSLE_MOVW_TPREL_G1 545 R_TILEPRO_RELATIVE 13 R_390_TLS_TPOFF 56 R_MICROBLAZE_64 5 SHT_MIPS_LOCSTR 0x70000018 R_ARC_H30_ME 0x20 R_PARISC_DPREL21L 18 STN_UNDEF 0 R_ARM_CALL 28 ELF64_ST_INFO(bind,type) ELF32_ST_INFO ((bind), (type)) _LINUX_CTYPE_H PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 2) R_ARC_SDA32 0x12 R_LARCH_ABS64_HI12 70 EF_SH2A 0xd R_METAG_TLS_IENONPIC_LO16 55 R_PPC_DTPREL16 74 EF_ARM_EABI_VER5 0x05000000 R_PPC_REL16_HA 252 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 EI_MAG3 3 R_LARCH_GOT_PC_LO12 76 R_RISCV_RELAX 51 R_IA64_DTPREL64I 0xb3 SHN_UNDEF 0 STT_COMMON 5 R_68K_PC32 4 EM_56800EX 200 R_PPC64_GOT_TPREL16_HA 90 EF_MIPS_MACH_OCTEON 0x008b0000 EF_CSKY_OTHER 0X0FFF0000 NT_PRPSINFO 3 R_TILEGX_IMM16_X1_HW0_PLT_PCREL 67 R_PPC_GOT_TLSLD16_HA 86 R_PPC_TLSGD 95 EM_68HC05 72 SHT_MIPS_PACKAGE 0x70000007 R_AARCH64_PREL16 262 R_CKCORE_ADDRPLT_LO16 39 EF_MIPS_MACH_SB1 0x008a0000 R_68K_TLS_LDO16 32 PT_HP_HSL_ANNOT (PT_LOOS + 0x13) EM_MAXQ30 169 R_METAG_LO16_GOTPC 37 GNU_PROPERTY_HIPROC 0xdfffffff R_AARCH64_MOVW_PREL_G0 287 R_PARISC_LTOFF14DR 100 R_CKCORE_PCRELJSR_IMM11BY2 6 GNU_PROPERTY_X86_ISA_1_V3 (1U << 2) DT_PLTREL 20 R_PARISC_PLTOFF16F 117 R_LARCH_32 1 PPC_OPT_TLS 1 R_MICROMIPS_CALL_LO16 154 R_MN10300_ALIGN 34 R_LARCH_TLS_DTPREL64 9 EM_NUM 259 MIPS_AFL_ASE_VIRT 0x00000100 R_ARM_JUMP_SLOT 22 R_PPC_EMB_NADDR16_LO 103 EM_SNP1K 99 NT_ARM_PACA_KEYS 0x407 DT_MIPS_SYMTABNO 0x70000011 EF_PPC64_ABI 3 LL_EXACT_MATCH (1 << 0) EF_MIPS_ABI_ON32 64 EM_RX 173 R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 EF_PARISC_TRAPNIL 0x00010000 R_IA64_PLTOFF64LSB 0x3f R_X86_64_SIZE64 33 R_390_GOT20 58 RHF_NOTPOT (1 << 1) R_PPC64_TOC16_LO 48 R_AARCH64_MOVW_UABS_G2_NC 268 R_LARCH_CFA 104 R_TILEGX_IMM16_X1_HW1_LAST 47 R_CKCORE_PCRELIMM8BY4 2 R_MIPS_SHIFT5 16 R_AARCH64_PREL32 261 R_RISCV_64 2 DF_1_NORELOC 0x00400000 R_CKCORE_ADDRPLT 18 R_SPARC_WDISP22 8 SHT_INIT_ARRAY 14 EF_ARM_DYNSYMSUSESEGIDX 0x08 R_PPC_TLS 67 R_CKCORE_PCREL_IMM16BY4 21 EF_MIPS_FP64 512 R_SPARC_PC22 17 R_ALPHA_NONE 0 AT_MINSIGSTKSZ 51 R_TILEPRO_8 3 R_PPC_GOT_DTPREL16 91 R_ALPHA_GOTTPREL 37 R_ARC_GOTPC32 0x33 DT_GNU_PRELINKED 0x6ffffdf5 R_AARCH64_MOVW_GOTOFF_G1_NC 303 DF_SYMBOLIC 0x00000002 EF_LARCH_ABI_SOFT_FLOAT 0x01 R_ARM_LDR_SB_G2 77 R_NIOS2_TLS_LDM16 29 R_PARISC_LTOFF_TP21L 162 ODK_NULL 0 R_SPARC_GOTDATA_OP 84 R_NIOS2_GOT_LO 42 DT_MIPS_RLD_VERSION 0x70000001 R_PPC64_TPREL16_HIGH 112 DT_FINI_ARRAY 26 R_MN10300_GOTOFF32 12 R_OR1K_32_PCREL 9 SHT_MIPS_DENSE 0x70000013 PT_HIPROC 0x7fffffff R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 EI_NIDENT (16) ODK_HWPATCH 4 SHT_MIPS_PDR_EXCEPTION 0x70000029 EF_RISCV_RVC 0x0001 R_IA64_SECREL64MSB 0x66 R_MIPS_LO16 6 R_AARCH64_LD64_GOT_LO12_NC 312 SHN_BEFORE 0xff00 EM_ARM 40 R_X86_64_DTPOFF64 17 R_M32R_COPY 50 R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 ELFMAG "\177ELF" SHT_IA_64_EXT (SHT_LOPROC + 0) R_TILEGX_HW2_LAST 15 R_TILEPRO_TLS_DTPMOD32 82 DF_1_NOW 0x00000001 R_RISCV_ADD16 34 R_PPC64_TOCSAVE 109 R_SPARC_L44 52 EM_METAG 174 R_MIPS_TLS_DTPREL32 39 LL_NONE 0 R_RISCV_SUB32 39 PT_GNU_EH_FRAME 0x6474e550 R_ARM_TLS_IE32 107 RHF_NO_LIBRARY_REPLACEMENT (1 << 2) EF_PARISC_LSB 0x00040000 R_ALPHA_DTPRELLO 35 EF_MIPS_MACH_LS2F 0x00A10000 DT_PLTPAD 0x6ffffefd R_68K_NONE 0 R_X86_64_TLSDESC_CALL 35 R_IA64_PCREL64MSB 0x4e R_MICROBLAZE_GOTPC_64 13 DT_VALNUM 12 R_MN10300_TLS_GOTIE 27 EM_ARC_A5 EM_ARC_COMPACT R_SPARC_PLT32 24 R_IA64_REL64MSB 0x6e R_METAG_JMP_SLOT 44 R_LARCH_TLS_DTPMOD32 6 R_LARCH_ADD16 48 R_PPC64_TPREL16_HI 71 R_PPC64_ADDR30 37 EM_CRX 114 VER_FLG_BASE 0x1 R_PPC_TPREL16_LO 70 R_SPARC_TLS_LDM_LO10 61 DT_CONFIG 0x6ffffefa PF_HP_SBP 0x08000000 DF_1_IGNMULDEF 0x00040000 SHT_MIPS_CONFLICT 0x70000002 R_AARCH64_P32_TLS_DTPREL 185 R_ARM_THM_TLS_CALL 93 R_M32R_GOTPC24 55 R_TILEGX_IMM16_X1_HW3 43 R_TILEGX_IMM8_X1 25 R_TILEPRO_IMM16_X1_GOT_LO 42 R_68K_GOT8 9 DF_1_NODIRECT 0x00020000 EM_STM8 186 R_ARC_N24 0xA R_IA64_SEGREL64LSB 0x5f R_RISCV_SET6 53 R_ALPHA_GPRELHIGH 17 EM_FX66 66 NT_PPC_PPR 0x104 R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 STO_MIPS_DEFAULT 0x0 R_TILEPRO_32_PCREL 4 R_PPC64_SECTOFF_DS 61 R_IA64_LTOFF_TPREL22 0x9a R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 R_TILEGX_IMM16_X0_HW2 40 EF_SH4_NOFPU 0x10 NT_S390_PV_CPU_DATA 0x30e R_SPARC_UA64 54 SHF_EXECINSTR (1 << 2) R_LARCH_TLS_IE64_LO20 93 OEX_FPU_INVAL 0x10 R_MIPS_COPY 126 R_TILEPRO_JOFFLONG_X1_PLT 16 R_ARC_TLS_DTPOFF_S9 0x49 R_390_PLTOFF64 36 R_PPC_DIAB_RELSDA_HA 185 EF_SPARCV9_RMO 2 NT_386_IOPERM 0x201 EF_PPC_EMB 0x80000000 DT_RELA 7 MIPS_AFL_ASE_MSA 0x00000200 R_LARCH_GOT_LO12 80 R_X86_64_PC32 2 DT_NUM 38 R_TILEPRO_IMM16_X1_LO 26 SYMINFO_FLG_DIRECT 0x0001 EF_SPARCV9_PSO 1 R_MICROBLAZE_64_NONE 9 R_RISCV_LO12_I 27 SHT_GNU_versym 0x6fffffff R_TILEPRO_IMM16_X0_GOT_HA 45 DT_MIPS_DELTA_INSTANCE_NO 0x7000001a R_390_12 2 MIPS_AFL_REG_64 0x02 R_MIPS_GPREL16 7 EM_AMDGPU 224 R_CKCORE_PCREL_JSR_IMM26BY2 40 R_M32R_GOT16_HI_ULO 56 DT_VERSYM 0x6ffffff0 R_ARM_ABS16 5 R_386_TLS_TPOFF32 37 R_X86_64_COPY 5 EF_RISCV_FLOAT_ABI 0x0006 R_PPC_EMB_RELSEC16 111 R_MIPS_GLOB_DAT 51 R_PPC64_GOT16 R_PPC_GOT16 DT_TLSDESC_GOT 0x6ffffef7 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 R_CKCORE_GOTOFF_HI16 28 R_X86_64_PLTOFF64 31 R_ARM_LDC_PC_G1 68 R_SH_NONE 0 R_METAG_GNU_VTENTRY 31 PF_HP_PAGE_SIZE 0x00100000 R_390_GOTPLT12 29 R_PPC_GOT_TPREL16_LO 88 R_ALPHA_SREL16 9 R_TILEPRO_32 1 R_ARC_SECTOFF_ME_1 0x29 EM_MICROBLAZE 189 ODK_TAGS 6 EF_ARM_MAPSYMSFIRST 0x10 DT_RELAENT 9 R_CKCORE_GOT32 15 R_PPC_REL24 10 DT_AARCH64_PAC_PLT (DT_LOPROC + 3) R_PPC_EMB_SDA21 109 R_LARCH_NONE 0 EM_TMM_GPP 96 R_TILEGX_TLS_TPOFF64 108 R_MN10300_PLT16 16 R_PPC64_DTPREL16_HIGHESTA 106 EM_SPU 23 R_ARM_LDC_PC_G2 69 __TOOLS_KALLSYMS_H_ 1 R_CKCORE_PLT_IMM18BY4 49 R_68K_GOT16 8 EM_IP2K 101 EM_CDP 215 AT_NULL 0 R_ARC_SECTOFF_1 0x2B R_390_TLS_IEENT 49 R_PPC_GLOB_DAT 20 R_METAG_REG16OP1 9 R_TILEPRO_IMM16_X1_LO_PCREL 34 R_ARC_TLS_GD_CALL 0x47 EF_MIPS_ABI_EABI64 0x00004000 R_RISCV_RELATIVE 3 R_PPC64_REL24 R_PPC_REL24 R_ALPHA_SREL32 10 R_TILEGX_IMM16_X1_HW0_LAST 45 R_AARCH64_TLSLD_ADD_LO12_NC 519 R_PPC64_GOT_TPREL16_HI 89 R_ARM_THM_MOVT_ABS 48 R_ARM_TLS_DESCSEQ 92 EF_MIPS_CPIC 4 R_CKCORE_DOFFSET_LO16 42 R_AC_SECTOFF_U8_1 0x24 R_TILEPRO_JOFFLONG_X1 15 AT_HWCAP2 26 R_TILEGX_NONE 0 EM_ST19 74 R_TILEPRO_IMM16_X0_GOT 39 R_RISCV_JUMP_SLOT 5 R_CRIS_COPY 9 R_390_TLS_DTPMOD 54 R_ARM_THM_ALU_PREL_11_0 53 R_MICROMIPS_LO16 135 R_MIPS_GOT_LO16 23 NT_S390_SYSTEM_CALL 0x307 R_PPC64_ADDR16_DS 56 STV_HIDDEN 2 EM_NCPU 56 R_PARISC_IPLT 129 R_TILEGX_GNU_VTENTRY 129 R_TILEPRO_GNU_VTENTRY 129 R_PARISC_TLS_LDM14R 238 R_PPC64_REL16 249 R_386_TLS_DESC 41 ELFOSABI_AIX 7 R_PPC64_TOC16_HI 49 R_IA64_REL32LSB 0x6d NT_SIGINFO 0x53494749 SHF_ALLOC (1 << 1) R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 573 R_LARCH_ADD32 50 SHT_MIPS_EXTSYM 0x70000012 R_ARC_S25W_PCREL 0x11 R_SH_IND12W 4 R_MN10300_GNU_VTINHERIT 7 R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 R_ARM_MOVT_PREL 46 R_X86_64_DTPMOD64 16 R_TILEGX_IMM16_X0_HW0_TLS_GD 78 PT_GNU_PROPERTY 0x6474e553 R_CKCORE_PCREL_IMM10BY2 22 PT_SHLIB 5 KSYM_NAME_LEN 512 NT_PPC_EBB 0x106 R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 R_MIPS_TLS_GOTTPREL 46 R_LARCH_TLS_IE64_PC_HI12 90 R_ARC_GOTOFF 0x39 R_AC_SECTOFF_U8 0x23 R_ARM_GOTOFF12 98 R_LARCH_SOP_ASSERT 30 EM_C166 116 MIPS_AFL_EXT_10000 11 R_PPC64_ADDR14 R_PPC_ADDR14 R_PARISC_TLS_GDCALL 236 R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO R_OR1K_NONE 0 EM_PDSP 63 R_TILEGX_IMM16_X0_HW1_PLT_PCREL 68 R_SH_SWITCH8 33 EF_MIPS_MACH 0x00FF0000 R_TILEPRO_SHAMT_X0 51 R_TILEPRO_IMM16_X0_TLS_GD_HA 72 NT_FILE 0x46494c45 SHF_EXCLUDE (1U << 31) R_390_20 57 R_MN10300_GOTPC32 10 R_CKCORE_ADDRGOT_LO16 37 isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) R_RISCV_COPY 4 NT_PLATFORM 5 R_68K_TLS_LDM8 30 R_METAG_TLS_IENONPIC_HI16 54 R_68K_TLS_LE32 37 R_ARM_LDR_PC_G2 63 SHF_ORDERED (1 << 30) R_CKCORE_TLS_IE32 52 EM_ALPHA 0x9026 R_CKCORE_JUMP_SLOT 12 R_ARM_THM_TLS_DESCSEQ16 129 R_TILEPRO_16_PCREL 5 R_ARC_TLS_DTPOFF 0x43 R_AC_SECTOFF_S9_1 0x27 R_MICROMIPS_TLS_GOTTPREL 166 R_AARCH64_GOTREL64 307 STO_PPC64_LOCAL_BIT 5 OEX_FPU_OFLO 0x04 __ismask(x) (_ctype[(int)(unsigned char)(x)]) R_ARM_THM_MOVW_BREL 89 R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ELFDATANUM 3 R_PPC64_TOC16 47 R_PPC64_PLTREL32 R_PPC_PLTREL32 EF_MIPS_ARCH_5 0x40000000 DT_FLAGS_1 0x6ffffffb DT_REL 17 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 R_MN10300_GOT16 19 R_ARC_JMP_SLOT 0x37 R_IA64_DTPMOD64MSB 0xa6 R_PARISC_TPREL32 153 R_TILEPRO_HA16 9 R_X86_64_PLT32 4 GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) R_LARCH_TLS_LE64_LO20 85 DF_1_SYMINTPOSE 0x00800000 R_ALPHA_NUM 46 R_LARCH_MARK_PCREL 21 R_PPC64_ADDR16_HIGH 110 R_ARM_GOTOFF 24 R_NDS32_GLOB_DAT 40 DT_MIPS_INTERFACE_SIZE 0x7000002c R_PARISC_DIR32 1 EF_MIPS_ARCH_ASE_MDMX 0x08000000 RHF_DEFAULT_DELAY_LOAD (1 << 9) R_MIPS_PC32 248 STB_WEAK 2 R_AARCH64_TLS_DTPMOD 1028 io__get_hex PF_MASKPROC 0xf0000000 SHT_RELA 4 R_ARM_THM_TLS_DESCSEQ32 130 EF_RISCV_RVE 0x0008 R_OR1K_GOT16 14 SHT_MIPS_FDESC 0x70000011 R_TILEPRO_IMM16_X1_HI_PCREL 36 DT_VALRNGLO 0x6ffffd00 DT_ALPHA_NUM 1 R_SPARC_TLS_IE_LDX 70 PF_ARM_ABS 0x40000000 EM_8051 165 EM_VIDEOCORE3 137 SHT_FINI_ARRAY 15 R_OR1K_LO_16_IN_INSN 4 OPAD_PREFIX 0x1 R_NIOS2_CALL_HA 45 R_SPARC_REGISTER 53 NT_FDO_PACKAGING_METADATA 0xcafe1a7e R_ARM_RREL32 252 R_IA64_DTPREL64MSB 0xb6 R_AARCH64_TSTBR14 279 R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 R_IA64_DIR64LSB 0x27 R_PPC64_PLTGOT16_LO 53 EF_SH3 0x3 DT_RELRENT 37 R_ARM_MOVW_BREL_NC 84 R_390_PC32 5 EF_MIPS_MACH_5500 0x00980000 R_MICROBLAZE_TLSDTPREL64 27 R_SPARC_UA32 23 SHT_SYMTAB_SHNDX 18 SHT_MIPS_PIXIE 0x70000023 DT_NIOS2_GP 0x70000002 R_CKCORE_DOFFSET_IMM18BY2 45 R_AARCH64_TLSLE_MOVW_TPREL_G2 544 R_TILEGX_IMM16_X0_HW3_PLT_PCREL 76 R_SPARC_JMP_SLOT 21 R_MN10300_24 9 DF_ORIGIN 0x00000001 R_PPC64_TPREL64 73 NT_PPC_TM_CVSX 0x10b R_390_COPY 9 R_LARCH_TLS_LE_LO12 84 PT_INTERP 3 R_PPC_EMB_NADDR16 102 R_SPARC_IRELATIVE 249 R_PARISC_GPREL16F 93 R_SPARC_TLS_TPOFF64 79 R_MICROMIPS_TLS_DTPREL_LO16 165 EM_D10V 85 R_LARCH_SOP_POP_32_S_10_16 41 EF_CSKY_PROCESSOR 0X0000FFFF R_LARCH_SUB16 53 R_RISCV_ADD8 33 R_RISCV_TPREL_I 49 R_MIPS_16 1 STB_MIPS_SPLIT_COMMON 13 EF_PARISC_EXT 0x00020000 R_SH_ALIGN 29 R_IA64_PCREL60B 0x48 R_M32R_GNU_VTENTRY 12 R_X86_64_DTPOFF32 21 R_ARM_LDR_SBREL_11_0 35 R_AARCH64_TLSDESC_ADR_PAGE21 562 R_PPC_GOT_TPREL16_HI 89 R_386_TLS_LE 17 NT_ARM_TAGGED_ADDR_CTRL 0x409 DT_INIT_ARRAY 25 EF_MIPS_ARCH_ASE 0x0f000000 NT_PRSTATUS 1 R_M32R_GOT16_LO 58 PT_HP_TLS (PT_LOOS + 0x0) R_386_TLS_GD_32 24 DT_RELR 36 R_390_GOTOFF64 28 R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L R_ARM_IRELATIVE 160 R_PARISC_LTOFF_FPTR32 57 R_PPC_PLT32 27 R_PPC_TPREL16_HI 71 R_MIPS_TLS_DTPREL_LO16 45 R_NIOS2_TLS_LE16 32 R_TILEPRO_IMM16_X0_LO 25 R_TILEPRO_IMM16_X0_TLS_LE 85 R_ARC_TLS_LE_32 0x4B MIPS_AFL_EXT_5900 6 R_M32R_JMP_SLOT 52 R_PARISC_LTOFF_TP16WF 230 R_ALPHA_TLS_LDM 30 R_LARCH_B16 64 OEX_PAGE0 0x10000 EM_PPC64 21 R_390_GOTPCDBL 21 ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) VER_DEF_NUM 2 R_MIPS_HIGHER 28 R_ARM_THM_RPC22 251 R_68K_GLOB_DAT 20 R_MICROMIPS_PC23_S2 173 R_PPC_EMB_RELSDA 116 R_SPARC_TLS_GD_CALL 59 R_386_GOTPC 10 R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 STB_LOOS 10 R_SPARC_GOT22 15 R_390_TLS_GD32 40 iscntrl(c) ((__ismask(c)&(_C)) != 0) R_SH_TLS_DTPOFF32 150 R_ARC_S25H_PCREL 0x10 R_LARCH_SUB24 54 R_X86_64_GOTOFF64 25 NT_ASRS 8 SHT_MIPS_DEBUG 0x70000005 R_M32R_HI16_SLO 8 EM_CUDA 190 PF_X (1 << 0) R_IA64_FPTR64MSB 0x46 R_ARM_ALU_SB_G0 71 R_LARCH_PCALA64_HI12 74 LITUSE_ALPHA_BASE 1 R_TILEGX_GNU_VTINHERIT 128 MIPS_AFL_EXT_5400 15 R_RISCV_RVC_BRANCH 44 R_LARCH_TLS_LD_PC_HI20 95 SHT_MIPS_PDESC 0x70000014 R_MIPS_TLS_TPREL64 48 EM_TRIMEDIA 163 R_TILEGX_IMM8_X1_TLS_ADD 119 R_SH_DIR8WPZ 6 NT_PPC_VMX 0x100 STO_ALPHA_NOPV 0x80 R_MICROMIPS_HIGHEST 152 EF_SH2A_SH3E 0x18 R_386_TLS_LDM_PUSH 29 DT_HIPROC 0x7fffffff SHT_MIPS_LINE 0x70000019 R_ARM_TLS_LDO12 109 NT_S390_TDB 0x308 EM_ST7 68 R_RISCV_JAL 17 EM_68HC08 71 ELFDATA2LSB 1 R_ARC_TLS_DTPMOD 0x42 R_LARCH_TLS_TPREL64 11 DT_SPARC_REGISTER 0x70000001 R_M32R_10_PCREL_RELA 36 R_PPC_ADDR14_BRNTAKEN 9 R_AARCH64_MOVW_PREL_G1 289 R_NIOS2_CALL16 23 R_390_NONE 0 MIPS_AFL_EXT_4010 8 R_IA64_DTPREL32LSB 0xb5 R_RISCV_GPREL_I 47 R_PPC64_GOT_TLSGD16_HA 82 R_MIPS_REL16 33 R_RISCV_GNU_VTINHERIT 41 E_MIPS_ARCH_1 EF_MIPS_ARCH_1 R_CRIS_GLOB_DAT 10 R_68K_NUM 43 R_CKCORE_PLT_HI16 34 R_ARM_PREL31 42 R_ARM_V4BX 40 SHF_GNU_RETAIN (1 << 21) R_LARCH_TLS_IE_PC_LO12 88 R_PARISC_PLABEL32 65 R_ARC_GOTPC 0x3A R_MICROBLAZE_32_SYM_OP_SYM 10 EM_ZSP 79 R_RISCV_TLS_DTPREL64 9 R_NIOS2_ALIGN 21 R_SH_SWITCH16 25 R_SPARC_22 10 R_390_PLTOFF32 35 R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 R_ARC_TLS_TPOFF 0x44 E_MIPS_ARCH_3 EF_MIPS_ARCH_3 AT_L2_CACHEGEOMETRY 45 SHT_HASH 5 R_AARCH64_TLSDESC_OFF_G0_NC 566 R_METAG_GETSETOFF 5 ELFOSABI_FREEBSD 9 PT_NOTE 4 R_PPC64_DTPREL16_HIGHEST 105 ELF_NOTE_ABI NT_GNU_ABI_TAG R_PPC_ADDR16_HI 5 R_ARM_THM_MOVW_PREL_NC 49 R_M32R_SDA16_RELA 42 DT_MIPS_FLAGS 0x70000005 STT_FUNC 2 MIPS_AFL_EXT_4111 13 STB_HIOS 12 R_LARCH_ALIGN 102 R_TILEGX_HW2 11 AT_EXECFN 31 R_X86_64_64 1 EF_MIPS_MACH_ALLEGREX 0x00840000 R_SPARC_HIPLT22 25 SHT_MIPS_AUXSYM 0x70000016 R_SH_LABEL 32 E_MIPS_ARCH_5 EF_MIPS_ARCH_5 STB_LOCAL 0 R_AARCH64_MOVW_PREL_G2_NC 292 R_TILEPRO_LO16 7 SHT_MIPS_DELTADECL 0x7000001f R_PPC64_DTPMOD64 68 DT_JMPREL 23 R_SPARC_LOPLT10 26 R_LARCH_ADD_ULEB128 107 R_LARCH_TLS_TPREL32 10 R_CRIS_32_GOTREL 17 SHN_MIPS_ACOMMON 0xff00 DT_SYMBOLIC 16 R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 99 R_TILEGX_IMM8_Y1 26 STO_MIPS_PROTECTED 0x3 R_MICROBLAZE_GNU_VTINHERIT 11 PT_NULL 0 R_SPARC_TLS_DTPOFF64 77 GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002 R_SPARC_H44 50 NT_S390_RI_CB 0x30d R_OR1K_HI_16_IN_INSN 5 DT_HASH 4 ELF_NOTE_SOLARIS "SUNW Solaris" R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN R_ARC_32_PCREL 0x31 _P 0x10 R_METAG_TLS_LDO 51 R_M32R_26_PCREL_RELA 38 R_NIOS2_UJMP 18 R_OR1K_PLT26 15 R_OR1K_INSN_REL_26 6 R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 R_SPARC_PCPLT32 27 R_ARM_TLS_TPOFF32 19 R_IA64_SECREL32MSB 0x64 R_OR1K_TLS_LDM_HI16 24 R_PARISC_LTOFF21L 34 DT_X86_64_NUM 4 R_AARCH64_TLSDESC_LD_PREL19 560 R_LARCH_SOP_PUSH_ABSOLUTE 23 R_METAG_NONE 3 EM_SVX 73 R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN R_TILEPRO_IMM16_X1_TLS_LE_LO 88 SHT_MIPS_WHIRL 0x70000026 R_M32R_LO16 9 R_PPC64_UADDR64 43 SHT_MIPS_XLATE_DEBUG 0x70000025 SHT_SUNW_COMDAT 0x6ffffffb EF_PARISC_NO_KABP 0x00100000 R_PPC_GOT_TPREL16 87 PT_IA_64_ARCHEXT (PT_LOPROC + 0) R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN R_RISCV_PCREL_HI20 23 R_PARISC_HIRESERVE 255 ELF32_ST_VISIBILITY(o) ((o) & 0x03) R_AARCH64_TLSGD_ADD_LO12_NC 514 R_AARCH64_TLSLD_MOVW_G0_NC 521 R_MICROMIPS_TLS_GD 162 EF_PARISC_LAZYSWAP 0x00400000 EM_PPC 20 R_390_8 1 R_RISCV_NONE 0 R_METAG_REG16OP2 10 R_TILEPRO_IMM16_X0 23 R_AARCH64_TLSDESC_OFF_G1 565 R_SPARC_6 45 R_IA64_FPTR32LSB 0x45 R_MICROMIPS_TLS_TPREL_LO16 170 NT_S390_HIGH_GPRS 0x300 PT_HP_CORE_NONE (PT_LOOS + 0x1) R_TILEPRO_NONE 0 R_SPARC_TLS_GD_ADD 58 EF_SH4_NOMMU_NOFPU 0x12 R_PPC64_GOT_DTPREL16_HI 93 DT_PLTRELSZ 2 R_LARCH_GOT_HI20 79 R_NIOS2_U16 2 R_68K_TLS_GD32 25 R_AARCH64_GOTREL32 308 R_IA64_PCREL21F 0x4b R_PPC64_ADDR32 R_PPC_ADDR32 EI_DATA 5 R_PPC64_PLTGOT16 52 R_68K_TLS_TPREL32 42 R_MICROBLAZE_GOTOFF_64 19 R_SPARC_LOX10 49 DT_INIT_ARRAYSZ 27 EM_CRIS 76 R_68K_PLT32 13 R_PARISC_LTOFF64 96 DT_GNU_CONFLICTSZ 0x6ffffdf6 SHF_INFO_LINK (1 << 6) R_M32R_GOTOFF 54 R_ARC_W_ME 0x1F R_METAG_REG32OP2 7 DT_VERNEEDNUM 0x6fffffff R_SPARC_HIX22 48 NT_GNU_GOLD_VERSION 4 R_390_PC16 16 R_X86_64_IRELATIVE 37 R_SH_JMP_SLOT 164 R_TILEPRO_IMM16_X1_TLS_GD_HA 73 R_OR1K_RELATIVE 21 R_RISCV_TLS_GOT_HI20 21 R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 R_ARC_SECTOFF_2 0x2C R_PARISC_LTOFF_TP16DF 231 R_MIPS_REL32 3 R_PPC64_COPY R_PPC_COPY R_TILEPRO_IMM16_X0_HI 27 EF_LARCH_ABI_DOUBLE_FLOAT 0x03 R_ARM_ALU_PC_G1_NC 59 SHT_SUNW_move 0x6ffffffa R_IA64_TPREL64MSB 0x96 NOTE_GNU_PROPERTY_SECTION_NAME ".note.gnu.property" R_ARC_N8 0x8 EM_SH 42 R_M32R_10_PCREL 4 R_MIPS_TLS_DTPMOD64 40 R_M32R_GOTOFF_LO 64 R_MIPS_NUM 255 SHT_GNU_HASH 0x6ffffff6 R_MN10300_RELATIVE 23 EF_ARM_INTERWORK 0x04 EF_RISCV_FLOAT_ABI_SINGLE 0x0002 DF_1_ORIGIN 0x00000080 GNU_PROPERTY_X86_ISA_1_BASELINE (1U << 0) SYMINFO_NONE 0 ELF32_ST_TYPE(val) ((val) & 0xf) EF_MIPS_ARCH_4 0x30000000 ELFOSABI_NETBSD 2 EM_TSK3000 131 R_MIPS_JALR 37 R_ARM_THM_PC8 11 EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000 ELFCLASSNONE 0 NT_FPREGSET 2 R_PARISC_LTOFF_TP14DR 228 PT_HISUNW 0x6fffffff R_PPC_UADDR16 25 EF_MIPS_ABI_O32 0x00001000 R_TILEGX_32 2 EM_FR20 37 DT_SPARC_NUM 2 R_ARM_ALU_PC_G0 58 DT_RELRSZ 35 R_PPC_REL16 249 EF_IA_64_MASKOS 0x0000000f read_to_eol EM_STARCORE 58 ELFMAG1 'E' ELF64_R_TYPE(i) ((i) & 0xffffffff) R_PARISC_DIR14R 6 R_PPC_REL16_HI 251 R_TILEPRO_IMM8_X0 17 EF_SH_DSP 0x4 R_ALPHA_LITUSE 5 EM_HUANY 81 SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) R_CRIS_32_PCREL 6 R_CRIS_32_PLT_PCREL 19 R_PARISC_DIR16WF 86 R_ARM_THM_XPC22 16 R_LARCH_SOP_SUB 32 PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) R_390_GOTOFF32 13 DT_MIPS_PLTGOT 0x70000032 DT_FINI 13 EM_PJ 91 R_PPC64_TLSLD 108 R_SPARC_TLS_TPOFF32 78 R_PARISC_DIR14WR 83 R_NIOS2_COPY 36 R_PPC64_GOT_TLSLD16 83 R_NIOS2_CALLR 20 EM_XTENSA 94 R_MIPS_DELETE 27 R_CKCORE_ADDRPLT_HI16 38 R_IA64_LTV64LSB 0x77 STV_INTERNAL 1 EI_CLASS 4 SHT_MIPS_SYMBOL_LIB 0x70000020 R_SPARC_TLS_DTPMOD64 75 R_PPC64_PLTGOT16_LO_DS 66 R_386_TLS_LDM 19 R_MIPS_PC26_S2 61 GNU_PROPERTY_LOUSER 0xe0000000 SHT_MIPS_GPTAB 0x70000003 RHF_RLD_ORDER_SAFE (1 << 14) R_SPARC_64 32 R_ARM_TLS_LE12 110 R_LARCH_SOP_POP_32_S_10_12 40 R_RISCV_TLS_DTPMOD32 6 R_LARCH_SOP_POP_32_S_10_16_S2 42 AT_PHDR 3 R_386_PC8 23 EFA_PARISC_1_1 0x0210 PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) R_MIPS_GNU_VTENTRY 254 EM_V850 87 EM_ST100 60 R_PPC64_GOT16_HA R_PPC_GOT16_HA R_PARISC_PCREL17F 12 R_TILEPRO_IMM16_X0_TLS_IE_LO 76 R_SPARC_GNU_VTENTRY 251 SHF_WRITE (1 << 0) EF_MIPS_ABI2 32 R_ARM_ALU_SBREL_19_12 36 R_METAG_ADDR32 2 R_NIOS2_TLS_GD16 28 DT_RELACOUNT 0x6ffffff9 R_RISCV_LO12_S 28 R_NIOS2_GNU_VTENTRY 17 LITUSE_ALPHA_JSR 3 R_X86_64_GOTPC64 29 R_RISCV_NUM 62 R_PPC_PLT16_LO 29 R_390_GOT12 6 R_IA64_LTOFF_FPTR64I 0x53 DT_VERDEFNUM 0x6ffffffd R_ARM_THM_JUMP6 52 R_RISCV_TPREL_LO12_I 30 R_TILEPRO_IMM16_X1_GOT_HA 46 SHT_MIPS_DELTASYM 0x7000001b R_PPC64_DTPREL16_DS 101 SHN_ABS 0xfff1 R_SH_DIR8BP 7 AT_BASE_PLATFORM 24 R_390_16 3 EF_MIPS_ARCH_32R6 0x90000000 DT_SYMTAB_SHNDX 34 EM_TI_C6000 140 R_ARM_REL32_NOI 56 R_TILEPRO_SHAMT_Y0 53 R_ARM_THM_TLS_DESCSEQ 129 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 EM_SPARC 2 R_IA64_PCREL22 0x7a R_IA64_LTOFF_DTPREL22 0xba R_LARCH_SOP_PUSH_TLS_GOT 27 EF_ARM_SYMSARESORTED 0x04 ET_REL 1 R_X86_64_32 10 R_NIOS2_HI16 9 ELFOSABI_STANDALONE 255 R_MIPS_TLS_TPREL32 47 EF_MIPS_MACH_OCTEON3 0x008e0000 GNU_PROPERTY_UINT32_AND_LO 0xb0000000 RHF_NO_MOVE (1 << 3) STV_DEFAULT 0 isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) R_M32R_HI16_ULO_RELA 39 R_TILEPRO_COPY 10 SHT_MIPS_EH_REGION 0x70000027 R_MICROMIPS_GOT16 138 GNU_PROPERTY_NO_COPY_ON_PROTECTED 2 EF_ARC_OSABI_MSK 0x00000f00 R_MIPS_GOT16 9 R_MICROBLAZE_TLSDTPMOD32 25 STO_AARCH64_VARIANT_PCS 0x80 R_OR1K_TLS_LE_LO16 31 DT_MIPS_HIPAGENO 0x70000014 PT_HP_PARALLEL (PT_LOOS + 0x10) R_IA64_GPREL64LSB 0x2f R_CKCORE_GOT_HI16 31 R_OR1K_16_PCREL 10 R_PARISC_DIR17R 3 R_PARISC_SECREL32 41 R_AARCH64_PREL64 260 R_AARCH64_ADR_PREL_PG_HI21 275 EF_MIPS_MACH_LS2E 0x00A00000 EF_SH3_DSP 0x5 R_AARCH64_MOVW_UABS_G3 269 R_PPC_DIAB_SDA21_HA 182 R_TILEPRO_HI16 8 R_ARC_N16 0x9 R_X86_64_GOTPCREL 9 R_ARM_LDRS_SB_G2 80 R_ARM_LDC_SB_G0 81 DT_MOVESZ 0x6ffffdfb EF_ARM_APCS_26 0x08 R_ALPHA_TPREL16 41 R_ARM_GNU_VTENTRY 100 R_RISCV_SUB_ULEB128 61 R_TILEGX_IMM16_X1_HW1_PLT_PCREL 69 R_LARCH_RELATIVE 3 EM_IA_64 50 R_390_NUM 62 R_TILEGX_IMM16_X0_HW0_GOT 64 R_MN10300_PLT32 15 OEX_FPU_INEX 0x01 SHN_MIPS_TEXT 0xff01 R_TILEPRO_IMM16_X1_TLS_LE_HI 90 EM_AVR 83 R_RISCV_SUB6 52 R_ALPHA_GPRELLOW 18 EM_RCE 39 R_PPC64_GOT16_HI R_PPC_GOT16_HI DF_1_GLOBAL 0x00000002 SHT_NOTE 7 R_M32R_32_RELA 34 AT_RSEQ_FEATURE_SIZE 27 R_AARCH64_LDST8_ABS_LO12_NC 278 R_IA64_LTOFF_FPTR32LSB 0x55 R_MN10300_GOTOFF24 13 PT_IA_64_UNWIND (PT_LOPROC + 1) R_MIPS_TLS_GD 42 EM_COOL 217 STT_SPARC_REGISTER 13 ELFCOMPRESS_HIPROC 0x7fffffff R_LARCH_SOP_POP_32_U 46 RHF_CORD (1 << 12) MIPS_AFL_ASE_MIPS16 0x00000400 SHT_STRTAB 3 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 EF_MIPS_MACH_5400 0x00910000 EF_LARCH_ABI_SINGLE_FLOAT 0x02 R_X86_64_GOTPCREL64 28 R_LARCH_ABS_LO12 68 EF_SH4 0x9 LITUSE_ALPHA_TLS_LDM 5 R_CKCORE_PCREL_IMM7BY4 50 R_PARISC_LTOFF14R 38 NT_PSTATUS 10 R_SH_PLT32 161 R_PPC_EMB_RELST_LO 112 R_SPARC_HH22 34 R_TILEGX_RELATIVE 19 R_IA64_PLTOFF64I 0x3b EM_68HC11 70 STO_MIPS_SC_ALIGN_UNUSED 0xff R_SPARC_TLS_DTPOFF32 76 SHT_NULL 0 R_LARCH_PCREL20_S2 103 EM_ECOG2 134 R_PPC_COPY 19 R_RISCV_PCREL_LO12_S 25 SHT_HIPROC 0x7fffffff R_PPC_DIAB_RELSDA_HI 184 R_NDS32_TLS_DESC 119 AT_L3_CACHESIZE 46 R_TILEGX_JUMPOFF_X1_PLT 22 R_PPC64_GOT_TLSLD16_LO 84 SHT_SYMTAB 2 R_PARISC_TLS_LDMCALL 239 R_PPC64_SECTOFF_LO_DS 62 R_IA64_PLTOFF64MSB 0x3e R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 DT_EXTRANUM 3 AT_L3_CACHESHAPE 37 ELFOSABI_SOLARIS 6 R_MN10300_GLOB_DAT 21 R_LARCH_ABS_HI20 67 DT_MIPS_GOTSYM 0x70000013 DT_MIPS_RLD_MAP 0x70000016 R_MICROMIPS_GOT_OFST 147 R_PPC64_TPREL16_HA 72 R_386_TLS_GD_CALL 26 R_PPC_ADDR24 2 R_X86_64_JUMP_SLOT 7 EF_PARISC_ARCH 0x0000ffff ELFOSABI_LINUX ELFOSABI_GNU EM_L10M 180 R_LARCH_SOP_POP_32_S_5_20 43 MIPS_AFL_ASE_MT 0x00000040 VER_NDX_ELIMINATE 0xff01 DT_VERSIONTAGNUM 16 R_X86_64_NONE 0 DT_NULL 0 R_X86_64_GOT64 27 R_386_JMP_SLOT 7 MIPS_AFL_REG_NONE 0x00 R_PPC64_UADDR16 R_PPC_UADDR16 R_ARM_RPC24 254 R_AARCH64_MOVW_GOTOFF_G2_NC 305 R_LARCH_B26 66 EM_LATTICEMICO32 138 R_M32R_16_RELA 33 R_M32R_GOT24 48 R_TILEGX_IMM16_X1_HW1_PCREL 53 R_ARM_ALU_PC_G0_NC 57 EM_MN10200 90 R_METAG_LO16_PLT 39 NT_PPC_TM_CFPR 0x109 R_PARISC_GPREL16WF 94 STT_GNU_IFUNC 10 R_LARCH_TLS_LD_HI20 96 STV_PROTECTED 3 EM_F2MC16 104 R_M32R_HI16_SLO_RELA 40 LL_IGNORE_INT_VER (1 << 1) isspace(c) ((__ismask(c)&(_S)) != 0) R_TILEPRO_GNU_VTINHERIT 128 VER_NEED_NONE 0 ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) R_ARM_LDR_SB_G1 76 R_TILEPRO_IMM16_X1_HA 30 R_MIPS_TLS_DTPREL_HI16 44 R_METAG_TLS_LDO_LO16 50 R_ARC_GLOB_DAT 0x36 R_CKCORE_TLS_DTPOFF32 57 R_ARM_ABS32 2 R_PARISC_DIR16DF 87 R_CKCORE_PCRELIMM11BY2 3 R_NIOS2_TLS_TPREL 35 R_SPARC_TLS_IE_ADD 71 R_METAG_RELBRANCH_PLT 40 EM_DSPIC30F 118 R_LARCH_IRELATIVE 12 __compiletime_assert(condition,msg,prefix,suffix) do { } while (0) DT_ADDRRNGLO 0x6ffffe00 SYMINFO_BT_SELF 0xffff DT_VERNEED 0x6ffffffe R_PARISC_DIR14DR 84 R_MN10300_GOTPC16 11 DT_FINI_ARRAYSZ 28 R_METAG_TLS_TPOFF 56 R_MIPS_TLS_DTPMOD32 38 SHT_MIPS_SHDR 0x70000010 DT_MIPS_PROTECTED_GOTIDX 0x70000028 R_OR1K_GOTPC_HI16 12 R_ARM_MOVT_BREL 85 R_SPARC_11 31 EM_DSP24 136 ELFDATA2MSB 2 R_MICROBLAZE_GOTOFF_32 20 R_PPC64_GOT_TPREL16_DS 87 R_SPARC_8 1 R_ARC_N32 0xB R_LARCH_TLS_LE_HI20 83 R_68K_GOT32 7 EM_NS32K 97 R_MICROBLAZE_SRO32 7 GNU_PROPERTY_X86_ISA_1_V4 (1U << 3) toupper(c) __toupper(c) DT_MIPS_DELTA_SYM_NO 0x7000001e R_NIOS2_GOTOFF_LO 24 STT_LOOS 10 R_NIOS2_PCREL_HA 27 VER_NEED_CURRENT 1 R_MN10300_NONE 0 DT_RELSZ 18 AT_ENTRY 9 R_PPC64_ADDR16 R_PPC_ADDR16 AT_DCACHEBSIZE 19 R_IA64_LTOFF_FPTR64MSB 0x56 R_AARCH64_MOVW_PREL_G2 291 EF_MIPS_32BITMODE 0x00000100 _SP 0x80 R_IA64_SEGREL64MSB 0x5e NT_S390_GS_BC 0x30c R_METAG_HI16_PLT 38 R_NIOS2_S16 1 R_TILEPRO_IMM16_X0_TLS_IE_HI 78 EF_MIPS_MACH_GS264E 0x00A40000 R_AARCH64_TLSLD_MOVW_G1 520 DT_PPC64_GLINK (DT_LOPROC + 0) R_MICROMIPS_LITERAL 137 R_TILEGX_IMM16_X0_HW1 38 SHT_MIPS_LIBLIST 0x70000000 R_MICROBLAZE_32_LO 6 R_PPC_PLT16_HI 30 R_ARM_COPY 20 R_TILEGX_IMM16_X1_HW2 41 R_TILEGX_IMM8_X0 23 R_CRIS_32_PLT_GOTREL 18 R_MIPS_GPREL32 12 R_TILEGX_SHAMT_Y1 35 EM_PRISM 82 R_AARCH64_MOVW_UABS_G0 263 OEX_PRECISEFP OEX_FPDBUG R_PARISC_LTOFF_FPTR21L 58 R_386_8 22 R_PPC64_PLT16_LO R_PPC_PLT16_LO AT_L1D_CACHESIZE 42 SHT_CHECKSUM 0x6ffffff8 R_ARM_THM_ABS5 7 EM_MIPS 8 EM_PDP11 65 EM_X86_64 62 R_AARCH64_TLSDESC_ADD_LO12 564 R_390_GOTENT 26 R_OR1K_GLOB_DAT 19 EF_MIPS_ARCH_3 0x20000000 R_AARCH64_COPY 1024 R_TILEGX_16_PCREL 7 R_PARISC_TLS_LE14R R_PARISC_TPREL14R EF_SPARC_HAL_R1 0x000400 SHT_MIPS_UCODE 0x70000004 R_TILEGX_IMM16_X0_HW2_LAST 48 R_PPC_GOT16_LO 15 R_X86_64_TPOFF64 18 DT_VERDEF 0x6ffffffc R_LARCH_TLS_IE64_PC_LO20 89 R_PPC_ADDR16_HA 6 EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) R_ARM_LDRS_PC_G2 66 R_68K_TLS_IE16 35 R_MIPS16_TLS_TPREL_HI16 111 ODK_PAD 3 R_RISCV_SET32 56 MIPS_AFL_EXT_LOONGSON_2F 18 R_SPARC_TLS_DTPMOD32 74 R_CKCORE_DOFFSET_IMM18BY4 46 NT_S390_TODCMP 0x302 R_AARCH64_MOVW_PREL_G1_NC 290 STT_TLS 6 R_METAG_TLS_IE 52 R_PARISC_LTOFF16WF 102 R_SPARC_DISP16 5 R_LARCH_TLS_IE_LO12 92 R_M32R_GNU_VTINHERIT 11 MIPS_AFL_EXT_LOONGSON_2E 17 R_PPC_ADDR14_BRTAKEN 8 R_PPC64_TOC16_HA 50 DT_FEATURE_1 0x6ffffdfc R_ARM_LDC_PC_G0 67 SHN_MIPS_DATA 0xff02 PT_LOAD 1 R_SPARC_M44 51 R_ARM_NONE 0 PT_IA_64_HP_STACK (PT_LOOS + 0x14) OEX_FPDBUG 0x40000 DF_1_INTERPOSE 0x00000400 R_NIOS2_GOT_HA 43 R_LARCH_SOP_POP_32_S_10_5 38 R_AARCH64_JUMP_SLOT 1026 R_NIOS2_NONE 0 R_MIPS_PCLO16 65 SHT_ARC_ATTRIBUTES (SHT_LOPROC + 1) PT_PHDR 6 R_PPC64_PLT32 R_PPC_PLT32 R_CRIS_GNU_VTINHERIT 7 ELFOSABI_TRU64 10 R_RISCV_TLS_TPREL64 11 R_MIPS_RELATIVE 128 STT_LOPROC 13 R_AARCH64_IRELATIVE 1032 ELF_NOTE_OS_GNU 1 EF_MIPS_OPTIONS_FIRST 0x00000080 EF_MIPS_MACH_GS464E 0x00A30000 SHN_HIRESERVE 0xffff EI_MAG0 0 AT_PHNUM 5 R_MICROMIPS_SCN_DISP 155 R_MICROBLAZE_GLOB_DAT 18 R_OR1K_GOTOFF_HI16 16 PT_HP_OPT_ANNOT (PT_LOOS + 0x12) EF_SH_UNKNOWN 0x0 R_SPARC_HM10 35 AT_RANDOM 25 R_TILEPRO_IMM16_X0_TLS_LE_HI 89 STO_ALPHA_STD_GPLOAD 0x88 EF_ARM_EABIMASK 0XFF000000 MIPS_AFL_ASE_DSPR2 0x00000002 R_LARCH_GOT64_LO20 81 DT_MOVEENT 0x6ffffdfa NT_LOONGARCH_CPUCFG 0xa00 EM_960 19 R_PPC64_GOT_TLSLD16_HI 85 ELF32_M_SIZE(info) ((unsigned char) (info)) R_ARM_SBREL31 39 R_CRIS_32_GOT 14 R_IA64_PCREL32MSB 0x4c R_AARCH64_P32_TLS_DTPMOD 184 EFA_PARISC_2_0 0x0214 R_AARCH64_TLSLD_ADR_PREL21 517 R_IA64_PCREL32LSB 0x4d R_METAG_PLT 42 NT_386_TLS 0x200 R_IA64_REL32MSB 0x6c EM_IAMCU 6 R_PPC64_REL16_HI 251 EF_MIPS_MACH_9000 0x00990000 EM_ARC_COMPACT 93 DT_PREINIT_ARRAY 32 PF_MIPS_LOCAL 0x10000000 R_RISCV_ADD64 36 DT_AUXILIARY 0x7ffffffd SHF_MASKPROC 0xf0000000 R_PPC_TPREL16_HA 72 PT_MIPS_RTPROC 0x70000001 OHWA0_R4KEOP_CHECKED 0x00000001 R_MICROMIPS_PC16_S1 141 R_68K_TLS_IE32 34 EM_MMDSP_PLUS 160 EM_COLDFIRE 52 R_X86_64_PC16 13 symbol_type R_AARCH64_TLSGD_MOVW_G0_NC 516 R_MIPS_RELGOT 36 NT_PPC_PKEY 0x110 SHT_MIPS_MSYM 0x70000001 R_ARM_THM_PC9 103 R_386_COPY 5 EI_VERSION 6 R_IA64_SEGREL32LSB 0x5d MIPS_AFL_ASE_MICROMIPS 0x00000800 AT_EXECFD 2 PT_DYNAMIC 2 R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 DT_MIPS_IVERSION 0x70000004 PT_ARM_EXIDX (PT_LOPROC + 1) R_PPC_EMB_SDAI16 106 R_ARM_ALU_SB_G1_NC 72 EF_SPARC_EXT_MASK 0xFFFF00 R_TILEPRO_IMM16_X0_GOT_HI 43 R_386_PC16 21 SHN_MIPS_SUNDEFINED 0xff04 EM_78KOR 199 R_CKCORE_NONE 0 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN R_PPC64_PLTGOT16_HI 54 DF_1_NOOPEN 0x00000040 SHT_SUNW_syminfo 0x6ffffffc R_CRIS_32 3 STT_HIPROC 15 R_68K_TLS_LDM16 29 DT_MIPS_DYNSTR_ALIGN 0x7000002b SHT_DYNAMIC 6 R_CRIS_NONE 0 EF_SH2A_SH3_NOFPU 0x16 NT_PPC_TM_CPPR 0x10e R_METAG_TLS_LE_LO16 61 R_PPC64_ADDR64 38 R_PARISC_PCREL64 72 STT_ARM_TFUNC STT_LOPROC ET_NONE 0 R_390_GOTPLT32 31 DF_1_DIRECT 0x00000100 SHF_IA_64_SHORT 0x10000000 R_PPC64_ADDR16_HIGHEST 41 SHT_MIPS_XHASH 0x7000002b R_MIPS_32 2 DT_MIPS_LIBLISTNO 0x70000010 EF_ALPHA_CANRELAX 2 EM_H8_500 49 R_ARC_SECTOFF_ME_2 0x2A R_ARM_GOTPC 25 EM_TILEPRO 188 R_X86_64_REX_GOTPCRELX 42 R_SH_TLS_GD_32 144 R_PPC_DTPREL16_LO 75 R_ARM_LDR_PC_G1 62 R_PARISC_GPREL16DF 95 OPAD_SYMBOL 0x4 R_ARM_THM_PC11 102 R_METAG_LOOG 14 R_LARCH_64 2 R_M32R_GOTOFF_HI_ULO 62 PF_HP_CODE 0x01000000 R_CKCORE_COPY 10 R_PPC64_GOT16_LO R_PPC_GOT16_LO EM_MMA 54 R_AARCH64_GOT_LD_PREL19 309 EM_BPF 247 STO_MIPS_PLT 0x8 R_AARCH64_TLSDESC_LD64_LO12 563 RHF_SGI_ONLY (1 << 4) R_SH_DIR8L 9 R_OR1K_TLS_IE_LO16 29 R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 R_CKCORE_GOTPC_LO16 27 R_CKCORE_ADDRGOT 17 AT_SECURE 23 R_IA64_PCREL21M 0x4a R_AARCH64_TLSLD_LD_PREL19 522 R_TILEGX_IMM8_X0_TLS_ADD 118 R_ALPHA_TPRELLO 40 R_PARISC_TLS_LDM21L 237 DT_LOPROC 0x70000000 R_SPARC_PC_LM22 39 LL_REQUIRE_MINOR (1 << 2) ET_EXEC 2 EM_MMIX 80 R_ALPHA_TLS_GD_HI 28 R_PPC64_ADDR16_HA R_PPC_ADDR16_HA ELFCOMPRESS_LOOS 0x60000000 R_IA64_COPY 0x84 R_PPC64_ADDR16_HIGHESTA 42 R_TILEPRO_MMSTART_X0 47 R_PPC_GOT_TPREL16_HA 90 R_LARCH_TLS_DTPMOD64 7 R_M32R_NUM 256 R_MIPS_CALL_LO16 31 R_TILEGX_IMM16_X1_HW2_PLT_PCREL 71 R_MICROMIPS_GOT_DISP 145 SHT_CSKY_ATTRIBUTES (SHT_LOPROC + 1) _ELF_H 1 R_NIOS2_TLS_IE16 31 NT_RISCV_VECTOR 0x901 DF_1_LOADFLTR 0x00000010 EF_CSKY_ABIV1 0X10000000 R_IA64_DIR64MSB 0x26 R_NIOS2_GOT16 22 R_PARISC_GPREL14R 30 R_390_PC32DBL 19 GNU_PROPERTY_LOPROC 0xc0000000 NT_ARM_TLS 0x401 R_MN10300_COPY 20 R_RISCV_SUB16 38 R_TILEGX_8 4 R_PPC_REL16_LO 250 R_ARC_S21W_PCREL_PLT 0x3C EF_ARM_APCS_FLOAT 0x10 DT_RUNPATH 29 R_MICROBLAZE_COPY 21 ELFCOMPRESS_ZLIB 1 R_ARM_TLS_LDO32 106 R_SH_SWITCH32 26 AT_L3_CACHEGEOMETRY 47 PF_ARM_SB 0x10000000 OEX_SMM 0x20000 R_PPC_TPREL32 73 EF_MIPS_PIC 2 R_PPC_GOT16_HI 16 R_PARISC_PCREL14R 14 R_OR1K_TLS_GD_LO16 23 VER_NEED_NUM 2 EM_KMX32 211 R_ARM_ALU_SBREL_27_20 37 R_390_GOTPLTENT 33 EM_FIREPATH 78 SHT_MIPS_DELTACLASS 0x7000001d R_TILEPRO_IMM16_X0_TLS_LE_HA 91 R_386_NONE 0 R_PPC_PLTREL32 28 R_RISCV_GOT_HI20 20 R_68K_TLS_LDO8 33 R_ARC_JLI_SECTOFF 0x3F R_390_RELATIVE 12 R_RISCV_IRELATIVE 58 R_PPC64_IRELATIVE 248 R_MIPS_GOT_HI16 22 GNU_PROPERTY_1_NEEDED GNU_PROPERTY_UINT32_OR_LO R_PARISC_LTOFF16DF 103 R_PPC_EMB_SDA2REL 108 SHT_MIPS_XLATE 0x70000024 R_68K_JMP_SLOT 21 EF_ALPHA_32BIT 1 R_TILEPRO_BROFF_X1 14 EF_PPC_RELOCATABLE 0x00010000 R_METAG_TLS_DTPMOD 57 R_ARM_LDRS_PC_G0 64 R_390_PLT32DBL 20 R_390_TLS_LDO64 53 EF_ARM_EABI_VER2 0x02000000 EF_ARC_ALL_MSK (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK) R_PPC_TOC16 255 EM_AVR32 185 R_IA64_LTV32MSB 0x74 R_AARCH64_P32_IRELATIVE 188 ELFDATANONE 0 EM_FR30 84 R_SH_TLS_LD_32 145 PT_PARISC_ARCHEXT 0x70000000 R_386_TLS_LDM_POP 31 R_PARISC_TPREL16F 221 DF_P1_LAZYLOAD 0x00000001 NT_ARM_SYSTEM_CALL 0x404 R_ARM_PC13 4 R_AARCH64_MOVW_GOTOFF_G0 300 R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 R_ARC_S25W_PCREL_PLT 0x4C NT_PPC_TM_CDSCR 0x10f EM_M32R 88 RHF_REQUICKSTART (1 << 10) EF_MIPS_ABI 0x0000F000 R_MICROMIPS_CALL_HI16 153 EM_ECOG1X 168 R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 R_PPC64_GOT_TLSGD16 79 R_OR1K_GNU_VTENTRY 7 R_ARM_PLT32 27 R_TILEPRO_IMM16_X1_TLS_IE_HI 79 R_LARCH_SOP_ADD 35 R_SH_REL32 2 R_SPARC_PC10 16 R_TILEPRO_GLOB_DAT 11 R_TILEPRO_MT_IMM15_X1 21 SHN_HIOS 0xff3f R_PARISC_TLS_DTPOFF32 244 R_AARCH64_TLSDESC_CALL 569 R_PPC_DTPREL32 78 R_SPARC_TLS_IE_LD 69 R_SPARC_WDISP16 40 EM_TILEGX 191 R_M32R_GOT16_HI_SLO 57 EM_V800 36 PT_HP_CORE_SHM (PT_LOOS + 0x8) SHF_MIPS_NAMES 0x02000000 EM_M32C 120 _D 0x04 R_CKCORE_GOT_IMM18BY4 48 R_TILEPRO_JMP_SLOT 12 R_386_TLS_LE_32 34 R_SH_NUM 256 DT_MIPS_LOCAL_GOTNO 0x7000000a R_TILEPRO_IMM16_X1_TLS_IE_LO 77 R_PARISC_TLS_LE21L R_PARISC_TPREL21L R_METAG_TLS_LE_HI16 60 OHW_R5KEOP 0x4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 R_RISCV_TPREL_LO12_S 31 R_IA64_LTOFF_FPTR22 0x52 EF_MIPS_MACH_4111 0x00880000 R_TILEGX_IMM16_X1_HW0_PCREL 51 R_IA64_DTPREL32MSB 0xb4 R_68K_TLS_LDO32 31 R_PPC_SECTOFF 33 R_PPC64_PLT16_LO_DS 60 STO_MIPS_HIDDEN 0x2 R_NIOS2_IMM8 8 R_METAG_LOADDR16 1 EM_BA1 201 R_PARISC_PLABEL21L 66 R_TILEPRO_8_PCREL 6 R_ARC_SECTOFF_U8 0x21 R_SPARC_PCPLT10 29 DT_MIPS_GP_VALUE 0x70000030 R_X86_64_TPOFF32 23 PF_R (1 << 2) EF_MIPS_ARCH_2 0x10000000 R_AARCH64_LDST32_ABS_LO12_NC 285 R_390_TLS_IE32 47 ELFOSABI_ARM 97 NT_LOONGARCH_HW_BREAK 0xa05 DT_DEBUG 21 R_TILEPRO_IMM16_X1_TLS_LE 86 PF_HP_FAR_SHARED 0x00200000 PT_HP_CORE_PROC (PT_LOOS + 0x5) R_SPARC_LM22 36 AT_BASE 7 EF_ARM_OLD_ABI 0x100 R_MIPS_SUB 24 R_ALPHA_HINT 8 R_IA64_DIR32LSB 0x25 R_386_16 20 R_PPC64_PLTGOT16_HA 55 DT_CHECKSUM 0x6ffffdf8 DT_GNU_CONFLICT 0x6ffffef8 EM_Z80 220 R_TILEGX_8_PCREL 8 R_M32R_18_PCREL 5 R_PPC_SECTOFF_LO 34 NT_MIPS_MSA 0x802 R_NIOS2_CALL26_NOAT 41 EI_MAG2 2 DT_SONAME 14 R_ALPHA_GPDISP 6 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 R_PARISC_PLTOFF14R 54 NT_PRXREG 4 MIPS_AFL_ASE_MCU 0x00000008 E_MIPS_ARCH_32 EF_MIPS_ARCH_32 ET_LOPROC 0xff00 R_PPC64_GOT_DTPREL16_HA 94 R_TILEGX_TLS_DTPMOD32 109 DF_1_PIE 0x08000000 R_CRIS_NUM 20 R_AARCH64_JUMP26 282 R_386_32 1 R_MIPS_JUMP_SLOT 127 PT_NUM 8 DT_ADDRNUM 11 PT_TLS 7 R_PPC_DTPREL16_HI 76 R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 97 R_TILEGX_SHAMT_X0 32 R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 R_ALPHA_TPRELHI 39 EM_MIPS_RS3_LE 10 EM_NONE 0 ELFCOMPRESS_HIOS 0x6fffffff EF_MIPS_ARCH_64R6 0xa0000000 R_M32R_HI16_ULO 7 DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) R_TILEGX_JUMPOFF_X1 21 R_X86_64_RELATIVE64 38 R_AARCH64_GLOB_DAT 1025 R_LARCH_PCALA_HI20 71 R_TILEGX_64 1 R_MICROBLAZE_GNU_VTENTRY 12 R_ARM_TLS_DESC 13 VER_NDX_GLOBAL 1 SHT_ARM_EXIDX (SHT_LOPROC + 1) R_390_PLT32 8 R_ARM_RABS22 253 R_PPC_GOT_DTPREL16_LO 92 R_MIPS_ADD_IMMEDIATE 34 DT_STRTAB 5 R_TILEGX_IMM16_X0_HW0_TLS_LE 80 SHF_MIPS_STRINGS 0x80000000 EM_SEP 108 R_RISCV_ADD32 35 R_AARCH64_TLSDESC_ADR_PREL21 561 SHN_PARISC_HUGE_COMMON 0xff01 R_390_TLS_LE64 51 R_TILEPRO_IMM16_X0_HA 29 DT_MIPS_LOCAL_GOTIDX 0x70000026 R_MICROBLAZE_TLSGD 23 R_LARCH_GNU_VTENTRY 58 R_RISCV_PCREL_LO12_I 24 R_PPC64_REL16_HA 252 R_AARCH64_ADR_PREL_LO21 274 R_PPC_GOT_TLSGD16_HI 81 EM_CSR_KALIMBA 219 R_ARM_THM_JUMP24 30 MIPS_AFL_EXT_5500 16 EM_ARCA 109 DT_SYMENT 11 R_OR1K_JMP_SLOT 20 R_SPARC_OLO10 33 PT_MIPS_REGINFO 0x70000000 R_RISCV_TPREL_HI20 29 R_PARISC_DPREL14R 22 EF_ARM_EABI_VER4 0x04000000 DT_MIPS_DELTA_INSTANCE 0x70000019 R_PARISC_TLS_DTPMOD32 242 R_NIOS2_HIADJ16 11 R_MIPS_INSERT_B 26 R_AARCH64_MOVW_UABS_G0_NC 264 AT_EGID 14 R_MICROMIPS_GOT_LO16 149 R_RISCV_SUB64 40 EF_SH2A_NOFPU 0x13 R_SH_TLS_IE_32 147 R_PPC64_RELATIVE R_PPC_RELATIVE R_TILEGX_IMM16_X1_HW0_TLS_LE 81 R_TILEGX_IMM16_X0_HW2_PCREL 54 DT_MIPS_PIXIE_INIT 0x70000023 R_METAG_GETSET_GOTOFF 34 NT_AUXV 6 R_IA64_FPTR32MSB 0x44 R_PPC_IRELATIVE 248 R_ALPHA_RELATIVE 27 R_SPARC_JMP_IREL 248 R_AARCH64_MOVW_PREL_G3 293 R_M32R_18_PCREL_RELA 37 DT_MIPS_AUX_DYNAMIC 0x70000031 EM_VIDEOCORE5 198 R_IA64_DTPREL22 0xb2 R_M32R_GLOB_DAT 51 ELFOSABI_MODESTO 11 PPC64_OPT_TLS 1 R_ARM_TLS_GOTDESC 90 R_390_GOTPLT20 59 R_TILEGX_IMM16_X0_HW2_PLT_PCREL 70 EM_68HC12 53 R_IA64_IMM14 0x21 PF_W (1 << 1) R_SPARC_5 44 R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 96 EM_PARISC 15 EF_MIPS_MACH_4650 0x00850000 R_386_32PLT 11 R_SH_GOTPC 167 R_SH_DIR8WPL 5 R_AARCH64_P32_GLOB_DAT 181 R_AARCH64_MOVW_UABS_G1 265 R_ARM_ALU_PCREL_7_0 32 R_MIPS_LITERAL 8 R_METAG_REL8 15 R_MICROMIPS_SUB 150 SHT_LOOS 0x60000000 NT_PPC_TM_CVMX 0x10a R_RISCV_SET8 54 DT_MIPS_DELTA_RELOC_NO 0x7000001c R_SPARC_TLS_LDM_ADD 62 R_MICROMIPS_JALR 156 R_AARCH64_ABS16 259 R_ARC_TLS_LE_S9 0x4A ODK_REGINFO 1 NT_PRCRED 14 AT_ICACHEBSIZE 20 EF_MIPS_MACH_OCTEON2 0x008d0000 R_TILEPRO_IMM16_X0_HI_PCREL 35 ODK_HWAND 7 DT_MIPS_UNREFEXTNO 0x70000012 SHT_HISUNW 0x6fffffff AT_GID 13 R_PARISC_PCREL16F 77 R_MIPS16_TLS_LDM 107 EF_IA_64_ABI64 0x00000010 GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 R_RISCV_TLS_DTPMOD64 7 SHT_RISCV_ATTRIBUTES (SHT_LOPROC + 3) DT_MIPS_XHASH 0x70000036 R_MN10300_GNU_VTENTRY 8 R_PPC_DIAB_SDA21_HI 181 R_MICROMIPS_GPREL16 136 R_OR1K_8_PCREL 11 R_AARCH64_TLSDESC 1031 R_AARCH64_LDST64_ABS_LO12_NC 286 R_MICROMIPS_HI16 134 R_390_32 4 R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 R_PARISC_LTOFF14WR 99 EM_S390 22 GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1) R_PPC64_DTPREL16_LO_DS 102 R_ALPHA_GPREL16 19 R_M32R_26_PLTREL 49 ELFCLASS32 1 DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) R_PARISC_TLS_GD14R 235 AT_PLATFORM 15 R_386_NUM 44 NT_MIPS_DSP 0x800 R_X86_64_GOTPC32_TLSDESC 34 SHT_PREINIT_ARRAY 16 DT_MIPS_RWPLT 0x70000034 R_METAG_REG16OP3 11 DT_PLTPADSZ 0x6ffffdf9 DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d DT_RELCOUNT 0x6ffffffa RHF_REQUICKSTARTED (1 << 11) R_PARISC_GPREL14DR 92 R_AARCH64_TLSDESC_ADD 568 R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 R_ARM_RXPC25 249 R_ARC_S13_PCREL 0x19 R_CKCORE_PLT12 33 R_ARM_TLS_IE12GP 111 EM_TINYJ 61 EF_MIPS_MACH_XLR 0x008c0000 EF_RISCV_TSO 0x0010 EM_TPC 98 SHF_IA_64_NORECOV 0x20000000 R_MN10300_16 2 R_RISCV_SET_ULEB128 60 AT_L1I_CACHEGEOMETRY 41 R_MN10300_TLS_LDO 26 R_TILEGX_IMM16_X1_HW3_PLT_PCREL 77 R_MIPS_PC18_S3 62 R_TILEPRO_IMM8_Y0 18 R_MIPS16_LO16 105 EV_CURRENT 1 R_IA64_LTV64MSB 0x76 R_SPARC_LO10 12 R_IA64_IPLTLSB 0x81 EI_MAG1 1 R_PARISC_PLTOFF21L 50 EM_TRICORE 44 R_390_TLS_LDO32 52 R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 R_CRIS_32_GOTPLT 16 R_PARISC_SEGBASE 48 EV_NUM 2 SHT_LOUSER 0x80000000 R_ARC_SDA 0xC R_MIPS_EH 249 R_NIOS2_LO16 10 R_RISCV_TPREL_ADD 32 EF_ARM_ABI_FLOAT_HARD 0x400 R_OR1K_TLS_LDM_LO16 25 EF_ARM_SOFT_FLOAT 0x200 R_TILEGX_IMM16_X0_HW0_LAST 44 _U 0x01 R_PPC_SECTOFF_HI 35 R_386_GOT32X 43 R_TILEPRO_IMM16_X1_TLS_LE_HA 92 NT_UTSNAME 15 DT_X86_64_PLT (DT_LOPROC + 0) R_ARM_RELATIVE 23 R_CRIS_16_GOTPLT 15 DT_PPC_OPT (DT_LOPROC + 1) R_SPARC_TLS_IE_LO10 68 ELF64_M_SIZE(info) ELF32_M_SIZE (info) OPAD_POSTFIX 0x2 NT_GNU_HWCAP 2 STT_ARM_16BIT STT_HIPROC AT_HWCAP4 30 R_TILEGX_64_PCREL 5 R_IA64_IMM64 0x23 R_SPARC_TLS_GD_LO10 57 R_OR1K_TLS_DTPOFF 33 R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 94 R_TILEPRO_MF_IMM15_X1 22 R_SPARC_COPY 19 EM_H8S 48 DT_PPC_GOT (DT_LOPROC + 0) R_AARCH64_LDST128_ABS_LO12_NC 299 SHF_COMPRESSED (1 << 11) EM_ALTERA_NIOS2 113 DT_ADDRRNGHI 0x6ffffeff R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 R_METAG_REG32OP4 12 E_MIPS_ARCH_64 EF_MIPS_ARCH_64 R_NIOS2_TLS_DTPMOD 33 R_AARCH64_ADD_ABS_LO12_NC 277 EF_CPU32 0x00810000 R_PPC64_REL16_LO 250 R_CKCORE_PCREL_IMM10BY4 23 R_SPARC_TLS_LDM_CALL 63 MIPS_AFL_EXT_OCTEON2 2 R_NIOS2_GPREL 15 DT_PPC64_OPDSZ (DT_LOPROC + 2) EM_ARCV2 195 LITUSE_ALPHA_TLS_GD 4 R_386_TLS_GOTDESC 39 R_PPC_LOCAL24PC 23 MIPS_AFL_EXT_OCTEONP 3 AT_CLKTCK 17 R_NDS32_JMP_SLOT 41 DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) NT_LOONGARCH_LBT 0xa04 RHF_NO_UNRES_UNDEF (1 << 13) STB_HIPROC 15 R_386_GLOB_DAT 6 R_ARM_MOVW_BREL 86 R_IA64_GPREL64MSB 0x2e R_PARISC_COPY 128 DT_MIPS_LIBLIST 0x70000009 R_MICROBLAZE_32_PCREL 2 SELFMAG 4 R_RISCV_TPREL_S 50 R_ARM_RBASE 255 R_LARCH_RELAX 100 R_ARM_LDRS_SB_G1 79 ELF32_M_SYM(info) ((info) >> 8) EF_MIPS_ARCH_64 0x60000000 NT_S390_PREFIX 0x305 R_ARC_H30 0x7 R_TILEGX_IMM16_X1_HW3_PCREL 57 R_METAG_HI16_GOTOFF 32 EM_EMX16 212 R_IA64_GPREL32MSB 0x2c R_AARCH64_TLSGD_ADR_PREL21 512 R_M32R_REL32 45 R_LARCH_SOP_PUSH_PCREL 22 R_MN10300_GOT32 17 R_LARCH_ADD8 47 R_ALPHA_DTPREL16 36 EM_NDS32 167 R_TILEGX_GLOB_DAT 17 DT_POSFLAG_1 0x6ffffdfd R_TILEGX_IMM16_X0_HW1_LAST 46 ELFMAG3 'F' R_PPC64_GOT_DTPREL16_LO_DS 92 AT_RSEQ_ALIGN 28 DT_MIPS_COMPACT_SIZE 0x7000002f R_390_TLS_DTPOFF 55 EM_CRAYNV2 172 DT_MIPS_DELTA_RELOC 0x7000001b R_IA64_TPREL14 0x91 R_ALPHA_COPY 24 R_IA64_TPREL64I 0x93 R_LARCH_SOP_PUSH_TLS_TPREL 26 EF_PARISC_WIDE 0x00080000 NT_GNU_ABI_TAG 1 ODK_EXCEPTIONS 2 EF_MIPS_ARCH_1 0x00000000 R_MICROMIPS_TLS_DTPREL_HI16 164 SHT_MIPS_IFACE 0x7000000b R_MICROBLAZE_SRW32 8 SHT_HIOS 0x6fffffff OEX_FPU_UFLO 0x02 EM_XGATE 115 R_M32R_RELA_GNU_VTINHERIT 43 R_IA64_LTOFF_FPTR32MSB 0x54 R_SPARC_PCPLT22 28 GNU_PROPERTY_STACK_SIZE 1 R_390_PC64 23 EM_MCHP_PIC 204 R_METAG_COPY 43 R_SH_GOTOFF 166 EM_TI_C5500 142 R_METAG_TLS_LE 59 PT_HP_CORE_COMM (PT_LOOS + 0x4) R_PPC64_ADDR16_HI R_PPC_ADDR16_HI PPC64_OPT_LOCALENTRY 4 R_RISCV_ALIGN 43 R_PPC64_REL64 44 R_MN10300_TLS_LD 25 GNU_PROPERTY_UINT32_AND_HI 0xb0007fff R_PARISC_TLS_GD21L 234 R_PPC_EMB_NADDR32 101 R_ARC_SECTOFF_S9 0x22 EM_QDSP6 164 DT_MIPS_CONFLICTNO 0x7000000b PT_MIPS_OPTIONS 0x70000002 DF_1_INITFIRST 0x00000020 R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 SHT_MIPS_EVENTS 0x70000021 R_NIOS2_PCREL16 3 NT_GNU_BUILD_ID 3 RHF_GUARANTEE_START_INIT (1 << 7) DT_SYMINSZ 0x6ffffdfe NT_PPC_TAR 0x103 R_IA64_LTV32LSB 0x75 R_ARM_THM_MOVW_BREL_NC 87 NT_PPC_VSX 0x102 R_LARCH_GOT_PC_HI20 75 R_NIOS2_PCREL_LO 26 SHF_MIPS_MERGE 0x20000000 EF_IA_64_ARCH 0xff000000 R_M32R_GOTPC_HI_ULO 59 SHT_LOSUNW 0x6ffffffa R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 R_CRIS_16_PCREL 5 PT_RISCV_ATTRIBUTES (PT_LOPROC + 3) R_CKCORE_GOTOFF 13 EM_PCP 55 R_390_64 22 PF_MASKOS 0x0ff00000 R_390_TLS_LE32 50 R_SH_COUNT 28 SHF_MIPS_LOCAL 0x04000000 EM_TI_C2000 141 R_390_TLS_GD64 41 R_CKCORE_ADDRGOT_HI16 36 R_SPARC_DISP8 4 R_ARM_TLS_GD32 104 R_MICROMIPS_TLS_LDM 163 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 SHT_MIPS_CONTENT 0x7000000c ET_DYN 3 R_SPARC_GOT10 13 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 ELF32_R_TYPE(val) ((val) & 0xff) R_PPC64_ADDR16_HIGHERA 40 R_PARISC_SECREL64 104 MIPS_AFL_ASE_SMARTMIPS 0x00000080 R_OR1K_16 2 R_MN10300_SYM_DIFF 33 R_SH_GLOB_DAT 163 R_TILEPRO_IMM16_X0_TLS_IE_HA 80 R_386_TLS_DTPOFF32 36 STB_GNU_UNIQUE 10 R_ARM_TLS_LDM32 105 PF_ARM_PI 0x20000000 R_IA64_GPREL32LSB 0x2d R_MIPS_GOT_PAGE 20 R_PPC_ADDR14 7 R_TILEGX_IMM8_X1_TLS_GD_ADD 114 EFA_PARISC_1_0 0x020b EF_SH2A_SH4 0x17 EF_MIPS_ABI_O64 0x00002000 EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 R_PPC_PLT16_HA 31 DT_RISCV_VARIANT_CC (DT_LOPROC + 1) isupper(c) ((__ismask(c)&(_U)) != 0) R_CKCORE_ADDR32 1 R_SH_DIR8WPN 3 R_IA64_LTOFF22X 0x86 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 R_RISCV_RVC_LUI 46 SYMINFO_CURRENT 1 R_AC_SECTOFF_S9 0x26 SHN_COMMON 0xfff2 EM_TILE64 187 SHF_MIPS_NOSTRIP 0x08000000 R_CKCORE_PCREL_IMM16BY2 20 R_SPARC_TLS_IE_HI22 67 SHT_MIPS_REGINFO 0x70000006 R_390_GLOB_DAT 10 R_68K_TLS_DTPREL32 41 PT_HP_FASTBIND (PT_LOOS + 0x11) _ctype R_PPC64_DTPREL16 74 R_390_TLS_LDCALL 39 R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44 R_ARM_LDR_SB_G0 75 R_ARC_SDA16_LD 0x16 R_OR1K_TLS_LE_HI16 30 R_ARC_SDA_12 0x2D SHT_MIPS_XLATE_OLD 0x70000028 EM_MANIK 171 R_PPC64_TPREL16 69 R_TILEPRO_SHAMT_Y1 54 MIPS_AFL_EXT_OCTEON 5 R_SPARC_WDISP19 41 R_68K_16 2 R_AARCH64_CALL26 283 ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) R_SPARC_DISP32 6 R_LARCH_SOP_SR 34 DT_SYMINFO 0x6ffffeff DF_BIND_NOW 0x00000008 R_M32R_32 2 R_PPC64_GOT16_DS 58 R_TILEGX_TLS_IE_LOAD 117 R_ARM_ALU_SB_G2 74 SHN_PARISC_ANSI_COMMON 0xff00 R_IA64_SECREL64LSB 0x67 R_PPC64_DTPREL16_HIGH 114 R_SPARC_TLS_GD_HI22 56 R_AARCH64_TLSLD_ADR_PAGE21 518 EM_CR 103 R_ALPHA_TPREL64 38 R_MN10300_GOTOFF16 14 EF_CSKY_ABIMASK 0XF0000000 DF_1_DISPRELPND 0x00010000 EM_68K 4 R_OR1K_32 1 R_NDS32_TLS_TPOFF 102 EM_BA2 202 R_CKCORE_GOTOFF_LO16 29 R_PARISC_TPREL14DR 220 R_ARC_PC32 0x32 R_PARISC_TLS_DTPMOD64 243 EM_ETPU 178 R_LARCH_MARK_LA 20 MIPS_AFL_EXT_4100 9 R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 R_SPARC_DISP64 46 DT_LOOS 0x6000000d R_MN10300_TLS_DTPOFF 31 R_MIPS16_GOT16 102 R_PPC64_PLT16_HA R_PPC_PLT16_HA NT_LOONGARCH_LASX 0xa03 EM_RL78 197 R_TILEGX_16 3 R_CKCORE_TLS_LDO32 55 R_TILEGX_IMM16_X1_HW1 39 NT_PPC_DSCR 0x105 R_METAG_GOTOFF 41 EF_MIPS_UCODE 16 ELFOSABI_OPENBSD 12 R_AARCH64_P32_JUMP_SLOT 182 R_OR1K_TLS_LDO_LO16 27 R_SPARC_NONE 0 R_ARC_TLS_GD_LD 0x46 NT_PRFPREG 2 R_TILEGX_BROFF_X1 20 R_TILEPRO_IMM16_X0_PCREL 31 R_MICROBLAZE_TLSLD 24 EM_STXP7X 166 PT_HP_CORE_MMF (PT_LOOS + 0x9) R_PPC_EMB_NADDR16_HA 105 EF_RISCV_FLOAT_ABI_QUAD 0x0006 R_TILEGX_IMM16_X0_HW0 36 R_386_TLS_IE_32 33 EM_MN10300 89 SHF_MIPS_GPREL 0x10000000 EM_SHARC 133 R_390_TLS_GOTIE64 44 R_PPC64_GOT_TLSLD16_HA 86 R_MIPS16_26 100 R_TILEGX_SHAMT_Y0 34 R_ALPHA_REFLONG 1 MIPS_AFL_EXT_4120 14 R_390_GOT16 15 PT_LOSUNW 0x6ffffffa SHT_MIPS_LOCSYM 0x70000015 RHF_QUICKSTART (1 << 0) ELFOSABI_IRIX 8 R_AARCH64_P32_RELATIVE 183 R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R EF_SH2E 0xb EF_ARM_LE8 0x00400000 ELFOSABI_HPUX 1 R_ARC_GOT32 0x3B R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 R_RISCV_TLS_GD_HI20 22 LITUSE_ALPHA_ADDR 0 EM_COREA_2ND 194 DT_HIOS 0x6ffff000 R_PARISC_TPREL16WF 222 R_68K_TLS_IE8 36 SHT_NOBITS 8 EF_SH3_NOMMU 0x14 ELF64_M_SYM(info) ELF32_M_SYM (info) kallsyms2elf_type SHT_GNU_verdef 0x6ffffffd R_SPARC_TLS_LDO_LOX10 65 R_ARM_LDRS_PC_G1 65 R_LARCH_SOP_POP_32_U_10_12 39 EF_SH4A 0xc R_LARCH_SOP_PUSH_DUP 24 MIPS_AFL_REG_128 0x03 R_LARCH_32_PCREL 99 R_AARCH64_ADR_PREL_PG_HI21_NC 276 R_TILEPRO_IMM16_X0_TLS_LE_LO 87 SHT_MIPS_DELTAINST 0x7000001c R_TILEGX_IMM8_X0_TLS_GD_ADD 113 EF_ARM_MAVERICK_FLOAT 0x800 GRP_COMDAT 0x1 SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) R_NIOS2_JUMP_SLOT 38 EM_ST200 100 R_X86_64_GOTPCRELX 41 AT_L2_CACHESHAPE 36 R_ARC_SDA16_LD2 0x18 R_MIPS_64 18 R_SPARC_TLS_LDO_HIX22 64 DT_AARCH64_VARIANT_PCS (DT_LOPROC + 5) R_PARISC_TPREL14WR 219 DT_MIPS_CXX_FLAGS 0x70000022 R_PARISC_LTOFF_TP14R 166 R_TILEGX_TLS_DTPMOD64 106 isdigit(c) __builtin_isdigit(c) R_MIPS_SCN_DISP 32 R_OR1K_COPY 18 R_68K_COPY 19 EF_SPARC_32PLUS 0x000100 EM_K10M 181 EF_ARM_ABI_FLOAT_SOFT 0x200 R_390_IRELATIVE 61 ELF32_M_INFO(sym,size) (((sym) << 8) + (unsigned char) (size)) R_386_TLS_GD_PUSH 25 AT_L1D_CACHEGEOMETRY 43 R_LARCH_SOP_AND 36 EF_MIPS_ARCH_32 0x50000000 R_MN10300_8 3 R_PPC64_TPREL16_DS 95 R_NIOS2_GLOB_DAT 37 EI_PAD 9 PT_GNU_STACK 0x6474e551 DT_GNU_LIBLIST 0x6ffffef9 PF_HP_LAZYSWAP 0x04000000 R_ARM_GNU_VTINHERIT 101 R_390_PLT16DBL 18 R_PARISC_LTOFF_FPTR16WF 126 R_386_IRELATIVE 42 R_TILEPRO_IMM16_X0_HA_PCREL 37 isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) R_MN10300_PCREL16 5 R_CRIS_JUMP_SLOT 11 _C 0x08 R_386_TLS_DTPMOD32 35 DF_1_NOCOMMON 0x40000000 R_LARCH_SOP_IF_ELSE 37 DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) R_MICROMIPS_PC7_S1 139 R_AARCH64_MOVW_UABS_G2 267 NT_ARM_PAC_MASK 0x406 R_LARCH_TLS_IE_PC_HI20 87 R_NIOS2_GOTOFF 40 R_MICROMIPS_CALL16 142 R_ARC_16 0x2 R_ALPHA_GPREL32 3 ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) R_MIPS_TLS_TPREL_HI16 49 R_SPARC_WDISP30 7 SYMINFO_BT_LOWRESERVE 0xff00 EF_ARM_PIC 0x20 SHF_TLS (1 << 10) EM_TI_ARP32 143 VER_FLG_WEAK 0x2 DF_1_NODUMP 0x00001000 R_PPC64_JMP_IREL 247 R_386_TLS_GD_POP 27 R_LARCH_TLS_LE64_HI12 86 SHF_GROUP (1 << 9) R_PARISC_TLS_LDO14R 241 R_LARCH_SUB_ULEB128 108 R_PARISC_PCREL22F 74 EM_TI_PRU 144 R_IA64_SEGREL32MSB 0x5c R_METAG_GNU_VTINHERIT 30 MIPS_AFL_EXT_LOONGSON_3A 4 R_MIPS_GNU_REL16_S2 250 DT_DEPAUDIT 0x6ffffefb R_PPC64_DTPREL16_LO 75 SHF_PARISC_HUGE 0x40000000 AT_IGNOREPPC 22 R_AARCH64_LD_PREL_LO19 273 EM_MSP430 105 R_386_TLS_GD 18 DT_RELENT 19 R_SPARC_GOTDATA_LOX10 81 STO_MIPS_INTERNAL 0x1 R_LARCH_GOT64_HI12 82 R_ARM_PLT32_ABS 94 R_PARISC_LTOFF_FPTR14WR 123 R_SH_GNU_VTENTRY 35 R_AARCH64_P32_TLS_TPREL 186 R_NIOS2_TLS_LDO16 30 R_TILEGX_IMM8_Y0_TLS_ADD 120 SHT_GROUP 17 R_PARISC_LTOFF_TP64 224 R_ARM_GOTRELAX 99 R_SPARC_H34 85 R_ALPHA_GLOB_DAT 25 R_MN10300_JMP_SLOT 22 __tolower EF_MIPS_ARCH 0xf0000000 R_METAG_REL16 16 R_386_TLS_LDM_32 28 EM_EXCESS 111 R_RISCV_GNU_VTENTRY 42 R_SPARC_GOTDATA_HIX22 80 R_PPC_GOT16_HA 17 R_PPC_UADDR32 24 R_MICROBLAZE_TLSGOTTPREL32 28 EF_LARCH_ABI_MODIFIER_MASK 0x07 ELF_NOTE_OS_LINUX 0 R_X86_64_32S 11 R_68K_PLT16 14 DF_1_WEAKFILTER 0x20000000 R_LARCH_DELETE 101 R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 NT_LWPSTATUS 16 R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 ELFMAG0 0x7f R_METAG_REG32OP1 6 R_ARM_THM_MOVT_PREL 50 R_PPC_EMB_RELST_HA 114 EF_MIPS_MACH_5900 0x00920000 R_RISCV_HI20 26 OHWA1_R4KEOP_CLEAN 0x00000002 R_MIPS_PC21_S2 60 R_MIPS_GOT_DISP 19 R_PPC_JMP_SLOT 21 EM_SCORE7 135 R_390_TLS_GOTIE12 42 R_ARC_B22_PCREL 0x6 EM_RH32 38 R_PPC64_UADDR32 R_PPC_UADDR32 R_ARC_SDA_LDST1 0x14 R_MIPS_GOT_OFST 21 R_PARISC_DIR64 80 R_PPC_DIAB_SDA21_LO 180 AT_L1D_CACHESHAPE 35 R_PPC64_TLSGD 107 R_PARISC_LTOFF_FPTR14R 62 R_TILEGX_IMM16_X1_HW2_LAST 49 R_68K_TLS_LE16 38 SHF_PARISC_SBP 0x80000000 R_MIPS16_GPREL 101 R_ARM_ALU_PC_G2 61 R_PPC_ADDR16 3 SHT_PARISC_EXT 0x70000000 ELFCLASSNUM 3 R_SH_GNU_VTINHERIT 34 R_SH_TLS_LDO_32 146 E_MIPS_ARCH_2 EF_MIPS_ARCH_2 R_TILEGX_TLS_GD_CALL 112 DT_INIT 12 R_METAG_TLS_LDO_HI16 49 R_TILEGX_MT_IMM14_X1 28 R_AARCH64_TLSLE_ADD_TPREL_LO12 550 R_SH_DIR8W 8 NT_LOONGARCH_LSX 0xa02 R_PPC64_SECTOFF R_PPC_SECTOFF EF_ARC_MACH_MSK 0x000000ff DT_PPC64_OPD (DT_LOPROC + 1) R_PPC64_TOC16_DS 63 SHF_ALPHA_GPREL 0x10000000 EM_S370 9 SHT_MIPS_OPTIONS 0x7000000d R_386_PLT32 4 OEX_DISMISS 0x80000 R_386_TLS_IE 15 R_TILEPRO_IMM16_X0_TLS_GD 66 R_RISCV_CALL 18 EM_LOONGARCH 258 first_read DT_TLSDESC_PLT 0x6ffffef6 R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 R_SH_COPY 162 R_TILEGX_IMM16_X1_HW0_TLS_IE 93 NT_S390_GS_CB 0x30b R_LARCH_TLS_IE64_HI12 94 R_PPC64_TOC 51 R_ALPHA_JMP_SLOT 26 R_PPC64_TPREL16_HIGHA 113 E_MIPS_ARCH_4 EF_MIPS_ARCH_4 R_390_PLT64 25 SHT_MIPS_TRANSLATE 0x70000022 AT_FLAGS 8 R_LARCH_SOP_NOT 31 R_NIOS2_RELATIVE 39 R_PPC_GOT_TLSLD16_LO 84 R_ARM_SBREL32 9 R_LARCH_PCALA_LO12 72 R_MIPS_TLS_TPREL_LO16 50 SHT_DYNSYM 11 NT_RISCV_CSR 0x900 R_TILEPRO_MMEND_X1 50 R_MIPS16_TLS_GD 106 GNU_PROPERTY_UINT32_OR_HI 0xb000ffff R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 R_ALPHA_BRADDR 7 ODK_FILL 5 R_IA64_LTOFF_DTPMOD22 0xaa R_TILEPRO_IMM16_X1_TLS_GD_HI 71 R_PARISC_DIR17F 4 R_PPC_PLTREL24 18 R_PARISC_TPREL16DF 223 R_METAG_HIOG 13 EM_386 3 EM_DXP 112 R_390_GOT32 7 DF_1_DISPRELDNE 0x00008000 R_IA64_GPREL22 0x2a R_TILEPRO_IMM16_X1_TLS_IE_HA 81 ET_NUM 5 R_AARCH64_MOVW_GOTOFF_G1 302 ELF_NOTE_PAGESIZE_HINT 1 DF_1_TRANS 0x00000200 R_MICROBLAZE_TLSDTPREL32 26 NT_S390_LAST_BREAK 0x306 SHT_MIPS_ABIFLAGS 0x7000002a R_SPARC_RELATIVE 22 AT_UID 11 DT_IA_64_NUM 1 R_ARM_PC24 1 SHT_MIPS_PACKSYM 0x70000008 R_ARM_TARGET2 41 SYMINFO_FLG_LAZYLOAD 0x0008 R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 SHT_MIPS_OPTSYM 0x70000017 R_RISCV_SUB8 37 DT_MIPS_CONFLICT 0x70000008 ELF32_R_SYM(val) ((val) >> 8) PT_HP_CORE_VERSION (PT_LOOS + 0x2) PT_LOOS 0x60000000 SHF_MIPS_NODUPE 0x01000000 R_SH_TLS_LE_32 148 R_PARISC_PCREL14WR 75 R_NIOS2_GNU_VTINHERIT 16 PT_LOPROC 0x70000000 EF_MIPS_NOREORDER 1 R_TILEPRO_IMM16_X0_TLS_GD_LO 68 R_CKCORE_GOT_LO16 32 EM_COGE 216 R_NIOS2_BFD_RELOC_8 14 R_CKCORE_PLT_LO16 35 R_TILEGX_TLS_DTPOFF32 110 EI_OSABI 7 DT_X86_64_PLTENT (DT_LOPROC + 3) DF_1_ENDFILTEE 0x00004000 VER_NDX_LORESERVE 0xff00 SHN_LOPROC 0xff00 DF_1_NODEFLIB 0x00000800 R_PARISC_TLS_LDO21L 240 ET_HIOS 0xfeff R_ARM_GOT32 26 R_ARM_GLOB_DAT 21 R_SH_RELATIVE 165 R_PPC_DTPMOD32 68 LITUSE_ALPHA_BYTOFF 2 R_CKCORE_RELATIVE 9 R_M32R_RELATIVE 53 ELF_NOTE_GNU "GNU" R_SPARC_GNU_VTINHERIT 250 R_390_TLS_LDM32 45 R_PARISC_LTOFF_FPTR64 120 R_ARM_LDC_SB_G2 83 R_NDS32_COPY 39 R_PARISC_LTOFF_FPTR16DF 127 R_CKCORE_TOFFSET_LO16 41 DF_1_CONFALT 0x00002000 isalpha(c) ((__ismask(c)&(_U|_L)) != 0) R_386_SIZE32 38 R_TILEPRO_TLS_DTPOFF32 83 R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 R_68K_PLT8O 18 ET_LOOS 0xfe00 R_PARISC_PLTOFF16WF 118 R_AARCH64_MOVW_SABS_G2 272 ET_HIPROC 0xffff SHN_LOOS 0xff20 DT_SYMTAB 6 R_CKCORE_PCREL_IMM18BY2 43 R_LARCH_ADD64 51 R_MIPS_PC19_S2 63 NT_PPC_TM_CGPR 0x108 NT_LOONGARCH_CSR 0xa01 PT_HP_CORE_STACK (PT_LOOS + 0x7) R_ARC_W 0x1A R_390_TLS_GOTIE32 43 PT_HP_STACK (PT_LOOS + 0x14) R_X86_64_PC64 24 R_390_TLS_GDCALL 38 DF_1_NOHDR 0x00100000 R_390_PC16DBL 17 R_OR1K_GOTOFF_LO16 17 GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0) EM_CSKY 252 R_LARCH_SOP_PUSH_TLS_GD 28 R_MIPS_NONE 0 SHT_ALPHA_REGINFO 0x70000002 R_ARM_REL32 3 R_390_TLS_IE64 48 R_390_TLS_GOTIE20 60 R_SPARC_GOT13 14 R_TILEPRO_NUM 130 R_ARC_RELATIVE 0x38 EF_MIPS_MACH_GS464 0x00A20000 R_ARC_SECTOFF_ME 0x1D R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 R_ARC_SDA16_ST2 0x30 R_AARCH64_TLSDESC_LDR 567 SYMINFO_NUM 2 R_MIPS16_TLS_DTPREL_LO16 109 DT_X86_64_PLTSZ (DT_LOPROC + 1) PT_MIPS_ABIFLAGS 0x70000003 R_ARM_NUM 256 STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT) __STDC_VERSION__ 201112L R_SPARC_7 43 R_ARM_THM_JUMP19 51 R_PARISC_LTOFF_FPTR16F 125 EF_ARM_BE8 0x00800000 DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) R_PARISC_LTOFF_FPTR14DR 124 R_SPARC_UA16 55 R_PPC64_DTPREL16_HI 76 DT_MIPS_PERF_SUFFIX 0x7000002e EF_ARM_RELEXEC 0x01 R_390_PLTOFF16 34 R_MICROMIPS_PC10_S1 140 R_IA64_TPREL22 0x92 R_LARCH_SUB6 106 R_ARC_SDA_LDST2 0x15 R_IA64_DIR32MSB 0x24 R_IA64_GPREL64I 0x2b EM_MIPS_X 51 STT_HP_STUB (STT_LOOS + 0x2) R_NIOS2_CJMP 19 R_X86_64_GLOB_DAT 6 R_AARCH64_MOVW_SABS_G0 270 R_PPC64_TLS 67 EM_KVARC 214 R_LARCH_TLS_DTPREL32 8 EM_EMX8 213 R_390_GOTPC 14 EF_SPARC_LEDATA 0x800000 EM_COREA_1ST 193 R_SPARC_GLOB_JMP 42 isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) STO_RISCV_VARIANT_CC 0x80 NT_PPC_HASHKEYR 0x112 R_ARM_MOVT_ABS 44 ELF_NOTE_OS_SOLARIS2 2 ELFMAG2 'L' RHF_DELTA_C_PLUS_PLUS (1 << 6) R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 95 EM_860 7 DT_FLAGS 30 ELFOSABI_ARM_AEABI 64 EF_LARCH_OBJABI_V1 0x40 R_MICROMIPS_GPREL7_S2 172 R_AARCH64_MOVW_GOTOFF_G2 304 R_SPARC_PC_HM10 38 SYMINFO_FLG_COPY 0x0004 EM_RISCV 243 DT_MIPS_BASE_ADDRESS 0x70000006 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 R_PPC64_ADDR16_HIGHA 111 SYMINFO_BT_PARENT 0xfffe R_NIOS2_BFD_RELOC_16 13 R_SPARC_13 11 R_PARISC_NONE 0 R_CKCORE_ADDR_HI16 24 R_CRIS_GNU_VTENTRY 8 R_68K_PLT16O 17 R_TILEGX_IMM8_Y0 24 R_PPC64_DTPREL16_HIGHER 103 DF_1_KMOD 0x10000000 R_MIPS_SHIFT6 17 R_TILEPRO_IMM16_X0_GOT_LO 41 NT_PPC_TM_SPR 0x10c DF_TEXTREL 0x00000004 R_TILEGX_MMEND_X0 31 DT_TEXTREL 22 EM_ME16 59 R_NDS32_NONE 0 EF_MIPS_ARCH_64R2 0x80000000 DT_MIPS_SYMBOL_LIB 0x70000024 R_ALPHA_DTPRELHI 34 R_NIOS2_CACHE_OPX 6 R_68K_PLT32O 16 R_MICROBLAZE_32 1 R_RISCV_GPREL_S 48 R_METAG_TLS_LDM 48 R_IA64_NONE 0x00 DT_AARCH64_BTI_PLT (DT_LOPROC + 1) R_TILEGX_MF_IMM14_X1 29 EF_SH4A_NOFPU 0x11 R_MICROMIPS_26_S1 133 SHN_LORESERVE 0xff00 GNU_PROPERTY_X86_ISA_1_V2 (1U << 1) DT_MIPS_DELTA_CLASS 0x70000017 R_AARCH64_ABS64 257 R_SPARC_32 3 R_PPC_GOT_TLSLD16 83 R_AARCH64_TLSGD_MOVW_G1 515 NT_TASKSTRUCT 4 AT_IGNORE 1 R_AARCH64_MOVW_GOTOFF_G0_NC 301 EF_S390_HIGH_GPRS 0x00000001 R_AARCH64_MOVW_UABS_G1_NC 266 VER_NDX_LOCAL 0 NT_PRFPXREG 20 R_IA64_LDXMOV 0x87 EM_FAKE_ALPHA 41 R_TILEPRO_MMSTART_X1 49 R_CKCORE_GOTPC 14 R_SPARC_WPLT30 18 R_X86_64_RELATIVE 8 ELFCLASS64 2 PT_HIOS 0x6fffffff SYMINFO_FLG_PASSTHRU 0x0002 R_SH_USES 27 R_PPC_EMB_SDA2I16 107 R_MIPS_INSERT_A 25 R_PPC_GOT_TLSLD16_HI 85 R_MN10300_32 1 R_CRIS_8_PCREL 4 EF_SH_MACH_MASK 0x1f DF_1_GROUP 0x00000004 EM_CE 119 EM_D30V 86 R_68K_PC16 5 R_ARM_THM_SWI8 14 ELF32_ST_INFO(bind,type) (((bind) << 4) + ((type) & 0xf)) EM_BLACKFIN 106 R_ARM_GOT_BREL12 97 R_ARM_ABS8 8 R_ARC_32_ME 0x1B R_METAG_REG32OP3 8 R_PPC64_DTPREL16_HIGHA 115 R_PPC64_TPREL16_HIGHER 97 EM_VISIUM 221 EM_H8_300 46 R_ARM_TLS_CALL 91 PT_SUNWSTACK 0x6ffffffb DT_PPC64_NUM 4 R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 SHN_AFTER 0xff01 EM_RS08 132 R_IA64_PCREL64LSB 0x4f ELF32_R_INFO(sym,type) (((sym) << 8) + ((type) & 0xff)) SHT_RELR 19 DTF_1_CONFEXP 0x00000002 DT_RPATH 15 DT_RELASZ 8 R_PPC64_GOT_TPREL16_LO_DS 88 R_LARCH_GOT64_PC_HI12 78 R_PPC64_ADDR24 R_PPC_ADDR24 R_TILEGX_IMM16_X0_HW0_TLS_IE 92 R_IA64_REL64LSB 0x6f R_ARC_SDA32_ME 0x1E R_NIOS2_BFD_RELOC_32 12 R_390_TLS_LOAD 37 R_X86_64_SIZE32 32 R_SPARC_PC_HH22 37 ELF64_M_INFO(sym,size) ELF32_M_INFO (sym, size) R_TILEGX_MMSTART_X0 30 _S 0x20 R_PARISC_PCREL16DF 79 EM_CR16 177 SHT_MIPS_RFDESC 0x7000001a R_PARISC_GPREL14WR 91 R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 R_MIPS_TLS_LDM 43 DT_MIPS_MSYM 0x70000007 R_TILEGX_IMM16_X0_HW3 42 R_PARISC_GNU_VTENTRY 232 R_68K_TLS_GD16 26 R_PPC_SECTOFF_HA 36 R_AARCH64_TLSGD_ADR_PAGE21 513 R_RISCV_TLS_TPREL32 10 STT_HP_OPAQUE (STT_LOOS + 0x1) R_PPC_TLSLD 96 R_PPC64_GOT_DTPREL16_DS 91 AT_PHENT 4 R_IA64_IMM22 0x22 ELFOSABI_SYSV 0 R_PARISC_PCREL32 9 R_AARCH64_TLS_TPREL 1030 R_CKCORE_GOT12 30 R_PPC64_PLTGOT16_DS 65 PT_GNU_SFRAME 0x6474e554 R_METAG_HI16_GOTPC 36 EF_SH4AL_DSP 0x6 DT_MIPS_HIDDEN_GOTIDX 0x70000027 PF_HP_MODIFY 0x02000000 R_MIPS16_TLS_GOTTPREL 110 R_LARCH_GNU_VTINHERIT 57 R_PARISC_LTOFF_TP14F 167 R_TILEGX_HW1 10 R_SPARC_REV32 252 R_X86_64_TLSLD 20 R_TILEPRO_TLS_IE_LOAD 65 R_PPC_GOT_TLSGD16_LO 80 R_IA64_LTOFF64I 0x33 R_ARM_JUMP24 29 DT_STRSZ 10 R_PPC64_GLOB_DAT R_PPC_GLOB_DAT R_AARCH64_P32_TLSDESC 187 R_SH_TLS_TPOFF32 151 R_AARCH64_P32_ABS32 1 R_ARC_SDA_LDST 0x13 R_MN10300_TLS_GD 24 R_LARCH_ADD24 49 STB_NUM 3 R_PPC_GOT_DTPREL16_HA 94 R_390_TLS_LDM64 46 R_TILEGX_SHAMT_X1 33 R_ARC_8 0x1 R_PPC64_NONE R_PPC_NONE STT_HIOS 12 EF_MIPS_MACH_4010 0x00820000 R_MICROBLAZE_32_PCREL_LO 4 R_LARCH_ABS64_LO20 69 R_IA64_IPLTMSB 0x80 R_RISCV_32_PCREL 57 EF_MIPS_NAN2008 1024 R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 R_AARCH64_ADR_GOT_PAGE 311 R_PPC64_TPREL16_HIGHEST 99 NT_LWPSINFO 17 R_PPC_EMB_BIT_FLD 115 EM_JAVELIN 77 R_TILEGX_IMM8_Y1_TLS_ADD 121 R_MN10300_GOT24 18 AT_SYSINFO_EHDR 33 R_IA64_PCREL21BI 0x79 R_386_PC32 2 SHT_NUM 20 R_PPC_REL32 26 R_OR1K_GOTPC_LO16 13 R_386_TLS_GOTIE 16 R_PARISC_SEGREL64 112 R_M32R_LO16_RELA 41 R_NIOS2_IMM5 5 R_CKCORE_PLT32 16 SHT_MIPS_RELD 0x70000009 R_TILEGX_TLS_DTPOFF64 107 R_NDS32_RELATIVE 42 R_METAG_RELATIVE 45 OHW_R5KCVTL 0x8 GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002 NT_ARM_PAC_ENABLED_KEYS 0x40a AT_HWCAP3 29 DTF_1_PARINIT 0x00000001 R_ALPHA_TLSGD 29 R_ARM_THM_PC12 54 R_PARISC_PLTOFF14DR 116 R_NIOS2_CALL_LO 44 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 SHF_MERGE (1 << 4) NT_S390_CTRS 0x304 process_symbol R_SH_DIR32 1 R_OR1K_TLS_LDO_HI16 26 R_M32R_24_RELA 35 DT_MOVETAB 0x6ffffefe R_LARCH_TLS_GD_HI20 98 R_ARM_GOT_PREL 96 R_AARCH64_LD64_GOTOFF_LO15 310 R_M32R_16 1 SHT_PROGBITS 1 R_MN10300_TLS_DTPMOD 30 SHT_IA_64_UNWIND (SHT_LOPROC + 1) R_OR1K_8 3 NT_MIPS_FP_MODE 0x801 R_TILEPRO_IMM16_X0_TLS_IE 74 SHN_MIPS_SCOMMON 0xff03 R_OR1K_GNU_VTINHERIT 8 R_ARC_32 0x4 GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0) EM_MOXIE 223 R_ARC_TLS_IE_GOT 0x48 R_SPARC_TLS_LE_LOX10 73 GNU_PROPERTY_UINT32_OR_LO 0xb0008000 R_390_GOTOFF16 27 R_ARC_SECTOFF 0xD DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 SHT_PARISC_UNWIND 0x70000001 R_SPARC_SIZE32 86 STB_LOPROC 13 EF_MIPS_MACH_4120 0x00870000 R_ARC_N32_ME 0x1C R_68K_TLS_LDM32 28 R_TILEPRO_IMM16_X1_HA_PCREL 38 R_X86_64_8 14 R_TILEGX_IMM16_X0_HW1_PCREL 52 R_SH_GOT32 160 R_MN10300_TLS_IE 28 R_ALPHA_LITERAL 4 R_PARISC_PCREL16WF 78 DT_AARCH64_NUM 6 PT_SUNWBSS 0x6ffffffa R_PARISC_DIR21L 2 EM_CYPRESS_M8C 161 EF_SPARC_SUN_US3 0x000800 R_PARISC_FPTR64 64 R_SPARC_TLS_LE_HIX22 72 R_ALPHA_GOTDTPREL 32 ELF_NOTE_FDO "FDO" EM_MCST_ELBRUS 175 R_MICROBLAZE_REL 16 DF_1_NOKSYMS 0x00080000 R_PARISC_PLTOFF14WR 115 R_MIPS_PCHI16 64 R_TILEGX_IMM16_X0_HW3_PCREL 56 EF_SH1 0x1 R_TILEPRO_SHAMT_X1 52 R_TILEPRO_16 2 R_MICROBLAZE_PLT_64 15 DF_1_STUB 0x04000000 R_TILEGX_HW0_LAST 13 R_ARM_LDRS_SB_G0 78 NT_S390_TODPREG 0x303 R_TILEPRO_IMM16_X1_GOT_HI 44 R_PPC64_ADDR16_LO R_PPC_ADDR16_LO R_LARCH_SOP_PUSH_GPREL 25 R_LARCH_SUB64 56 NT_S390_VXRS_HIGH 0x30a RHF_NONE 0 R_SPARC_10 30 R_X86_64_16 12 R_LARCH_COPY 4 R_AARCH64_TLSLE_MOVW_TPREL_G0 547 DT_NEEDED 1 SHF_MASKOS 0x0ff00000 NT_ARM_VFP 0x400 MIPS_AFL_ASE_MDMX 0x00000010 EM_NDR1 57 nr_jited_func_lens extra_kconfig BPF_FUNC_csum_update map_btf_datasec_resize bpf_object__section_to_libbpf_map_type FEAT_EXP_ATTACH_TYPE orig_val kern_type PERF_RECORD_NAMESPACES bpf_map__get_next_key BPF_LINK_TYPE_CGROUP btf_func_linkage bpf_object__kversion btf_custom_path targ_var_name mark_btf_static nr_func_info sec_def_flags bpf_core_equal_fn attach_btf_obj_id bpf_perf_event_opts PERF_RECORD_BPF_EVENT BPF_FUNC_perf_event_read_value BPF_FUNC_skb_change_tail ELF_T_SWORD LIBBPF_ERRNO__FORMAT relo_idx bpf_object__sanitize_maps has_func PROBE_ATTACH_MODE_PERF bpf_object__load BPF_LINK_TYPE_TCX nelems max_last_line_cnt rlim_cur prog_attach_fn BPF_F_PRESERVE_ELEMS PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT bpf_map_update_elem BPF_CGROUP_DEVICE Elf_Scn sh_flags BPF_FUNC_get_route_realm data_start bpf_map PROBE_ATTACH_MODE_LEGACY sh_type BPF_FUNC_skb_get_tunnel_opt BPF_MAP_TYPE_RINGBUF feature_probe_fn available_functions_file bpf_map__btf_value_type_id has_type_tag forward FEAT_GLOBAL_DATA bpf_program__log_level SEC_ATTACHABLE_OPT BPF_FUNC_skb_cgroup_id libbpf_set_print BPF_FUNC_inode_storage_get __builtin_memcpy BPF_FUNC_skb_output LIBBPF_ERRNO__NLPARSE bpf_core_relo bpf_object__next_program link_ids BPF_MAP_TYPE_HASH PERF_SAMPLE_ADDR BPF_FUNC_unspec BPF_F_CLONE BPF_FUNC_skb_vlan_push BPF_MAP_TYPE_DEVMAP elf64_getehdr new_insns BPF_LIRC_MODE2 nr_types legacy_probe error_ BPF_F_MMAPABLE BPF_FUNC_sock_from_file BPF_FUNC_override_return LIBBPF_ERRNO__KVER find_prog_by_sec_insn attempts fcntl64 bpf_map_freeze bpf_map__set_ifindex cpu_bufs subprog_name fail_memsz_adjust st_name perf_event_type BPF_CORE_TYPE_EXISTS BPF_MAP_TYPE_QUEUE init_slots new_prog_info usdt_manager_attach_usdt ELF_C_NULL BPF_FUNC_get_branch_snapshot core_relo_len btf__add_func btf_is_enum64 kfunc_name ensure_good_fd tp_cat st_ops retry_load prog_ids ERR_PTR mmap_new_sz find_elf_var_sym bpf_get_map_info_from_fdinfo new_map_fd Elf_Data libbpf_prog_handler_opts BTF_KIND_ENUM BPF_FUNC_map_push_elem PERF_TYPE_SOFTWARE BPF_FUNC_csum_diff set_kcfg_value_num new_array_id bpf_link__fd ext_segs prog_sz bpf_map__value_size elf_sym_by_idx PERF_SAMPLE_PERIOD cmp_progs BPF_FUNC_sk_release PERF_SAMPLE_REGS_INTR btf__add_func_param dummy_var_btf_id BPF_LINK_TYPE_PERF_EVENT SEC_ATTACHABLE ELF_C_READ btf__type_by_id btf_member_bitfield_size BTF_KIND_ARRAY perf_buffer bpf_object__open_file BPF_FUNC_skb_vlan_pop BPF_CGROUP_GETSOCKOPT PERF_TYPE_BREAKPOINT new_prog_fd var_skel_sz errout elf_sym_str reloc_type raw_len gzFile_s bpf_program__set_log_level bpf_map__set_key_size PERF_COUNT_SW_CPU_CLOCK run_cnt bpf_object__load_skeleton bpf_core_cand hashmap_entry btf_vmlinux_override BPF_TRACE_FENTRY bpf_object__pin_programs PERF_COUNT_SW_PAGE_FAULTS_MAJ ELF_T_HALF elf_sec_name kern_data_off usdt_man kernel_log_buf perf_buffer_event_fn sample_cb local_cand EPOLL_CLOEXEC bpf_map__set_pin_path btf_is_mod btf_is_func_proto FEAT_MODULE_BTF sh_addralign BTF_KIND_PTR is_prog_array page_sz insn_is_pseudo_func BPF_FUNC_get_listener_sock FEAT_UNKNOWN bpf_kprobe_multi_opts ELF_C_RDWR_MMAP BPF_F_STACK_BUILD_ID bpf_core_relo_res probe_kern_btf FEAT_BPF_COOKIE BPF_XDP kfunc_id rlim_t PERF_COUNT_SW_EMULATION_FAULTS kfunc_proto_id BPF_FUNC_for_each_map_elem BPF_FUNC_read_branch_records bpf_gen__prog_load epoll_ctl orig_fn_id map_set_def_max_entries init_struct_ops_maps __rlim64_t PERF_RECORD_SWITCH_CPU_WIDE libbpf_bpf_prog_type_str probe_perf_link elf64_getshdr BPF_FUNC_rc_keydown legacy_is_retprobe str_has_sfx check_path bpf_core_free_cands bpf_object__pin libbpf_print_level elf_ndxscn BPF_FUNC_spin_lock bpf_object__elf_init BPF_LINK_TYPE_RAW_TRACEPOINT find_int_btf_id ELF_T_AUXV prog_setup_fn init_map_in_map_slots query_flags new_val perf_branch_sample_type_shift targ_type_id ___err BPF_FUNC_skc_to_tcp6_sock __read_chk sec_num func_pattern bpf_program__insns bpf_kprobe_opts PERF_TYPE_TRACEPOINT BPF_MAP_TYPE_CGROUP_ARRAY core_relo_rec_size BPF_FUNC_skb_set_tunnel_key HASHMAP_APPEND obj_buf_sz LIBBPF_MAP_BSS avail_kallsyms_data BTF_FUNC_EXTERN BPF_SK_SKB_STREAM_VERDICT FEAT_BTF_GLOBAL_FUNC bpf_gen__populate_outer_map EXT_UNKNOWN usdt_provider sym_addr BPF_LINK_TYPE_NETNS map_skel_sz BPF_CGROUP_INET6_CONNECT LIBBPF_ERRNO__RELOC sym_is_subprog BPF_FUNC_redirect_peer LIBBPF_MAP_RODATA RLIMIT_STACK bpf_object__resolve_ksym_var_btf_id bpf_object__open_subskeleton bpf_object__resolve_ksym_func_btf_id btf_is_enum EPOLLRDBAND bpf_program__unload BPF_FUNC_get_socket_cookie probe_fd BPF_FUNC_set_retval ksym_sec elf_sec_desc bpf_object__relocate_core tmp_name btf_member kern_data_member btf__type_cnt is_inner btf_var_idx EPOLLEXCLUSIVE resolved_path btf_log_level bpf_object PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT RLIMIT_AS EPOLLHUP BPF_FUNC_get_func_ip path_fd out_batch PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT PERF_COUNT_SW_PAGE_FAULTS_MIN e_shentsize PERF_SAMPLE_BRANCH_USER_SHIFT ptr_to_u64 BPF_CORE_TYPE_ID_TARGET find_prev_line targ_btf_name is_weak btf__resolve_type BPF_MAP_TYPE_REUSEPORT_SOCKARRAY bpf_object__next_map is_call_insn str_len libbpf_get_error bpf_object_init_progs bpf_link_create_opts bpf_object__check_endianness nr_maps LIBBPF_STRICT_DIRECT_ERRS bpf_map__set_autocreate libbpf_prepare_prog_load ELF_C_SET data_in BPF_CORE_FIELD_EXISTS bpf_program__type BPF_CGROUP_ITER_SELF_ONLY insn_is_subprog_call ELF_T_NUM btf__load_from_kernel_by_id reloc_desc ELF_T_NHDR libbpf_major_version sec_offset BPF_FUNC_d_path BPF_F_PATH_FD HASHMAP_SET in_batch kallsyms_cb_t pid_fd bpf_object__collect_map_relos bpf_ksyscall_opts expected_revision LIBBPF_ERRNO__LIBELF bpf_core_essential_name_len elf_sec_by_idx BPF_FUNC_xdp_adjust_meta btf_int_encoding target_ifindex epoll_wait PERF_SAMPLE_PHYS_ADDR bpf_core_accessor BPF_FUNC_load_hdr_opt map_type_name BTF_KIND_CONST is_pow_of_2 duration ELF_C_FDDONE btf_kind_core_compat legacy_is_kprobe ELF_T_VDAUX btf_type_by_id private_data elf_nextscn bpf_gen__load_btf exception_cb_idx btf_vmlinux main_btf e_phnum validate_map_op st_ops_shndx RELO_DATA btf_is_type_tag nr_fd_array btf_vlen bpf_prog_bind_map archive_path bpf_core_spec bpf_map__btf_key_type_id BPF_SK_SKB_VERDICT key_sz find_elf_sec_sz btf_ext__free __bpf_program__iter need_vmlinux_btf bpf_program__attach_perf_event_opts PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT BPF_F_WRONLY btf__load_vmlinux_btf Elf64_Off BPF_FUNC_sysctl_get_current_value bpf_link__update_map PERF_COUNT_SW_CGROUP_SWITCHES bpf_program__pin bpf_object__process_kconfig_line e_version Elf64_Section core_relo_cnt BTF_KIND_DECL_TAG PERF_TYPE_MAX prefixes BPF_PROG_TYPE_EXT bpf_object__relocate_data BPF_TCX_INGRESS resolved_offsets TRI_YES RELO_SUBPROG_ADDR find_relo_core __rlimit_resource_t bpf_object__load_progs bpf_link_perf_dealloc ctx_in populate_skeleton_progs BPF_FUNC_probe_read bpf_link__detach patch_sz bpf_program__log_buf elf_rawdata link_fd perf_type_id BPF_CGROUP_UNIX_SENDMSG BPF_CGROUP_INET4_BIND core_relo_info TRI_MODULE target_opts jited_line_info_rec_size btf_var bpf_object_unload bpf_program__fd target_name def_t bpf_link_update probe_kern_arg_ctx_tag bpf_netkit_opts BPF_F_INNER_MAP elf_kind FEAT_SYSCALL_WRAPPER func_info_len btf_is_typedef ctx_out BPF_LINK_TYPE_XDP ELF_C_WRITE BPF_MAP_TYPE_STACK_TRACE ctx_size_out search_paths ext_ptr btf_type_name is_ldimm64_insn kern_mtype ELF_T_REL Elf64_Half BPF_FUNC_store_hdr_opt BPF_FUNC_skb_change_type orig_sz access_str_off libbpf_kallsyms_parse LIBBPF_STRICT_NONE spec_len zip_archive_open __MAX_BPF_REG BPF_FUNC_map_pop_elem open_flags BPF_FUNC_ringbuf_submit bpf_object_open_opts BPF_MAP_TYPE_LRU_HASH __bpf_map__iter determine_kprobe_perf_type bpf_program__attach_uprobe_multi PERF_RECORD_AUX btf__add_decl_tag bpf_program__record_reloc bpf_program__set_ifindex btf__add_int e_ident fd_array_cap bpf_map__numa_node root_type_id bpf_gen__record_relo_core elf_end libbpf_version_string bpf_btf_get_info_by_fd PERF_RECORD_MMAP line_info_len BPF_FUNC_kptr_xchg BPF_MAP_TYPE_UNSPEC e_ehsize PERF_SAMPLE_IDENTIFIER PERF_SAMPLE_MAX st_value find_kernel_btf_id BPF_FUNC_get_current_cgroup_id kernel_needs_btf nr_reloc probe_uprobe_multi_link BPF_FUNC_ringbuf_reserve_dynptr btf__add_struct bpf_object_prepare_struct_ops event_cb MAP_DEF_MAP_EXTRA PERF_RECORD_COMM BPF_MODIFY_RETURN bpf_map_mmap_sz bpf_map_get_next_key MAP_DEF_KEY_SIZE PERF_SAMPLE_WEIGHT sh_link bpf_link_perf MAP_DEF_MAX_ENTRIES LIBBPF_STRICT_NO_OBJECT_LIST ext_idx copy_start btf_log_size feature_probes BPF_FUNC_tcp_check_syncookie bpf_iter_link_info bpf_program__set_flags ELF_T_CHDR btf__add_var SEC_EXP_ATTACH_OPT BPF_FUNC_sysctl_set_new_value bpf_program__attach_tcx pvalue recursion_misses ksym_relo_desc netns_ino BPF_FUNC_redirect_neigh parse_uint_from_file elf_memory btf__str_by_offset BPF_FUNC_set_hash_invalid bpf_object__relocate BPF_FUNC_strtoul has_available_filter_functions_addrs bpf_map_delete_elem_flags resolve_func_ptr __RLIMIT_NICE bpf_tracepoint_opts EPOLLIN BPF_FUNC_skc_to_mptcp_sock bpf_prog_get_info_by_fd BPF_FUNC_xdp_get_buff_len BPF_REG_7 bpf_cgroup_iter_order RLIMIT_CORE ELF_K_NONE libbpf_is_mem_zeroed BPF_FUNC_skb_ecn_set_ce local_t kernel_btf BPF_FUNC_timer_cancel sec_insn_off bpf_program__unpin data_out adjust_prog_btf_ext_info BPF_LINK_TYPE_NETKIT num_cpu remove_uprobe_event_legacy BPF_REG_2 BPF_FUNC_user_ringbuf_drain specs_scratch PERF_COUNT_SW_ALIGNMENT_FAULTS determine_uprobe_perf_type BPF_FUNC_fib_lookup bpf_object__open_skeleton BPF_SK_REUSEPORT_SELECT_OR_MIGRATE fn_name SEC_UNUSED BPF_FUNC_sk_storage_get prog_type_name fixup_log_failed_core_relo lopts BPF_FUNC_sk_redirect_hash TRI_NO perf_buffer__consume cur_key libbpf_prog_setup_fn_t file_name bpf_object__init_maps BPF_FUNC_sk_redirect_map bpf_program__attach_tracepoint cmp_relo_by_insn_idx kern_type_id PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE BPF_REG_0 BPF_REG_1 BPF_REG_3 BPF_REG_4 BPF_REG_5 BPF_REG_6 BPF_REG_8 BPF_REG_9 obj_buf lost_cb btf_log_true_size LIBBPF_ERRNO__ENDIAN bpf_program__flags BPF_PROG_TYPE_KPROBE bpf_program__attach_lsm BPF_FUNC_get_stackid bpf_object__append_subprog_code perf_buffer__free orig_proto_id func_rec sh_name bpf_core_hash_fn btf__add_array hashmap hashmap__free orig_type_id len_secnd kern_mdata BPF_MAP_TYPE_STACK __builtin___strcpy_chk ELF_K_COFF bpf_attach_type PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT BPF_FUNC_task_pt_regs PROBE_ATTACH_MODE_LINK BPF_CGROUP_UDP6_SENDMSG poison_map_ldimm64 perf_event_read_simple BPF_FUNC_task_storage_delete BPF_FUNC_skc_to_tcp_request_sock determine_uprobe_retprobe_bit btf_int_bits PERF_SAMPLE_REGS_USER BPF_CGROUP_INET4_GETPEERNAME Elf64_Xword res_mod_btf nr_line_info elf_strptr has_custom_fallback_def BPF_CGROUP_INET4_CONNECT BPF_MAP_TYPE_INODE_STORAGE BPF_FUNC_strncmp bpf_object__read_kallsyms_file BPF_MAP_TYPE_TASK_STORAGE bpf_program__attach_kprobe_opts BPF_FUNC_get_current_uid_gid targ_essent_len force old_fd SEC_NONE BPF_F_KPROBE_MULTI_RETURN LIBBPF_ERRNO__PROG2BIG PERF_SAMPLE_STACK_USER user_sz bpf_object__free_relocs ELF_K_AR BTF_KIND_INT __uint16_t LIBBPF_ERRNO__VERIFY btf_fixup_datasec BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE BPF_FUNC_sock_hash_update BPF_FUNC_l3_csum_replace bpf_object_init_prog_arrays BPF_FUNC_copy_from_user_task ext_name BPF_CGROUP_INET_INGRESS object_name bpf_prog_assign_exc_cb bpf_object__gen_loader attach_func_name probe_attach_mode PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT perf_buffer__consume_buffer copy_size RELO_LD64 BPF_CORE_TYPE_ID_LOCAL buff PERF_SAMPLE_WEIGHT_STRUCT is_ld64 fixup_log_missing_kfunc_call BPF_FUNC_get_numa_node_id inner_map_name has_debugfs avail_kallsyms_cb rlim_max perf_event_sample_format libbpf_minor_version perf_buffer__buffer_fd st_ops_link_shndx btf_kflag populate_skeleton_maps BTF_VAR_STATIC __xpg_basename btf_data BPF_PROG_TYPE_SYSCALL custom_sec_def_cnt BPF_FUNC_map_delete_elem gen_loader_opts use_debugfs perf_sw_ids hashmap_find reused last_custom_sec_def_handler_id var_skel __read_alias BPF_FUNC_get_current_task validate BPF_FUNC_tcp_gen_syncookie BPF_PROG_TYPE_LWT_OUT fd_array_cnt bpf_program__attach_kprobe PERF_RECORD_ITRACE_START geteuid bpf_program__attach_iter PERF_RECORD_FORK bpf_core_cand_list EXT_KCFG ext_val PERF_RECORD_TEXT_POKE BPF_FUNC_xdp_store_bytes PERF_SAMPLE_BRANCH_ANY_SHIFT find_ksym_btf_id elf_rel_by_idx bpf_map__set_numa_node BPF_CGROUP_ITER_DESCENDANTS_PRE bpf_object__prev_map BPF_FUNC_timer_start BPF_PROG_TYPE_CGROUP_SYSCTL BPF_CORE_FIELD_BYTE_OFFSET libbpf_available_kprobes_parse bpf_object__elf_collect append_subprog_relos zip_archive_close btf__align_of kern_func_off FEAT_SUPPORTED kernel_supports cur_line PERF_RECORD_SWITCH ctx_name btf_member_bit_offset ELF_T_VNAUX kconfig_map_idx link_id BPF_F_NO_PREALLOC kern_mtype_id func_info_cnt tag_id BPF_LINK_TYPE_ITER FEAT_BTF_FUNC map_is_ringbuf targ_start_id btf__raw_data BTF_FUNC_STATIC __compar func_info_rec_size insn_start BPF_FUNC_kallsyms_lookup_name BPF_CGROUP_UNIX_GETPEERNAME BPF_CGROUP_UNIX_CONNECT BPF_FUNC_ringbuf_submit_dynptr libbpf_validate_opts __RLIMIT_RSS skip_mods_and_typedefs nr_map_ids bpf_link_struct_ops cpu_cnt ELF_T_SYMINFO fixup_verifier_log btf_module_cap __bpf_core_types_are_compat bpf_link__open RLIMIT_NOFILE sh_size btf_vmlinux_value_type_id BPF_FUNC_sk_assign __MAX_BPF_LINK_TYPE libbpf_err_errno BPF_PROG_TYPE_SK_REUSEPORT find_extern_btf_id __RLIMIT_NPROC btf_kind LIBBPF_INFO line_info_cnt BPF_MAP_TYPE_DEVMAP_HASH create_placeholder_fd perf_buffer__open_cpu_buf build_map_pin_path elf_find_func_offset_from_archive bpf_gen__record_attach_target elf_find_func_offset bpf_insn BPF_FUNC_map_update_elem BPF_FUNC_ktime_get_coarse_ns BPF_FUNC_current_task_under_cgroup BPF_MAP_TYPE_ARRAY probe_kern_btf_datasec bpf_object__set_kversion __RLIMIT_OFILE err_unpin_programs BPF_FUNC_skb_set_tunnel_opt BPF_FUNC_sk_ancestor_cgroup_id BPF_FUNC_bind PROBE_ATTACH_MODE_DEFAULT bpf_object__create_map BPF_PROG_TYPE_UNSPEC BPF_FUNC_per_cpu_ptr RELO_CALL BPF_FUNC_skc_to_unix_sock bpf_core_relo_kind BPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED bit_sz log_sz libbpf_num_possible_cpus FEAT_ARRAY_MMAP target_btf_path elf_sec_hdr LIBBPF_STRICT_SEC_NAME BPF_TRACE_KPROBE_MULTI ELF_C_READ_MMAP_PRIVATE probe_kern_array_mmap EPOLL_EVENTS bpf_program__set_type BPF_CORE_ENUMVAL_VALUE init_prog_array_slots libbpf_needs_btf bpf_map__initial_value PERF_SAMPLE_BRANCH_COND_SHIFT hashmap_hash_fn BPF_PROG_TYPE_SK_MSG libbpf_find_attach_btf_id has_func_global map_fill_btf_type_info IS_ERR_OR_NULL bpf_func_id usdt_cookie BPF_FUNC_skb_change_proto BPF_FUNC_skb_set_tstamp bpf_core_find_cands bpf_core_patch_insn usdt_manager bpf_program__attach_usdt tracefs_kprobe_events BPF_PROG_TYPE_SCHED_ACT err_clean_legacy bpf_object__find_program_by_name BPF_FUNC_xdp_adjust_head LIBBPF_WARN libbpf_find_prog_btf_id ELF_T_VNEED BPF_PROG_TYPE_LWT_XMIT bpf_map_lookup_and_delete_elem_flags ELF_T_LIB ksys_pfx bpf_map__map_extra Elf_Kind PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT ehdr_size __btf_kind_str ELF_T_MOVE fcpu is_signed bpf_object__add_map BPF_FUNC_trace_printk epoll_create1 new_cands BPF_FUNC_spin_unlock link_opts attach_name __builtin___memset_chk target_btf_id LIBBPF_STRICT_CLEAN_PTRS BPF_FUNC_get_current_pid_tgid bpf_link__unpin BPF_FUNC_l4_csum_replace nr_programs BTF_FUNC_GLOBAL len_first mname BPF_FUNC_probe_read_kernel bpf_map__attach_struct_ops BTF_KIND_STRUCT FEAT_BTF_DATASEC patch_log relaxed_maps perf_sample_lost ELF_C_CLR FEAT_BTF_ENUM64 BPF_FUNC_seq_printf_btf prog_attach_flags BPF_FUNC_sk_lookup_udp BPF_PROG_TYPE_XDP bpf_raw_tracepoint_open btf_mandatory bpf_object__unpin_programs targ_btf bpf_prog_info bpf_sec_def netns_dev bpf_object__init_kern_struct_ops_maps __RLIMIT_RTTIME perf_buffer_lost_fn BPF_TRACE_ITER bpf_program__attach_tracepoint_opts bpf_object__add_programs PERF_RECORD_READ bpf_object__resolve_ksyms_btf_id BTF_KIND_UNION BPF_FUNC_bprm_opts_set bpf_map__reuse_fd bpf_map__map_flags BPF_XDP_CPUMAP bpf_gen__map_create bpf_program_fixup_func_info libbpf_strlcpy ELF_T_RELA SEC_USDT bpf_link__disconnect st_ops_data map_ifindex bpf_object__reuse_map elf_getshdrstrndx bump_rlimit_memlock btf__find_by_name_kind bpf_trace_opts BPF_FUNC_ringbuf_discard ELF_T_GNUHASH EPOLLRDNORM BPF_F_ZERO_SEED new_insn_cnt bpf_tcx_opts elf_version BPF_MAP_TYPE_CGRP_STORAGE bpf_map__inner_map BPF_FUNC_get_current_ancestor_cgroup_id bpf_object__init_kversion KCFG_INT fn_proto_id line3 bpf_object__read_kconfig_mem BPF_FUNC_timer_init local_type bpf_program__attach_uprobe EPOLLERR BPF_FUNC_xdp_output BPF_FUNC_snprintf_btf BPF_F_WRONLY_PROG HASHMAP_ADD FEAT_UPROBE_MULTI_LINK bpf_object__unpin bpf_func_info_min bpf_program__attach_freplace bpf_object__sanitize_btf Elf_Cmd __RLIMIT_RTPRIO BPF_CGROUP_INET_SOCK_CREATE RELO_CORE find_kcfg_type BPF_CGROUP_SYSCTL BPF_F_RDONLY BTF_KIND_UNKN BPF_FUNC_ringbuf_query BPF_PROG_TYPE_CGROUP_SKB PERF_SAMPLE_BRANCH_CALL_SHIFT cookies file_flags BPF_FUNC_send_signal_thread bpf_map__key_size rec_end BPF_FUNC_btf_find_by_name_kind btf_module_cnt BPF_MAP_TYPE_SK_STORAGE libbpf_errno cleanup_label fixup_offsets BPF_FUNC_dynptr_write find_prog_insn_relo bpf_object__probe_loading LIBBPF_PIN_NONE targ_res nr_jited_line_info BPF_PROG_TYPE_PERF_EVENT BPF_CGROUP_UDP4_SENDMSG bpf_core_is_flavor_sep e_machine __LIBBPF_ERRNO__START prog_rec_cnt nodename bpf_program__insn_cnt insns_sz bpf_map__name ELF_T_RELR IS_ERR bpf_link__pin_path insns_cnt sort_vars BPF_FUNC_get_netns_cookie append_to_file bpf_object__attach_skeleton LIBBPF_STRICT_AUTO_RLIMIT_MEMLOCK log_buf_size sanitize_pin_path btf_is_void EPOLLPRI clone_func_btf_info bpf_map__destroy BTF_KIND_VAR btf_ext_info_sec map_is_mmapable page_cnt LIBBPF_ERRNO__INTERNAL force_ioctl_attach sec_name_off BPF_FUNC_redirect st_other SEC_DATA BPF_LINK_TYPE_KPROBE_MULTI usdt_name PERF_SAMPLE_TIME BPF_FUNC_tcp_raw_gen_syncookie_ipv4 BPF_FUNC_tcp_raw_gen_syncookie_ipv6 mask_sz libbpf__load_raw_btf BPF_FUNC_perf_event_output err_unpin_maps bpf_map__lookup_elem btf__set_fd MAP_DEF_VALUE_TYPE cached_result feof kernel_log_size BPF_PROG_TYPE_CGROUP_SOCK libbpf_get_type_names BPF_FUNC_skb_change_head btf_is_decl_tag LIBBPF_PIN_BY_NAME num_info nr_extern bpf_link__detach_struct_ops faccessat BPF_FUNC_sk_select_reuseport bpf_perf_event_print_t local_type_id bpf_link__destroy bpf_iter_attach_opts bpf_object__btf prog_rec_sz Elf64_Sym PERF_COUNT_SW_CPU_MIGRATIONS PERF_TYPE_HARDWARE st_info off_adj bpf_program__attach_perf_event BPF_LINK_TYPE_NETFILTER bpf_object__init_btf sh_addr bpf_map__lookup_and_delete_elem BPF_MAP_TYPE_XSKMAP libbpf_available_kallsyms_parse BPF_CGROUP_SETSOCKOPT bpf_object__load_vmlinux_btf kernel_log_level maps_cap bpf_map__is_pinned bpf_uprobe_multi_opts kern_member_idx libbpf_find_vmlinux_btf_id BPF_FUNC_rc_repeat determine_kprobe_perf_type_legacy kern_member load_module_btfs BPF_MAP_TYPE_USER_RINGBUF BPF_CGROUP_UNIX_RECVMSG gzgets FEAT_PROG_BIND_MAP bpf_map__set_map_extra BPF_FUNC_msg_cork_bytes SEC_RODATA bpf_obj_pin buf_idx BPF_CORE_TYPE_SIZE BPF_SK_LOOKUP bpf_link__pin BPF_FUNC_getsockopt BPF_FUNC_sock_ops_cb_flags_set ELF_C_NUM next_line BPF_SK_REUSEPORT_SELECT bpf_map__set_value_size st_ops_link BPF_TRACE_UPROBE_MULTI kern_feature_id raw_spec kcfg_data btf_maps_sec_btf_id bpf_object__elf_finish BPF_CGROUP_INET6_POST_BIND BPF_FUNC_lwt_seg6_store_bytes BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED PERF_RECORD_UNTHROTTLE BPF_FUNC_seq_printf map_info_len probe_memcg_account MAP_DEF_KEY_TYPE BPF_FUNC_msg_pop_data __FEAT_CNT BTF_KIND_VOLATILE bpf_map__fd init_slots_sz BPF_CORE_FIELD_BYTE_SIZE fd_array_idx btf_size bpf_object__btf_fd bpf_program__attach_trace_opts BTF_KIND_FUNC bpf_object__collect_relos arch_specific_lib_paths bpf_gen__map_update_elem BPF_FUNC_msg_pull_data extern_desc PERF_SAMPLE_DATA_SRC kprobe_multi_resolve BPF_FUNC_this_cpu_ptr BPF_CORE_FIELD_RSHIFT_U64 btf_fd_idx __RLIMIT_MEMLOCK bpf_map__is_struct_ops __uint32_t BPF_FUNC_timer_set_callback PERF_SAMPLE_BRANCH_COUNTERS_SHIFT iter_info_len btf_params enum64_placeholder_id replace_bpf_fd MAP_DEF_ALL legacy_probe_name nr_elements BTF_KIND_MAX pinning BPF_FUNC_perf_event_read targ_type bpf_map_prepare_vdata map_cnt BPF_CGROUP_ITER_ORDER_UNSPEC SEC_SLEEPABLE bpf_object_init_struct_ops BPF_FUNC_seq_write nr_jited_ksyms bpf_object_open section_have_execinstr BPF_FUNC_perf_prog_read_value probe_kern_global_data BPF_FUNC_ima_inode_hash FEAT_BTF parse_cpu_mask_file perf_event_open_tracepoint bpf_obj_get bpf_map__init_kern_struct_ops BPF_CGROUP_INET6_GETPEERNAME new_fd BPF_CGROUP_INET4_GETSOCKNAME bpf_link_detach LIBBPF_ERRNO__LOAD perf_buffer__buffer bpf_program__set_insns perf_event_fd bpf_uprobe_opts fgets pin_root_path ELF_T_WORD attach_type_name btf_modules find_struct_ops_kern_types getpid BPF_F_UPROBE_MULTI_RETURN compression sec_cnt bpf_program__autoattach bpf_object__collect_prog_relos ELF_T_OFF NR_BTF_KINDS e_shoff PERF_RECORD_EXIT __read_chk_warn extra_log_level BPF_PROG_TYPE_SCHED_CLS resolve_full_path zip_entry bpf_object__relocate_calls e_shstrndx nr_syms data_size_out ref_ctr_off rec_idx BPF_FUNC_skb_load_bytes find_extern_by_name HASHMAP_UPDATE sym_off map_keys next_path BPF_FUNC_jiffies64 sanitize btf_modules_loaded ELF_T_PHDR btf_is_int btf_var_linkage_str attach_tp perf_event_open_probe BPF_FUNC_sysctl_get_name epoll_data bpf_object__prev_program BPF_FUNC_skb_cgroup_classid epoll_data_t have custom_sec_defs probe_kern_btf_func_global map_uses_real_name e_phoff probe_prog_bind_map __builtin___sprintf_chk PERF_SAMPLE_BRANCH_IN_TX_SHIFT kern_vtype probe_kern_prog_name mmap64 sub_insn_idx BPF_FUNC_dynptr_from_mem find_member_by_offset btf_var_secinfos perf_event_uprobe_open_legacy bpf_object__init_license BPF_FUNC_tcp_send_ack pe_opts spec_buf perf_buffer_sample_fn bpf_program__attach_cgroup BPF_FUNC_send_signal attach_bpf_fd btf_needs_sanitization BPF_CORE_TYPE_MATCHES remove_kprobe_event_legacy BPF_FUNC_sock_map_update ELF_K_ELF bpf_link_create sec_idxs bpf_link__update_program is_typeless BPF_FUNC_sysctl_get_new_value __LIBBPF_STRICT_LAST FEAT_BTF_TYPE_TAG perf_buffer__buffer_cnt BPF_FUNC_tcp_sock BPF_FUNC_probe_write_user PERF_SAMPLE_BRANCH_HV_SHIFT btf_is_func ELF_T_ADDR bpf_program__attach_raw_tracepoint bpf_map__pin BPF_MAP_TYPE_LRU_PERCPU_HASH last_ext bpf_map_skeleton BPF_CGROUP_UDP6_RECVMSG map_needs_vmlinux_btf ksym_name poison_kfunc_call BPF_FUNC_ktime_get_tai_ns bpf_gen__map_freeze BPF_PROG_TYPE_SK_SKB PERF_RECORD_AUX_OUTPUT_HW_ID ELF_K_NUM ctx_size_in BPF_FUNC_get_prandom_u32 LIBBPF_STRICT_ALL BPF_MAP_TYPE_HASH_OF_MAPS kern_data bpf_prog_load_opts BPF_FUNC_get_local_storage BPF_MAP_TYPE_CGROUP_STORAGE BPF_FUNC_sk_storage_delete need_kallsyms targ_btf_path Elf64_Rel BPF_LINK_TYPE_UPROBE_MULTI BPF_NETFILTER e_shnum bpf_struct_ops BPF_FUNC_get_func_ret btf__fd has_float probe_kern_btf_type_tag bpf_btf_get_fd_by_id __fgets_chk bpf_object__init_internal_map libbpf_attach_type_by_name sh_entsize targ_var tp_category __RLIMIT_SIGPENDING link_attach_flags PERF_SAMPLE_ID binary_path BTF_VAR_GLOBAL_ALLOCATED attr_sz ELF_C_FDREAD PERF_RECORD_MAX PERF_SAMPLE_IP PERF_SAMPLE_CGROUP nrels insn_cur __nbytes BPF_PROG_TYPE_SK_LOOKUP BPF_FUNC_get_func_arg __RLIMIT_LOCKS BPF_FUNC_cgrp_storage_get BPF_FUNC_probe_read_user prog_is_subprog new_type_id tmp_fd bpf_program__section_name FEAT_MEMCG_ACCOUNT st_link usdt_manager_new libbpf_prog_type_by_name iter_info element_sz sh_offset archive_sep uname BPF_FUNC_ringbuf_output old_prog_fd MAP_DEF_PINNING bpf_map__set_inner_map_fd ELF_T_SXWORD LIBBPF_PERF_EVENT_DONE parse_u64 bpf_program__attach_ksyscall bpf_program__name BPF_MAP_TYPE_PERF_EVENT_ARRAY BPF_PROG_TYPE_FLOW_DISSECTOR attach_kind attach_raw_tp BPF_MAP_TYPE_PROG_ARRAY ret_type_id PERF_COUNT_SW_PAGE_FAULTS arr_t libbpf_unregister_prog_handler EXT_KSYM local_func_proto_id map_is_created BPF_FUNC_dynptr_data bpf_map__autocreate btf_var_secinfo fn_proto_t bpf_object__create_maps btf__find_by_name_kind_own libbpf_set_strict_mode targ_prog data_size_in add_kprobe_event_legacy BPF_FUNC_task_storage_get bpf_core_resolve_relo BPF_FUNC_get_retval BPF_CGROUP_INET_SOCK_RELEASE SEC_XDP_FRAGS bpf_program__attach_trace scn_data libbpf_tristate FEAT_MISSING prog_flags Elf_Type BPF_FUNC_copy_from_user libbpf_err_ptr xlated_prog_len libbpf_register_prog_handler sysname ignore_elf_section BPF_SK_MSG_VERDICT getrlimit64 bpf_netfilter_opts cleanup bpf_object__pin_maps mmap_size bpf_map__unpin sym_sec_name kver has_decl_tag bpf_ptr_sz LIBBPF_MAP_UNSPEC BTF_VAR_GLOBAL_EXTERN ELF_C_EMPTY SEC_ATTACH_BTF parse_cpu_mask_str SEC_RELO compare_vsi_off btf_get_from_fd bpf_map_info bpf_link_type libbpf_print_fn_t pathname probe_kern_probe_read_kernel make_parent_dir has_datasec BPF_FUNC_tail_call global_ctx_map PTR_ERR BPF_MAP_TYPE_CPUMAP ref_ctr_offsets targ_sec_idx ELF_C_RDWR load_time data_cur BPF_FUNC_get_smp_processor_id elf_getscn core_relo_off BPF_FUNC_csum_level LIBBPF_MAP_KCONFIG BPF_PROG_TYPE_TRACING ext_btf_id EPOLLONESHOT PERF_RECORD_MMAP2 sfx_len BPF_FUNC_lwt_seg6_adjust_srh BPF_FUNC_ktime_get_boot_ns array_type find_member_by_name bpf_map_def glob_match old_errno bpf_link_update_opts bpf_program_attach_fd bpf_link_perf_detach cmp_relocs BPF_FUNC_get_current_task_btf btf__parse tp_name BPF_FUNC_msg_push_data BPF_PROG_TYPE_STRUCT_OPS targ_map datasec_type prog_contains_insn gpl_compatible __libbpf_pr __perf_buffer__new BPF_FUNC_trace_vprintk BPF_MAP_TYPE_SOCKHASH copy_end hashmap_insert_strategy datasec_id BPF_TRACE_RAW_TP bpf_object_subskeleton RLIMIT_DATA btf_is_float poison link_info_len BPF_REG_10 dst_reg arg_idx bpf_program__set_expected_attach_type BPF_TCX_EGRESS tracefs_uprobe_events PERF_SAMPLE_DATA_PAGE_SIZE fixed_fd BPF_FUNC_ktime_get_ns cand_cache btf_array bpf_object__collect_externs local_btf Elf64_Word fill_map_from_def BPF_FUNC_sys_bpf perm LIBBPF_PERF_EVENT_ERROR RLIMIT_CPU zip_archive_find_entry ELF_T_VDEF BPF_FUNC_get_stack PERF_SAMPLE_TRANSACTION KCFG_UNKNOWN bpf_map__pin_path __rlimit_resource PERF_RECORD_SAMPLE bpf_object__collect_st_ops_relos BPF_PERF_EVENT bpf_var_skeleton bpf_object_load_prog __RLIMIT_NLIMITS BPF_NETKIT_PRIMARY bpf_program__set_log_buf BPF_FUNC_snprintf BPF_FUNC_tcp_raw_check_syncookie_ipv4 perf_buffer_params BPF_FUNC_tcp_raw_check_syncookie_ipv6 symbols nr_prog_tags bpf_core_parse_spec batch_size old_print_fn result_sz obj_needs_vmlinux_btf MAP_DEF_MAP_TYPE perf_buffer_opts btf__resolve_size bpf_object__open_mem hdr_len run_time_ns data_length line1 line2 PERF_COUNT_SW_CONTEXT_SWITCHES PERF_TYPE_HW_CACHE libbpf_bpf_attach_type_str perf_buffer__process_records saved_errno BPF_FUNC_skb_get_tunnel_key libbpf_prog_attach_fn_t BPF_F_LINK bpf_program__attach_xdp prog_ifindex BPF_FUNC_cgrp_storage_delete fn_name_off rem_sz PERF_SAMPLE_BRANCH_MAX_SHIFT PERF_SAMPLE_BRANCH_STACK BPF_FUNC_get_current_comm secs BPF_FUNC_sk_fullsock EPOLLWRNORM d_align avail_func_cmp perf_buffer__epoll_fd btf__name_by_offset symbols_shndx PERF_SAMPLE_TID bpf_object__open ELF_T_SHDR BPF_PROG_TYPE_NETFILTER probe_kern_syscall_wrapper elf_begin probe_kern_bpf_cookie local_name prog_skel_sz MAP_DEF_VALUE_SIZE bpf_object__reloc_code KCFG_CHAR bpf_map__set_type BPF_PROG_TYPE_LWT_SEG6LOCAL PERF_SAMPLE_STREAM_ID btf_maps_shndx bpf_program__set_autoload map_id cmp_externs hashmap_insert bpf_link sec_insn_cnt bpf_object__destroy_skeleton BPF_CGROUP_ITER_ANCESTORS_UP PERF_RECORD_LOST BPF_LSM_MAC bpf_program__attach_uprobe_opts BPF_FUNC_dynptr_read kcfg_sec BPF_MAP_TYPE_LPM_TRIE check_value_sz BPF_FUNC_probe_read_user_str PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT bpf_program__exit bpf_gen Elf64_Addr probe_kern_exp_attach_type sh_info BPF_FUNC_ringbuf_discard_dynptr PERF_COUNT_SW_DUMMY main_prog btf_is_ptr bpf_map__set_initial_value kern_version need_config BPF_FUNC_skc_lookup_tcp kern_moff st_shndx BPF_CGROUP_UNIX_GETSOCKNAME BPF_FUNC_skb_adjust_room seg_len bpf_object__detach_skeleton PERF_SAMPLE_READ __MAX_BPF_ATTACH_TYPE res_btf __LIBBPF_ERRNO__END var_extra LIBBPF_ERRNO__KVERSION btf__set_pointer_size perf_buffer__new_raw BTF_KIND_FUNC_PROTO st_ops_link_data libbpf_bpf_map_type_str PERF_RECORD_CGROUP libbpf_print find_btf_by_prefix_kind btf_ext_header PERF_COUNT_SW_MAX elf_state tname FEAT_PERF_LINK ELF_T_XWORD BPF_FUNC_lwt_seg6_action func_infos mmap_old_sz btf_load_into_kernel BTF_KIND_DATASEC BPF_FUNC_sys_close cgroup_fd unlink reloc_prog_func_and_line_info hashmap_equal_fn btf_get_kernel_prefix_kind bpf_usdt_opts bpf_object__find_map_fd_by_name set_kcfg_value_str map_def_parts btf__add_func_proto BPF_XDP_DEVMAP BPF_FUNC_skc_to_udp6_sock BPF_MAP_TYPE_PERCPU_ARRAY BPF_PROG_TYPE_LIRC_MODE2 bpf_object__close BPF_MAP_TYPE_ARRAY_OF_MAPS BPF_FUNC_map_peek_elem find_sec_def BPF_FUNC_ringbuf_reserve BPF_FUNC_ima_file_hash sym_is_extern prog_needs_vmlinux_btf attach_prog_fd get_kernel_version btf_param BTF_KIND_ENUM64 new_cnt is_kcfg_value_in_range relo_sec_name dummy_var BPF_FUNC_xdp_load_bytes __RLIM_NLIMITS kern_feature_desc bpf_prog_bind_opts get_map_field_int parse_btf_map_def BPF_PROG_TYPE_RAW_TRACEPOINT SEC_BSS sec_off EPOLLRDHUP tracefs_available_filter_functions need_func_arg_type_fixup MAP_DEF_INNER_MAP BPF_FLOW_DISSECTOR libbpf_strict_mode determine_kprobe_retprobe_bit libbpf_ensure_mem BPF_NETKIT_PEER libbpf_strerror_r BPF_PROG_TYPE_CGROUP_SOCKOPT insn_data_sz RELO_EXTERN_LD64 bpf_object__init_user_btf_maps elf_sec_str btf_ext__new tp_id perf_buffer__free_cpu_buf BPF_CGROUP_UDP4_RECVMSG __fgets_alias dirname bpf_program__attach_btf_id btf__free BPF_FUNC_skb_ancestor_cgroup_id bpf_gen__free var_type online_cpus_file determine_tracepoint_id obj_name BPF_SK_SKB_STREAM_PARSER local_id BPF_PROG_TYPE_SOCK_OPS perf_buffer_raw_opts probe_module_btf FEAT_PROG_NAME BPF_CGROUP_INET6_BIND link_type_name bpf_map__ifindex bpf_map__max_entries zip_archive BPF_CGROUP_INET4_POST_BIND efile PERF_SAMPLE_AUX bpf_object_load bpf_program_record_relos map_is_reuse_compat BPF_FUNC_msg_redirect_hash pathname_concat internal_map_name BPF_CORE_FIELD_LSHIFT_U64 bpf_object__sanitize_prog out_warn Elf64_Ehdr kern_vtype_id copy_mem bpf_object__read_kconfig_file fixup_log_missing_map_load gzclose component_idx bpf_map__set_map_flags probe_kern_btf_enum64 btf_tmp_path set_kcfg_value_tri sec_def_matches prog_prepare_load_fn EPOLLWRBAND find_struct_ops_map_by_offset bpf_gen__finish bpf_btf_get_next_id bpf_program__set_attach_target jited_prog_insns disconnected elf_getshdrnum BPF_CGROUP_INET6_GETSOCKNAME add_dummy_ksym_var ELF_T_EHDR __BPF_FUNC_MAX_ID prog_cnt BPF_FUNC_check_mtu bpf_object__init_global_data_maps bpf_object__init_prog bpf_map__is_internal PERF_RECORD_KSYMBOL bpf_object__resolve_externs BPF_PROG_TYPE_TRACEPOINT __comparison relative_fd adjust_ringbuf_sz perf_event_kprobe_open_legacy LIBBPF_ERRNO__PROGTYPE PERF_RECORD_THROTTLE gen_kprobe_legacy_event_name host_ptr_sz ksym EPOLLMSG BTF_KIND_TYPE_TAG BPF_MAP_TYPE_SOCKMAP nr_progs BPF_FUNC_get_ns_current_pid_tgid elf_resolve_syms_offsets PERF_COUNT_SW_BPF_OUTPUT memfd_create probe_kern_btf_float BPF_CGROUP_SOCK_OPS bpf_object_skeleton bpf_map_create __s16 probe_type fd_type retried bpf_map_type__is_map_in_map essent_name mmap_mem libbpf_bpf_link_type_str bpf_program__attach_netfilter func_info_off LIBBPF_STRICT_MAP_DEFINITIONS bpf_prog_skeleton tracefs_path BTF_KIND_FLOAT ELF_C_READ_MMAP is_set index_type struct_id map_key BPF_FUNC_sk_cgroup_id BPF_FUNC_get_hash_recalc relative_id epoll_event prog_btf_fd BPF_FUNC_lwt_push_encap BPF_FUNC_map_lookup_percpu_elem BPF_FUNC_loop fmemopen netns_fd d_buf BPF_CGROUP_ITER_DESCENDANTS_POST RELO_EXTERN_CALL xlated_prog_insns FEAT_PROBE_READ_KERN patch str_is_empty BPF_FUNC_sk_lookup_tcp PERF_SAMPLE_CPU is_sec_name_dwarf attach_kprobe_multi bpf_object__populate_internal_map elf_find_func_offset_from_file insn_is_helper_call nr_ksyms bpf_program__set_autoattach jited_prog_len BPF_LINK_TYPE_STRUCT_OPS arch_specific_syscall_pfx mkdir has_subcalls bpf_program__attach_netkit FEAT_BTF_FLOAT BPF_FUNC_strtol line_info_off perf_buffer__poll BPF_CORE_ENUMVAL_EXISTS BPF_F_RDONLY_PROG BPF_PROG_TYPE_CGROUP_SOCK_ADDR strrchr verified_insns has_rodata bpf_program__attach BPF_FUNC_skb_load_bytes_relative Elf64_Shdr BPF_FUNC_msg_apply_bytes targ_name bpf_object__sort_relos BPF_PROG_TYPE_CGROUP_DEVICE BPF_PROG_TYPE_SOCKET_FILTER bpf_map_get_info_by_fd KCFG_TRISTATE btf_is_var BPF_FUNC_skb_get_xfrm_state btf_is_array perf_buffer__process_record PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT BPF_F_NUMA_NODE orig_ids kern_feature_result BTF_KIND_FWD BPF_LINK_TYPE_TRACING BTF_KIND_RESTRICT BPF_FUNC_map_lookup_elem BPF_FUNC_skc_to_tcp_sock sub_insn_off text_shndx kern_msize bpf_program__attach_netns arr_info getrlimit bpf_object__find_map_by_name PERF_SAMPLE_CODE_PAGE_SIZE BPF_CORE_FIELD_SIGNED BPF_FUNC_clone_redirect ELF_T_DYN __key BPF_FUNC_xdp_adjust_tail opts_sz BPF_FUNC_skb_under_cgroup bpf_object_fixup_btf e_phentsize bpf_map_delete_elem PERF_SAMPLE_BRANCH_NO_TX_SHIFT hooknum __vfprintf_chk bpf_program__attach_kprobe_multi_opts bpf_btf_info btf_members BPF_FUNC_skb_pull_data PERF_SAMPLE_BRANCH_IND_CALL_SHIFT BPF_FUNC_redirect_map BPF_FUNC_skc_to_tcp_timewait_sock bpf_object__destroy_subskeleton elf_getdata created_by_uid libbpf_prog_prepare_load_fn_t bpf_object__name find_extern_sec_btf_id sys_bpf_prog_load BPF_FUNC_skb_store_bytes usdt_manager_free ELF_T_SYM PERF_TYPE_RAW perf_cpu_buf kcfg err_free_new_name perf_sample_raw BPF_TRACE_FEXIT PERF_RECORD_LOST_SAMPLES bpf_map_mmap_resize bpf_attr bpf_object__shndx_is_data local_essent_len BPF_MAP_TYPE_BLOOM_FILTER available_path BPF_CGROUP_INET_EGRESS value_end add_uprobe_event_legacy BPF_FUNC_msg_redirect_map KCFG_CHAR_ARR gzFile libbpf_pin_type EPOLLWAKEUP tracefs_available_filter_functions_addrs getpagesize ptr_id LIBBPF_PERF_EVENT_CONT bpf_map__delete_elem elf_sec_data BPF_FUNC_inode_storage_delete utsname MAP_DEF_MAP_FLAGS BPF_PROG_TYPE_LWT_IN probe_kern_btf_func kernel_btf_obj_fd bpf_core_format_spec bpf_object__init_user_btf_map BPF_FUNC_rc_pointer_rel gelf_getclass bpf_object__sanitize_and_load_btf btf__add_ptr btf_is_struct BTF_KIND_TYPEDEF BPF_FUNC_find_vma FEAT_BTF_DECL_TAG LIBBPF_DEBUG BPF_LINK_TYPE_UNSPEC gzopen64 BPF_STRUCT_OPS BPF_FUNC_get_socket_uid libbpf_err bpf_object__shndx_is_maps btf_type insn_data pfx_len BPF_FUNC_get_func_arg_cnt libbpf_reallocarray BPF_FUNC_probe_read_kernel_str __base bpf_object__init_kconfig_map LIBBPF_ERRNO__WRNGPID has_enum64 bpf_perf_event_ret bpf_program__autoload old_map_fd btf_log_buf bpf_map__set_max_entries probe_kern_btf_decl_tag ref_ctr_offset ELF_C_WRITE_MMAP EPOLLOUT BPF_FUNC_probe_read_str btf_is_any_enum btf__find_by_name bpf_object__new res_id elem_sz kern_func __nmemb LIBBPF_MAP_DATA bpf_map_create_opts BPF_F_NO_COMMON_LRU btf_is_datasec RLIMIT_FSIZE hashmap__new btf__new ext_essent_len bpf_map_lookup_elem_flags BPF_MAP_TYPE_PERCPU_HASH BPF_MAP_TYPE_STRUCT_OPS BPF_FUNC_reserve_hdr_opt elf_errmsg BPF_FUNC_set_hash bpf_map__type bpf_core_add_cands target_fd ELF_T_BYTE gen_uprobe_legacy_event_name sym_global own_log_buf PERF_SAMPLE_RAW syscall_name bpf_core_calc_relo_insn kern_vdata bpf_link__detach_fd attach_btf_obj_fd PERF_SAMPLE_BRANCH_KERNEL_SHIFT pr_perm_msg __RLIMIT_MSGQUEUE bpf_gen__record_extern elf_resolve_pattern_offsets GNU C89 13.3.0 -mtune=generic -march=x86-64 -g -O2 -std=gnu90 -fvisibility=hidden -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection BPF_PROG_TYPE_LSM bpf_map__update_elem ELF_T_NHDR8 bpf_object__unpin_maps __fgets_chk_warn section_defs pin_fd KCFG_BOOL LIBBPF_ERRNO__INVSEQ BPF_FUNC_get_attach_cookie BPF_FUNC_get_cgroup_classid extern_type BPF_FUNC_get_task_stack PERF_SAMPLE_CALLCHAIN shdr_idx BPF_LSM_CGROUP determine_uprobe_perf_type_legacy bpf_program__expected_attach_type mmaped bpf_program PERF_COUNT_SW_TASK_CLOCK BPF_FUNC_setsockopt bsearch MAP_DEF_NUMA_NODE seg_num __bpf_core_types_match EPOLLET libbpf_ptr libbpf_type bpf_gen__init setrlimit64 BPF_MAP_LOOKUP_AND_DELETE_BATCH BPF_PROG_TEST_RUN BPF_PROG_QUERY BPF_MAP_FREEZE bpf_obj_get_opts proceed BPF_LINK_GET_NEXT_ID bpf_enable_stats BPF_LINK_DETACH BPF_ENABLE_STATS memlock_bumped BPF_MAP_UPDATE_ELEM BPF_LINK_GET_FD_BY_ID BPF_MAP_LOOKUP_ELEM bpf_stats_type BPF_MAP_CREATE BPF_BTF_LOAD bpf_obj_pin_opts BPF_LINK_CREATE bpf_obj_get_info_by_fd bpf_prog_detach bpf_prog_detach_opts BPF_TASK_FD_QUERY bpf_btf_load_opts bpf_prog_get_fd_by_id_opts BPF_PROG_LOAD BPF_MAP_DELETE_BATCH bpf_map_lookup_and_delete_elem alloc_zero_tailing_info BPF_MAP_UPDATE_BATCH bpf_prog_get_next_id bpf_map_lookup_batch setrlimit bpf_task_fd_query bpf_link_get_fd_by_id_opts BPF_OBJ_GET_INFO_BY_FD BPF_PROG_DETACH bpf_cmd BPF_PROG_BIND_MAP BPF_BTF_GET_NEXT_ID bpf_prog_detach2 bpf_map_get_fd_by_id target_name_len BPF_LINK_UPDATE bpf_test_run_opts bpf_map_get_next_id bpf_map_update_batch BPF_PROG_GET_NEXT_ID bpf_prog_query memlock_bytes bpf_prog_test_run_opts bpf_prog_get_fd_by_id BPF_ITER_CREATE replace_fd BPF_PROG_GET_FD_BY_ID BPF_MAP_GET_NEXT_KEY missed target_obj_id sys_bpf_fd bpf_link_get_fd_by_id bpf_map_batch_opts nrecord replace_prog_fd bpf_prog_attach_opts BPF_PROG_ATTACH BPF_MAP_LOOKUP_BATCH tp_name_len bpf_iter_create bpf_get_fd_by_id_opts libbpf_set_memlock_rlim bpf_link_info bpf_link_get_info_by_fd actual_rec_size BPF_BTF_GET_FD_BY_ID bpf_map_lookup_elem bpf_map_lookup_and_delete_batch BPF_MAP_LOOKUP_AND_DELETE_ELEM bpf_obj_get_next_id BPF_RAW_TRACEPOINT_OPEN expected_rec_size __off orecord bpf_link_get_next_id bpf_map_delete_batch bpf_btf_get_fd_by_id_opts bpf_map_batch_common BPF_MAP_GET_NEXT_ID BPF_OBJ_PIN bpf_prog_query_opts path_size BPF_STATS_RUN_TIME BPF_PROG_RUN bpf_prog_attach bpf_map_get_fd_by_id_opts BPF_OBJ_GET BPF_MAP_DELETE_ELEM bpf_btf_load BPF_MAP_GET_FD_BY_ID nlmsgerr nlmsg_flags nla_attr_minlen LIBBPF_NLA_FLAG LIBBPF_NLA_U64 maxtype nlmsg_pid libbpf_nla_parse_nested NLMSGERR_ATTR_OFFS LIBBPF_NLA_U32 LIBBPF_NLA_NESTED __LIBBPF_NLA_TYPE_MAX LIBBPF_NLA_UNSPEC hlen NLMSGERR_ATTR_COOKIE nla_next LIBBPF_NLA_STRING nlattr nla_type __NLMSGERR_ATTR_MAX nlmsg_type nla_ok libbpf_nla_policy nlmsg_seq nlmsg_len libbpf_nla_data alen extack_policy validate_nla LIBBPF_NLA_U16 libbpf_nla_len NLMSGERR_ATTR_UNUSED libbpf_nla_dump_errormsg totlen nlmsgerr_attrs LIBBPF_NLA_U8 NLMSGERR_ATTR_MSG LIBBPF_NLA_MSECS libbpf_nla_parse num_records btf_dedup_ref_types btf_equal_common btf__add_datasec canon_id __bswap_16 resolved_type_id type_len btf_type_is_void btf_header btf_dedup_is_equiv btf__add_enum resolve_fwd_id info1 add_sz btf__add_volatile file_name_off __bswap_32 btf_last_type btf__add_field btf_is_modifiable val_lo32 btf__add_fwd cand_m btf__find_str real_kind from_id btf__add_datasec_var_info __fread_alias btf_enum end_type btf_invalidate_raw_data start_str_off btf_dedup_table_add btf_dedup btf_hash_array temp_ptr canon_type_id btf_ext_setup_func_info btf_dedup_identical_structs strset__data_size btf_ext_visit_str_offs btf__parse_raw is_bitfield cand_type line_col __domainname btf__parse_split strs_set btf_validate_id btf_type_visit_str_offs btf_equal_fnproto btf__add_btf btf_equal_array btf__add_union btf_equal_enum_members swapped_endian info2 determine_ptr_size btf__load_from_kernel_by_id_split add_cnt strset__free btf_dedup_collision_hash_fn libbpf_add_mem btf_dedup_identity_hash_fn strset btf_add_type_mem btf_type_size btf_add_composite btf_compat_fnproto strs_dedup_remap_str_off btf_new_empty btf__add_float btf_bswap_type_base dedup_table bpf_line_info_min btf_hash_fnproto strset__data btf_dedup_free visit btf_is_composite btf_add_enum_common max_align btf_dedup_struct_types raw_data_swapped cand_kind btf_parse_type_sec btf_add_type_idx_entry btf_ext_sec_setup_param is_host_big_endian hypot_list btf_ext_visit_type_ids btf_hash_struct btf_equal_enum btf__add_enum64_value info_left btf_dedup_prep btf__add_enum64 btf_type_visit_type_ids btf_validate_str btf_dedup_hypot_map_add long_aliases btf_compat_array byte_sz __bsx btf__parse_raw_split btf_dedup_remap_type_id is_type_mapped uintptr_t next_type force_collisions btf__add_restrict btf_dedup_new btf_parse_elf hash_bits btf_fwd_kind btf_dedup_prim_type btf_dedup_equal_fn ext_sec need_cnt type_id_visit_fn value_off type_offs_cap btf_parse_str_sec btf__new_empty_split btf_rewrite_type_ids cand_id btf_dedup_prim_types btf__load_into_kernel strset__find_str btf_shallow_equal_struct btf_bswap_hdr cand_p cand_t new_offs btf__add_enum_value depth btf_pipe btf_ro btf_equal_int_tag btf_ptr_sz btf_void index_type_id btf_dedup_ref_type btf_is_enum_fwd type_offs ref_type_id canon_arr swap_endian proto_type_id btf__new_empty hypot_cnt fseek nr_elems ftell btf__dedup btf_parse_raw btf_dedup_strings btf_dedup_compact_types cur_cnt line_off t_kind btf_dedup_fill_unique_names_map exit_free btf_type_is_void_or_null canon_kind btf_dedup_resolve_fwds min_rec_size btf_validate_type btf_compat_enum cap_cnt str_off_map types_data_cap btf_ext_setup_line_info btf__add_str btf_parse elem_type_id btf_parse_hdr btf__add_const sinfo btf__base_btf btf_sanity_check btf__parse_elf canon_type type_off btf_get_raw_data btf__load_module_btf what gelf_getehdr BTF_FWD_UNION btf__add_typedef btf__add_type btf__set_endianness btf_equal_enum64_members locations btf_add_ref_kind btf_dedup_resolve_fwd btf_dedup_struct_type bit_size BTF_LITTLE_ENDIAN btf_hash_common strs_deduped btf_dedup_identical_arrays base_size btf__add_type_tag BTF_FWD_ENUM validate_type_id btf_commit_type hash_combine canon_m gelf_getshdr module_name btf_dedup_clear_hypot_map btf__parse_elf_split GElf_Ehdr btf_is_fwd var_type_id BTF_BIG_ENDIAN c_kind __fread_chk BTF_FWD_STRUCT sec_hdrlen last_size btf_for_each_str_off btf_new new_id old_strs_len btf_ext__get_raw_data canon_p GElf_Shdr btf_ext_setup_info btf_dedup_remap_types str_off_visit_fn __fread_chk_warn src_btf strset__new hash_entry btf_add_type_offs_mem next_type_id btf_ensure_modifiable str_off_ptr cand_arr btf__endianness val_hi32 btf_hash_int_decl_tag new_list resolve_type_id max_cnt hypot_cap btf_dedup_merge_hypot_map btf_endianness btf_is_union btf_hash_enum ctx_id fread hypot_adjust_canon hypot_type_id btf_strs_data btf_ext_parse_hdr src_type mapped_off btf_dedup_opts btf_ext_setup_core_relos btf_bswap_type_rest btf__pointer_size total_record_size btf_rewrite_str strset__add_str types_data btf_type_inc_vlen meta_left libbpf_strerror __builtin_snprintf libbpf_strerror_table TCA_INGRESS_BLOCK RTM_GETTUNNEL sa_family TCA_BPF_UNSPEC RTM_SETLINK msg_name MSG_RST bpf_tc_hook RTM_NEWADDRLABEL nlattr_add MSG_WAITFORONE IFLA_XDP_FD RTM_GETNEIGHTBL parse_xdp_features IFLA_IFNAME RTM_DELCHAIN xdp_features_md unicast nl_pid RTM_NEWNETCONF RTM_NEWPREFIX IFLA_DPLL_PIN MSG_PEEK SOCK_RAW __TCA_BPF_MAX CTRL_ATTR_POLICY MSG_TRUNC IFLA_PHYS_SWITCH_ID xdp_tb MSG_CTRUNC NETDEV_CMD_NAPI_GET parse_attr RTM_NEWNEIGH TCA_BPF_POLICE __uint8_t MSG_FASTOPEN RTM_DELACTION multipart MSG_WAITALL TCA_EGRESS_BLOCK IFLA_AF_SPEC IFLA_PERM_ADDRESS CTRL_ATTR_OP_POLICY SOCK_DCCP __TCA_MAX SOCK_RDM NETDEV_CMD_PAGE_POOL_CHANGE_NTF ifinfo RTM_NEWNSID RTM_GETNEIGH IFLA_GSO_IPV4_MAX_SIZE IFLA_IFALIAS __bpf_tc_detach IFLA_PRIORITY __builtin_malloc RTM_DELLINK CTRL_CMD_GETOPS libbpf_netlink_recv NETDEV_A_DEV_PAD RTM_NEWNEIGHTBL IFLA_TARGET_NETNSID bpf_xdp_attach_opts IFLA_LINKINFO nl_pad RTM_NEWACTION RTM_DELMDB TCA_FCNT RTM_NEWMDB SOCK_SEQPACKET IFLA_CARRIER_DOWN_COUNT CTRL_ATTR_MAXATTR MSG_BATCH IFLA_OPERSTATE nl_family NETDEV_A_DEV_XSK_FEATURES TCA_BPF_NAME CTRL_CMD_DELMCAST_GRP RTM_DELTCLASS RTM_NEWTFILTER parse_msg RTM_SETDCB IFLA_XDP_DRV_PROG_ID XDP_ATTACHED_NONE MSG_CMSG_CLOEXEC MSG_EOR nbuf MSG_FIN SOCK_STREAM IFLA_NUM_VF MSG_OOB RTM_GETNSID IFLA_MTU __RTM_MAX bpf_tc_attach IFLA_ALT_IFNAME IFLA_MAX_MTU bpf_tc_attach_point IFLA_ALLMULTI NETDEV_CMD_PAGE_POOL_ADD_NTF tc_add_fd_and_name RTM_DELADDR msg_namelen msg_control IFLA_PROTO_DOWN RTM_GETTCLASS qdisc_config_t ifi_family RTM_DELQDISC __socklen_t parse_genl_family_id __socket_type __CTRL_CMD_MAX bpf_tc_flags NETDEV_CMD_DEV_CHANGE_NTF IFLA_PROTO_DOWN_REASON RTM_NEWTCLASS bpf_tc_query RTM_NEWNDUSEROPT TCA_STATS NETDEV_CMD_PAGE_POOL_STATS_GET NL_NEXT TCA_DUMP_FLAGS bpf_xdp_query_opts IFLA_VF_PORTS IFLA_LINKMODE RTM_DELNEIGH bpf_xdp_detach CTRL_CMD_UNSPEC TCA_BPF_CLASSID getsockname TCA_XSTATS addrlen IFLA_WIRELESS tc_qdisc_delete RTM_NEWROUTE CTRL_ATTR_FAMILY_NAME RTM_GETNETCONF TCA_CHAIN IFLA_XDP_PROG_ID drv_prog_id get_xdp_info IFLA_MIN_MTU IFLA_DEVLINK_PORT RTM_NEWADDR IFLA_XDP_SKB_PROG_ID MSG_SYN RTM_DELVLAN RTM_GETLINK mhdr RTM_GETMDB CTRL_ATTR_VERSION __dump_link_nlmsg NETDEV_A_DEV_XDP_ZC_MAX_SEGS RTM_DELNEXTHOPBUCKET CTRL_ATTR_FAMILY_ID NETDEV_A_DEV_XDP_FEATURES CTRL_CMD_DELFAMILY RTM_DELNEXTHOP RTM_GETROUTE IFLA_CARRIER_UP_COUNT iov_len sockaddr_nl xdp_id_md NETDEV_CMD_DEV_DEL_NTF CTRL_ATTR_OPS libbpf_netlink_send_recv NL_CONT TCA_STATS2 IFLA_TSO_MAX_SEGS TCA_BPF_TAG tcm__pad1 tcm__pad2 send RTM_GETACTION netlink_recvmsg libbpf_dump_nlmsg_t protocol __NETDEV_CMD_MAX IFLA_GROUP MSG_ZEROCOPY __bpf_set_link_xdp_fd_replace RTM_GETANYCAST IFLA_GSO_MAX_SEGS iovec IFLA_NUM_RX_QUEUES CTRL_CMD_NEWFAMILY IFLA_CARRIER RTM_GETADDR RTM_BASE req_tail XDP_ATTACHED_HW RTM_NEWVLAN IFLA_VFINFO_LIST TCA_BPF_FD RTM_NEWQDISC bpf_cb_ctx IFLA_CARRIER_CHANGES __ifi_pad libbpf_nla_getattr_u16 IFLA_NEW_IFINDEX RTM_GETNEXTHOPBUCKET __IFLA_XDP_MAX bpf_xdp_query_id alloc_iov IFLA_WEIGHT IFLA_PAD IFLA_PROMISCUITY IFLA_PHYS_PORT_NAME hw_prog_id __IFLA_MAX RTM_DELRULE xdp_id libbpf_nla_getattr_u8 RTM_GETDCB xdp_flags IFLA_XDP_UNSPEC RTM_DELNSID RTM_GETQDISC IFLA_EVENT SOCK_NONBLOCK NETDEV_A_DEV_XDP_RX_METADATA_FEATURES TCA_BPF_FLAGS_GEN TCA_OPTIONS BPF_TC_CUSTOM IFLA_QDISC RTM_GETTFILTER __NETDEV_A_DEV_MAX CTRL_ATTR_OP CTRL_CMD_NEWMCAST_GRP BPF_TC_EGRESS libbpf_nla_getattr_u32 IFLA_PORT_SELF NETDEV_CMD_DEV_GET IFLA_NEW_NETNSID XDP_ATTACHED_MULTI MSG_DONTWAIT NETDEV_CMD_DEV_ADD_NTF RTM_DELTUNNEL RTM_GETRULE IFLA_PARENT_DEV_NAME RTM_NEWCACHEREPORT CTRL_ATTR_UNSPEC TCA_BPF_ID RTM_DELROUTE nl_groups RTM_NEWNEXTHOP RTM_GETVLAN bpf_tc_hook_create IFLA_MAP IFLA_COST RTM_DELADDRLABEL tc_qdisc_modify MSG_PROXY IFLA_PARENT_DEV_BUS_NAME CTRL_CMD_NEWOPS IFLA_XDP_FLAGS BPF_TC_INGRESS SOCK_DGRAM libbpf_netlink_resolve_genl_family_id IFLA_PROP_LIST RTM_NEWRULE xdp_zc_max_segs MSG_CONFIRM TCA_EXT_WARN_MSG libbpf_nla_req MSG_NOSIGNAL IFLA_MASTER IFLA_XDP_ATTACHED bpf_xdp_query ifi_type xdp_link_info XDP_ATTACHED_SKB __get_tc_info IFLA_PHYS_PORT_ID RTM_NEWTUNNEL libbpf_nla_getattr_u64 BPF_TC_F_REPLACE tcmsg sa_data TCA_BPF_ACT RTM_DELTFILTER RTM_NEWSTATS TCA_DUMP_INVISIBLE bpf_tc_hook_destroy sockaddr IFLA_STATS64 IFLA_PROTINFO RTM_SETSTATS IFLA_GRO_IPV4_MAX_SIZE IFLA_BROADCAST IFLA_ADDRESS TCA_HW_OFFLOAD RTM_SETNEIGHTBL __dump_nlmsg_t nlattr_end_nested IFLA_UNSPEC genlmsghdr TCA_STAB TCA_BPF_FLAGS CTRL_CMD_GETMCAST_GRP RTM_DELLINKPROP bpf_flags TCA_RATE IFLA_TXQLEN RTM_GETSTATS RTM_NEWNEXTHOPBUCKET ifi_flags RTM_NEWCHAIN msg_controllen msg_iovlen libbpf_netlink_close SOCK_CLOEXEC IFLA_STATS RTM_GETLINKPROP TCA_BPF_OPS_LEN SOCK_PACKET NETDEV_CMD_PAGE_POOL_DEL_NTF msg_iov NETDEV_CMD_PAGE_POOL_GET IFLA_LINK CTRL_ATTR_HDRSIZE CTRL_CMD_GETFAMILY tcm_ifindex TCA_PAD tc_get_tcm_parent IFLA_LINK_NETNSID ifi_change IFLA_XDP_EXPECTED_FD RTM_GETCHAIN MSG_ERRQUEUE RTM_DELNETCONF clsact_config NETDEV_CMD_QUEUE_GET NETDEV_A_DEV_IFINDEX bpf_xdp_attach socket skb_prog_id ifi_index IFLA_IF_NETNSID tcm_info nlattr_begin_nested CTRL_ATTR_MCAST_GROUPS tcm_family RTM_GETADDRLABEL IFLA_TSO_MAX_SIZE IFLA_NET_NS_FD MSG_DONTROUTE XDP_ATTACHED_DRV bpf_tc_opts __kernel_sa_family_t tc_qdisc_create_excl IFLA_NET_NS_PID tcm_handle iov_base IFLA_GSO_MAX_SIZE TCA_KIND RTM_NEWLINK processed libbpf_netlink_open IFLA_XDP_HW_PROG_ID attach_point_to_config IFLA_GRO_MAX_SIZE IFLA_NUM_TX_QUEUES skip_feature_flags IFLA_XDP ifinfomsg RTM_NEWLINKPROP TCA_BPF_OPS CTRL_CMD_DELOPS NL_DONE MSG_MORE IFLA_EXT_MASK CTRL_CMD_GETPOLICY __CTRL_ATTR_MAX RTM_GETNEXTHOP RTM_GETMULTICAST TCA_UNSPEC nr_jited_func nr_skip last_jited_linfo nr_linfo bpf_prog_linfo__free err_free bpf_prog_linfo__lfind_addr_func raw_linfo bpf_prog_linfo jited_linfo_func_idx bpf_prog_linfo__new raw_jited_linfo jited_rec_size bpf_prog_linfo__lfind ksym_len prev_i bpf_line_info ksym_func dissect_jited_func nr_jited_linfo_per_func get_debian_kernel_version libbpf_probe_bpf_prog_type probe_map_create types_len libbpf_probe_bpf_map_type ubuntu_kver_file raw_types probe_prog_load __isoc99_sscanf exp_msg log_buf_sz helper_id minor btf_len exp_err fd_inner get_ubuntu_kernel_version libbpf_probe_bpf_helper load_local_storage_btf major hashmap_del_entry new_buckets hashmap__capacity hashmap__size new_cap prev_ptr hashmap__clear hashmap_delete old_value hashmap__init hashmap_grow hashmap_add_entry hashmap_needs_to_grow old_key new_cap_bits hashmap_find_entry indent_level btf_dump_drop_mods new_cont_id bytecmp right_shift_bits btf_dump_bitfield_check_zero emit_queue_cap new_stack pad_type EMITTING prev_bitfield btf_dump_datasec_data btf_dump_int_data new_off new_queue type_states moffset next_align fmt_str ident_names btf_dump_is_blacklisted is_array_member btf_dump_order_type btf_dump_data_newline btf_dump__new btf_dump_emit_type_chain btf_dump_opts btf_dump_emit_type_cast btf_dump_printf is_array_terminated btf_dump_ident_name str_equal_fn btf_dump__dump_type btf_dump_push_decl_stack_id btf_dump_emit_name btf_dump_free_names btf_dump_emit_fwd_def is_strong ORDERING last_was_ptr __builtin_memcmp btf_dump_bitfield_data PREFIXES orig_name elem_type btf_dump_emit_type_decl btf_dump_type_data_check_overflow typed_dump stack_start is_array_char btf_dump_resize btf_dump_emit_enum_fwd btf_dump_emit_typedef_def btf_dump_emit_missing_aliases btf_dump_data_pfx btf_dump_emit_enum_def cached_names_cap pads needs_word_mode btf_dump_emit_enum32_val btf_dump_emit_type btf_dump_type_data_opts check_num decl_stack_cap btf_dump_array_data emit_queue_cnt enum_val btf_dump_var_data next_t multidim dup_cnt pad_bits separate data_end btf_dump_emit_enum64_val field_name emit_zeroes elem_size print_num btf_dump_printf_fn_t next_off btf_dump__dump_type_data btf_dump_emit_type_decl_opts decl_stack btf_dump_resolve_name btf_name_of fname decl_stack_cnt nr_bytes btf_dump__emit_type_decl old_name btf_dump_emit_mods btf_dump_base_type_check_zero in_bitfield left_shift_bits bits_offset printf_fn btf_dump_struct_data btf_dump_get_enum_value indent_str btf_dump_add_emit_queue_id compact NOT_ORDERED btf_dump_data_delim btf_dump_mark_referenced top_level btf_dump_float_data through_ptr btf_enum64_value btf_is_struct_packed btf_dump_type_aux_state str_hash_fn last_id btf_dump_get_bitfield_value m_align cached_name NOT_EMITTED emit_queue btf_dump__free btf_dump_type_name btf_dump_type_emit_state name_map btf_dump id_stack nr_copy_bits btf_dump_ptr_data btf_dump_unsupported_data skip_mod btf_dump_dump_type_data btf_dump_data decls type_states_cap ptr_is_aligned skip_names cur_off btf_dump_emit_struct_fwd ischar missing_base_types btf_dump_emit_struct_def skip_anon_defs btf_dump_type_data_check_zero top_level_def cached_names str_hash alignment tstate btf_dump_name_dups PREFIX_CNT strip_mods fwd_emitted name_resolved btf_dump_enum_data indent_lvl btf_dump_type_order_state btf_dump_emit_bit_padding ring_id ns_per_ms ring_buffer__add ns_per_s ringbuf_free_ring ring__size prod_pos ring__avail_data_size ms_remaining ring__consume hdr_offset BPF_RINGBUF_BUSY_BIT got_new_data user_ringbuf_commit user_ring_buffer ring_buffer__ring ring__producer_pos ring__map_fd BPF_RINGBUF_HDR_SZ roundup_len user_ring_buffer__free ring_cnt user_ring_buffer__reserve_blocking ring_buffer_sample_fn ms_elapsed user_ringbuf_map BPF_RINGBUF_DISCARD_BIT ring__consumer_pos len_ptr clock_gettime __clockid_t start_ns ring_buffer__poll curr cons_pos ringbuf_process_ring total_size user_ring_buffer_opts end_ns user_ring_buffer__submit ringbuf_hdr ring_buffer__consume ns_elapsed_timespec user_ring_buffer__new max_size user_ring_buffer__reserve rb_epoll ring_buffer__epoll_fd user_ring_buffer__discard avail_size user_ringbuf_unmap_ring str1 strs_data_cap key2 strs_data_len strset_hash_fn str2 key1 strs_hash old_off max_data_sz strs_data_max_len strset_equal_fn strset_add_str_mem init_data_sz init_data finalize_btf bpf_linker__finalize underlying_btf_id extra_def finalize_btf_ext glob_syms linker_append_elf_relos extra_btf recs is_ignored_sec btf_type_map sec_content_is_same var_linkage glob_t linker_append_btf_ext init_sym btf_is_non_static dst_sym_idx is_data_sec raw_sz elf_update sec_var_cnt linker_sanity_check_elf_relos core_relos_sz dst_id linker_sanity_check_btf_ext funcs_sz sym_update_type extend_sec has_btf recur src_rec src_rel dst_var bpf_linker line_rec_sz secs_match btf2 strtab_strs emit_elf_data_sec shstrs_sec_idx dst_sym link_sec linker_sanity_check_elf_symtab skipped linker_fixup_btf core_relo_rec_sz linker_append_elf_sym strs_sz extra_inner_def glob_syms_match bpf_linker_file_opts glob_sym_btf_matches exact src_sym_idx func_rec_sz lines_sz btf1 linker_sanity_check_btf dst_p dst_t src_p bpf_linker__new src_t src_symtab bpf_linker__add_file src_inner_def find_sym_by_name complete_extern_btf_info btf_ext_sec_data is_static1 is_static2 strtab_sec_idx add_dst_sec sec_sym_idx out_btf_sec_id check_btf_type_id dst_def src_var linker_append_sec_data elf_newscn sym_update_visibility init_output_elf sym_map sym_vis bpf_linker_opts dst_btf elf_newdata dst_off glob_sym_cnt src_id elf64_newehdr src_sym sym_bind src_linked_sec dst_final_sz glob_map_defs_match sec_type_id linker_append_elf_syms add_sym add_btf_ext_rec sec_vars add_glob_sym find_src_sec_by_name linker_sanity_check_elf check_btf_str_off main_def sec_info init_sec linker_append_btf find_glob_sym_btf ephemeral is_relo_sec mismatch host_endianness dst_align_sz add_new_sym dst_linked_sec is_dwarf_sec_name add_src_sec bpf_linker__free out_btf_id src_align src_def get_sym_by_idx src_obj total_sz symtab_sec_idx find_glob_sym dst_rec dst_rel dst_align find_dst_sec_by_name emit_btf_ext_data str_sec_idx dst_inner_def sym_update_bind linker_load_obj_file main_inner_def elf_hdr prog_idx emit_relo_kfunc_btf debug_regs outer_map_idx insns_off btf_raw_size emit_bpf_find_by_name_kind realloc_data_buf emit2 reg1 reg2 map_update_attr insn_bytes_to_bpf_size res_off add_kfunc_btf_fd emit_sys_close_stack emit add_map_fd emit_relo stack_off __builtin___strcat_chk attr_size prog_load_attr emit_sys_close_blob size8 slot move_ctx2blob emit_relo_ksym_btf check_non_zero stack_sz map_freeze_attr __emit_sys_close inner_map_idx blob_off cleanup_core_relo add_data map_attr ctx_off emit_find_attach_target src_reg_mask kdesc debug_ret get_ksym_desc move_blob2ctx emit_debug license_off insn1 insn2 emit_rel_store is_simm16 emit_sys_bpf nr_progs_sz move_blob2blob clear_src_reg emit_bpf_kallsyms_lookup_name emit_ksym_relo_log move_stack2blob blob_fd_array_off emit_relo_ksym_typeless BPF_SKEL_KERNEL move_stack2ctx emit_relos map_create_attr close_inner_map_fd cleanup_relos realloc_insn_buf btf_raw_data emit_check_err btf_load_attr core_relo_kind_str local_len orig_t targ_sgn targ_name_off insn_bpf_sz next_targ_id btf_int_offset core_relo_is_type_based found bpf_core_calc_relo targ_len byte_off bpf_core_fields_are_compat bpf_core_composites_match targ_vlen core_relo_is_field_based bpf_core_spec_match new_t core_relo_is_enumval_based spec_str local_spec local_array behind_ptr local_acc targ_array is_flex_arr local_name_off local_n_off field_sz local_f local_k local_m local_n local_p access_idx local_vlen local_member targ_acc matched insn_bpf_size_to_bytes bpf_core_enums_match bpf_core_calc_field_relo targ_n_off bpf_core_calc_enumval_relo field_type_id parsed_len bpf_core_poison_insn bpf_core_match_member bit_off targ_spec targ_f targ_k targ_m targ_n targ_p targ_t local_sgn cand_spec bpf_core_names_match flex cand_res bpf_core_calc_type_relo insn_bytes_sz p_vaddr specs_equal_fn find_vma_seg realpath virtaddr elf_close ip_to_spec_id_map has_sema_refcnt ip_map_fd allocate_spec_id __realpath_alias parse_vma_segs Elf64_Nhdr is_exec parse_usdt_spec specs_hash elf_fd BPF_ANY calc_pt_regs_off is_new arg_signed usdt_abs_ip parse_usdt_arg n_namesz parse_elf_segs BPF_F_LOCK lib_path BPF_NOEXIST next_free_spec_id elf_open Elf64_Phdr p_filesz base_shdr vma_seg_cnt arg_sz GElf_Nhdr seg_end usdt_target usdt_arg_type sema_addr tmp_pid notes_shdr reg_off memchr usdt_rel_ip specs_map new_free_ids bpf_link_usdt_detach specs_hash_fn p_align has_bpf_cookie free_spec_ids USDT_ARG_REG_DEREF USDT_ARG_REG seg_off GElf_Phdr uprobes usdt_arg_spec usdt_link gelf_getnote val_off __resolved elf_getphdrnum opts_multi reg_name p_memsz base_scn notes_scn spec_map_fd seg_start bpf_link_usdt_dealloc out_target_cnt cmp_elf_segs has_uprobe_multi p_paddr collect_usdt_targets loc_addr uprobe_link free_spec_cnt ref_ctr_sysfs_path reg_map BPF_EXIST arg_str desc_off parse_usdt_note arg_bitshift __realpath_chk find_elf_seg gelf_getphdr usdt_sema_off n_descsz arg_num bpf_link_usdt sanity_check_usdt_elf out_targets base_addr new_ids nhdr find_elf_sec_by_name uprobe_cnt USDT_ARG_CONST extra_field_length this_disk cd_offset local_file_header_at_offset cdfh_name last_modified_date cdfh external_attributes min_version lseek cd_size cd_file_header file_name_length cd_records_total lseek64 try_parse_end_of_cd local_file_header last_modified_time cd_disk check_access get_entry_at_offset cdfh_name_length eocd cd_records internal_attributes file_comment_length end_of_cd_record cdfh_flags uncompressed_size find_cd vd_version gelf_getsym cur_bind symbol_match elf_get_vername sym_a sym_b elf_find_next_scn_by_type vd_aux vd_next ver_name vd_ndx vda_next verdefs GElf_Versym Elf64_Verdef versyms poffsets Elf64_Verdaux GElf_Sym symbol_cmp is_shared_lib lib_ver gelf_getverdef Elf64_Versym vd_cnt gelf_getverdaux at_symbol vd_flags elf_sym_offset elf_sym_iter_new gelf_getversym next_sym_idx elf_sym_iter pcnt vd_hash GElf_Verdaux cnt_done vda_name sh_types sym_scn hidden verdef_strtabidx elf_sym_iter_next last_bind GElf_Verdef /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/perf tests/workloads/leafloop.c tests/workloads /usr/include/x86_64-linux-gnu/bits /usr/include/x86_64-linux-gnu/bits/types /usr/include tests/workloads/.. sig_atomic_t.h signal.h tests.h unistd.h stdlib.h tests/workloads/sqrtloop.c /usr/include/x86_64-linux-gnu/sys wait.h mathcalls.h tests/workloads/brstack.c tests/workloads/datasym.c fd/array.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/api /usr/lib/gcc/x86_64-linux-gnu/13/include /usr/include/x86_64-linux-gnu/gnu /usr/include/linux /usr/include/x86_64-linux-gnu/asm /usr/include/asm-generic stddef.h struct_FILE.h stdio.h string.h stdc-predef.h libc-header-start.h features.h features-time64.h wordsize.h timesize.h cdefs.h long-double.h stubs.h stubs-64.h stdarg.h typesizes.h __fpos_t.h __mbstate_t.h __fpos64_t.h __FILE.h cookie_io_functions_t.h stdio_lim.h floatn.h floatn-common.h errno.h errno-base.h fcntl.h fcntl-linux.h struct_timespec.h endian.h endianness.h time_t.h struct_stat.h waitflags.h waitstatus.h clock_t.h clockid_t.h timer_t.h stdint-intn.h byteswap.h uintn-identity.h select.h __sigset_t.h struct_timeval.h pthreadtypes.h thread-shared-types.h pthreadtypes-arch.h atomic_wide_counter.h struct_mutex.h struct_rwlock.h alloca.h stdlib-float.h posix_opt.h environments.h confname.h getopt_posix.h getopt_core.h unistd_ext.h __locale_t.h strings.h fs/fs.c fs fs/.. /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/linux /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/asm-generic /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/uapi/asm-generic statfs.h pthread.h mount.h assert.h ctype.h syslimits.h posix1_lim.h local_lim.h pthread_stack_min-dynamic.h pthread_stack_min.h posix2_lim.h stdbool.h vfs.h sched.h struct_sched_param.h cpu-set.h time.h struct_tm.h struct_itimerspec.h setjmp.h struct___jmp_buf_tag.h stdint.h wchar.h stdint-uintn.h stdint-least.h ioctl.h ioctls.h ioctl-types.h ttydefaults.h int-ll64.h bitsperlong.h posix_types.h posix_types_64.h debug-internal.h debug.h fs/tracing_path.c dirent.h error_t.h close_range.h tracing_path.h dirent_ext.h fs/cgroup.c stringify.h cpu.c cpu.h debug.c <built-in> ../str_error_r.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/perf /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/perf/include/perf /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/perf/include/internal cpumap.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/asm/../../arch/x86/include/asm atomic.h compiler.h refcount.h cpumap.h threadmap.c threadmap.h evsel.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/include/uapi/linux xyarray.h evsel.h perf_event.h mmap.h zalloc.h evlist.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/api/fd evlist.h hash.h mmap.c ring_buffer.h math64.h mman.h ../../lib/zalloc.c ../../lib xyarray.c lib.c exec-cmd.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/subcmd subcmd-util.h stdio2.h string_fortified.h subcmd-config.h unistd-decl.h stdio2-decl.h compiler_types.h compiler-gcc.h strings_fortified.h select2.h select-decl.h statx-generic.h struct_statx_timestamp.h struct_statx.h stdlib-bsearch.h exec-cmd.h help.c help.h termios.h termios-struct.h termios-c_cc.h termios-c_iflag.h termios-c_oflag.h termios-baud.h termios-c_cflag.h termios-c_lflag.h termios-tcflow.h termios-misc.h pager.c run-command.h sigchain.h signum-generic.h signum-arch.h siginfo_t.h __sigval_t.h siginfo-arch.h siginfo-consts.h siginfo-consts-arch.h sigevent_t.h sigevent-consts.h sigaction.h sigcontext.h stack_t.h ucontext.h sigstksz.h ss_flags.h struct_sigstack.h sigthread.h signal_ext.h pager.h parse-options.c parse-options.h kernel.h build_bug.h math.h panic.h run-command.c fcntl2.h struct_iovec.h falloc.h idtype_t.h sigchain.c subcmd-config.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/symbol kallsyms.c kallsyms.h libbpf.c /build/linux-rzYwLF/linux-6.8.0/debian/build/tools-perarch/tools/lib/bpf libbpf_internal.h btf.h err.h epoll.h utsname.h resource.h libelf.h zlib.h libbpf_legacy.h libbpf.h relo_core.h hashmap.h bpf_gen_internal.h zip.h libgen.h mman-shared.h gelf.h str_error.h nlattr.c nlattr.h btf.c strset.h libbpf_errno.c str_error.c netlink.c sockaddr.h socket.h pkt_cls.h if_link.h rtnetlink.h netdev.h socket_type.h genetlink.h bpf_prog_linfo.c libbpf_probes.c hashmap.c btf_dump.c ringbuf.c strset.c linker.c gen_loader.c skel_internal.h relo_core.c usdt.c zip.c elf.c a UZUZU 1PpPpP xb. p U U VUUU P\ U VUUU 0 P p q0qQq0 PP P V V P S V \ S S , \ \ V U T U U V P U V U v p " P S S p UYU U U 0 0 + `U` U Up U TT QpQ RR UU 6U6:X:U T:Y:T 0:Y:;T 06U6:X:;U 0; 03w3;S ;b + B]p ]aU UVUUVUV TSTTSTS TSSS _\\\ \0 _\\ P]] _\ ] \ \ S \ \X_ V S , V T VU BL* VU SU , V S UV ] , UV V T P P UU TST 0]P] U]U]U] T\T\T\ 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